Integrated circuit and method of forming the same

Abstract

Embodiments of the present application relate to an integrated circuit (IC) including a boundary region defined between a low voltage region and a high voltage region, and to a method of forming the integrated circuit. In some embodiments, the integrated circuit includes an isolation structure disposed in the boundary region of a substrate. A first polysilicon component is disposed above the substrate side by side with the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on a sacrificial dielectric layer.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuits and methods of forming integrated circuits. Background Art

[0002] Over the past few decades, the semiconductor manufacturing industry has experienced exponential growth. In the process of IC evolution, high voltage technology has been widely used in power management, voltage regulators, battery protectors, DC motors, automotive related, panel display drivers (STN, TFT, OLED, etc.), color display drivers, power related, telecommunications, etc. On the other hand, as the geometric size (i.e., the smallest component (or line) that can be created using the manufacturing process) decreases, the functional density (i.e., the number of interconnected devices per unit chip area) is generally increasing. In some IC designs, an advancement achieved with the reduction of technology nodes is to replace the typical polysilicon gate electrode of the logic core with a metal gate electrode and a high-k dielectric, also known as a HKMG replacement gate device, to provide device performance with reduced device size. The high voltage device is integrated on the same chip with the HKMG logic core and supports the logic core to achieve the intended function and limit or eliminate inter-chip communication. Summary of the invention

[0003] According to one embodiment of the present application, an integrated circuit (IC) is provided, comprising: a substrate, comprising a low-voltage region, a high-voltage region, and a boundary region defined between the low-voltage region and the high-voltage region; an isolation structure, arranged in the boundary region of the substrate; a first polysilicon component, arranged side by side with the isolation structure above the substrate; a boundary dielectric layer, arranged on the isolation structure; and a second polysilicon component, arranged on the boundary dielectric layer.

[0004] According to another embodiment of the present application, a method for forming an integrated circuit (IC) is provided, comprising: providing a substrate, comprising a low voltage region, a high voltage region, and a boundary region defined between the low voltage region and the high voltage region; forming a supporting layer above the substrate in the high voltage region, wherein the supporting layer has an inclined sidewall in the boundary region, and the inclined sidewall is inclined toward the high voltage region from bottom to top; forming a stack of low voltage gate precursor layers above the substrate in the low voltage region and on the supporting layer in the high voltage region; and patterning the stack of low voltage gate precursor layers to form a changed low voltage gate precursor layer in the low voltage region; wherein, when the changed low voltage gate precursor layer is formed, the stack of low voltage gate precursor layers is removed from the boundary region and the high voltage region.

[0005] According to another embodiment of the present application, a method for forming an integrated circuit (IC) is provided, including: providing a substrate, including a low voltage region, a high voltage region, and a boundary region defined between the low voltage region and the high voltage region; forming and patterning a first supporting layer above the substrate in the high voltage region; forming a second supporting layer above the substrate in the low voltage region and on the first supporting layer in the high voltage region; performing an etching process on the second supporting layer and the first supporting layer to remove the second supporting layer from the low voltage region and form an inclined sidewall in the boundary region; and forming a stack of low voltage gate precursor layers above the substrate in the low voltage region and above the first supporting layer in the high voltage region; and patterning the stack of low voltage gate precursor layers to form a low voltage transistor device in the low voltage region.

[0006] Embodiments of the present application relate to boundary design for high voltage integration on HKMG technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 Cross-sectional views of some embodiments of an integrated circuit (IC) including a boundary region defined between a low voltage region and a high voltage region are shown.

[0009] Figure 2-Figure 8 A series of cross-sectional views illustrating some embodiments of methods for fabricating an IC including a boundary region defined between a low voltage region and a high voltage region.

[0010] Figure 9-Figure 26 A series of cross-sectional views illustrating some alternative embodiments of methods for fabricating an IC including a boundary region defined between a low voltage region and a high voltage region.

[0011] Fig. 27 A flow chart illustrating some embodiments of a method for fabricating an IC including a boundary region defined between a low voltage region and a high voltage region.

[0012] Fig.28 Flowcharts illustrating some alternative embodiments of methods for fabricating an IC including a boundary region defined between a low voltage region and a high voltage region. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are only examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numbers and / or letters in various examples. This repetition is only for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] High-k metal gate (HKMG) technology has also become one of the leaders for next-generation CMOS devices. HKMG technology uses high-k dielectrics to increase transistor capacitance and reduce gate leakage. Metal gate electrodes are used to help Fermi level pinning and allow the gate to be adjusted to a low threshold voltage. By combining metal gate electrodes and high-k dielectrics, HKMG technology makes further scaling possible and allows integrated chips to operate at reduced power. HKMG technology can be used for memory devices, display devices, sensor devices, and other applications that require high-voltage areas, and is included in integrated circuits to provide higher power and have higher breakdown voltages compared to traditional MOS devices. However, embedding HKMG devices and high-voltage devices is challenging, especially at 28nm nodes and higher processes. The problem associated with such integrated circuits is the boundary defects between the high-voltage region where the high-voltage device is located and the low-voltage device region where the device operates at a relatively low voltage. For example, the gate dielectrics for the high-voltage region and the low-voltage region often require different thicknesses and may therefore need to be processed separately. Due to the patterning and removal of the gate dielectric, relatively high isolation damage and toxic residues may be introduced. For example, high-k dielectric residues may remain in the boundary region, which may cause contamination of subsequent processes. Additionally, the boundary region between the high-voltage region and the low-voltage region may lack structural support, and the dishing effect introduced by the planarization process may cause an uneven surface and affect device performance in the low-voltage region and / or the high-voltage region.

[0016] The present disclosure relates to an integrated circuit (IC) including a boundary structure disposed in a boundary region between a low voltage region and a high voltage region, and to a method of forming the same. Figure 1 , the integrated circuit 100 includes a substrate 106, which includes a low voltage region 102, a medium voltage region 103, a high voltage region 104, and a boundary region 130 defined between the low voltage region 102 and the medium voltage region 103. A boundary structure 150 is disposed in the boundary region 130. The boundary structure 150 may include an isolation structure 108, a first polysilicon component 112 disposed above the substrate 106 adjacent to the isolation structure 108, a boundary dielectric layer 110 disposed above the isolation structure 108, and a second polysilicon component 114 disposed above the boundary dielectric layer 110. By arranging the boundary structure 150 in the boundary region, isolation damage and uneven surfaces are reduced, thereby improving device performance. In some other embodiments, the method of forming the boundary structure 150 includes forming a support layer covering the high voltage region before forming and patterning a low voltage device precursor layer (which may include a high-k dielectric material). The support layer is formed to have an inclined sidewall surface in the boundary region so that the patterned residue from the low voltage device precursor layer is minimized in the boundary region. Therefore, pollution is reduced.

[0017] refer to Figure 2-Figure 8 In some embodiments, a first support layer 202 is formed in the high voltage region 104 above the high voltage transistor device 142, and then a second support layer 204 is formed, such as Figure 2 The second supporting layer 204 is formed above the first supporting layer 202 in the high pressure region 104 , so that its height is different from the lower portion in the low pressure region 102 .

[0018] like Figure 3 As shown, in some embodiments, an etching process is then performed on the second supporting layer 204 to form an inclined sidewall 204s. In some alternative embodiments, the etching process also removes a portion of the first supporting layer 202, so that the inclined sidewall 204s is formed by the first supporting layer 202 and the second supporting layer 204 (for example, as shown in FIG. Figure 15-16 The first support layer 202 and the second support layer 204 may be collectively referred to as support layers. The inclined sidewall 204s is inclined toward the high pressure region from the bottom to the top and may have an inclination angle α substantially equal to 45 degrees or in a range between about 30 degrees and about 45 degrees.

[0019] like Figure 4As shown, in some embodiments, a stack of low voltage gate precursor layers 1702 is formed over the substrate 106 in the low voltage region 102 and over the second support layer 204 in the high voltage region 104. The low voltage gate precursor layer 1702 may include a low voltage gate electrode layer 118', a low voltage gate dielectric layer 120', and a masking layer 402'.

[0020] like Figure 5 As shown, in some embodiments, the low voltage gate precursor layer 1702 is patterned to be removed from the high voltage region 104, and a changed low voltage gate precursor layer 1702' is left in the low voltage region 102. The patterning process may include a photolithography process, wherein the changed low voltage gate precursor layer 1702' may be covered by a masking layer 502 to prevent removal. The masking layer 502 may be made of a photoresist mask or a transfer hard mask made of a dielectric or other applicable material. The low voltage gate precursor layer 1702 is completely removed from the boundary region 130 due to the continuous and inclined sidewalls 204s.

[0021] like Figure 6 As shown, in some embodiments, a boundary filling process is performed to fill the gap between the low voltage region 102 and the high voltage region 104. In some embodiments, a conformal layer and a filling layer are formed to fill the gap. For example, a conformal polysilicon layer 2002 is deposited on the changed low voltage gate precursor layer 1702' and the second support layer 204. A filling layer 2004 (e.g., made of a photoresist material) can then be coated or spun to form a flat top surface.

[0022] like Figure 7 As shown, in some embodiments, a patterning process is performed to form a low voltage transistor device 140 in the low voltage region 102, a boundary structure 150 in the boundary region 130, and a gate masking structure layer 128 in the high voltage region 104 from the altered low voltage gate precursor layer 1702', the conformal polysilicon layer 2002, the first support layer 202, and / or the second support layer 204, respectively. A pair of source / drain regions 144a can be formed in the substrate 106 on opposite sides of the low voltage gate stack 1702".

[0023] like Figure 8 As shown, in some embodiments, the ILD layer 802 is formed over the low voltage transistor device 140 in the low voltage region 102, over the boundary structure 150 in the boundary region 130, and over the gate masking structure layer 128 in the high voltage region 104. The contact structure 152 is formed through the ILD layer 802 to reach the low voltage transistor device 140 and the high voltage transistor device 142.

[0024] As described above, by forming the boundary structure 150 within the boundary region 130, residue contamination and isolation damage caused by patterning and removal of the gate dielectric can be reduced or even eliminated, because a portion of the precursor layer is formed on the inclined sidewalls of the support layer and is therefore completely removed during the subsequent etching process. Moreover, the disclosed boundary structure 150 provides support during manufacturing, thereby reducing or eliminating the recess effect. As a result, device performance is improved and the manufacturing process is simplified, making further scaling possible in emerging technology nodes.

[0025] Figure 1 A cross-sectional view of an integrated circuit 100 is shown, which includes a boundary region 130 defined between a low voltage region 102 and a medium voltage region 103. In some embodiments, a low voltage transistor device 140 is disposed in the low voltage region 102. The low voltage transistor device 140 has a low voltage gate electrode 118, which is disposed above a low voltage gate dielectric layer 120 between a first pair of source / drain regions 144a. In some embodiments, the low voltage gate electrode 118 includes polysilicon. In some other embodiments, the low voltage gate electrode 118 can be made of a metal or metal alloy material. The low voltage gate dielectric layer 120 can include a high-k gate dielectric layer. The low voltage gate dielectric layer 120 can cover the bottom and sidewall surfaces of the low voltage gate electrode 118 as Figure 1 An alternative to the planar structure shown. By using the HKMG structure in the transistor in the low voltage region 102, the transistor capacitance (and thus the drive current) is increased, and the gate leakage and threshold voltage are reduced. In some embodiments, the low voltage gate electrode 118 may include a core metal layer such as copper (Cu), tungsten (W) or aluminum (Al) or an alloy thereof and a barrier layer such as titanium (Ti), tantalum (Ta), zirconium (Zr) or an alloy thereof. In some embodiments, the low voltage gate dielectric layer 120 includes a high-k dielectric material with a dielectric constant greater than 3.9. Examples of the low voltage gate dielectric layer 120 may be hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO) or hafnium tantalum oxide (HfTaO).

[0026] The medium voltage transistor device 1206 is arranged in the medium voltage region 103. The high voltage transistor device 142 is arranged in the high voltage region 104. The high voltage transistor device 142 has a high voltage gate electrode 122, which is arranged above the high voltage gate dielectric layer 124 between the second pair of source / drain regions 144b. The high voltage transistor device 142 is configured to operate at an operating voltage greater than the low voltage transistor device 140. In some embodiments, the high voltage gate electrode 122 includes polysilicon. In some other embodiments, the high voltage gate electrode 122 can be made of a metal or metal alloy material. The high voltage gate electrode 122 can have a gate length and a gate width greater than the low voltage gate electrode 118. The high voltage gate electrode 122 can be recessed in the substrate 106. In some embodiments, the high voltage gate electrode 122 can include a polysilicon material. In applications, the second transistor can be a driver transistor, a power transistor. The second transistor can be an LDMOS (laterally diffused metal oxide semiconductor) transistor designed for low on-resistance and high blocking voltage. The source / drain region 144b is arranged side by side with the high voltage gate electrode 122 and may be asymmetric. The thickness of the high voltage gate dielectric layer 124 may be greater than the thickness of the low voltage gate dielectric layer 120. In some embodiments, the thickness of the high voltage gate dielectric layer 124 is about 2 to 5 times the thickness of the low voltage gate dielectric layer 120, so that the high voltage gate dielectric layer 124 can support a larger breakdown voltage. For example, the thickness of the low voltage gate dielectric layer 120 may be about 30 angstroms. In the range of about 100 angstroms, the thickness of the high-voltage gate dielectric layer 124 can be in the range of about 150 angstroms to about 400 angstroms. It is understood that these dimensions and other dimensions discussed herein can be scaled for different process nodes. In some embodiments, the medium-voltage transistor device 1206 can have a structure similar to the high-voltage transistor device 142, but with a smaller size. The high-voltage transistor device 142 can be used to drive a memory cell and can have a relatively high operating voltage level (e.g., greater than 10V). The medium-voltage transistor device 1206 can be, for example, an RF (radio frequency) device or a MIM (metal-insulator-metal) device and can have an operating voltage level (e.g., about 6-10V) smaller than that of the high-voltage device. The low-voltage transistor device 140 can have an operating voltage level less than the medium-voltage transistor device 1206, and can be a core device with an operating voltage level less than 1.5V or about 0.9-1.1V, a word line device with an operating voltage level of about 1V to 2V, or an I / O (input and output) device with an operating voltage level of about 1.5V to 3V. In some embodiments, the gate shielding structure layer 128 may be disposed over the substrate 106 at a peripheral region of the high voltage gate electrode 122. A sacrificial dielectric layer 126 may be disposed between the gate shielding structure layer 128 and the substrate 106.

[0027] In the boundary region 130, an isolation structure 108 (such as a shallow trench isolation (STI) structure or a deep trench isolation (DTI) structure) is disposed in an upper portion of the substrate 106. The isolation structure 108 may protrude from the substrate 106 and have a top surface located higher than the upper surface of the substrate 106. The first polysilicon component 112 may be disposed on the upper surface of the substrate 106, adjacent to the isolation structure 108. The boundary dielectric layer 110 may be disposed directly on the top surface of the isolation structure 108. The second polysilicon component 114 may be disposed directly on the boundary dielectric layer 110. In some embodiments, the boundary dielectric layer 110 may be a continuous portion of the sacrificial dielectric layer 126, and therefore, the boundary dielectric layer 110 may be made of the same material and have the same thickness as the sacrificial dielectric layer 126 in the high voltage region 104. In some embodiments, the first polysilicon component 112 and the second polysilicon component 114 may be made of the same material. The first polysilicon component 112 or the second polysilicon component 114 may include pure polysilicon or very lightly doped polysilicon. In some embodiments, the boundary dielectric layer 110 may include an oxide material, such as silicon dioxide.

[0028] Still within the boundary region 130, the first polysilicon component 112 may have a continuous flat top surface. In some embodiments, the top surface of the second polysilicon component 114 may include a first flat portion 132 and a second flat portion 134. The first flat portion 132 is closer to the low pressure region 102, and the second flat portion 134 is closer to the high pressure region 104. In the illustrated embodiment, the first flat portion 132 is positioned lower than the second flat portion 134 relative to the substrate 106. In some embodiments, the first flat portion 132 and the second flat portion 134 may have substantially the same lateral length. The maximum thickness of the second polysilicon component 114 may be equal to the maximum thickness of the first polysilicon component 112. The thickness of the second polysilicon component 114 may also be greater than or less than the thickness of the first polysilicon component 112. In some embodiments, the second polysilicon component 114 and the boundary dielectric layer 110 may be disposed on a portion of the top surface of the isolation structure 108 closer to the low voltage region 102, while leaving the remaining portion of the top surface of the isolation structure 108 closer to the high voltage region 104 without the boundary dielectric layer 110. In some alternative embodiments, the second polysilicon component 114 and the boundary dielectric layer 110 may cover the entire top surface of the isolation structure 108 in the boundary region 130.

[0029] In some embodiments, a first interlayer dielectric (ILD) layer 136 is disposed around the low voltage transistor device 140, the high voltage transistor device 142, and the boundary structure 150. A second interlayer dielectric (ILD) layer 138 may be disposed above the first interlayer dielectric (ILD) layer 136. The first interlayer dielectric (ILD) layer 136 and / or the second interlayer dielectric (ILD) layer 138 may include the same or different low-k dielectric layers, ultra-low-k dielectric layers, extremely low-k dielectric layers, and / or silicon dioxide layers. One or more of the plurality of contact structures may extend through the first interlayer dielectric (ILD) layer 136 and be coupled to the source / drain region. In some embodiments, the plurality of contact structures 152 may include metals such as tungsten, copper, and / or aluminum.

[0030] In some embodiments, the low voltage gate electrode 118 and the second polysilicon component 114 may have aligned top surfaces. The top surface of the high voltage gate electrode 122 may be lower than the surface of the low voltage gate electrode 118 or the second polysilicon component 114. In some embodiments, the gate shielding structure layer 128 may have a top surface aligned with the low voltage gate electrode 118 or the second polysilicon component 114.

[0031] Figure 9-Figure 26 A series of cross-sectional views 900 - 2600 illustrate some embodiments of methods for fabricating an IC including a boundary structure disposed between a low voltage region and a medium voltage region or a high voltage region.

[0032] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , in some embodiments, a substrate 106 including a low voltage region 102, a medium voltage region 103, and a high voltage region 104 is provided. In various embodiments, the substrate 106 may include any type of semiconductor body (e.g., silicon / CMOS block, SiGe, SOI, etc.) such as a semiconductor wafer or one or more dies on a wafer, as well as any other type of semiconductor material. In some embodiments, an isolation structure 108 may be formed within the substrate 106. The isolation structure 108 may be formed by selectively etching the substrate 106 to form a trench defined by the sidewalls of the substrate 106. The trench is then filled with one or more dielectric materials, such as silicon dioxide, to form the isolation structure 108.

[0033] like Fig.10 As shown in the cross-sectional view 1000 of FIG. 1 , in some embodiments, a plurality of trenches 1002, 1004 are formed in the upper region of the substrate 106 as gate trenches in the medium voltage region 103 and the high voltage region 104. The trenches 1002, 1004 may be formed by one or more photolithography processes and subsequently one or more etching processes of the substrate 106 between the isolation structures 108. The depth of the trenches 1002 in the medium voltage region 103 may be less than the depth of the trenches 1004 in the high voltage region 104.

[0034] The depth of the trenches 1002, 1104 may have a depth in a range of, for example, between about 70 nanometers and about 150 nanometers. Although not shown in the figure, the substrate 106 may then be ion implanted to form doped regions (e.g., n-type or p-type) between the isolation structures 108, as device wells, source / drain regions, and other doped structures.

[0035] like Fig.11 As shown in the cross-sectional view 1100 of , in some embodiments, a medium voltage dielectric layer 1102 and a high voltage gate dielectric layer 124 are formed along the trenches 1002 and 1004. The medium voltage dielectric layer 1102 and the high voltage gate dielectric layer 124 can be formed by different thermal treatments or deposition processes combined with patterning processes, and can be formed with different thicknesses. The thickness of the high voltage gate dielectric layer 124 can be about 2 to 5 times the thickness of the medium voltage dielectric layer 1102. The medium voltage dielectric layer 1102 and the high voltage gate dielectric layer 124 can be oxide layers, such as silicon dioxide layers, but other suitable gate dielectric materials are also applicable. The thickness of the medium voltage dielectric layer 1102 and the high voltage gate dielectric layer 124 depends on the application, ranging from about a few nanometers (nm) or tens of nanometers at current nodes to a few angstroms at emerging nodes.

[0036] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , in some embodiments, the medium voltage gate electrode 1202 and the high voltage gate electrode 122 are respectively formed on the medium voltage dielectric layer 1102 and the high voltage gate dielectric layer 124, using a mask layer 1204 and filling the spaces of the trenches 1002 and 1004, thereby forming a medium voltage transistor device 1206 and a high voltage transistor device 142. The medium voltage gate electrode 1202 and the high voltage gate electrode 122 are formed by one or more deposition processes (e.g., chemical vapor deposition, physical vapor deposition, etc.). The medium voltage gate electrode 1202 and the high voltage gate electrode 122 can be made of doped polysilicon.

[0037] like Fig.13As shown in the cross-sectional view 1300 of FIG. 1300 , in some embodiments, a first support layer 202 is formed above the medium voltage transistor device 1206 and the high voltage transistor device 142. In some embodiments, the first support layer 202 includes a stack of different materials formed by a deposition technique. For example, the first support layer 202 may include a stack of CMP protective layers disposed above a sacrificial dielectric layer 126 (e.g., a sacrificial silicon dioxide layer). Examples of such a stack of CMP protective layers may include a gate masking structure layer 128 (e.g., a silicon nitride layer) and a thin polysilicon liner 1302. A stack of hard mask layers may be deposited above the stack of CMP protective layers. Examples of such a stack of hard mask layers may include a first thin dielectric liner 1304 (e.g., a silicon nitride liner) and a second dielectric layer 1306 (e.g., a silicon dioxide liner) disposed above the first thin dielectric liner 1304 (e.g., a silicon nitride liner). The first supporting layer 202 may further include a first polysilicon layer 1308 disposed over the stack of hard mask layers and configured to define a desired height of the first supporting layer 202 .

[0038] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1402 , in some embodiments, the first support layer 202 is patterned to be removed from the low voltage region 102 by a series of dry etching processes using the mask layer 1402 . In some embodiments, the sacrificial dielectric layer 126 may remain in the low voltage region 102 .

[0039] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , in some embodiments, the second supporting layer 204 is formed over the substrate 106 in the low pressure region 102 and over the first supporting layer 202 in the medium pressure region 103 and the high pressure region 104. In some embodiments, the second supporting layer 204 may include a second polysilicon layer and is deposited to a designed thickness to define a tilt angle of the tilted sidewall after an etch-back process discussed below.

[0040] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 16A , in some embodiments, the second support layer 204 is etched back to be removed from the low pressure region 102, and the first support layer 202 and the second support layer 204 together define a continuous and inclined sidewall 204s. In some embodiments, a series of blanket etching processes are performed on the first support layer 202 and the second support layer 204. The etching process may include dry etching (e.g., plasma etching using tetrafluoromethane (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), etc.). The inclined sidewall 204s is inclined from the bottom to the top toward the high pressure region 104, and may have an inclination angle α substantially equal to 45 degrees or in a range between about 30 degrees and about 45 degrees. In some embodiments, the inclination angle α is in a range of 40 degrees to 50 degrees.

[0041] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 17 , in some embodiments, a low voltage gate precursor layer 1702 is formed over the substrate 106 in the low voltage region 102 and over the second support layer 204 in the medium voltage region 103 and the high voltage region 104. In some embodiments, the low voltage gate precursor layer 1702 may include a low voltage gate dielectric layer 120 (e.g., an interface layer (IL), a high-k dielectric layer, and a barrier layer (e.g., titanium nitride) stacked in sequence), a low voltage gate electrode layer 118', and a hard mask layer (e.g., a silicon dioxide layer 1706 stacked on a silicon nitride liner 1704 or one or more stacked silicon nitride and silicon dioxide layers).

[0042] like Fig.18 As shown in the cross-sectional view 1800 of FIG. 1 , in some embodiments, the low voltage gate precursor layer 1702 is patterned to be removed from the medium voltage region 103 and the high voltage region 104, and a modified low voltage gate precursor layer 1702' is left in the low voltage region 102. The low voltage gate precursor layer 1702 is completely removed from the boundary region due to the continuous and inclined sidewalls. Therefore, contamination from the residue of the low voltage gate precursor layer 1702 is minimized.

[0043] like Fig.19 As shown in the cross-sectional view 1900 of FIG. 1 , in some embodiments, a sealing process is performed to protect the sidewalls of the modified low voltage gate precursor layer 1702′ in the low voltage region 102. The sealing layer 1902 may include a silicon nitride liner and may be deposited on the sidewalls of the modified low voltage gate precursor layer 1702 by a conformal deposition technique (e.g., CVD), followed by a dry etching process to remove from the side and inclined surfaces.

[0044] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 2001 , in some embodiments, a boundary filling process is performed to fill the gap between the low voltage region 102 and the medium voltage region 103. In some embodiments, a polysilicon layer 2002 is deposited on the changed low voltage gate precursor layer 1702' and the second support layer 204. The polysilicon layer 2002 can be conformally formed and can be formed by a chemical vapor deposition (CVD) process, so that the gap between the low voltage region 102 and the medium voltage region 103 can be well filled. A filling layer 2004 (for example, made of a photoresist material) can then be coated or spin-coated to form a flat top surface.

[0045] like Fig.21 As shown in the cross-sectional view 2100 of FIG. 21 , in some embodiments, an etch-back process is performed to remove the second support layer 204 and some upper layers of the first support layer 202. At the same time, the polysilicon layer 2002 is etched back to a position laterally aligned with the remaining portion of the first support layer 202'.

[0046] like Fig. 22 As shown in the cross-sectional view 2200 of , in some embodiments, the altered low voltage gate precursor layer 1702' is patterned to form a low voltage gate stack 1702", which includes a low voltage gate dielectric layer 120 and a polysilicon gate electrode 118". At the same time, the remaining portion of the first support layer 202' is patterned to form discrete portions 2202a, 2202b covering the medium voltage transistor device 1206 and the high voltage transistor device 142, respectively. A pair of source / drain regions 144a can be formed in the substrate 106, located on opposite sides of the low voltage gate stack 1702". A boundary structure 150 is formed between the low voltage region 102 and the medium voltage region 103.

[0047] like Fig.23 As shown in the cross-sectional view 2300 of FIG. 2300 , in some embodiments, the first ILD layer 136 is formed around the low voltage transistor device 140. The first ILD layer 136 can be formed over the low voltage transistor device 140, the medium voltage transistor device 1206, and the high voltage transistor device 142, and then a planarization process is performed. The planarization process may include a chemical mechanical polishing (CMP) process. The gate masking structure layer 128 may be exposed after the planarization process.

[0048] like Fig.24 As shown in the cross-sectional view 2400 of , in some embodiments, a replacement gate process may then be performed to form a low voltage gate electrode 118 by replacing the polysilicon gate electrode 118" with a metal material. A series of deposition and etching processes may be performed to form different metal compositions for different devices or different components of the same device to achieve desired working functions.

[0049] like Fig.25 As shown in the cross-sectional view 2500 of FIG. 25, in some embodiments, the second ILD layer 138 is formed above the first ILD layer 136. In some embodiments, the discrete portions 2202a, 2202b of the remaining portion of the first support layer 202' can be patterned before forming the second ILD layer 138 to form exposed gate electrodes 1202, 122 (see FIG. Figure 21 to Figure 22 A silicide layer 2502 may be formed on the exposed surfaces of the gate electrodes 1202 and 122. The second ILD layer 138 may also fill the openings formed before the gate electrodes 1202 and 122 and cover the gate electrodes.

[0050] like Fig.26As shown in the cross-sectional view 2600 of FIG. 26 , in some embodiments, the contact structure 152 is formed to pass through the second ILD layer 138 to reach the upper surface of the gate electrode 1202, 122. The contact structure 152 can be formed by selectively etching the second ILD layer 138 and / or the first ILD layer 136 to form an opening (e.g., with a patterned photoresist mask in place), and then by depositing a conductive material in the opening. In some embodiments, for example, the conductive material may include tungsten (W) or titanium nitride (TiN).

[0051] Fig. 27 A flow chart illustrating some embodiments of a method 2700 for fabricating an IC including a boundary structure between a low voltage region and a high voltage region.

[0052] Although Figures 9 to 26 Describe method 2700, but it will be understood that method 2700 is not limited to such a structure, but can exist separately as a method independent of the structure. In addition, although the disclosed method (e.g., method 2700) is shown and described as a series of steps or events herein, it should be understood that the order of these steps or events shown should not be interpreted as limiting. For example, some steps may occur in different orders and / or occur simultaneously with other steps or events other than the steps or events shown and / or described herein. In addition, it is not required that all the steps shown are used to implement one or more aspects or embodiments described herein. In addition, one or more of the steps described herein may be performed in one or more separated steps and / or stages.

[0053] At 2702, a substrate including a low-pressure region and a high-pressure region is provided. In some embodiments, an isolation structure can be formed within the substrate between the low-pressure region and the high-pressure region. Fig. 9 Some embodiments of the cross-sectional view 900 corresponding to step 2702 are shown.

[0054] At 2704, a trench is formed in an upper region of the substrate to serve as a gate trench in the high voltage region. Fig.10 Some embodiments of the cross-sectional view 1000 corresponding to step 2704 are shown.

[0055] At 2706, a high voltage gate dielectric layer is formed along the trench. A high voltage gate electrode is then formed on the high voltage gate dielectric layer filling the space of the gate trench. Figure 11-Figure 12 Some embodiments of cross-sectional views 1100 , 1200 corresponding to step 2706 are shown.

[0056] At 2708, a first supporting layer is formed and patterned to be removed from the low pressure areas and to remain in the high pressure areas. Figure 13-Figure 14Some embodiments of cross-sectional views 1300 , 1400 corresponding to step 2708 are shown.

[0057] At 2710, a second supporting layer is formed and patterned to be removed from the low pressure region and to remain over the first supporting layer in the high pressure region. The first and second supporting layers together define a continuous and sloped sidewall. Figure 15-16 Some embodiments of cross-sectional views 1500 , 1600 corresponding to step 2710 are shown.

[0058] At 2712, a low voltage gate precursor layer is formed over the substrate in the low voltage region and over the second support layer in the high voltage region. The low voltage gate precursor layer is then patterned to be removed from the high voltage region and leave the patterned low voltage gate precursor layer in the low voltage region. The low voltage gate precursor layer 1702 is completely removed from the boundary region due to the continuous and sloped sidewalls. Figure 17-Figure 18 Some embodiments of cross-sectional views 1700 , 1800 corresponding to step 2712 are shown.

[0059] At 2714, a gate dielectric and a gate electrode are patterned to form a low voltage device. A boundary structure is formed between the low voltage region and the high voltage region. Figure 19-22 Some embodiments of cross-sectional views 1900 - 2200 corresponding to step 2714 are shown.

[0060] At 2716 , in some embodiments, a replacement gate process may then be performed by replacing the gate electrode with a metallic material. Figure 23-Figure 24 Some embodiments of cross-sectional views 2300 , 2400 corresponding to step 2716 are shown.

[0061] At 2718, a silicide layer and contact structure are formed. Figure 25-26 Some embodiments of cross-sectional views 2500 , 2600 corresponding to step 2718 are shown.

[0062] Fig.28 A flow chart illustrating some alternative embodiments of a method 2800 for fabricating an IC including a boundary structure between a low voltage region and a high voltage region.

[0063] Although Figure 2-Figure 8Describe method 2800, but it will be understood that method 2800 is not limited to such a structure, but can exist separately as a method independent of the structure. In addition, although the disclosed method (e.g., method 2800) is shown and described as a series of steps or events herein, it should be understood that the order of these steps or events shown should not be interpreted as limiting. For example, some steps may occur in different orders and / or occur simultaneously with other steps or events other than the steps or events shown and / or described herein. In addition, it is not required that all the steps shown are used to implement one or more aspects or embodiments described herein. In addition, one or more of the steps described herein may be performed in one or more separated steps and / or stages.

[0064] At 2802, a substrate including a low-voltage region and a high-voltage region is provided. In some embodiments, an isolation structure can be formed in the substrate between the low-voltage region and the high-voltage region. A first support layer is then formed above the high-voltage transistor device in the high-voltage region. A second support layer is formed above the first support layer in the high-voltage region so that its height is different from the lower portion in the low-voltage region. Figure 2 Some embodiments of the cross-sectional view 200 corresponding to step 2802 are shown.

[0065] At 2804, an etching process is performed to form an inclined sidewall. The inclined sidewall 204s is inclined from the bottom to the top toward the high voltage region and may have an inclination angle α substantially equal to 45 degrees or in a range between about 30 degrees and about 45 degrees. Figure 3 Some embodiments of the cross-sectional view 300 corresponding to step 2804 are shown.

[0066] At 2806, a stack of low voltage gate precursor layers is formed over the substrate in the low voltage region and on the second support layer in the high voltage region. The low voltage gate precursor layer may include a low voltage gate electrode layer, a low voltage gate dielectric layer, and a masking layer. Then, the low voltage gate precursor layer is patterned to be removed from the high voltage region and leave a changed low voltage gate precursor layer in the low voltage region. The low voltage gate precursor layer is completely removed from the boundary region due to the continuous and inclined sidewalls. Figure 4-Figure 5 Some embodiments of cross-sectional views 400 , 500 corresponding to step 2806 are shown.

[0067] At 2808, a boundary filling process is performed to fill the gap between the low pressure region and the high pressure region. In some embodiments, a conformal layer and a filling layer are formed to fill the gap. Figure 6 Some embodiments of the cross-sectional view 600 corresponding to step 2808 are shown.

[0068] At 2810, a patterning process is performed to form a low voltage transistor device in the low voltage region, a boundary structure in the boundary region, and a gate masking structure layer in the high voltage region. A pair of source / drain regions may be formed in the substrate on opposite sides of the low voltage gate stack. Figure 7 Some embodiments of the cross-sectional view 700 corresponding to step 2810 are shown.

[0069] At 2812, an ILD layer is formed over the low voltage transistor device in the low voltage region, over the boundary structure in the boundary region, and over the gate masking structure layer in the high voltage region. Contact structures are formed through the ILD layer to the low voltage transistor device and the high voltage transistor device. Figure 8 Some embodiments of a cross-sectional view 800 corresponding to step 2812 are shown.

[0070] Therefore, the present disclosure relates to an integrated circuit (IC) including a boundary structure defining a boundary region between a low voltage region and a high voltage region, and a forming method, providing small scale and high performance, and a forming method.

[0071] In some embodiments, the present invention relates to an integrated circuit. The integrated circuit includes a substrate, the substrate including a low voltage region, a high voltage region, and a boundary region defined between the low voltage region and the high voltage region. An isolation structure is disposed in the boundary region of the substrate. A first polysilicon component is disposed side by side with the isolation structure above the substrate. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrificial dielectric layer.

[0072] In other embodiments, the present disclosure relates to a method for forming an integrated circuit. The method includes providing a substrate, the substrate including a low-voltage region, a high-voltage region, and a boundary region defined between the low-voltage region and the high-voltage region. A support layer is formed above the substrate in the high-voltage region. The support layer has an inclined sidewall in the boundary region, and the inclined sidewall is inclined from bottom to top toward the high-voltage region. A stack of low-voltage gate precursor layers is formed above the substrate in the low-voltage region and on the support layer in the high-voltage region. The stack of low-voltage gate precursor layers is patterned to form a changed low-voltage gate precursor layer in the low-voltage region. When the changed low-voltage gate precursor layer is formed, the stack of low-voltage gate precursor layers is removed from the boundary region and the high-voltage region.

[0073] In yet another embodiment, the present disclosure relates to a method for forming an integrated circuit. The method includes providing a substrate, the substrate including a low-voltage region, a high-voltage region, and a boundary region defined between the low-voltage region and the high-voltage region. A first supporting layer is formed above the substrate in the high-voltage region and is patterned. A second supporting layer is formed above the substrate in the low-voltage region and is formed on the first supporting layer in the high-voltage region. An etching process is performed on the second supporting layer and the first supporting layer to remove the second supporting layer from the low-voltage region and to form an inclined sidewall in the boundary region. A stack of low-voltage gate precursor layers is formed above the substrate in the low-voltage region and above the first supporting layer in the high-voltage region. The stack of low-voltage gate precursor layers is patterned to form a low-voltage transistor device in the low-voltage region.

[0074] According to one embodiment of the present application, an integrated circuit (IC) is provided, comprising: a substrate, comprising a low voltage region, a high voltage region, and a boundary region defined between the low voltage region and the high voltage region; an isolation structure, arranged in the boundary region of the substrate; a first polysilicon component, arranged side by side with the isolation structure above the substrate; a boundary dielectric layer, arranged on the isolation structure; and a second polysilicon component, arranged on the boundary dielectric layer. The above integrated circuit also includes: a first transistor device, arranged in the low voltage region, and having a first gate electrode arranged above the first gate dielectric layer; a second transistor device, arranged in the high voltage region, and having a second gate electrode arranged above the second gate dielectric layer, the second transistor device being configured to operate at an operating voltage greater than the first transistor device. The above integrated circuit also includes: a gate shielding structure, arranged at a peripheral region of the second gate electrode, wherein the top surface of the gate shielding structure is coplanar with the top surface of the second polysilicon component. The above integrated circuit also includes: a sacrificial dielectric layer, arranged between the gate shielding structure and the substrate; wherein the boundary dielectric layer is a continuous portion of the sacrificial dielectric layer, and wherein the boundary dielectric layer is made of the same material as the sacrificial dielectric layer in the high voltage region and has the same thickness. In some embodiments, the first gate electrode includes a metal gate electrode, and the sidewalls and bottom surface of the metal gate electrode are covered by a high-k dielectric layer. In some embodiments, the second gate electrode is grooved to a lower position compared to the top surface of the substrate. In some embodiments, the top surface of the first gate electrode is coplanar with the top surface of the second polysilicon component. In some embodiments, the second polysilicon component includes: a first flat upper surface closer to the low voltage region and a second flat upper surface closer to the high voltage region, wherein the first flat upper surface is located at a lower position than the second flat upper surface relative to the substrate. In some embodiments, the integrated circuit also includes a first interlayer dielectric (ILD) layer, the first interlayer dielectric layer is disposed above the first polysilicon component and has a top surface aligned with the top surface of the second polysilicon component. In some embodiments, the second polysilicon component and the boundary dielectric layer are disposed on a portion of the top surface of the isolation structure closer to the low voltage region, while leaving the boundary dielectric layer absent from the remaining portion of the top surface of the isolation structure closer to the high voltage region.

[0075] According to another embodiment of the present application, a method for forming an integrated circuit (IC) is provided, comprising: providing a substrate, comprising a low voltage region, a high voltage region, and a boundary region defined between the low voltage region and the high voltage region; forming a support layer above the substrate in the high voltage region, wherein the support layer has an inclined sidewall in the boundary region, and the inclined sidewall is inclined from bottom to top toward the high voltage region; forming a stack of low voltage gate precursor layers above the substrate in the low voltage region and on the support layer in the high voltage region; and patterning the stack of low voltage gate precursor layers to form a changed low voltage gate precursor layer in the low voltage region; wherein when the changed low voltage gate precursor layer is formed, the stack of low voltage gate precursor layers is removed from the boundary region and the high voltage region. In some embodiments, the stack of low voltage gate precursor layers is formed by at least depositing a low voltage gate dielectric layer, depositing a low voltage gate electrode layer above the low voltage gate dielectric layer, and depositing a masking layer above the low voltage gate electrode layer. In some embodiments, the inclined sidewall has an inclination angle in the range of 40 degrees to 50 degrees. In some embodiments, forming a support layer includes: forming and patterning a first support layer in a high voltage region; forming a second support layer in a low voltage region over the substrate and over the first support layer in the high voltage region; and performing an etch back process to remove an upper portion of the second support layer, and forming an inclined sidewall by a lower portion of the second support layer and the first support layer. In some embodiments, wherein a high voltage device is formed in the high voltage region before forming the support layer; and wherein the support layer is etched and patterned so that the lower portion covers and protects the high voltage device. In some embodiments, the method of forming an integrated circuit also includes: forming a conformal layer and a filling layer in a gap in a boundary region between the altered low voltage gate precursor layer and the inclined sidewall of the support layer; performing an etch back process on the filling layer and the conformal layer; and performing a patterning process to form a low voltage transistor device in the low voltage region, and forming a boundary structure in the boundary region.

[0076] According to another embodiment of the present application, a method for forming an integrated circuit (IC) is provided, comprising: providing a substrate, comprising a low voltage region, a high voltage region, and a boundary region defined between the low voltage region and the high voltage region; forming and patterning a first support layer over the substrate in the high voltage region; forming a second support layer over the substrate in the low voltage region and on the first support layer in the high voltage region; performing an etching process on the second support layer and the first support layer to remove the second support layer from the low voltage region and form an inclined sidewall in the boundary region; and forming a stack of low voltage gate precursor layers over the substrate in the low voltage region and over the first support layer in the high voltage region; and patterning the stack of low voltage gate precursor layers to form a low voltage transistor device in the low voltage region. In some embodiments, the stack of low voltage gate precursor layers comprises a high k dielectric layer disposed over the substrate and a polysilicon gate electrode layer disposed over the high k dielectric layer. In some embodiments, the method for forming an integrated circuit further comprises: removing the polysilicon gate electrode layer and replacing it with a metal gate electrode. In some embodiments, the first supporting layer is formed by depositing a gate shielding structure layer over the substrate, depositing a hard mask layer over the gate shielding structure layer, and depositing a first polysilicon layer over the hard mask layer.

[0077] The parts of several embodiments are discussed above so that those skilled in the art can better understand the various embodiments of the present invention. Those skilled in the art should understand that it is easy to use this disclosure as a basis to design or change other processes and structures for achieving the same purpose and / or achieving the same advantages as the embodiments introduced here. Those skilled in the art should also appreciate that these equivalent structures do not deviate from the spirit and scope of the present invention, and can make various changes, substitutions and changes without deviating from the spirit and scope of the present invention.

Claims

1. An integrated circuit, comprising: A substrate comprising a low pressure region, a high pressure region, and a boundary region defined between the low pressure region and the high pressure region; An isolation structure, disposed in a boundary region of the substrate; A first polysilicon component is disposed above the substrate in parallel with the isolation structure; a boundary dielectric layer, disposed on the isolation structure; as well as A second polysilicon component is disposed on the boundary dielectric layer, and the second polysilicon component includes a first flat upper surface closer to the low-voltage region and a second flat upper surface closer to the high-voltage region, wherein the first flat upper surface is located at a lower position than the second flat upper surface relative to the substrate.

2. The integrated circuit of claim 1 , further comprising: a first transistor device disposed in the low voltage region and having a first gate electrode disposed above a first gate dielectric layer; A second transistor device is disposed in the high voltage region and has a second gate electrode disposed over a second gate dielectric layer, the second transistor device being configured to operate at an operating voltage greater than that of the first transistor device.

3. The integrated circuit of claim 2, further comprising: A gate shielding structure is disposed at a peripheral region of the second gate electrode, wherein a top surface of the gate shielding structure is coplanar with a top surface of the second polysilicon component.

4. The integrated circuit of claim 3, further comprising: a sacrificial dielectric layer disposed between the gate shielding structure and the substrate; wherein the boundary dielectric layer is a continuous portion of the sacrificial dielectric layer, and wherein the boundary dielectric layer is made of the same material and has the same thickness as the sacrificial dielectric layer in the high voltage region.

5. The integrated circuit according to claim 2, wherein: The first gate electrode comprises a metal gate electrode, and a sidewall and a bottom surface of the metal gate electrode are covered by a high-k dielectric layer.

6. The integrated circuit according to claim 2, wherein: The second gate electrode is recessed to a lower position compared to a top surface of the substrate.

7. The integrated circuit according to claim 2, wherein: A top surface of the first gate electrode is coplanar with a top surface of the second polysilicon component.

8. The integrated circuit of claim 1, wherein: The boundary dielectric layer includes silicon dioxide. 9 . The integrated circuit of claim 1 , further comprising a first interlayer dielectric layer disposed over the first polysilicon component and having a top surface aligned with a top surface of the second polysilicon component.

10. The integrated circuit of claim 1, wherein: The second polysilicon component and the boundary dielectric layer are disposed on a portion of the top surface of the isolation structure closer to the low voltage region, while the boundary dielectric layer is absent from a remaining portion of the top surface of the isolation structure closer to the high voltage region.

11. A method of forming an integrated circuit, comprising: Providing a substrate, comprising a low-pressure region, a high-pressure region, and a boundary region defined between the low-pressure region and the high-pressure region; forming a support layer above the substrate in the high voltage region, wherein the support layer has an inclined sidewall in the boundary region, the inclined sidewall being inclined toward the high voltage region from bottom to top; forming a stack of low voltage gate precursor layers over the substrate in the low voltage region; forming a conformal layer and a filling layer, the conformal layer and the filling layer including a low-voltage region portion above the stack of the low-voltage gate precursor layers, a high-voltage region portion above the support layer, and a boundary region portion filling in a slit of the boundary region between the stack of the low-voltage gate precursor layers and the inclined sidewall of the support layer; An etch-back process is performed on the filling layer and the conformal layer to expose an upper surface of the stack of low voltage gate precursor layers and leave a portion of the boundary region having a reduced height.

12. The method according to claim 11, wherein: The stack of low voltage gate precursor layers is formed by at least depositing a low voltage gate dielectric layer, depositing a low voltage gate electrode layer over the low voltage gate dielectric layer, and depositing a masking layer over the low voltage gate electrode layer.

13. The method according to claim 11, wherein: The inclined side wall has an inclination angle in the range of 40 degrees to 50 degrees.

14. The method according to claim 11, wherein: Forming the support layer comprises: forming and patterning a first support layer in the high voltage region; forming a second supporting layer over the substrate in the low pressure region and over the first supporting layer in the high pressure region; and An etch-back process is performed to remove an upper portion of the second supporting layer, and to form an inclined sidewall together with a lower portion of the second supporting layer and the first supporting layer.

15. The method according to claim 11, in, forming a high voltage device in the high voltage region before forming the supporting layer; and The supporting layer is etched and patterned so that the lower portion covers and protects the high-voltage device.

16. The method according to claim 11, further comprising: A patterning process is performed on the stack of the low voltage gate precursor layers and the reduced height portion of the boundary region to form a low voltage transistor device in the low voltage region and to form a boundary structure in the boundary region.

17. A method of forming an integrated circuit, comprising: Providing a substrate, comprising a low-pressure region, a high-pressure region, and a boundary region defined between the low-pressure region and the high-pressure region; forming and patterning a first support layer over the substrate in the high voltage region; forming a second supporting layer over the substrate in the low pressure region and on the first supporting layer in the high pressure region; performing an etching process on the second supporting layer and the first supporting layer to remove the second supporting layer from the low pressure region and form an inclined sidewall in the boundary region; and forming a stack of low voltage gate precursor layers over the substrate in the low voltage region and over the first supporting layer in the high voltage region; as well as The stack of low voltage gate precursor layers is patterned to form a low voltage transistor device in the low voltage region.

18. The method according to claim 17, wherein: The stack of low voltage gate precursor layers includes a high-k dielectric layer disposed over the substrate and a polysilicon gate electrode layer disposed over the high-k dielectric layer.

19. The method according to claim 18, further comprising: The polysilicon gate electrode layer is removed and replaced with a metal gate electrode.

20. The method according to claim 17, wherein: The first supporting layer is formed by depositing a gate shielding structure layer over the substrate, depositing a hard mask layer over the gate shielding structure layer, and depositing a first polysilicon layer over the hard mask layer.

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