Display device

Abstract

The present disclosure relates to a display device. According to one embodiment, the display device includes: a substrate; a polycrystalline semiconductor, including a channel, a first electrode and a second electrode of a driving transistor located on the substrate; a gate electrode of the driving transistor, located on the channel of the driving transistor; a first maintaining electrode, located on the gate electrode of the driving transistor; a light blocking layer of a third transistor and a light blocking layer of a seventh transistor, located on the substrate; an oxide semiconductor, including a channel, a first electrode, a second electrode of a third transistor and a channel, a first electrode and a second electrode of a seventh transistor, wherein the channel, the first electrode and the second electrode of the third transistor are located on the light blocking layer of the third transistor, and the channel, the first electrode and the second electrode of the seventh transistor are located on the light blocking layer of the seventh transistor; the gate electrode of the third transistor is located on the channel of the third transistor; and the gate electrode of the seventh transistor is located on the channel of the seventh transistor.

Description

Technical Field

[0001] The invention relates to a display device. Background Art

[0002] An organic light-emitting display device includes two electrodes and an organic light-emitting layer located therebetween. Electrons injected from one electrode and holes injected from the other electrode combine in the organic light-emitting layer to form excitons. The excitons change from an excited state to a ground state and emit energy to emit light.

[0003] Such an organic light emitting display device includes a plurality of pixels including an organic light emitting diode as a self-luminous element, and each pixel is formed with a plurality of transistors for driving the organic light emitting diode and one or more capacitors. The plurality of transistors basically include a switching transistor and a driving transistor.

[0004] In order to improve the resolution of the organic light-emitting display device and increase the number of pixels, in order to achieve stable video, the aperture ratio may be reduced, the current density may be increased, and the driving voltage may be increased during high-speed driving. As a result, there are problems such as spots and reduced reliability of components such as transistors. Summary of the invention

[0005] The embodiment is to stably drive a display device, enhance reliability, and improve power consumption.

[0006] According to one embodiment, a display device includes: a substrate; a polycrystalline semiconductor including a channel, a first electrode and a second electrode of a driving transistor located on the substrate; a gate electrode of the driving transistor located on the channel of the driving transistor; a first sustaining electrode located on the gate electrode of the driving transistor; a light blocking layer of a third transistor and a light blocking layer of a seventh transistor located on the substrate; an oxide semiconductor including a channel, a first electrode, a second electrode of a third transistor and a channel, a first electrode and a second electrode of a seventh transistor, wherein the channel, the first electrode and the second electrode of the third transistor are located on the light blocking layer of the third transistor, and the channel, the first electrode and the second electrode of the seventh transistor are located on the light blocking layer of the seventh transistor; a gate electrode of the third transistor located on the channel of the third transistor; and a gate electrode of the seventh transistor located on the channel of the seventh transistor, wherein the light blocking layer of the third transistor and the first sustaining electrode are located on the same layer, and the light blocking layer of the seventh transistor and the gate electrode of the driving transistor are located on the same layer.

[0007] The driving transistor may have p-type transistor characteristics, and the third transistor and the seventh transistor may have n-type transistor characteristics.

[0008] The light blocking layer of the third transistor may overlap with a channel of the third transistor and a gate electrode of the third transistor, and the light blocking layer of the seventh transistor may overlap with a channel of the seventh transistor and a gate electrode of the seventh transistor.

[0009] According to one embodiment, the display device may further include: a first gate insulating film located between the polycrystalline semiconductor and the gate electrode of the driving transistor; a second gate insulating film located between the gate electrode of the driving transistor and the first sustaining electrode; a first interlayer insulating film located between the light blocking layer of the third transistor and the oxide semiconductor, and between the light blocking layer of the seventh transistor and the oxide semiconductor; a third gate insulating film located between the oxide semiconductor and the gate electrode of the third transistor, and between the oxide semiconductor and the gate electrode of the seventh transistor; and a second interlayer insulating film located on the gate electrode of the third transistor and the gate electrode of the seventh transistor.

[0010] The display device according to an embodiment may further include: a connecting electrode connecting the second electrode of the driving transistor and the first electrode of the third transistor.

[0011] According to one embodiment, the display device may further include: a first opening portion, formed on the first gate insulating film, the second gate insulating film, the first interlayer insulating film, the third gate insulating film and the second interlayer insulating film in a manner overlapping with the second electrode of the driving transistor; and a second opening portion, formed on the third gate insulating film and the second interlayer insulating film in a manner overlapping with the first electrode of the third transistor, wherein the connecting electrode may be located on the second interlayer insulating film and may be connected to the second electrode of the driving transistor through the first opening portion, and may be connected to the first electrode of the third transistor through the second opening portion.

[0012] According to one embodiment, a display device includes: a substrate; a polycrystalline semiconductor including a channel, a first electrode and a second electrode of a driving transistor located on the substrate; a gate electrode of the driving transistor located on the channel of the driving transistor; a first sustaining electrode located on the gate electrode of the driving transistor; a light blocking layer of a third transistor and a light blocking layer of a seventh transistor located on the substrate; an oxide semiconductor including a channel, a first electrode, a second electrode of a third transistor and a channel, a first electrode and a second electrode of a seventh transistor, wherein the channel, the first electrode and the second electrode of the third transistor are located on the light blocking layer of the third transistor, and the channel, the first electrode and the second electrode of the seventh transistor are located on the light blocking layer of the seventh transistor; a gate electrode of the third transistor located on the channel of the third transistor; and a gate electrode of the seventh transistor located on the channel of the seventh transistor, wherein an inverted scan signal is applied to the light blocking layer of the third transistor and the gate electrode of the third transistor, and a first light emitting control signal is applied to the light blocking layer of the seventh transistor and the gate electrode of the seventh transistor.

[0013] The driving transistor may have p-type transistor characteristics, and the third transistor and the seventh transistor may have n-type transistor characteristics.

[0014] The light blocking layer of the third transistor may overlap with a channel of the third transistor and a gate electrode of the third transistor, and the light blocking layer of the seventh transistor may overlap with a channel of the seventh transistor and a gate electrode of the seventh transistor.

[0015] The light blocking layer of the third transistor and the light blocking layer of the seventh transistor may be located at different layers from each other.

[0016] The light blocking layer of the third transistor may be located at the same layer as the first sustaining electrode, and the light blocking layer of the seventh transistor may be located at the same layer as the gate electrode of the driving transistor.

[0017] The display device according to an embodiment may further include: an inverting scan line extending in a direction on the substrate and applied with the inverting scan signal, and the light blocking layer and the gate electrode of the third transistor may be connected to the inverting scan line.

[0018] The inverted scan line may include: a lower inverted scan line, which is located at the same layer as the light blocking layer of the third transistor and the first sustaining electrode; and an upper inverted scan line, which is located at the same layer as the gate electrode of the third transistor and overlaps with the lower inverted scan line, the light blocking layer of the third transistor can be connected to the lower inverted scan line, and the gate electrode of the third transistor can be connected to the upper direction scan line.

[0019] The display device according to an embodiment may further include: a first light emitting control line extending in a direction on the substrate and applied with the first light emitting control signal, wherein the light blocking layer and the gate electrode of the seventh transistor may be connected to the first light emitting control line.

[0020] The first light-emitting control line may include: a lower first light-emitting control line, which is located at the same layer as the light blocking layer of the seventh transistor and the gate electrode of the driving transistor; and an upper first light-emitting control line, which is located at the same layer as the gate electrode of the seventh transistor and overlaps with the lower first light-emitting control line, wherein the light blocking layer of the seventh transistor can be connected to the lower first light-emitting control line, and the gate electrode of the seventh transistor can be connected to the upper first light-emitting control line.

[0021] According to one embodiment, a display device includes: a light emitting diode connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; a driving transistor connected between the driving voltage line and the light emitting diode; a second transistor connected between a first electrode of the driving transistor connected to the driving voltage line and a data line to which a data voltage is applied; a third transistor connected between a second electrode of the driving transistor connected to the light emitting diode and a gate electrode of the driving transistor; a seventh transistor connected between the light emitting diode and an initialization voltage line to which an initialization voltage is applied; and a maintenance capacitor connected between the driving voltage line and the gate electrode of the driving transistor, wherein the driving transistor includes a polycrystalline semiconductor, and the third transistor and the seventh transistor include an oxide semiconductor.

[0022] According to one embodiment, the display device may further include: a fifth transistor and an eighth transistor, connected between the driving voltage line and the first electrode of the driving transistor; a sixth transistor, connected between the second electrode of the driving transistor and the light-emitting diode; a fourth transistor, connected between the gate electrode of the fifth transistor and the second electrode of the driving transistor; a first light-emitting control signal line, connected to the gate electrode of the fifth transistor and the gate electrode of the seventh transistor, and applied with a first light-emitting control signal; a second light-emitting control signal line, connected to the gate electrode of the sixth transistor and the gate electrode of the eighth transistor, and applied with a second light-emitting control signal; and a third light-emitting control signal line, connected to the gate electrode of the fourth transistor, and applied with a third light-emitting control signal.

[0023] According to one embodiment, the display device may further include: a scan line connected to the gate electrode of the second transistor and applied with a scan signal; and an inverted scan line connected to the gate electrode of the third transistor and applied with an inverted scan signal, wherein, at the same timing, the polarity of the voltage applied to the scan line and the polarity of the voltage applied to the inverted scan line may be opposite to each other.

[0024] The display device according to an embodiment may further include: a boosting capacitor connected between the gate electrode of the second transistor and the gate electrode of the driving transistor.

[0025] The driving transistor may have p-type transistor characteristics, and the third transistor and the seventh transistor may have n-type transistor characteristics.

[0026] According to the embodiment, the display device can be stably driven, the reliability can be improved, and the power consumption can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a circuit diagram of a display device according to an embodiment.

[0028] Figure 2 is a plan view showing a display device according to an embodiment.

[0029] Figure 3 is along Figure 2 The cross-sectional view is shown along line III-III.

[0030] Figure 4 is along Figure 2 The IV-IV line shows a cross-sectional view.

[0031] Figure 5 is a plan view showing a polycrystalline semiconductor of a display device according to an embodiment.

[0032] Figure 6 FIG. 4 is a plan view showing a polycrystalline semiconductor and a first gate conductor of a display device according to an embodiment.

[0033] Figure 7 is a plan view showing a polycrystalline semiconductor, a first gate conductor, and a second gate conductor of a display device according to an embodiment.

[0034] Figure 8 is a plan view showing a polycrystalline semiconductor, a first gate conductor, a second gate conductor, and an oxide semiconductor.

[0035] Fig. 9 is a plan view showing a polycrystalline semiconductor, a first gate conductor, a second gate conductor, an oxide semiconductor, and a third gate conductor.

[0036] Description of Reference Numerals

[0037] 127: Initialize voltage line

[0038] 151: Scan Line

[0039] 152: Inverted scan line

[0040] 155: First light-emitting control line

[0041] 156: Second light-emitting control line

[0042] 157: The third light-emitting control line

[0043] 171: Data line

[0044] 172: Driving voltage line

[0045] 741: Common voltage line

[0046] 1131: First electrode of driving transistor

[0047] 1132: Channel of driver transistor

[0048] 1133: Second electrode of driving transistor

[0049] 1153: First sustaining electrode

[0050] 3136: First electrode of the third transistor

[0051] 3137: Channel of the third transistor

[0052] 3138: Second electrode of the third transistor

[0053] 7136: First electrode of the seventh transistor

[0054] 7137: Channel of the seventh transistor

[0055] 7138: Second electrode of the seventh transistor

[0056] 1175: First connection electrode

[0057] 3175: Second connection electrode DETAILED DESCRIPTION

[0058] Hereinafter, multiple embodiments of the present invention will be described in detail with reference to the accompanying drawings so that a person having basic knowledge in the technical field to which the present invention belongs can easily implement the present invention. The present invention can be implemented in many different forms and is not limited to the embodiments described herein.

[0059] In order to clearly describe the present invention, parts not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

[0060] Furthermore, for the sake of convenience, the size and thickness of each structure shown in the drawings are arbitrarily shown, and therefore the present invention is not necessarily limited to the contents shown in the drawings. In order to clearly express multiple layers and regions in the drawings, the thickness is enlarged and shown. Furthermore, in the drawings, for the sake of convenience, the thickness of some layers and regions is exaggerated.

[0061] Furthermore, when a layer, film, region, plate or the like is mentioned as being "above" or "on" another part, it includes not only the situation where it is "immediately above" another part, but also the situation where there is another part between the two. In contrast, when a part is mentioned as being "immediately above" another part, it means that there is no other part between the two. Furthermore, being "above" or "on" a part used as a reference means being above or below the part used as a reference, and does not necessarily mean being "above" or "on" in the direction opposite to gravity.

[0062] Furthermore, throughout the specification, when it is mentioned that a certain part “includes” a certain constituent element, this does not mean that other constituent elements are excluded, but rather that other constituent elements may be included, unless otherwise stated.

[0063] Also, throughout the specification, when “on a plane” is mentioned, this means that the subject portion is observed from above, and when “on a cross section” is mentioned, this means that a cross section obtained by vertically cutting the subject portion is observed from the side.

[0064] First, refer to Figure 1 A description of one pixel of a display device according to an embodiment is as follows.

[0065] Figure 1 1 is a circuit diagram of a display device according to an embodiment. A pixel PX of a display device according to an embodiment includes a plurality of transistors T1, T2, T3, T4, T5, T6, T7, T8 connected to a plurality of signal lines 127, 151, 152, 155, 156, 157, 171, 172, 741, a holding capacitor Cst, a boost capacitor Cboost, and a light emitting diode LED.

[0066] The display device according to an embodiment includes a display area for displaying an image, and such pixels PX are arranged in the display area in various forms.

[0067] The plurality of transistors T1, T2, T3, T4, T5, T6, T7, T8 may include a driving transistor T1, and may include a second transistor T2 and a third transistor T3 as switch transistors. The other transistors are compensation transistors, and may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

[0068] Multiple signal lines 127, 151, 152, 155, 156, 157, 171, 172, 741 include an initialization voltage line 127, a scan line 151, an inverted scan line 152, a first light-emitting control line 155, a second light-emitting control line 156, a third light-emitting control line 157, a data line 171, a driving voltage line 172 and a common voltage line 741.

[0069] The scanning line 151 is connected to a gate driving unit (not shown) and transmits a scanning signal GW to the second transistor T2. The inverted scanning line 152 is applied with a voltage having a polarity opposite to that of the voltage applied to the scanning line 151 at the same timing as the signal of the scanning line 151. For example, when a high voltage is applied to the scanning line 151, a low voltage may be applied to the inverted scanning line 152. The inverted scanning line 152 transmits the inverted scanning signal GC to the third transistor T3.

[0070] The first light emitting control line 155 transmits the first light emitting control signal EM1 to the fifth transistor T5. The second light emitting control line 156 transmits the second light emitting control signal EM2 to the sixth transistor T6 and the seventh transistor T7. The third light emitting control line 157 transmits the third light emitting control signal EB to the fourth transistor T4.

[0071] The data line 171 is a wiring for transmitting a data voltage DATA generated by a data driving unit (not shown), and the brightness of light emitted by the light emitting diode LED changes according to the data voltage DATA applied to the pixel PX.

[0072] The driving voltage line 172 applies the driving voltage ELVDD. The initialization voltage line 127 transmits the initialization voltage VINT. The common voltage line 741 applies the common voltage ELVSS to the cathode electrode of the light emitting diode LED. In this embodiment, the voltages applied to the driving voltage line 172, the initialization voltage line 127 and the common voltage line 741 can be constant voltages.

[0073] The following is a detailed look at the structures and connection relationships of multiple transistors.

[0074] The driving transistor T1 may have a p-type transistor characteristic and may include a polycrystalline semiconductor. Furthermore, the driving transistor T1 is a transistor that adjusts the magnitude of the current output to the anode electrode of the light emitting diode LED according to the data voltage DATA applied to the gate electrode of the driving transistor T1. The brightness of the light emitting diode LED is adjusted according to the magnitude of the driving current output to the anode electrode of the light emitting diode LED, and thus the brightness of the light emitting diode LED can be adjusted according to the data voltage DATA applied to the pixel PX. To this end, the first electrode of the driving transistor T1 is arranged to be able to receive the driving voltage ELVDD, thereby being connected to the driving voltage line 172 via the fifth transistor T5 and the eighth transistor T8. Furthermore, the first electrode of the driving transistor T1 is also connected to the second electrode of the second transistor T2 to receive the data voltage DATA. In addition, the second electrode of the driving transistor T1 is arranged to be able to output current to the light emitting diode LED, thereby being connected to the anode of the light emitting diode LED via the sixth transistor T6. Furthermore, the second electrode of the driving transistor T1 transmits the data voltage DATA applied to the first electrode to the third transistor T3. In addition, the gate electrode of the driving transistor T1 is connected to an electrode (hereinafter referred to as the second sustaining electrode) of the sustaining capacitor Cst. Therefore, the gate voltage of the driving transistor T1 changes according to the voltage stored in the sustaining capacitor Cst, thereby changing the driving current output by the driving transistor T1. The sustaining capacitor Cst also plays a role in maintaining the gate voltage of the driving transistor T1 constant during one frame period.

[0075] The second transistor T2 may have a p-type transistor characteristic and may include a polycrystalline semiconductor. The second transistor T2 is a transistor that receives the data voltage DATA into the pixel PX. The gate electrode of the second transistor T2 is connected to the scan line 151 and the first electrode of the boost capacitor Cboost. The first electrode of the second transistor T2 is connected to the data line 171. The second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1. If the second transistor T2 is turned on by a low voltage in the scan signal GW transmitted through the scan line 151, the data voltage DATA transmitted through the data line 171 is transmitted to the first electrode of the driving transistor T1.

[0076] The third transistor T3 may have an n-type transistor characteristic and may include an oxide semiconductor. The third transistor T3 electrically connects the second electrode of the driving transistor T1 to the gate electrode of the driving transistor T1. As a result, the third transistor T3 is a transistor for transmitting the compensation voltage changed by the data voltage DATA via the driving transistor T1 to the second sustaining electrode of the sustaining capacitor Cst. The gate electrode of the third transistor T3 is connected to the inverting scan line 152, and the first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1. The second electrode of the third transistor T3 is connected to the second sustaining electrode of the sustaining capacitor Cst, the gate electrode of the driving transistor T1, and the second electrode of the boosting capacitor Cboost. The third transistor T3 is turned on by the high voltage in the inverting scan signal GC received through the inverting scan line 152, so that the gate electrode of the driving transistor T1 is connected to the second electrode of the driving transistor T1, and the voltage applied to the gate electrode of the driving transistor T1 is transmitted to the second sustaining electrode of the sustaining capacitor Cst and stored in the sustaining capacitor Cst.

[0077] The fourth transistor T4 may have a p-type transistor characteristic and may include a polycrystalline semiconductor. A gate electrode of the fourth transistor T4 is connected to the third light emission control line 157. A first electrode of the fourth transistor T4 is connected to the first light emission control line 155. A second electrode of the fourth transistor T4 is connected to the second electrode of the driving transistor T1, the first electrode of the third transistor T3, and the first electrode of the sixth transistor T6. If the fourth transistor T4 is turned on by a low voltage in the third light emission control signal EB transmitted through the third light emission control line 157, the first light emission control signal EM1 transmitted through the first light emission control line 155 is transmitted to the first electrode of the sixth transistor T6.

[0078] The fifth transistor T5 may have a p-type transistor characteristic and may include a polycrystalline semiconductor. The fifth transistor T5 may play a role in transmitting the driving voltage ELVDD to the driving transistor T1 via the eighth transistor T8. The gate electrode of the fifth transistor T5 is connected to the first light emitting control line 155. The first electrode of the fifth transistor T5 is connected to the driving voltage line 172. The second electrode of the fifth transistor T5 is connected to the first electrode of the eighth transistor T8.

[0079] The sixth transistor T6 may have a p-type transistor characteristic and may include a polycrystalline semiconductor. The sixth transistor T6 serves to transmit the driving current output by the driving transistor T1 to the light emitting diode LED. The gate electrode of the sixth transistor T6 is connected to the second light emitting control line 156. The first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T1. The second electrode of the sixth transistor T6 is connected to the anode of the light emitting diode LED.

[0080] The seventh transistor T7 may have an n-type transistor characteristic and may include an oxide semiconductor. The seventh transistor T7 serves to initialize the anode of the light emitting diode LED. The gate electrode of the seventh transistor T7 is connected to the first light emitting control line 155. The first electrode of the seventh transistor T7 is connected to the anode of the light emitting diode LED. The second electrode of the seventh transistor T7 is connected to the initialization voltage line 127. If the seventh transistor T7 is turned on by the high voltage in the first light emitting control signal EM1 transmitted through the first light emitting control line 155, the initialization voltage VINT is applied to the anode of the light emitting diode LED, so that the anode of the light emitting diode LED is initialized.

[0081] The eighth transistor T8 may have a p-type transistor characteristic and may include a polycrystalline semiconductor. The gate electrode of the eighth transistor T8 is connected to the second light emitting control line 156. The first electrode of the eighth transistor T8 is connected to the second electrode of the fifth transistor T5. The second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T1 and the second electrode of the second transistor T2. If the eighth transistor T8 is turned on by the low voltage in the second light emitting control signal EM2 transmitted through the second light emitting control line 156, the driving voltage ELVDD transmitted through the fifth transistor T5 is transmitted to the first electrode of the driving transistor T1.

[0082] In the above content, a pixel PX is described as including eight transistors T1, T2, T3, T4, T5, T6, T7, T8, a maintenance capacitor Cst, and a boost capacitor Cboost. However, this embodiment is not limited to this, and the number of transistors, capacitor data, and their connection relationship can be changed in various ways.

[0083] In this embodiment, the driving transistor T1 may include a polycrystalline semiconductor. In addition, the third transistor T3 and the seventh transistor T7 may include an oxide semiconductor. The second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may include a polycrystalline semiconductor. However, it is not limited to this, and at least one of the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may also include an oxide transistor. In this embodiment, the third transistor T3 and the seventh transistor T7 include semiconductor materials different from the driving transistor T1, so that they can be driven more stably and the reliability can be improved.

[0084] As described above, when a high voltage is applied to the scan line 151, a low voltage is applied to the inverted scan line 152, and when a low voltage is applied to the scan line 151, a high voltage is applied to the inverted scan line 152. That is, the inverted scan signal GC applied to the inverted scan line 152 and the scan signal GW applied to the scan line 151 constitute an inverted signal, thereby pulling down the gate voltage of the driving transistor T1 after the data is input. On the contrary, the scan signal GW will pull up the gate voltage of the driving transistor T1. Therefore, in the case of inputting a black voltage, the black voltage may be reduced. In this embodiment, the boost capacitor Cboost is located between the scan line 151 to which the scan signal GW is applied and the gate electrode of the driving transistor T1, so that the gate voltage of the driving transistor T1 can be increased and the black voltage can be stably output. As the capacity of the boost capacitor Cboost increases, the gate voltage of the driving transistor T1 can be increased more. By adjusting the capacity of the boost capacitor Cboost, the gate voltage of the driving transistor T1 can be controlled.

[0085] Below, refer to Figures 2 to 9 , the planar and cross-sectional structures of the driving transistor T1, the third transistor T3, the seventh transistor T7, etc. are described in more detail.

[0086] Figure 2 is a plan view showing a display device according to an embodiment, Figure 3 is along Figure 2 The cross-sectional view shown on line III-III, Figure 4 is along Figure 2 The IV-IV line shows a cross-sectional view. Figures 5 to 9 1 and 2 are plan views sequentially showing a manufacturing sequence of a display device according to an embodiment. Figures 2 to 9 Two adjacent pixels are shown, and the two pixels may have shapes symmetrical to each other. In the following, the pixel located on the left side is mainly described.

[0087] like Figures 2 to 9 As shown, a polycrystalline semiconductor including a channel 1132 , a first electrode 1131 , and a second electrode 1133 of the driving transistor T1 may be located on the substrate 110 . Figure 5 The polycrystalline semiconductor is shown in the figure. The polycrystalline semiconductor includes not only the channel, the first electrode and the second electrode of the driving transistor T1, but also the channels, the first electrode and the second electrode of the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8.

[0088] The channel 1132 of the driving transistor T1 may be configured to be bent in a plane. However, the shape of the channel 1132 of the driving transistor T1 is not limited thereto and may be varied. For example, the channel 1132 of the driving transistor T1 may be bent into other shapes or may be configured into a rod shape. The first electrode 1131 and the second electrode 1133 of the driving transistor T1 may be located on both sides of the channel 1132 of the driving transistor T1. The first electrode 1131 of the driving transistor T1 may extend up and down in a plane, so that the portion extending upward may be connected to the second electrode of the second transistor T2, and the portion extending downward may be connected to the second electrode of the eighth transistor T8. The second electrode 1133 of the driving transistor T1 may extend downward in a plane and be connected to the first electrode of the sixth transistor T6.

[0089] The buffer layer 111 may be located between the substrate 110 and the polycrystalline semiconductor including the channel 1132 of the driving transistor T1, the first electrode 1131, and the second electrode 1133. The buffer layer 111 may have a single layer or a multi-layer structure. The buffer layer 111 may include an organic insulating material or an inorganic insulating material.

[0090] The first gate insulating film 141 may be located on the polycrystalline semiconductor including the channel 1132 of the driving transistor T1, the first electrode 1131, and the second electrode 1133. The first gate insulating film 141 may include silicon nitride, silicon oxide, or the like.

[0091] A first gate conductor including the gate electrode 1151 of the driving transistor T1 and the light blocking layer 7155 of the seventh transistor T7 may be located on the first gate insulating film 141 . Figure 6 The polycrystalline semiconductor and the first gate conductor are also shown. The first gate conductor may also include a scan line 151, a lower first light-emitting control line 155a, a second light-emitting control line 156, and a third light-emitting control line 157. In addition, the first gate conductor may also include a gate electrode of the second transistor T2, a gate electrode of the fourth transistor T4, a gate electrode of the fifth transistor T5, a gate electrode of the sixth transistor T6, a gate electrode of the eighth transistor T8, and a first electrode of the boost capacitor Cboost.

[0092] The gate electrode 1151 of the driving transistor T1 may overlap with the channel 1132 of the driving transistor T1. The channel 1132 of the driving transistor T1 is covered by the gate electrode 1151 of the driving transistor T1. The light blocking layer 7155 of the seventh transistor T7 may overlap with the channel 7132 and the gate electrode 7151 of the seventh transistor T7. The light blocking layer 7155 of the seventh transistor T7 may be connected to the first light emission control line 155. At this time, the light blocking layer 7155 of the seventh transistor T7 may be connected to the lower first light emission control line 155a. The scan line 151, the lower first light emission control line 155a, the second light emission control line 156, and the third light emission control line 157 may extend substantially in the transverse direction. The gate electrode of the second transistor T2 and the first electrode of the boost capacitor Cboost may be connected to the scan line 151. The gate electrode of the fourth transistor T4 may be connected to the third light emission control line 157. The gate electrode of the fifth transistor T5 may be connected to the first light emission control line 155. At this time, the gate electrode of the fifth transistor T5 may be connected to the lower first light emission control line 155 a , and the gate electrode of the sixth transistor T6 and the gate electrode of the eighth transistor T8 may be connected to the second light emission control line 156 .

[0093] After forming the first gate conductor including the gate electrode 1151 of the driving transistor T1 and the light blocking layer 7155 of the seventh transistor T7, a doping process may be performed. The portion of the polycrystalline semiconductor blocked by the first gate conductor will not be doped, while the portion of the polycrystalline semiconductor not covered by the first gate conductor may be doped to have the same characteristics as the conductor. At this time, a doping process may be performed using a p-type dopant, and the driving transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 including the polycrystalline semiconductor may have p-type transistor characteristics.

[0094] The second gate insulating film 142 may be located on the first gate conductor including the gate electrode 1151 of the driving transistor T1, the light blocking layer 7155 of the seventh transistor T7, and the first gate insulating film 141. The second gate insulating film 142 may include silicon nitride, silicon oxide, or the like.

[0095] The first sustain electrode 1153 including the sustain capacitor Cst and the second gate conductor of the light blocking layer 3155 of the third transistor T3 may be located on the second gate insulating film 142 . Figure 7 The polycrystalline semiconductor, the first gate conductor and the second gate conductor are also shown. The second gate conductor may further include a lower inverted scan line 152a.

[0096] The first sustaining electrode 1153 overlaps with the gate electrode 1151 of the driving transistor T1 to form a sustaining capacitor Cst. An opening 1152 is formed in the first sustaining electrode 1153 of the sustaining capacitor Cst. The opening 1152 of the first sustaining electrode 1153 of the sustaining capacitor Cst may overlap with the gate electrode 1151 of the driving transistor T1. The light blocking layer 3155 of the third transistor T3 may overlap with the channel 3137 and the gate electrode 3151 of the third transistor T3. The light blocking layer 3155 of the third transistor T3 may be connected to the inverting scan line 152. At this time, the light blocking layer 3155 of the third transistor T3 may be connected to the lower inverting scan line 152a. The lower inverting scan line 152a may extend substantially in the lateral direction.

[0097] The first interlayer insulating film 161 may be located on the first sustain electrode 1153 including the sustain capacitor Cst and the second gate conductor of the light blocking layer 3155 of the third transistor T3. The first interlayer insulating film 161 may include silicon nitride, silicon oxide, or the like.

[0098] An oxide semiconductor including a channel 3137 , a first electrode 3136 , a second electrode 3138 of the third transistor T3 , a channel 7137 , a first electrode 7136 , and a second electrode 7138 of the seventh transistor T7 may be located on the first interlayer insulating film 161 . Figure 8 The polycrystalline semiconductor, the first gate conductor, the second gate conductor, and the oxide semiconductor are also shown. The oxide semiconductor may further include a second electrode of the boost capacitor Cboost.

[0099] The oxide semiconductor may include at least one of the following oxides: a monometallic oxide such as indium oxide (In), tin oxide (Sn) or zinc oxide (Zn); a binary metal oxide such as an In-Zn oxide, a Sn-Zn oxide, an Al-Zn oxide, a Zn-Mg oxide, a Sn-Mg oxide, an In-Mg oxide or an In-Ga oxide; an In-Ga-Zn oxide, an In-Al-Zn oxide, an In-Sn-Zn oxide, a Sn-Ga-Zn oxide, an Al-Ga-Zn oxide, a Sn-Al-Zn oxide, an In-Hf-Zn oxide, an In-La-Zn oxide, an In-Ce-Zn oxide, an In-Pr-Zn oxide In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, or In-Lu-Zn ​​oxides, etc.; and In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, or In-Hf-Al-Zn oxides. For example, the oxide semiconductor may include indium gallium zinc oxide (IGZO: Indium-Gallium-ZincOxide) in the In-Ga-Zn oxide.

[0100] The first electrode 3136 and the second electrode 3138 of the third transistor T3 may be located at both sides of the channel 3137 of the third transistor T3. The channel 3137 of the third transistor T3 may overlap with the light blocking layer 3155 of the third transistor T3. The width of the light blocking layer 3155 of the third transistor T3 may be wider than the width of the channel 3137. Therefore, the light blocking layer 3155 of the third transistor T3 may also overlap with a portion of the first electrode 3136 and a portion of the second electrode 3138 located at both sides of the channel 3137.

[0101] The first electrode 7136 and the second electrode 7138 of the seventh transistor T7 may be located at both sides of the channel 7137 of the seventh transistor T7. The channel 7137 of the seventh transistor T7 may overlap with the light blocking layer 7155 of the seventh transistor T7. The width of the light blocking layer 7155 of the seventh transistor T7 may be wider than the width of the channel 7137. Therefore, the light blocking layer 7155 of the seventh transistor T7 may also overlap with a portion of the first electrode 7136 and a portion of the second electrode 7138 located at both sides of the channel 7137.

[0102] The second electrode of the boost capacitor Cboost may be connected to the second electrode 3138 of the third transistor T3. The second electrode of the boost capacitor Cboost may overlap with the first electrode. The capacity of the boost capacitor Cboost may be determined by the overlapping area of ​​the first electrode and the second electrode of the boost capacitor Cboost, the thickness of the second gate insulating film 142 and the first interlayer insulating film 161 located between the first electrode and the second electrode, and the like.

[0103] The third gate insulating film 143 may be located on the oxide semiconductor including the channel 3137 of the third transistor T3, the first electrode 3136, the second electrode 3138, the channel 3137 of the seventh transistor T7, the first electrode 7136, and the second electrode 7138. The third gate insulating film 143 may be located on the entire surface of the oxide semiconductor and the first interlayer insulating film 161. That is, the third gate insulating film 143 covers the upper surface and side surfaces of the channel 3137 of the third transistor T3, the first electrode 3136, the second electrode 3138, the channel 7137 of the seventh transistor T7, the first electrode 7136, and the second electrode 7138. However, the present embodiment is not limited thereto, and the third gate insulating film 143 may not be located on the entire surface of the oxide semiconductor and the first interlayer insulating film 161. For example, the third gate insulating film 143 may also overlap with the channel 3137 of the third transistor T3, but not overlap with the first electrode 3136 and the second electrode 3138. Furthermore, the third gate insulating film 143 may overlap with the channel 7137 of the seventh transistor T7 , but not overlap with the first electrode 7136 and the second electrode 7138 .

[0104] A third gate conductor including a gate electrode 3151 of the third transistor T3 and a gate electrode 7151 of the seventh transistor T7 may be located on the third gate insulating film 143 . Fig. 9 The polycrystalline semiconductor, the first gate conductor, the second gate conductor, the oxide semiconductor and the third gate conductor are also shown. The third gate conductor may further include an upper inverting scan line 152b and an upper first light emission control line 155b.

[0105] The gate electrode 3151 of the third transistor T3 may overlap with the channel 3137 of the third transistor T3 and the light blocking layer 3155. The gate electrode 3151 of the third transistor T3 may be connected to the inverting scan line 152. At this time, the gate electrode 3151 of the third transistor T3 may be connected to the upper inverting scan line 152b. The light blocking layer 3155 and the gate electrode 3151 of the third transistor T3 may receive the inverting scan signal GC through the inverting scan line 152.

[0106] The gate electrode 7151 of the seventh transistor T7 may overlap with the channel 7137 of the seventh transistor T7 and the light blocking layer 7155. The gate electrode 7151 of the seventh transistor T7 may be connected to the first light emission control line 155. At this time, the gate electrode 7151 of the seventh transistor T7 may be connected to the upper first light emission control line 155b. The light blocking layer 7155 and the gate electrode 7151 of the seventh transistor T7 may receive the first light emission control signal EM1 through the first light emission control line 155b.

[0107] The upper inverted scan line 152b and the upper first light emitting control line 155b may extend substantially in the horizontal direction. The upper inverted scan line 152b may constitute the inverted scan line 152 together with the lower inverted scan line 152a. The upper inverted scan line 152b may overlap with the lower inverted scan line 152a. The upper first light emitting control line 155b may constitute the first light emitting control line 155 together with the lower first light emitting control line 155b. The upper first light emitting control line 155b may overlap with the lower first light emitting control line 155b.

[0108] A doping process may be performed after forming the third gate conductor including the gate electrode 3151 of the third transistor T3 and the gate electrode 7151 of the seventh transistor T7. The portion of the oxide semiconductor blocked by the third gate conductor will not be doped, while the portion of the oxide semiconductor not covered by the third gate conductor may be doped to have the same characteristics as the conductor. The channel 3137 of the third transistor T3 may be located below the gate electrode 3151 in a manner overlapping with the gate electrode 3151. The first electrode 3136 and the second electrode 3138 of the third transistor T3 may not overlap with the gate electrode 3151. The channel 7137 of the seventh transistor T7 may be located below the gate electrode 7151 in a manner overlapping with the gate electrode 7151. The first electrode 7136 and the second electrode 7138 of the seventh transistor T7 may not overlap with the gate electrode 7151. The doping process of the oxide semiconductor may be performed using an n-type dopant, and the third transistor T3 and the seventh transistor T7 including the oxide semiconductor may have n-type transistor characteristics.

[0109] The second interlayer insulating film 162 may be located on the third gate conductor including the gate electrode 3151 of the third transistor T3 and the gate electrode 7151 of the seventh transistor T7 .

[0110] The first opening 165, the second opening 166, and the third opening 167 may be formed in the second interlayer insulating film 162 and the third gate insulating film 143. The first opening 165 may overlap at least partially with the gate electrode 1151 of the driving transistor T1. The first opening 165 may be formed not only in the second interlayer insulating film 162 and the third gate insulating film 143, but also in the first interlayer insulating film 161 and the second gate insulating film 142. The first opening 165 may overlap with the opening 1152 of the first sustaining electrode 1153. The first opening 165 may be located inside the opening 1152 of the first sustaining electrode 1153. The second opening 166 may overlap at least partially with the second electrode 1133 of the driving transistor T1. The second opening 166 may be formed not only in the second interlayer insulating film 162 and the third gate insulating film 143, but also in the first interlayer insulating film 161, the second gate insulating film 142, and the first gate insulating film 141. The third opening portion 167 may at least partially overlap with the first electrode 3136 of the third transistor T3 .

[0111] The first connection electrode 1175 and the second connection electrode 3175 may be located on the second interlayer insulating film 162. The first connection electrode 1175 may overlap with the gate electrode 1151 of the driving transistor T1. The first connection electrode 1175 may be connected to the gate electrode 1151 of the driving transistor T1 through the first opening 165. The first connection electrode 1175 may overlap with the boost capacitor Cboost. The first connection electrode 1175 may be connected to the second electrode of the boost capacitor Cboost. Therefore, the gate electrode 1151 of the driving transistor T1 and the second electrode of the boost capacitor Cboost may be connected by the first connection electrode 1175. The second connection electrode 3175 may overlap with the second electrode 1133 of the driving transistor T1. The second connection electrode 3175 may be connected to the second electrode 1133 of the driving transistor T1 through the second opening 166. The second connection electrode 3175 may overlap with the first electrode 3136 of the third transistor T3. The second connection electrode 3175 may be connected to the first electrode 3136 of the third transistor T3 through the third opening 167. Therefore, the second electrode 1133 of the driving transistor T1 and the first electrode 3136 of the third transistor T3 may be connected via the second connection electrode 3175 .

[0112] The third interlayer insulating film 180 may be located on the first connection electrode 1175 and the second connection electrode 3175 .

[0113] The data line 171 and the driving voltage line 172 may be located on the third interlayer insulating film 180. The data line 171 and the driving voltage line 172 may extend substantially in the longitudinal direction. The data line 171 may be connected to the second transistor T2. The driving voltage line 172 may be connected to the first electrode of the fifth transistor T5. The driving voltage line 172 may be connected to the first sustaining electrode 1153 of the sustaining capacitor Cst. The first sustaining electrodes 1153 of the sustaining capacitors Cst of adjacent pixels are connected to each other and extend substantially in the transverse direction.

[0114] The protective film 182 may be located on the data line 171 and the driving voltage line 172. Although not shown in the figure, the anode electrode may be located on the protective film 182. The anode electrode may be connected to the sixth transistor T6 and may receive the output current of the driving transistor T1. The partition wall may be located on the anode electrode. An opening may be formed in the partition wall, and the opening of the partition wall may overlap with the anode electrode. The light-emitting element layer may be located in the opening of the partition wall. The cathode electrode may be located on the light-emitting element layer and the partition wall. The cathode electrode, the light-emitting element layer and the anode electrode constitute a light-emitting diode LED.

[0115] As described above, in the display device according to an embodiment, the driving transistor T1 may include a polycrystalline semiconductor, and the third transistor T3 and the seventh transistor T7 may include an oxide semiconductor. In this way, the third transistor T3 and the seventh transistor T7 and the driving transistor T1 include semiconductor materials different from each other, so that they can be driven more stably and reliability can be improved.

[0116] In this embodiment, the third transistor T3 including an oxide semiconductor includes a light blocking layer 3155. The light blocking layer 3155 of the third transistor T3 can be located in the same layer as the first sustaining electrode 1153 of the sustaining capacitor Cst, can be formed using the same material, and can be formed in the same process. In addition, the light blocking layer 3155 of the third transistor T3 can be located in the same layer as the inverted scan line 152 (especially, the lower inverted scan line 152a), can be formed using the same material, and can be formed in the same process. The light blocking layer 3155 of the third transistor T3 can be connected to the inverted scan line 152 and can receive the inverted scan signal GC from the inverted scan line 152. The light blocking layer 3155 of the third transistor T3 can receive the same signal as the gate electrode 3151, and the third transistor T3 can have a dual gate structure. In this way, the third transistor T3 does not need a separate additional process and has a structure including the light blocking layer 3155, so that leakage current can be prevented. Accordingly, the component characteristics and reliability can be improved.

[0117] Furthermore, the seventh transistor T7 including an oxide semiconductor includes a light blocking layer 7155. The light blocking layer 7155 of the seventh transistor T7 may be located at the same layer as the gate electrode 1151 of the driving transistor T1, may be formed using the same material, and may be formed using the same process. Furthermore, the light blocking layer 7155 of the seventh transistor T7 may be located at the same layer as the first light emission control line 155 (especially, the lower first light emission control line 155a), may be formed using the same material, and may be formed using the same process. The light blocking layer 7155 of the seventh transistor T7 may be connected to the first light emission control line 155, and may receive the first light emission control signal EM1 from the first light emission control line 155. The light blocking layer 7155 of the seventh transistor T7 may receive the same signal as the gate electrode 7151, and the seventh transistor T7 may have a dual gate structure. In this way, the seventh transistor T3 does not require a separate additional process and has a structure including the light blocking layer 7155, thereby preventing leakage current. Accordingly, the element characteristics and reliability may be improved.

[0118] Furthermore, the seventh transistor T7 may include an oxide semiconductor and have n-type transistor characteristics. The seventh transistor T7 is turned on by a high voltage in the first light emitting control signal EM1 transmitted through the first light emitting control line 155. Therefore, compared to the case where the seventh transistor T7 includes a polycrystalline semiconductor and has p-type transistor characteristics, the low voltage in the signal applied to the gate electrode of the seventh transistor T7 can be slightly increased. For example, in the case where the seventh transistor T7 includes a polycrystalline semiconductor and has p-type transistor characteristics, it is turned on by a low voltage, and in order to turn on the seventh transistor T7, the low voltage can be about -8.5V. The seventh transistor T7 of the display device according to the present embodiment is turned on by a high voltage, and the low voltage in the signal applied to the gate electrode of the seventh transistor T7 can rise to about -6V. With the increase of such a low voltage, the driving voltage of the display device can be reduced, and the power consumption can be improved.

[0119] The embodiments of the present invention are described in detail above, but the scope of the present invention is not limited thereto. Various modifications and improvements made by those skilled in the art using the basic concepts of the present invention defined in the claims also fall within the scope of the present invention.

Claims

1. A display device, comprising: substrate; A polycrystalline semiconductor including a channel of a driving transistor, a first electrode and a second electrode located on the substrate; A gate electrode of the driving transistor, located on the channel of the driving transistor; a first sustaining electrode, located on the gate electrode of the driving transistor; The light blocking layer of the third transistor and the light blocking layer of the seventh transistor are located on the substrate; an oxide semiconductor, comprising a channel, a first electrode, a second electrode of a third transistor, and a channel, a first electrode, and a second electrode of a seventh transistor, wherein the channel, the first electrode, and the second electrode of the third transistor are located on the light-blocking layer of the third transistor, and the channel, the first electrode, and the second electrode of the seventh transistor are located on the light-blocking layer of the seventh transistor; a gate electrode of a third transistor, located on a channel of the third transistor; and a gate electrode of the seventh transistor, located on the channel of the seventh transistor, The light blocking layer of the third transistor and the first sustaining electrode are located in the same layer. The light blocking layer of the seventh transistor is located at the same layer as the gate electrode of the driving transistor.

2. The display device according to claim 1, wherein: The driving transistor has p-type transistor characteristics, The third transistor and the seventh transistor have n-type transistor characteristics.

3. The display device according to claim 1, wherein: The light blocking layer of the third transistor overlaps with the channel of the third transistor and the gate electrode of the third transistor, The light blocking layer of the seventh transistor overlaps with a channel of the seventh transistor and a gate electrode of the seventh transistor.

4. The display device according to claim 1, further comprising: a first gate insulating film disposed between the polycrystalline semiconductor and the gate electrode of the driving transistor; a second gate insulating film, located between the gate electrode of the driving transistor and the first sustaining electrode; a first interlayer insulating film located between the light blocking layer of the third transistor and the oxide semiconductor, and between the light blocking layer of the seventh transistor and the oxide semiconductor; a third gate insulating film located between the oxide semiconductor and the gate electrode of the third transistor and between the oxide semiconductor and the gate electrode of the seventh transistor; as well as A second interlayer insulating film is located on the gate electrode of the third transistor and the gate electrode of the seventh transistor.

5. The display device according to claim 4, further comprising: A connecting electrode connects the second electrode of the driving transistor and the first electrode of the third transistor.

6. The display device according to claim 5, further comprising: A first opening is formed in the first gate insulating film, the second gate insulating film, the first interlayer insulating film, the third gate insulating film, and the second interlayer insulating film so as to overlap with the second electrode of the driving transistor; as well as A second opening is formed in the third gate insulating film and the second interlayer insulating film so as to overlap with the first electrode of the third transistor. The connecting electrode is located on the second interlayer insulating film, connected to the second electrode of the driving transistor through the first opening, and connected to the first electrode of the third transistor through the second opening.

7. A display device, comprising: A light emitting diode connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; A driving transistor connected between the driving voltage line and the light emitting diode; a second transistor connected between a first electrode of the driving transistor connected to the driving voltage line and a data line to which a data voltage is applied; a third transistor connected between the second electrode of the driving transistor connected to the light emitting diode and the gate electrode of the driving transistor; a seventh transistor connected between the light emitting diode and an initialization voltage line to which an initialization voltage is applied; a holding capacitor connected between the driving voltage line and the gate electrode of the driving transistor; a fifth transistor and an eighth transistor, connected between the driving voltage line and the first electrode of the driving transistor; a sixth transistor connected between the second electrode of the driving transistor and the light emitting diode; a fourth transistor connected between the gate electrode of the fifth transistor and the second electrode of the driving transistor; a first light emitting control signal line connected to the gate electrode of the fifth transistor and the gate electrode of the seventh transistor and applied with a first light emitting control signal; a second light emitting control signal line connected to the gate electrode of the sixth transistor and the gate electrode of the eighth transistor and applied with a second light emitting control signal; as well as a third light emitting control signal line connected to the gate electrode of the fourth transistor and supplied with a third light emitting control signal, wherein the driving transistor comprises a polycrystalline semiconductor, The third transistor and the seventh transistor include an oxide semiconductor.

8. The display device according to claim 7, further comprising: a scanning line connected to the gate electrode of the second transistor and applied with a scanning signal; as well as an inverted scanning line connected to the gate electrode of the third transistor and supplied with an inverted scanning signal, In which, at the same timing, the polarity of the voltage applied to the scanning line and the polarity of the voltage applied to the inverted scanning line are opposite to each other.

9. The display device according to claim 7, further comprising: A boost capacitor is connected between the gate electrode of the second transistor and the gate electrode of the driving transistor.

Images