Semiconductor structure and method for forming the same

Abstract

The present disclosure is directed to a gate-all-around (GAA) transistor structure with low levels of leakage current and low power consumption. For example, a GAA transistor includes a semiconductor layer having a first source / drain (S / D) epitaxial structure and a second S / D epitaxial structure disposed thereon, wherein the first and second S / D epitaxial structures are separated by a semiconductor nanosheet layer. The semiconductor structure also includes an isolation structure inserted between the semiconductor layer and each of the first and second S / D epitaxial structures. The GAA transistor also includes a gate stack surrounding the semiconductor nanosheet layer. Embodiments of the present invention also relate to semiconductor structures and methods of forming the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of forming the same. Background Art

[0002] The source / drain regions in a fin-based field effect transistor (finFET) grow from the sides of the fin structure and the top surface of the semiconductor substrate on which the fin structure is formed. During operation, leakage paths can form between the source / drain regions and the semiconductor substrate. The leakage paths can degrade the performance of the finFET. Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, a semiconductor structure is provided, comprising: a semiconductor layer; a first source / drain (S / D) epitaxial structure and a second S / D epitaxial structure, disposed on the semiconductor layer, wherein the first S / D epitaxial structure and the second S / D epitaxial structure are separated by a semiconductor nanosheet layer; an isolation structure inserted between the semiconductor layer and each of the first S / D epitaxial structure and the second S / D epitaxial structure; and a gate stack surrounding the semiconductor nanosheet layer.

[0004] According to another aspect of an embodiment of the present invention, a semiconductor structure is provided, comprising: a semiconductor layer; a source / drain (S / D) epitaxial structure pair having inclined inner side walls arranged relative to each other on the semiconductor layer; a nanosheet layer connecting the inclined inner side walls of the S / D epitaxial structure pair; an isolation structure inserted between the semiconductor layer and the S / D epitaxial structure pair; and a gate stack surrounding the nanosheet layer.

[0005] According to another aspect of an embodiment of the present invention, a method for forming a semiconductor structure is provided, comprising: forming a vertical structure on a semiconductor layer, the vertical structure comprising alternating first and second nanosheet layers; forming a first gate structure around a middle portion of the vertical structure and on a portion of the semiconductor layer, wherein an edge portion of the vertical structure is not covered by the first gate structure; removing the edge portion of the vertical structure; etching the edge portion of the first nanosheet layer from the vertical structure in a laterally direction; forming a spacer structure adjacent to each etched edge portion of the first nanosheet layer; forming an isolation structure in a top portion of the semiconductor layer not covered by the first gate structure; forming a source / drain (S / D) epitaxial layer on each isolation structure, wherein an edge portion of the second nanosheet layer is in contact with the S / D epitaxial layer; removing the first gate structure from the vertical structure; removing the first nanosheet layer from the vertical structure; and forming a second gate structure around the second nanosheet layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1 is a cross-sectional view of a gate-all-around nanosheet FET on a semiconductor-on-insulator substrate, according to some embodiments.

[0008] Figure 2 is a cross-sectional view of a gate-all-around nanosheet FET on a bulk semiconductor substrate, according to some embodiments.

[0009] Figure 3A and Figure 3B is a flow chart of a method for fabricating a gate-all-around nanosheet FET according to some embodiments.

[0010] Figure 4-Figure 10 is an isometric view of an intermediate structure during fabrication of a gate-all-around nanosheet FET structure, according to some embodiments.

[0011] Figure 11-Figure 20 is a cross-sectional view of an intermediate structure during fabrication of a gate-all-around nanosheet FET, according to some embodiments.

[0012] Fig.21 is a cross-sectional view of a gate-all-around nanosheet FET according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0015] As used herein, the term "nominal" refers to the desired or target value for a characteristic or parameter of a component or process operation, as set during the design phase of a product or process, and values ​​above and / or below the desired value. The range of values ​​is usually due to minor variations in the manufacturing process or tolerances.

[0016] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are examples only and are not intended to be limiting. It should be understood that the terms "about" and "substantially" may refer to a percentage of a value as interpreted by a person skilled in the relevant art based on the teachings herein.

[0017] As used herein, the term "vertical" refers to nominally perpendicular to the surface of a substrate.

[0018] As used herein, the term "insulating layer" refers to a layer that serves as an electrical insulator (eg, a dielectric layer).

[0019] Compared to other types of FETs in which the gate structure covers the sidewall portion and top surface of the semiconductor fin structure, a full-all-around gate (GAA) field effect transistor (GAA-FET), such as a nanosheet or nanowire GAA-FET, has improved gate control over the channel region. GAA nanosheet or nanowire FETs can achieve a larger effective channel width and a larger drive current due to the full-all-around gate geometry. At the same time, their unique geometry makes GAA nanosheet or nanowire FETs susceptible to leakage current. For example, the gate electrode wrapped around the nanosheet of the FET is formed to be adjacent to the semiconductor substrate. Therefore, during the operation of the GAA FET, a parasitic channel can be formed within the semiconductor substrate between the source / drain terminals grown directly on the semiconductor substrate. This parasitic channel can reduce the performance of the GAA FET and increase power consumption. In order to suppress the formation of the parasitic channel, the semiconductor substrate is "reverse doped", for example, doped with a dopant type opposite to the dopant type present in the channel region of the nanosheet or nanowire. Doping the semiconductor substrate increases the cost of the manufacturing process and / or may not effectively eliminate or suppress the formation of the parasitic channel.

[0020] The embodiments described herein are directed to methods for manufacturing a GAA FET with low power consumption that may not require substrate doping (e.g., counter-doping). In some embodiments, an isolation structure electrically isolates the source / drain epitaxial layer of the GAA FET from the semiconductor substrate, reducing or eliminating leakage current, and eliminating the need for substrate doping (e.g., counter-doping). In some embodiments, before forming the source / drain epitaxial layer, the semiconductor substrate is exposed to an oxygen treatment (e.g., directional decoupled plasma oxidation (DDPO)) to form an isolation structure on top of the undoped semiconductor substrate. Subsequently, a source / drain epitaxial layer is formed on the isolation structure.

[0021] Figure 1 1 is a cross-sectional view of a GAA nanosheet or nanowire FET structure 100 (GAA FET 100) according to some embodiments. Compared to a GAA FET without an isolation structure 105, the GAA FET 100 is characterized by inserting an isolation structure 105 between a source / drain (S / D) epitaxial layer 110 and a semiconductor layer 115, and has low power consumption. The S / D epitaxial layer 110 in the GAA FET is electrically separated from the semiconductor layer 115. In some embodiments, the semiconductor layer 115 is an undoped top layer of a semiconductor on insulator (SOI) substrate 120. Optionally, the semiconductor layer 115 can be doped. By way of example and not limitation, the dopant concentration in the semiconductor layer 115 can be about 2×10 14 cm 3 and about 1×10 15 cm 3 The SOI substrate 120 further includes a buried oxide (BOX) layer 125 disposed on the bulk substrate 130. The S / D epitaxial layer 110 is formed to be in physical contact with the semiconductor nanosheets or nanowires 135, which are separated by the spacer structure 140 and are formed by the spacer structure 140. Figure 1 The gate stack 145 is shown as being surrounded. In some embodiments, the gate stack 145 may include an interfacial layer (IL) 150, a high-k dielectric 155, and a gate electrode 160. In some embodiments, the gate electrode 160 also includes Figure 1 The GAA FET 100 further includes an S / D contact 165 disposed on the S / D epitaxial layer 110, and a silicide layer 170 is formed between the S / D epitaxial layer 110 and the S / D contact 165. Each S / D contact 165 further includes a conductive material 175 and a liner 180, such as Figure 1 In the GAA FET 100 , the gate spacer 185 provides electrical isolation for the gate stack 145 , while the interlayer dielectric (ILD) 190 provides electrical isolation for the S / D contacts 165 and the S / D epitaxial layer 110 .

[0022] In some embodiments, and for a gate bias greater than the threshold voltage of the GAA FET 100, a conductive channel is formed within the semiconductor nanosheet or nanowire 135. Assuming that an appropriate bias is applied to the S / D epitaxial layer 110 via the S / D contact 165, current flows between the S / D epitaxial layers 110 through the channel formed within the semiconductor nanosheet or nanowire 135. During the above operating conditions, the portion of the gate stack 145 closest to the semiconductor layer 115 can form a parasitic FET 195. If the epitaxial layer 110 is in physical contact with the semiconductor layer 115 (e.g., the isolation structure 105 is not formed), an undesirable leakage current may flow between the S / D epitaxial layer 110 via the semiconductor layer 115. An isolation structure 105 thicker than about 10 nm (e.g., about 40 nm) can provide sufficient electrical isolation and leakage current suppression for the S / D epitaxial layer 110. Furthermore, an isolation structure 105 thicker than about 10 nm (eg, about 40 nm) may eliminate the need for counter-doping in the semiconductor layer 115. In some embodiments, the thickness of the isolation structure 105 is substantially equal to Figure 1 The thickness of semiconductor layer 115 is shown in (eg, between about 20 nm and about 200 nm).

[0023] In some embodiments, Figure 2 As shown, the GAA FET 100 is formed on a bulk semiconductor substrate 200 (e.g., opposite to the SOI substrate 120). In some embodiments, the SOI substrate 120 can suppress parasitic capacitance more effectively than the semiconductor substrate 200. In some embodiments, the semiconductor layer 115 of the SOI substrate 120 or the bulk semiconductor substrate 200 includes crystalline silicon (Si) or another element semiconductor, such as germanium (Ge). Optionally, the semiconductor layer 115 may include (i) a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (ii) an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or (iv) a combination thereof.

[0024] For example purposes, we will refer to Figure 1 GAA FET 100 is described, and semiconductor layer 115 of SOI substrate 120 will be described in the context of crystalline silicon (Si). Based on the disclosure herein, other substrates and other substrate materials as described above may be used. These other substrates and substrate materials are within the spirit and scope of the present disclosure.

[0025] Assuming that the semiconductor layer 115 includes Si, the isolation structure 105 may include, for example, silicon oxide (SiO2). The semiconductor layer 115 is not limited to silicon oxide, and other insulating oxides are also possible based on the material selection for the semiconductor layer 115 (e.g., germanium oxide). In addition, a resistivity higher than about 1×10 10 Ohm-meter nitrides or other suitable dielectric materials (e.g., carbides). These other insulating materials are within the spirit and scope of the present disclosure.

[0026] In some embodiments, for p-type GAA FET, the S / D epitaxial layer 110 includes boron-doped (B-doped) silicon germanium (SiGe), B-doped germanium (Ge), B-doped germanium-tin (GeSn), or a combination thereof. In some embodiments, for n-type GAA FET, the S / D epitaxial layer 110 includes arsenic (As) or phosphorus (P) doped silicon (Si), carbon-doped silicon (Si:C), or a combination thereof. In some embodiments, the S / D epitaxial layer 110 may include two or more epitaxially grown layers, which are shown in FIG. 1 for simplicity. Figure 1 and Figure 2 In some embodiments, the S / D epitaxial layer 110 is grown from the exposed sidewall surfaces of the semiconductor nanosheets or nanowires 135 (eg, the semiconductor nanosheets or nanowires 135 are used as seeds for the semiconductor nanosheets or nanowires).

[0027] In some embodiments, when the width of the semiconductor nanosheet or nanowire 135 along the y direction is substantially different from its height along the z direction (e.g., when the width is greater / less than its height), the semiconductor nanosheet or nanowire 135 is referred to as a "nanosheet". In some embodiments, when the width of the semiconductor nanosheet or nanowire 135 along the y direction is substantially equal to its height along the z direction, it is referred to as a "nanowire". As an example and not limitation, the semiconductor nanosheet or nanowire 135 will be described in the context of a nanosheet. Based on the disclosure herein, the semiconductor nanowires described above are within the spirit and scope of the present disclosure.

[0028] In some embodiments, the vertical thickness (e.g., along the z direction) of each semiconductor nanosheet layer 135 is between about 5 nm and about 8 nm, and the width along the y direction is between about 15 nm and about 150 nm. Adjacent semiconductor nanosheet layers 135 are separated by a space between about 8 nm and about 12 nm in the vertical direction. In some embodiments, the semiconductor nanosheet layer 135 includes Si or SiGe with a Ge atomic concentration between about 20% and about 30%. Alternatively, the semiconductor nanosheet 135 may include a III-V compound semiconductor such as GaAs, InP, GaP, GaN, etc. For the purpose of example, the semiconductor nanosheet layer 135 will be described in the context of Si and SiGe nanosheet epitaxial layers. Based on the disclosure herein, other materials as described above may be used, and they are within the spirit and scope of the present disclosure. In some embodiments, depending on the characteristics of the FET, the GAA FET 100 may include 2 to 8 separate semiconductor nanosheet layers 135. Additional semiconductor nanosheet layers 135 are possible.

[0029] In some embodiments, the semiconductor nanosheet layer 135 is lightly doped or undoped. If lightly doped, the doping level of the semiconductor nanosheet layer 135 is less than about 10 13 Atom / cm 3 .

[0030] As mentioned above about Figure 1 As discussed, the space between the semiconductor nanosheet layers 135 is occupied by layers of the gate stack 145 (e.g., IL 150, high-k dielectric 155, and gate electrode 160). In some embodiments, the gate stack 145 covers a middle portion of the semiconductor nanosheet layer 135. Edge portions of the semiconductor nanosheet layer 135 are covered by the spacer structure 140. In some embodiments, the spacer structure 140 includes a nitride, such as silicon nitride (Si3N4 or "SiN"), silicon nitride carbon (SiCN), and silicon oxynitride carbon (SiCON). In some embodiments, the width of the spacer structure 140 along the x-direction is in a range between about 5 nm and about 10 nm. As shown in FIG. Figure 1 As shown, the spacer structure 140 is interposed between the gate stack 145 and the S / D epitaxial layer 110 to electrically isolate the gate stack 145 from the S / D epitaxial layer 110 .

[0031] The silicide layer 170 inserted between the S / D contact 165 and the S / D epitaxial layer 110 may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), platinum silicide (PtSi), or a suitable silicide material. As an example and not limitation, each silicide layer 170 may have a thickness between about 4 nm and about 8 nm. In some embodiments, the silicide layer 170 reduces the contact resistance between the conductive material 175 and the S / D epitaxial layer 110.

[0032] In some embodiments, the conductive material 175 may include tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), or another suitable conductive material. In some embodiments, the liner 180 covers the sidewall surface of the conductive material 175 and serves as an adhesion layer and / or barrier layer for the conductive material 175. In some embodiments, the liner 180 may include Ti, TiN, or other suitable materials.

[0033] like Figure 1 As shown, the gate spacer 185 covers the sidewall surface of the gate stack 145 disposed on the topmost semiconductor nanosheet 135. The gate spacer 185, like the spacer structure 140, may include a nitride such as SiN, SiCN, and SiCON. In some embodiments, the gate spacer 185 facilitates the formation of the gate stack 145.

[0034] In some embodiments, ILD 190 includes one or more layers of dielectric material. In some embodiments, ILD 190 is a silicon oxide-based dielectric with nitrogen, hydrogen, carbon, or a combination thereof. According to some embodiments, ILD 190 provides electrical isolation and structural support to gate stack 145, S / D contacts 165, and S / D epitaxial layer 110.

[0035] According to some embodiments, Figure 3A and Figure 3B Shows the description Figure 1 Flowchart of a manufacturing method 300 for forming a GAA FET 100 is shown. The method 300 is independent of the substrate used—for example, the method 300 can also be used to form Figure 2 The GAA FET 100 shown in FIG. 300 can also be used to produce a Fig.21 Other manufacturing operations may be performed between the various operations of method 300 and are omitted for clarity. The present disclosure is not limited to the operational descriptions. Rather, other operations are within the spirit and scope of the present disclosure. It should be understood that additional operations may be performed. Furthermore, not all operations may be required to perform the disclosure provided herein. Additionally, some operations may be performed simultaneously or in parallel. Figure 3A and Figure 3BIn some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described. For purposes of illustration, reference is made to Figures 4 to 21 The embodiment shown in describes method 300 .

[0036] The method 300 begins at operation 305 and the process of forming alternating first and second nanosheet layers on a substrate. Figure 4 is a partial isometric view of a first nanosheet layer 135a and a second nanosheet layer 135b formed on a substrate 120 according to operation 305. In some embodiments, the first nanosheet layer 135a corresponds to a SiGe nanosheet layer (SiGe nanosheet layer 135a), and the second nanosheet layer 135b corresponds to a Si nanosheet layer (Si nanosheet layer 135b).

[0037] In some embodiments, the SiGe nanosheet layer 135a and the Si nanosheet layer 135b can be grown directly on the substrate 120 (e.g., an SOI substrate or a bulk substrate) by a chemical vapor deposition (CVD) process, and the CVD uses silane (SiH4), disilane (Si2H6), germane (GeH4), digermane (Ge2H6), dichlorosilane (SiH2Cl2), other suitable gases or combinations thereof. As described above, the SiGe nanosheet layer 135a can contain about 20% to about 30% Ge, while the Si nanosheet layer 135b is substantially free of germanium, for example, the Ge concentration is between about 0.1% and about 1%. In some embodiments, the SiGe nanosheet layer 135a and / or the Si nanosheet layer 135b can be doped.

[0038] In some embodiments, the thickness of the SiGe nanosheet layer 135a sets the spacing between every other Si nanosheet layer 135b, and similarly, the thickness of the Si nanosheet layer 135b sets the spacing between every other SiGe nanosheet layer. The first layer 135a in the stack formed by the SiGe nanosheet layer 135a and the Si nanosheet layer 135b. For example, referring to Figure 5 , which is Figure 4 In the enlarged view of the portion 400 shown in FIG. 4 , the thickness 135a (T) of the SiGe nanosheet layer 135a can be used to define the spacing of the Si nanosheet layer 135b. Here, the spacing between the nanosheet layers can be defined. As described above, the thickness of each nanosheet layer can be in the range of, for example, about 5nm to about 8nm. Since the SiGe and Si nanosheet layers are grown separately, the SiGe nanosheet layer 135a and the Si nanosheet layer 135b can have thicknesses similar to or different from each other. In addition, each SiGe nanosheet layer can have a thickness similar to or different from each other, and similarly, each Si nanosheet layer can have a thickness similar to or different from each other. The foregoing thickness substitutions are within the spirit and scope of the present disclosure.

[0039] refer to Figure 3A The method 300 continues with operation 310 and patterns the first and second nanosheet layers to form a vertical nanosheet structure. In some embodiments, the vertical nanosheet structure may be formed as follows. Figure 6 and Fig. 7A , a photoresist layer is spin-coated on the uppermost Si nanosheet layer 135b, and then patterned to form a patterned photoresist structure 600. The patterned photoresist structure 600 is used as an etching mask in a subsequent etching process, in which portions of the Si nanosheet layer 135b and the SiGe nanosheet layer 135a that are not covered by the patterned photoresist structure 600 (e.g., not covered by the mask) are removed to form Fig. 7A The vertical nanosheet structure 700 is shown. After forming the vertical nanosheet structure 700, the patterned photoresist structure 600 can be removed from the vertical nanosheet structure 700 by a wet cleaning process. In some embodiments, during the aforementioned patterning process, the semiconductor layer 115 of the substrate 120 is also patterned to form a base structure 115p. The base structure 115p facilitates Figure 7B The formation of a shallow trench isolation (STI) structure 710 is shown.

[0040] In some embodiments, the width 600w of the patterned photoresist structure 600 defines the width of the vertical nanosheet layer structure 700 along the y dimension, which subsequently defines the width of the channel region in the GAA FET 100. The current density through the channel region is based on the width of the channel region in the GAA FET 100. For example, a wide channel region can carry a higher current density than a narrow channel region. In some embodiments, a narrow channel region can provide better gate control than a wide channel region. Therefore, the width of the nanosheet layer can be adjusted to provide a balance between current density and gate control over the channel region. In addition, by controlling the width 600w of the patterned photoresist structure 600, a vertical nanosheet layer structure 700 with different widths can be formed on the substrate 120. For example, a GAA FET can be constructed with different nanosheet layer widths at any desired location on the substrate 120.

[0041] After removing the patterned photoresist structure 600 from the vertical nanosheet structure 700, an STI structure 710 is formed on the patterned top surface of the semiconductor layer 115. In some embodiments, to form the STI structure 710, an STI material (e.g., a silicon oxide-based dielectric) is blanket deposited on the vertical nanosheet structure 700 and the semiconductor layer 115. The deposited STI material may then be planarized (e.g., using a chemical mechanical polishing (CMP) process) such that the top surface of the STI material is coplanar with the top surface of the vertical nanosheet structure 700. The planarized STI material is then etched back such that the height of the resulting STI structure 710 is substantially equal to the base structure 115p, as shown in FIG. Figure 7B In some embodiments, in order to facilitate subsequent processing operations, the vertical nanosheet structure 700 protrudes from the STI structure 710 so that the STI structure 710 does not cover any sidewall portion of the vertical nanosheet structure 700, such as Figure 7B shown.

[0042] In reference Figure 3A and Figure 8 , method 300 continues with operation 315 and forms a sacrificial gate structure 800 on the vertical nanosheet structure 700. In some embodiments, sacrificial gate structure 800 includes a polysilicon gate electrode 805 and a gate oxide 810. In some embodiments, polysilicon gate electrode 805 and gate oxide 810 may be blanket deposited to cover the side and top surface portions of vertical nanosheet structure 700 and the top surface of STI structure 710. Subsequently, blanket deposited polysilicon gate electrode 805 and gate oxide 810 are patterned to form Figure 8 The sacrificial gate structure 800 is shown. In some embodiments, the gate oxide 810 includes, for example, silicon oxide or silicon oxynitride (SiON), and is interposed between the polysilicon gate electrode 805 and the vertical nanosheet structure 700. For example, the gate oxide 810 is formed before the polysilicon gate electrode 805. In some embodiments, the sacrificial gate structure 800 is formed perpendicular to the length (e.g., the longest dimension) of the vertical nanosheet structure 700—for example, along the y direction and perpendicular to the x direction. In addition, the sacrificial gate structure 800 does not cover the entire length of the vertical nanosheet structure 700. In some embodiments, as Figure 8 As shown, and to facilitate subsequent operations, edge portions of the vertical nanosheet structure 700 are not covered (eg, not masked) by the sacrificial gate structure 800. In other words, the width 700L is greater than the width 800L—eg, 700L>800L.

[0043] The sidewalls of the sacrificial gate structure 800 are covered by gate spacers 185, which are also Figure 1 and Figure 2In some embodiments, the gate spacer 185 is not removed by a replacement gate process, during which the sacrificial gate structure 800 is replaced by the gate stack 145. In some embodiments, the top surface of the polysilicon gate electrode 805 is covered by a gate capping layer 815. In some embodiments, the gate capping layer 815 can be a stack of layers. For example, the gate capping layer 815 can include Figure 8 An oxide layer (eg, silicon oxide) and a nitride layer (eg, SiN, SiON, SiOCN, etc.) not shown in FIG. In some embodiments, the gate cap layer 815 and the gate spacer 185 protect the sacrificial gate structure from subsequent processing.

[0044] refer to Figure 3A The method 300 continues with operation 320 and the process of removing (eg, trimming) the portion of the vertical nanosheet structure 700 not covered by the sacrificial gate structure 800, such as Fig. 9 As shown. In some embodiments, the removal process includes a dry etching process, a wet etching process, or a combination thereof that is selective to the Si nanosheet layer 135b and the SiGe nanosheet layer 135a. In some embodiments, the dry etching process may include an etchant having an oxygen-containing gas, a fluorine-containing gas (e.g., carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), trifluoromethane (CHF3) and / or hexafluoroethane (C2F6)), a chlorine-containing gas (e.g., chlorine (Cl2), chloroform (CHCl3), carbon tetrachloride (CCl4) and / or boron trichloride (BCl3)), a bromine-containing gas (e.g., hydrogen bromide (HBr) and / or bromoform (CHBr3)), an iodine-containing gas, other suitable etching gases and / or plasmas, or a combination thereof. The wet etching process may include etching in dilute hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia, hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH), or a combination thereof. In some embodiments, the etching chemistry does not substantially etch the STI structure 510, the gate cap layer 815, and the gate spacer 185. In some embodiments, the STI structure 510 serves as an etch stop layer for the above-mentioned etching process.

[0045] refer to Figure 3A , the method 300 continues with operation 325 and the process of partially etching the first nanosheet layer (eg, SiGe nanosheet layer 135a) from the vertical nanosheet layer structure 700. According to some embodiments, Fig.10 After operation 325, Fig. 9 In some embodiments, the exposed edge of the SiGe nanosheet layer 135a is laterally recessed along the x-direction. Fig.11 yes Fig.10 The structure is shown in cross-section along plane 1000 .

[0046] According to some embodiments, Fig.11 As shown, the exposed edge of the SiGe nanosheet layer 135a is recessed (eg, partially etched) by an amount A along the x-direction, and the amount A is between about 5 nm and about 10 nm. In some embodiments, Figure 1 The spacer structure 140 shown will be formed on the recessed portion of the SiGe nanosheet layer 135a. According to some embodiments, a recess amount less than about 5 nm causes the spacer structure 140 to be too thin to provide sufficient electrical isolation between the gate structure 145 and the S / D epitaxial layer 110. On the other hand, a recess amount greater than about 10 nm causes the spacer structure 140 to be unnecessarily thick, wasting valuable space from the gate stack 145 and reducing the gate length of the resulting device.

[0047] In some embodiments, the recess in the SiGe nanosheet layer 135a can be achieved by a dry etching process that is selective for SiGe. For example, halogen-based chemicals exhibit high etching selectivity to Ge and low etching selectivity to Si. Therefore, the halogen gas etches the Ge-containing layer (e.g., SiGe nanosheet layer 135a) at a higher etching rate than the layer that is substantially free of Ge (e.g., Si nanosheet layer 135b). In some embodiments, the halogen-based chemical comprises a fluorine-based and / or chlorine-based gas. Alternatively, a wet etching chemical having high selectivity for SiGe can be used. In some embodiments, the wet etching chemical may include a mixture (SPM) of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2), or a mixture (APM) of ammonia with H2O2 and water. The aforementioned etching process is performed regularly to remove the desired amount of SiGe.

[0048] In some embodiments, the SiGe nanosheet layer 135a having a higher Ge atomic concentration has a higher etching rate than the SiGe nanosheet layer 135a having a lower Ge atomic concentration. Therefore, the etching rate of the above etching process can be adjusted by modulating the Ge atomic concentration (e.g., Ge content) in the SiGe nanosheet layer 135a. As described above, the Ge content in the SiGe nanosheet layer 135a can be in the range of about 20% to about 30%. A SiGe nanosheet layer with about 20% Ge can be etched slower than a SiGe nanosheet layer with about 30% Ge. Therefore, the Ge concentration can be adjusted accordingly to achieve a desired etching rate and selectivity between the SiGe nanosheet layer 135a and the Si nanosheet layer 135b.

[0049] In some embodiments, a Ge concentration below about 20% may not provide sufficient selectivity between the SiGe nanosheet layer 135a and the Si nanosheet layer 135b. For example, the etching rates between the SiGe nanosheet layer 135a and the Si nanosheet layer 135b become substantially similar to each other, and both types of nanosheet layers are etched during the etching process. On the other hand, for a Ge concentration above about 30%, Ge atoms may diffuse outward from the SiGe nanosheet layer 135a to the Si nanosheet layer 135b (e.g., during growth) and change the selectivity between the SiGe nanosheet layer 135a and the Si nanosheet layer 135b during etching. Since the outdiffusion of Ge cannot be controlled, a Ge concentration above about 30% may result in an unpredictable amount of etching.

[0050] In some embodiments, after operation 325, the etched edges of the SiGe nanosheet layer 135a are not as Fig.11 is shown vertically, but Fig.12 In the case of a recessed edge, the recess amount A is measured, for example, from the vertex of the recessed edge of the SiGe nanosheet layer 135a to the vertex of the adjacent vertical edge of the Si nanosheet layer 135b, as shown. Fig.12 In some embodiments, Fig.12 The recess amount A in is between about 5 nm and about 10 nm - for example, similar to Fig.11 The amount of recess A is shown.

[0051] In reference Figure 3A , method 300 continues with operation 330 and deposits a capping layer on the vertical nanosheet structure 700. In some embodiments, the capping layer is blanket deposited on Fig.11 For example, in Fig.13 In operation 330, the capping layer 1300 is deposited on the exposed surfaces of the substrate 120, the vertical nanosheet structure 700, the gate spacer 185, and the gate capping layer 815. However, in some embodiments, the capping layer 1300 is deposited with a thickness of about 5 nm to about 10 nm to fully fill the substrate 120. Fig.11 and Fig.12 The recess amount A is shown. In some embodiments, the capping layer 1300 includes a silicon-based dielectric such as SiN, SiOCN, SiCN, or SiON. In some embodiments, the capping layer 1300 can be deposited using a plasma enhanced atomic layer deposition (PEALD) process or another suitable method capable of depositing a conformal layer. Fig.13 As shown, the capping layer 1300 fills the space formed by the recessed edge portion of the SiGe nanosheet layer 135a. As a result of the deposition of the capping layer, the sidewall surfaces of the vertical nanosheet layer structure 700 are no longer exposed.

[0052] refer to Figure 3B The method 300 continues with operation 335 and exposes the substrate 120 to a process to form an isolation structure 105 (eg, in the semiconductor layer 115 ) in the top of the substrate 120 . Figure 1 and Figure 2 100). In some embodiments, the plasma treatment includes a directional decoupled plasma oxidation (DDPO) process using a gas mixture of oxygen and helium in a ratio of about 10 / 100 to about 50 / 100. In some embodiments, the DDPO process includes an RF plasma power between about 1 kW and about 2 kW, and the RF bias applied to the substrate 120 is between about 10 W and about 150 W. In some embodiments, the process pressure and temperature during the DDPO process are between about 10 mTorr and about 30 mTorr and between about 250° C. and about 450° C., respectively. In some embodiments, an RF plasma power of less than about 1 kW produces a lower density plasma that requires a longer processing time. The foregoing process ranges are exemplary and not restrictive. Therefore, other suitable ranges may be used. These other ranges are within the spirit and scope of the present disclosure.

[0053] One feature of the DDPO process discussed above is its directionality. In some embodiments, substrate bias, plasma density, temperature, and process pressure are adjusted so that oxidation occurs preferentially along a vertical axis (e.g., along the z-axis) to achieve a desired vertical thickness of the isolation structure 105. For example, as described above with reference to Figure 1 and Figure 2 As discussed, the resulting isolation structure 105 has a thickness greater than about 10 nm and equal to or less than Figure 1 The thickness of the semiconductor layer 115 shown is a vertical thickness (e.g., between about 20 nm and about 200 nm). For example, the isolation structure 105 can have a vertical thickness between about 10 nm and about 80 nm. In some embodiments, and with reference to Fig.14 , the edge portion of the isolation structure 105 may extend laterally (eg, along the x-direction) below the vertical nanosheet gate structure 700 by an amount between about 1 nm and about 3 nm, as shown by the dashed circle B. This is because oxidation may occur at a slower rate along the x and y directions.

[0054] In some embodiments, an isolation structure formed under the source terminal can have a different thickness than an isolation structure formed under the drain terminal. For example, if the voltage applied to the drain epitaxial layer (e.g., during operation) is higher than the voltage of the source epitaxial layer, the isolation structure under the drain epitaxial layer can be formed to be thicker than the isolation structure under the source epitaxial layer. For example, this can be achieved by masking the terminal receiving the lowest voltage during part of the DDPO process so that the isolation structure can be formed thinner.

[0055] In some embodiments, during operation 335, a portion of the capping layer 1300 is oxidized and converted to Fig.14 The oxide 1400 shown. Oxidation of the capping layer 1300 occurs from its top surface inward. Due to the directionality of the DDPO process, oxidation of the capping layer 1300 is accelerated along the vertical direction z. In some embodiments, the DDPO process is timed so that portions of the capping layer 1300 are oxidized except for portions of the capping layer 1300 adjacent to the recessed edges of the SiGe nanosheet layer 135a within the vertical nanosheet layer structure 700, as shown in FIG. Fig.14 As shown. Therefore, the unoxidized portion of the cover layer 1300 forms Figure 1 , Figure 2 and Fig.14 A spacer structure 140 is shown.

[0056] In subsequent operations, such as Fig.15 As shown, the oxide 1400 (e.g., the oxidized portion of the capping layer 1300) is removed. In some embodiments, the oxide 1400 can be removed by a dry etching process, which includes an ammonia (NH3) and nitrogen trifluoride (NF3) plasma (e.g., a SICONI process) that is selective to the oxide 1400 (e.g., silicon oxide). In some embodiments, if the deposition thickness of the capping layer 1300 is less than about 5 nm, the entire capping layer 1300 may be oxidized during the DDPO process, including the portion of the capping layer 1300 adjacent to the recessed edge of the SiGe nanosheet layer 135a. Therefore, the oxide 1400 will include the entire capping layer 1300. As a result, during the above-mentioned removal process, the entire oxidized capping layer will be removed and the spacer structure will not be formed. On the other hand, if the thickness of the capping layer 1300 is greater than about 10 nm, the desired portion of the capping layer 1300 may not be oxidized during the DDPO process because the capping layer 1300 will be too thick. These desired portions include sidewall portions of the capping layer 1300, except for portions of the capping layer 1300 adjacent to the recessed edge of the SiGe nanosheet layer 135a. Since only the oxidized portion is removed, any unoxidized portion of the capping layer 1300, including the unoxidized portion of the capping layer sidewall, will not be removed. Therefore, the formed spacer structure 140 will cover the side surfaces of the entire vertical nanosheet layer structure 700, including the side surfaces of the Si nanosheet layer 135b, which is undesirable.

[0057] Reference Figure 3B and Fig.16The method 300 continues with operation 340 and forms an S / D epitaxial layer 110 on the isolation structure 105. In some embodiments, the S / D epitaxial layer 110 is grown using a CVD process similar to that used to form the SiGe nanosheet layer 135a and the silicon nanosheet layer 135b. For example, a silane (SiH4) precursor may be used to grow a p-doped Si S / D epitaxial layer 110 (e.g., suitable for an n-type GAA FET). A phosphorus (P) dopant may be introduced during the growth process. In some embodiments, the phosphorus concentration may be about 1×10 21 Atom / cm 3 About 8×10 21 Atom / cm 3 The foregoing doping concentration ranges are not limiting, and other doping concentration ranges are within the spirit and scope of the present disclosure.

[0058] Therefore, the B-doped SiGe S / D epitaxial layer 110 (eg, suitable for p-type GAA FET) may include two or more epitaxial layers (eg, 110 ) grown successively and having different Ge atomic percentages and B concentrations. Fig.16 For example, the first layer may have a Ge atomic % in the range of 0 to about 40%, and a Ge atomic % in the range of about 5×10 19 Atom / cm 3 About 1×10 21 Atom / cm 3 The second epitaxial layer may have a Ge atomic % ranging from about 20% to about 80%, and a B dopant concentration ranging from about 3×10 20 Atom / cm 3 About 5×10 21 Atom / cm 3 In addition, the third epitaxial layer may be a capping layer having a Ge atomic % and a B dopant concentration similar to that of the first layer (e.g., Ge is 0 to about 40%, and about 5×10 19 Atom / cm 3 About 1×10 21 Atom / cm 3 The foregoing doping concentrations are not limiting, and other doping concentrations are within the spirit and scope of the present disclosure.

[0059] In some embodiments, after forming the S / D epitaxial layer 110, the ILD 190 is deposited and then planarized (e.g., by a CMP process) so that the top surface of the ILD 190 is substantially coplanar with the top surface of the polysilicon gate electrode 805. During the above-mentioned planarization process, the gate capping layer 815 used as a planarization etch stop layer is removed from the top surface of the polysilicon gate electrode 805. Therefore, after operation 340, the top surface of the polysilicon gate electrode 805 is exposed, as shown in FIG. Fig.16 In some embodiments, ILD 190 may include SiO2, SiOC, SiON, SiOCN, or SiCN deposited by CVD, physical vapor deposition (PVD), a thermal growth process, or any other suitable deposition method.

[0060] refer to Figure 3B , the method 300 continues with operation 345 and a process of removing the sacrificial gate structure 800. In some embodiments, operation 345 includes a double wet etching process during which the polysilicon gate electrode 805 and the sacrificial gate oxide 810 are sequentially removed. In some embodiments, the sacrificial gate structure 800 may be removed using a first wet etching process designed to be selective to the polysilicon gate electrode 805. As an example and not limitation, the selectivity of the first wet chemistry may be greater than about 1000:1 (e.g., 10000:1) so that the gate spacers 185, the sacrificial gate oxide 810, and the ILD 190 are not removed by the first wet etching process. Since the sacrificial gate oxide 810 is interposed between the vertical nanosheet layer structure 700 and the polysilicon gate electrode 805, the sacrificial gate oxide 810 may protect the SiGe / Si nanosheet layer 135a / b of the vertical nanosheet layer structure 700 from being etched during the first wet etching process. The subsequent second wet etching process removes the sacrificial gate oxide 810 without etching the gate spacers 185, the ILD 190, and the vertical nanosheet layer structure 700. In some embodiments, the second wet etching chemistry may be selective to the sacrificial gate oxide 810, so that surrounding materials such as the gate spacers 185, the SiGe / Si nanosheet layers 135a / b of the vertical nanosheet layer structure 700, and the ILD 190 are not removed. In the case where the second etching chemistry may etch the ILD 190, a capping layer or hard mask may be formed on the ILD 190 after operation 340 to protect the ILD 190 from the second wet etching process. According to some embodiments, after removing the sacrificial gate structure 800, the top surface and sidewall surfaces (e.g., parallel to the xz plane) of the vertical nanosheet structure 700 are exposed.

[0061] refer to Figure 3B , the method 300 continues with operation 350 and the process of removing the first nanosheet layer (e.g., SiGe nanosheet layer 135a) from the vertical nanosheet layer structure 700. For example, the SiGe nanosheet layer 135a is removed by an etching chemistry similar to that used to laterally etch the SiGe nanosheet layer 135a in operation 325. For example, in operation 350, the SiGe nanosheet layer 135a may be exposed to a halogen-based chemistry (e.g., a fluorine-based and / or chlorine-based gas) until the SiGe nanosheet layer 135a is completely removed from the vertical nanosheet 700. Fig.18As shown, after the SiGe nanosheet layer 135 a is removed, the Si nanosheet layer 135 b is suspended between the S / D epitaxial layers 110 .

[0062] In some embodiments, Fig.19 As shown, after operation 350, the surface of the Si nanosheet layer 135b may appear concave (eg, thinned), which is Fig.18 An enlarged view of the portion 1800 is shown. For example, the middle portion thickness M T The thickness E of the edge portion of the Si nanosheet layer 135b may be equal to or less than T (For example, E T ≥M T ). In some embodiments, after operation 350, the height difference between the middle and edge portions of the Si nanosheet layer 135b may be between about 2 nm and about 4 nm, for example, (ET-MT) is between about 2 nm and about 4 nm. In some embodiments, the aforementioned "thinning" of the Si nanosheet layer 135b during operation 350 is attributed to the selectivity of the etching gas used in operation 350. For example, the etching selectivity of the etching chemistry to the Si nanosheet layer 135b may not be zero.

[0063] refer to Figure 3B and Fig. 20 , the method 300 continues with operation 355 and forms a gate stack 145 around the Si nanosheet layer 135b. In some embodiments, the IL 150 is formed first, and then the high-k dielectric 155 and the gate electrode 160 are formed. As an example and not limitation, the IL 150 may include silicon oxide or silicon oxynitride, and the high-k dielectric 155 may include doped or undoped hafnium oxide (HfO2), hafnium silicate-based materials, or other suitable dielectrics with k values ​​greater than 3.9. In addition, the gate electrode 160 may include a capping layer on the high-k dielectric 155, one or more barrier layers, a work function metal (WFM) stack, and for simplicity, the gate electrode 160 may include a capping layer on the high-k dielectric 155, one or more barrier layers, a work function metal (WFM) stack, and for simplicity, the gate electrode 160 may include a capping layer on the high-k dielectric 155, one or more barrier layers, a work function metal (WFM) stack, and a gate electrode 160. Fig. 20 The number and type of layers in the WFM stack in the gate electrode 160 can modulate the threshold voltage of the GAA FET. By way of example and not limitation, the WFM stack may include a tantalum nitride (TaN) layer, a titanium nitride (TiN) layer, a (Ti / Al) bilayer, a titanium aluminum (Ti-Al) alloy layer, a tantalum aluminum (Ta-Al) alloy layer, or a combination thereof. The metal fill layer may include, for example, a TiN barrier layer and a tungsten (W) metal stack. The above list of materials for IL 150, high-k dielectric 155, and gate electrode 160 is not exhaustive; additional materials may be used within the spirit and scope of the present disclosure.

[0064] In some embodiments, the IL 150 and the high-k dielectric 155 are formed thicker on the Si nanosheet layer 135b toward the semiconductor layer 115. For example, the thickness of the IL 150 and the high-k dielectric 155 gradually decreases toward the semiconductor layer 115. In some embodiments, the above thickness variation is attributed to the reactant transport characteristics during the deposition of the IL 150 and the high-k dielectric 155, for example, the reactants take longer to reach the surface close to the semiconductor layer 115, thus producing a thinner film. By way of example and not limitation, the IL 150 can have a thickness between about 0.5 nm and about 1 nm, and the high-k dielectric 155 can have a thickness between about 1 nm and about 1.5 nm.

[0065] In some embodiments, after forming the gate stack 145, a planarization process (eg, a CMP process) removes excess deposited gate stack material on the ILD 190 and planarizes the structure so that the top surfaces of the gate stack 145 and the ILD 190 are as follows: Fig. 20 As shown, the S / D contacts 165 and the silicide layer 170 may be formed on Figure 1 On the S / D epitaxial layer 110 as shown.

[0066] In some embodiments, the Si nanosheet layer 135b may be removed to form a suspended SiGe nanosheet layer 135a. Figure 4 , the nanosheet layer 135a may correspond to a Si nanosheet layer, and the nanosheet layer 135b may correspond to a SiGe nanosheet layer. Figure 3A and Figure 3B Operations 325 and 350 of the illustrated method 300 utilize an etching chemistry that is selective to the Si nanosheet layer to recess and remove the Si nanosheet layer, respectively.

[0067] In some embodiments, the isolation structure 105 may include a nitride or a carbide, such as silicon nitride (SiN), silicon carbide (SiC), and a resistivity higher than about 1×10 10 Ohm·meter of other suitable materials. For example, in the case of silicon nitride isolation structure 105, a directional decoupled plasma nitridation (DPPN) process can be used to form a nitride layer in semiconductor layer 115 instead of an oxide layer. In some embodiments, isolation structure 105 can be formed by an implantation process, an ALD process, a CVD process, or a physical vapor deposition (PVD) process (e.g., sputtering). For example, in the case of an ALD, CVD, or PVD process, isolation structure 105 can be formed on the top surface of semiconductor layer 115—e.g., not within semiconductor layer 115.

[0068] According to some embodiments, Fig.21is an alternative GAA FET formed using method 300. Fig.21 In the embodiment, the GAA FET is characterized by a gradually shortened length of the Si nanosheet layer 135b toward the gate stack 145 and an inclined S / D epitaxial layer 110. For example, this can be achieved during operation 310, in which the etching process for etching the first and second nanosheet layers (e.g., SiGe nanosheet layer 135a and Si nanosheet layer 135b, respectively) is modified to form inclined sidewalls instead of substantially vertical sidewalls in the vertical nanosheet layer structure 700. In addition, Fig.21 The GAA FET structure is characterized by a hemispherical isolation structure 105. As above, the implantation process can produce an isolation structure 105 having a hemispherical shape. In some embodiments, the hemispherical isolation structure 105 can extend laterally (e.g., along the x-direction) below the spacer structure 140 by an amount between about 1 nm and about 3 nm, as shown by the dashed circle C. In some embodiments, Fig.21 The GAA FET in the embodiment has a spacer structure 140, and the spacer structure 140 has a protruding sidewall surface, which is the above Fig.12 Results of the SiGe nanosheet etching process are discussed.

[0069] Embodiments herein are directed to methods for manufacturing GAA FETs, which may have low power consumption without substrate doping (e.g., counter-doping). In some embodiments, the isolation structure disclosed herein is inserted between the source / drain epitaxial layer of the GAA FET and the semiconductor substrate to reduce or eliminate leakage current and the need for substrate doping (e.g., counter-doping). In some embodiments, the isolation structure is formed by a DDPO process, a DDPN process, an implantation process, an ALD process, a CVD process, or a PVD process. In some embodiments, the isolation structure has a thickness greater than about 10 nm and includes a resistivity greater than about 1×10 10 In some embodiments, the isolation structure has a substantially rectangular shape or a substantially hemispherical shape.

[0070] In some embodiments, the semiconductor structure includes a semiconductor layer on which a first S / D epitaxial structure and a second S / D epitaxial structure are arranged, wherein the first and second S / D epitaxial structures are separated by a semiconductor nanosheet layer. The semiconductor structure also includes: an isolation structure interposed between the semiconductor layer and each of the first and second S / D epitaxial structures; and a gate stack surrounding the semiconductor nanosheet layer.

[0071] In the above semiconductor structure, the thickness of the isolation structure is between about 10 nm and about 200 nm.

[0072] In the above semiconductor structure, the isolation structure has a hemispherical shape.

[0073] In the above semiconductor structure, the isolation structure has a rectangular shape.

[0074] In the semiconductor structure, the isolation structure extends laterally below the semiconductor nanosheet layer by an amount between about 1 nm and about 3 nm.

[0075] In the above semiconductor structure, the isolation structure is formed in the top of the semiconductor layer.

[0076] In the above semiconductor structure, the isolation structure is formed on the top surface of the semiconductor layer.

[0077] In the above semiconductor structure, the semiconductor layer is a top layer of a semiconductor-on-insulator (SOI) substrate.

[0078] In the above semiconductor structure, the semiconductor layer is the top of the bulk wafer.

[0079] In the above semiconductor structure, the semiconductor nanosheet layers are vertically spaced apart by the gate stack in the middle portion of the semiconductor nanosheet layers and by the spacer structure in the edge portion of the semiconductor nanosheet layers.

[0080] In some embodiments, the semiconductor structure includes: a semiconductor layer having an S / D epitaxial structure pair, the S / D epitaxial structure having opposite inclined inner sidewalls disposed on the semiconductor layer; a nanosheet layer connecting the inclined inner sidewalls of the S / D epitaxial structure pair; an isolation structure inserted between the semiconductor layer and the S / D epitaxial structure pair. The semiconductor structure also includes a gate stack surrounding the nanosheet layer.

[0081] In the above semiconductor structure, the nanosheet layers have different lengths.

[0082] In the above semiconductor structure, the nanosheet layer includes silicon or silicon germanium.

[0083] In the above semiconductor structure, the gate stack is isolated from the opposite inclined inner sidewalls of the S / D epitaxial structure pair by a spacer structure, and the spacer structure has a convex surface contacting the gate stack and an inclined surface contacting the opposite inclined inner sidewalls of the S / D epitaxial structure pair.

[0084] In the above semiconductor structure, the middle portion of the nanosheet layer is covered by the gate stack, and the edge portion of the nanosheet layer is covered by the spacer structure.

[0085] In the above semiconductor structure, the middle portion of the nanosheet layer is thinner than the edge portion.

[0086] In some embodiments, a method includes: forming a vertical structure on a semiconductor layer, the vertical structure including alternating first and second nanosheet layers; forming a first gate structure around a middle portion of the vertical structure and on a portion of the semiconductor layer, wherein an edge portion of the vertical structure is not covered by the first gate structure. The method also includes removing the edge portion of the vertical structure; etching the edge portion of the first nanosheet layer from the vertical structure in a lateral direction. In addition, the method includes: forming a spacer structure adjacent to each etched edge portion of the first nanosheet layer; forming an isolation structure in the top of the semiconductor layer not covered by the first gate structure. In addition, the method includes forming a source / drain (S / D) epitaxial layer on each isolation structure, wherein an edge portion of the second nanosheet layer contacts the S / D epitaxial layer; removing the first gate structure from the vertical structure. The method also includes removing the first nanosheet layer from the vertical structure; and forming a second gate structure around the second nanosheet layer.

[0087] In the above method, forming the spacer structure includes a directional oxidation or nitridation process.

[0088] In the above method, forming the spacer structure includes: depositing a capping layer on the first gate structure and on the etched edge portion of the first nanosheet layer, wherein during the formation of the isolation structure, a portion of the capping layer that is not adjacent to the etched edge portion of the first nanosheet layer is oxidized; and removing the oxidized portion of the capping layer to form the spacer structure.

[0089] In the above method, forming the isolation structure includes: forming the isolation structure at a resistivity greater than about 1×10 10 An oxide or nitride having a thickness of at least 10 nm is formed on top of the ohmic semiconductor layer.

[0090] It should be understood that the "Detailed Description" section, rather than the "Abstract" section, is intended to explain embodiments of the present invention. As the inventors intended, the abstract of the disclosure section may set forth one or more but not all possible embodiments of the present disclosure, and therefore, is not intended to limit the embodiments of the present invention in any way.

[0091] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: Semiconductor layer; A first source / drain epitaxial structure and a second source / drain epitaxial structure are disposed on the semiconductor layer, wherein the first source / drain epitaxial structure and the second source / drain epitaxial structure are separated by a semiconductor nanosheet layer; an isolation structure interposed between the semiconductor layer and each of the first source / drain epitaxial structure and the second source / drain epitaxial structure; and a gate stack surrounding the semiconductor nanosheet layer, wherein the semiconductor nanosheet layers are vertically spaced apart by the gate stacks in the middle portions of the semiconductor nanosheet layers and by spacer structures in the edge portions of the semiconductor nanosheet layers, and wherein the isolation structures extend laterally below the spacer structures and are in physical contact with bottom surfaces of the respective spacer structures.

2. The semiconductor structure according to claim 1, wherein: The thickness of the isolation structure is between about 10 nm and about 200 nm, wherein about means that the value of a given quantity varies within a range of ±5% of the value.

3. The semiconductor structure according to claim 1, wherein: The nanosheets have different lengths.

4. The semiconductor structure according to claim 1, wherein: The isolation structure has a rectangular shape.

5. The semiconductor structure according to claim 1, wherein: The isolation structure extends laterally below the semiconductor nanosheet layer by an amount between about 1 nm and about 3 nm, wherein about means that the value of a given quantity varies within a range of ±5% of the value.

6. The semiconductor structure according to claim 1, wherein: The isolation structure is formed in a top portion of the semiconductor layer.

7. The semiconductor structure according to claim 1, wherein: The isolation structure is formed on a top surface of the semiconductor layer.

8. The semiconductor structure according to claim 1, wherein: The semiconductor layer is the top layer of the semiconductor-on-insulator substrate.

9. The semiconductor structure according to claim 1, wherein: The semiconductor layer is on top of the bulk wafer.

10. The semiconductor structure according to claim 1, wherein: The isolation structure has a hemispherical shape.

11. A semiconductor structure comprising: Semiconductor layer; a source / drain epitaxial structure pair having oppositely inclined inner sidewalls, disposed on the semiconductor layer; a nanosheet layer connecting the inclined inner sidewalls of the source / drain epitaxial structure pair; an isolation structure interposed between the semiconductor layer and the source / drain epitaxial structure pair; as well as a gate stack surrounding the nanosheet layer, wherein the gate stack is isolated from the opposing inclined inner sidewalls of the source / drain epitaxial structure pair by a spacer structure, and wherein the isolation structure extends laterally below the spacer structure and is in physical contact with a bottom surface of the corresponding spacer structure.

12. The semiconductor structure according to claim 11, wherein: The nanosheets have different lengths.

13. The semiconductor structure according to claim 11, wherein: The nanosheet layer includes silicon or silicon germanium.

14. The semiconductor structure according to claim 11, wherein: The spacer structure has a convex surface in contact with the gate stack and an inclined surface in contact with the opposing inclined inner sidewalls of the pair of source / drain epitaxial structures.

15. The semiconductor structure according to claim 14, wherein: A middle portion of the nanosheet layer is covered by the gate stack, and an edge portion of the nanosheet layer is covered by the spacer structure.

16. The semiconductor structure according to claim 15, wherein: The middle portion of the nanosheet layer is thinner than the edge portion.

17. A method of forming a semiconductor structure, comprising: forming a vertical structure on the semiconductor layer, the vertical structure comprising alternating first nanosheet layers and second nanosheet layers; forming a first gate structure around a middle portion of the vertical structure and on a portion of the semiconductor layer, wherein an edge portion of the vertical structure is not covered by the first gate structure; removing the edge portion of the vertical structure; etching an edge portion of the first nanosheet layer in a lateral direction from the vertical structure; forming a spacer structure adjacent to each etched edge portion of the first nanosheet layer; forming an isolation structure in a top portion of the semiconductor layer not covered by the first gate structure; forming a source / drain epitaxial layer on each isolation structure, wherein an edge portion of the second nanosheet layer is in contact with the source / drain epitaxial layer; removing the first gate structure from the vertical structure; removing the first nanosheet layer from the vertical structure; and forming a second gate structure around the second nanosheet layer, Wherein, the isolation structure extends laterally below the spacer structure and is in physical contact with the bottom surface of the corresponding spacer structure.

18. The method for forming a semiconductor structure according to claim 17, wherein: Forming the spacer structure includes a directional oxidation or nitridation process.

19. The method for forming a semiconductor structure according to claim 17, wherein: Forming the spacer structure includes: depositing a capping layer on the first gate structure and on the etched edge portion of the first nanosheet layer, wherein a portion of the capping layer not adjacent to the etched edge portion of the first nanosheet layer is oxidized during formation of the isolation structure; and An oxidized portion of the capping layer is removed to form the spacer structure.

20. The method for forming a semiconductor structure according to claim 17, wherein: The isolation structure includes forming the isolation structure in a manner that the resistivity is greater than about 1×10 10 An oxide or nitride having a thickness of at least 10 nm is formed in the top portion of the semiconductor layer of about ohm·meter, wherein about means that the value of a given quantity varies within a range of ±5% of the value.

Images