Circuit of ring configuration, method of operating a circuit and phase-locked loop

Abstract

Circuits configured in a ring, methods of operating the circuits, and phase-locked loops are disclosed. According to embodiments, a ring oscillator includes a plurality of stages coupled in a ring configuration, wherein each stage of the plurality of stages has an input node coupled to an output node of a preceding stage of the plurality of stages. Each stage of the plurality of stages includes a ring oscillator transistor having a control node coupled to the input node and a load path coupled to the output node, and a direct injection circuit having a control node coupled to the first oscillator input node and a load path coupled between the control node and the output node of the ring oscillator transistor, a tail injection circuit having a control node coupled to the second oscillator input node and a load path coupled between the output node and a first supply node.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to injection circuitry and methods. BACKGROUND

[0002] Phase-locked loop (PLL) circuits are often used in radio frequency (RF) systems to generate high frequency signals that are either directly transmitted in the case of radar systems or used to modulate transmitted RF signals and demodulate received RF signals. Essentially, a PLL circuit is a feedback loop that controls the frequency of a high frequency oscillator such as a voltage controlled oscillator (VCO) by comparing the phase of a lower frequency reference signal to a divided down output of the high frequency oscillator. For example, a 10 MHz crystal oscillator can be used to control the frequency of a 1 GHz VCO by dividing the frequency of the 1 GHz VCO by 100 and using a phase detector circuit to compare the 10 MHz crystal oscillator signal to the divided down VCO signal.

[0003] Circuits used to divide the frequency of a VCO typically include a prescaler followed by a programmable frequency divider. The design of a prescaler is particularly challenging because at least a portion of the prescaler operates at the same frequency as the VCO. Many systems use a current mode logic (CML) prescaler, however, CML based prescalers are prone to high power consumption that increases with frequency. A low power option for a prescaler is an injection locked frequency divider (ILFD); however, the problem with using an ILFD based prescaler (also known as an injection locked prescaler) compared to a CML based prescaler is a reduced frequency operating range. SUMMARY

[0004] According to an embodiment, a ring oscillator includes a plurality of stages coupled in a ring configuration, wherein a stage of the plurality of stages has an input node coupled to an output node of a preceding stage of the plurality of stages. Each stage of the plurality of stages includes a ring oscillator transistor having a control node coupled to the input node and a load path coupled to the output node, a direct injection circuit having the load path coupled between the output node and the control node of the ring oscillator transistor and a control node coupled to a first oscillator input node, and a tail injection circuit having the load path coupled between the output node and a first supply node and a control node coupled to a second oscillator input node.

[0005] According to another embodiment, a method of operating a circuit including an injection-locked frequency divider (ILFD) having a plurality of stages coupled in a ring configuration, the method including injecting an oscillator signal in each of the plurality of stages using a respective direct injection circuit coupled between an input node and an output node of each of the plurality of stages, and injecting the oscillator signal at the output node of each of the plurality of stages using a respective tail injection circuit coupled between a first power supply node and the output node of each of the plurality of stages.

[0006] According to a further embodiment, a phase-locked loop includes an injection-locked prescaler including a ring oscillator, wherein each respective stage of the ring oscillator includes a respective direct injection circuit coupled between an input and an output of each respective stage, and a tail injection circuit coupled between the output of each respective stage and a power supply node, a phase detector having an input coupled to an output of at least one stage of the ring oscillator, and a voltage-controlled oscillator having an oscillator signal output coupled to each respective direct injection circuit and coupled to each respective tail injection circuit, and a frequency control input coupled to an output of the phase detector. BRIEF DESCRIPTION OF DRAWINGS

[0007] For a more complete understanding of the present application, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings in which:

[0008] Figure 1 is a block diagram of an embodiment of a PLL;

[0009] Figure 2A is a block diagram of an embodiment of an injection-locked frequency divider (ILFD); Figure 2B is a schematic diagram of a circuit implementation of a stage of the ILFD of Figure 2A ; and Figure 2C is a waveform diagram illustrating operation of the ILFD of Figure 2A ; and

[0010] Figure 3A is a block diagram of another embodiment of an ILFD; Figure 3B and Figure 3C is a schematic diagram of a circuit implementation of a stage of the ILFD of Figure 3A ; and

[0011] Figure 4A is a block diagram of another embodiment of an ILFD utilizing a phase shifter; and Figure 4B is a schematic diagram of an embodiment of a phase shifter;

[0012] Figure 5A shows a schematic diagram of an ILFD according to another embodiment; and Figure 5B is a schematic diagram showing an ILFD according to another embodiment; and Figure 5Awaveform diagrams of operation of an ILFD;

[0013] Figure 6A and Figure 6B shows a schematic diagram of an ILFD according to another embodiment;

[0014] Figure 7 shows a radar system utilizing an ILFD according to an embodiment; and

[0015] Figure 8 shows a block diagram of an embodiment of a method.

[0016] Unless otherwise indicated, corresponding reference characters in different figures generally refer to corresponding parts. The drawings are drawn to clearly illustrate relevant aspects of the preferred embodiments and are not necessarily drawn to scale. Letters indicating variations of the same structure, material, or process step can follow the reference characters in order to more clearly illustrate certain embodiments. DETAILED DESCRIPTION

[0017] The manufacture and use of the presently preferred embodiments will now be discussed in detail. It should be understood, however, that the present application provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the application, and do not limit the scope of the application.

[0018] The present application will be described in the particular context of a preferred embodiment, a system and method for a prescaler in a phase-locked loop that is implemented using an injection-locked frequency divider (ILFD). However, the present application can be applied to injection-locked oscillators used in other applications.

[0019] In embodiments of the present application, a ring oscillator includes a plurality of stages arranged in a ring configuration. In addition to the circuitry including the ring oscillator, other devices are used to provide injection signal paths into the ring oscillator. For example, in some embodiments, each stage of the ring oscillator includes a direct injection circuit coupled between an input and an output of each stage, and a tail injection circuit coupled to the output of each stage. By using multiple injection paths for each stage of the ring oscillator, the locking range of the ring oscillator can be increased. Thus, embodiments of the present application provide a way to implement a prescaler circuit that has a small chip area, low power consumption, and a wide locking range. For example, some embodiments of the ILFD circuit have a power consumption of less than 10 mW and a locking range of at least 30%.

[0020] Figure 1A block diagram of a PLL circuit 100 is shown, which includes a phase detector 102, a low pass filter 104, a VCO 106, a pre-divider 108, and an N-division counter 110. In embodiments of the invention, the PLL circuit 100 can be used to provide a VCO signal at node OUT having a frequency that is higher than a frequency of a reference clock signal at node REF. During operation, the phase detector 102 compares the phase of the reference clock signal at node REF to the phase of the divided oscillator signal at node DIV and provides a phase detection signal to a frequency control input of the VCO 106. If the phase of the reference clock signal at node REF leads the phase of the divided oscillator signal at node DIV, the output signal of the phase detector 102 (also referred to as the “phase detection signal”) increases, which causes the frequency of the VCO 106 to correspondingly increase. The input to the VCO can be referred to as a “VCO control signal” or a “frequency control input.” On the other hand, if the phase of the reference clock signal at node REF lags the phase of the divided oscillator signal at node DIV, the output signal of the phase detector 102 decreases, which causes the frequency of the VCO 106 to correspondingly decrease. The phase detector 102 can be implemented using phase detector circuits and / or phase frequency detector circuits known in the art. One commonly used phase frequency detector circuit includes one or more digital latch circuits followed by a charge pump. In such a circuit, the charge pump is configured to provide a current of a first polarity during a time period between when the divided oscillator signal is asserted and when the reference clock signal is asserted (when the reference clock signal at node REF leads the divided clock signal at node DIV), and is configured to provide a current of a second polarity opposite the first polarity during a time period between when the divided oscillator signal is asserted and when the reference clock signal is asserted (when the reference clock signal at node REF lags the divided clock signal at node DIV).

[0021] In some embodiments, the current pulses provided by the charge pump of the phase detector 102 are filtered by the low pass filter 104, which can also be referred to as a loop filter. The low pass filter 104 can be implemented using any suitable low pass filter circuit known in the art. For example, the low pass filter 104 can be implemented using at least one capacitor to filter the current pulses. The low pass filter 104 can also include additional components, such as additional capacitors and one or more resistors for shaping the loop dynamics of the PLL. In some embodiments, an active loop filter can be used.

[0022] The VCO 106 for generating an RF oscillator signal at the oscillator signal output can be implemented using any suitable RF VCO signal known in the art. For example, in some embodiments, the VCO 106 can be implemented using a Colpitts oscillator or a negative resistance oscillator including an LC tank circuit. In some embodiments, the VCO 106 is configured to oscillate at frequencies of about 30 GHz and higher, although lower frequencies are also possible.

[0023] The pre-divider 108 is configured to divide the frequency of the RF oscillator signal to a lower frequency. For example, in some embodiments, the pre-divider 108 is implemented as an ILFD configured to divide by a factor of five or seven, although other division ratios are possible. In some embodiments, the pre-divider 108 can have a programmable division ratio and can function as a dual modulus pre-divider. Circuit implementations of the pre-divider 108 will be further described with respect to the embodiments disclosed herein.

[0024] The N-dividing counter 110 is configured to provide further division of the divided RF oscillator signal provided by the pre-divider 108 and can be implemented using divider circuits known in the art. In one example, the N-dividing counter 110 is implemented using a counter such that the frequency at the input of the N-dividing counter 110 is an integer multiple of the frequency at the output of the N-dividing counter 110. In some embodiments, the N-dividing counter 110 can be implemented using a pulse-swallowing counter, a dual modulus counter, or a combination thereof to form a fractional-N counter. In some embodiments, the division ratio of the N-dividing counter 110 is programmable.

[0025] In various embodiments, all or a portion of the PLL 100 can be implemented as an integrated circuit disposed on a signal semiconductor substrate, such as a silicon substrate. In other embodiments, the various components of the PLL 100 can be divided across multiple integrated circuits and passive components. In one particular embodiment, the phase detector 102, the VCO 106, the pre-divider 108, and the N-dividing counter are implemented on an integrated circuit, while at least a portion of the low pass filter 104 is implemented using external components (e.g., one or more external capacitors). In some embodiments, the components included in the PLL 100 are disposed on a printed circuit board (PCB). The PLL 100 can also be integrated with other components of an RF system.

[0026] Figure 2A An exemplary implementation of the N-dividing counter 110 is shown in FIG. 2. The N-dividing counter 110 includes a pulse-swallowing counter 202 and a dual modulus counter 204. The pulse-swallowing counter 202 is configured to divide the frequency of the input signal by a factor of two. The pulse-swallowing counter 202 includes a first input 206, a second input 208, and an output 210. The first input 206 is coupled to receive the input signal. The second input 208 is coupled to receive a clock signal. The output 210 is coupled to provide the divided signal. Figure 1The ILFD 200 of the prescaler 108 is shown. As shown, the ILFD 200 is implemented as a ring oscillator, and includes a plurality of ring oscillator stages 206 coupled in a ring configuration. For example, the output of each ring oscillator stage 206 is coupled to the input of the immediately subsequent ring oscillator stage. In the embodiment shown, there are five ring oscillator stages. However, in alternative embodiments of the present application, any odd number of stages can be used. Each ring oscillator stage 206 is coupled to a respective direct injection circuit 204 and a tail injection circuit 202. Each respective direct injection circuit is connected between the input of its corresponding ring oscillator stage and the output of its corresponding ring oscillator stage. Each tail injection circuit 202 is coupled to the output of its corresponding ring oscillator stage 206. Figure 2A In the embodiment shown, there are five ring oscillator stages. However, in alternative embodiments of the present application, any odd number of stages can be used. Each ring oscillator stage 206 is coupled to a respective direct injection circuit 204 and a tail injection circuit 202. Each respective direct injection circuit is connected between the input of its corresponding ring oscillator stage and the output of its corresponding ring oscillator stage. Each tail injection circuit 202 is coupled to the output of its corresponding ring oscillator stage 206.

[0027] During operation, a VCO signal, such as the RF oscillator signal provided by the VCO 106 shown in Figure 1 is provided to the tail injection circuits 202 and the direct injection circuits 204. Each of these injection circuits injects a portion of the RF oscillator signal provided at the node INJ (also referred to as the "oscillator input node"). Thus, the frequency of the ILFD 200 is locked to a subharmonic of the RF oscillator signal. In the particular case of the embodiment shown, the operating frequency of the ILFD 200 is one fifth of the frequency of the RF oscillator signal. Thus, the ILFD 200 acts as a five-to-one prescaler with respect to the RF oscillator signal. For example, if the RF oscillator signal is 30 GHz, the ILFD 200 will oscillate at a frequency of 6 GHz. Figure 2A

[0028] In some embodiments, the direct injection circuits 204 and the tail injection circuits 202 are configured to have varying impedances with respect to the RF oscillator signal. For example, the tail injection circuits 202 can be configured to have a low impedance when the RF oscillator signal at the node INJ is at a lower voltage, while the direct injection circuits 204 can be configured to have a low impedance when the RF oscillator signal at the node INJ is near its peak voltage. One example of such a circuit configuration is shown in Figure 2B which shows a circuit 220 implementing a ring oscillator stage 206 and its associated direct injection circuit 204 and tail injection circuit 202.

[0029] In the embodiment shown, the direct injection circuit 204 is implemented as a diode-connected transistor 222, and the tail injection circuit 202 is implemented as a diode-connected transistor 224. In the embodiment shown, the diode-connected transistor 222 is connected between the input of the ring oscillator stage 206 and the output of the ring oscillator stage 206, while the diode-connected transistor 224 is connected between the output of the ring oscillator stage 206 and ground. In alternative embodiments of the present application, other circuit configurations can be used to implement the direct injection circuits 204 and the tail injection circuits 202. For example, in some embodiments, the direct injection circuits 204 and the tail injection circuits 202 can be implemented as resistors, inductors, or other circuit elements. Figure 2B ​In an embodiment, the ring oscillator element 206 is implemented using an NMOS transistor M2, the tail injection circuit 202 is implemented using a PMOS transistor Ml, and the direct injection circuit 204 is implemented using an NMOS transistor M3. The RF oscillator signal is provided at nodes INJl and INJ2. As shown, the RF oscillator signal at INJl is provided to the gate of PMOS transistor Ml via an AC coupling capacitor Cl. Similarly, the RF oscillator signal at INJ2 is provided to the gate of NMOS transistor M3 via an AC coupling capacitor C2. Resistor Rl is used to provide a DC bias to the gate of PMOS transistor Ml, and resistor R2 is used to provide a DC bias to the gate of NMOS transistor M3.

[0030] Although embodiments of the application are described herein using NMOS devices and PMOS devices that can be implemented using CMOS technology fabricated on a semiconductor substrate such as a silicon substrate, it should be understood that embodiments of the application can be implemented in other technologies using other device types. For example, JFETs and / or bipolar junction transistors (BJTs) can be used in place of MOS devices. The gates of the NMOS transistors and PMOS transistors described herein can also be referred to as "control nodes," and the circuit paths between the drains and sources of the NMOS transistors and PMOS transistors can be referred to as "load paths." The terms "control node" and "load path" also apply to non-MOS devices. For example, the base of a bipolar junction transistor can also be referred to as a "control node," and the circuit path between the collector and emitter can be referred to as a "load path."

[0031] During operation, the NMOS transistor M2 (also referred to as a "ring oscillator transistor") amplifies the input signal at the input node IN and provides an amplified and inverted signal at the output node OUT. This amplified signal propagates around the ring oscillator. For the tail injection circuit 202 implemented by PMOS transistor Ml, as the voltage of the RF oscillator signal at node INJl decreases, the PMOS transistor Ml begins to conduct and provides a low impedance path between the output node OUT and the power supply terminal VDD. On the other hand, as the voltage of the RF oscillator signal at node INJl increases, the PMOS transistor Ml is cut off and provides a higher impedance path between the output node OUT and the power supply terminal VDD. Thus, the operation of the ring oscillator becomes such that the timing of the peak voltage at node OUT becomes synchronized with the negative peak of the RF oscillator signal coupled to node INJl.

[0032] For the direct injection circuit 202 implemented by the NMOS transistor M3, as the voltage of the RF oscillator signal at node INJ2 increases, the NMOS transistor M3 begins to conduct and provide a low impedance path between the input node IN and the output terminal OUT. As the voltage of the RF oscillator signal at node INJ2 decreases, the NMOS transistor M3 turns off and provides a higher impedance path between the input node IN and the output node OUT. Thus, the operation of the ring oscillator becomes such that the time during which the voltage at node OUT equals the voltage at node IN during an oscillation cycle becomes synchronized with the positive peak of the RF oscillator signal coupled to node INJ2.

[0033] In some implementations, both nodes INJ1 and INJ2 are coupled to the output VCO 106 and are configured to have the same phase. In other implementations, one or more phase shifters can be used to adjust the relative phase of the signals at nodes INJ1 and INJ2. For example, in some implementations, the RF oscillator signal at node INJ1 can be 180 degrees out of phase with the RF oscillator signal at node INJ2. It will be appreciated that, Figure 2B The illustrated circuit level implementation is merely one of many ways to implement Figure 2A The illustrated ILFD 200 is one of many ways to implement an ILFD. In alternative implementations, other circuits can be used. For example, the ring oscillator stage 206 can be implemented using PMOS transistors instead of the NMOS transistor M2, or can be implemented using other transistor types known in the art; the NMOS transistor M3 used to implement the direct injection circuit 204 can be implemented using a PMOS transistor or other type of transistor; the PMOS transistor M1 used to implement the tail injection circuit 202 can be implemented using other transistors. In some implementations, the tail injection circuit 202 can be implemented using an NMOS transistor coupled between node OUT and ground.

[0034] Figure 2C The illustration shows when Figure 2B The circuit of FIG. 1 is used to implement each stage of the ring oscillator, Figure 2AA waveform diagram showing the relationship between the RF oscillator signal at node INJ of ILFD 200 and the individual output voltages o1, o2, o3, o4, and o5 of the ring oscillator stages 206. Since the tail injection circuit 202 provides a lower impedance between the supply node and the ring oscillator outputs o1, o2, o3, o4, and o5 via PMOS transistor M1, each negative peak of the RF oscillator signal at node INJ corresponds to a positive peak of one of the ring oscillator output signals at nodes o1, o2, o3, o4, and o5. For example, the negative peaks of the RF oscillator signal at node INJ at times t1, t3, t5, t7, and t9 correspond to the positive peaks of the ring oscillator output signals at nodes o1, o3, o5, o2, and o4, respectively.

[0035] With respect to the direct injection circuit 204 providing a lower impedance between the input and output of each stage 206 of the ring oscillator via NMOS transistor M3, a positive peak of the RF oscillator signal at node INJ corresponds to each time the voltage between the input and output of a ring oscillator stage 206 is approximately equal. For example, at time t2, the signals o4 and o5 corresponding to the input and output of the fifth oscillator stage 206 are approximately equal; at time t4, the signals o1 and o2 corresponding to the input and output of the first oscillator stage 206 are approximately equal; at time t6, the signals o3 and o4 corresponding to the input and output of the fifth oscillator stage 206 are approximately equal; and at time t8, the signals o4 and o5 corresponding to the input and output of the fifth oscillator stage 206 are approximately equal.

[0036] Figure 3A An ILFD 300 of a pre-divider 108 is also shown that can be used to implement Figure 1 The ILFD 300 of a pre-divider 108 is also shown that can be used to implement Figure 2A The ILFD 300 of a pre-divider 108 is also shown that can be used to implement

[0037] In some embodiments, the side injection circuit 306 is configured to effectively increase the gain of the direct injection circuit 204 during portions of the waveform cycle where the input and output voltages may cross each other, and decrease the gain of the direct injection circuit 204 during their associated ring oscillator cycles where the input and output voltages are unlikely to cross each other. Therefore, by applying a certain output sequence to the side injection circuit 306, gain conversion can be optimized, and in some embodiments, the useful injection of the system can be optimized.

[0038] It should be understood that Figure 3A The ILFD 300 is just one of many possible configurations of an ILFD utilizing side injection. In alternative embodiments, the relative positions of the direct injection circuit 204 and the side injection circuit 306 can be reversed. For example, the side injection circuit 306 can have its input coupled to the input of the ring oscillator element 206, and the direct injection circuit 204 can have its input coupled to the output of the side injection circuit 306 and its output coupled to the output of its respective ring oscillator element 206. In addition to or instead of the side injection circuit 306 coupled in series with the direct injection circuit 204, the side injection circuit can also be coupled in series with the tail injection circuit 202. It should also be understood that the ILFD 300 can have more or fewer ring oscillator elements than the five depicted ring oscillator elements 206 to achieve other division ratios.

[0039] Figure 3B A schematic diagram of circuit 320 is shown, which is Figure 3A The diagram illustrates an example implementation of the direct injection circuit 204, tail injection circuit 202, side injection circuit 306, and ring oscillator element 206. As shown, the ring oscillator element 206 is implemented using an NMOS transistor M2, the tail injection circuit 202 using a PMOS transistor M1, the direct injection circuit 204 using an NMOS transistor M3, and the side injection circuit 306 using a PMOS transistor M4. The RF oscillator signal at INJ1 is provided to the gate of the PMOS transistor M1 via an AC coupling capacitor C1, and a resistor R1 provides DC bias to the gate of the PMOS transistor M1. The gate of the PMOS transistor used to implement the side injection circuit 306 is coupled to node IN.

[0040] Figure 3B The operation of circuit 320 is similar to Figure 2BThe operation of the circuit 220 shown is similar to that of the circuit 220 shown in Figure 3A and Figure 3B except that when the voltage at the node IN is low (thereby turning on the PMOS transistor M4) and the voltage at the node INJ1 is high (thereby turning on the NMOS transistor M3), a series combination of the NMOS transistor M3 and the PMOS transistor M4 is used to provide a low impedance path between the node IN and the node OUT. It will be appreciated that in alternative embodiments of the application, the NMOS transistor M3 can be implemented using a PMOS transistor and / or the PMOS transistor M4 can be implemented using an NMOS transistor. Furthermore, the signal side injection circuit 306 can be different from that shown in the specific example of Figure 3A and Figure 3B . For example, the gate of the transistor M4 can be driven by a different stage to the immediately preceding stage and / or the signal driving the gate of the transistor M4 can be phase shifted.

[0041] Figure 3C A schematic diagram of a circuit 330 is shown, which is an example implementation of the direct injection circuit 204, the side injection circuit 306 and the ring oscillator element 206, in which the side injection circuit 306 is coupled in series with the tail injection circuit 202. As shown, the ring oscillator element 206 is implemented using an NMOS transistor M2, the tail injection circuit 202 is implemented using a PMOS transistor M1, the direct injection circuit 204 is implemented using an NMOS transistor M3 and the side injection circuit 306 is implemented using a PMOS transistor M5. The RF oscillator signal at INJ1 is provided to the gate of the PMOS transistor M1 via an ac coupling capacitor CI, and a resistor R1 is used to provide a dc bias to the gate of the PMOS transistor M1. The gate of the PMOS transistor M5 used to implement the side injection circuit 306 is coupled to the node IN.

[0042] Figure 3B The operation of the circuit 320 is similar to that of the circuit 220 shown in Figure 2B except that when the voltage at the node IN is low (thereby turning on the PMOS transistor M5) and the voltage at the node INJ1 is high (thereby turning on the NMOS transistor M4), a series combination of the PMOS transistor M1 and the PMOS transistor M5 is used to provide a low impedance path between the supply node VDD and the node OUT.

[0043] In some embodiments of the application, the injected RF oscillator signal can be phase shifted before being injected into the ring oscillator. In Figure 4AAn example of such a system is shown, illustrating an ILFD 400 comprising a ring oscillator 402 and a phase shifter 404. As shown, the phase shifter 404 generates n phase-shifted injection signals INJ1 to INJn based on the input RF oscillator signal at node INJin. In one embodiment, the phase of INJin is selectively shifted by 0° or 180° based on a selection signal SEL. Therefore, each of the n phase-shifted signals can have a phase shift of 0° or 180°. In alternative embodiments of the invention, the phase shifter 404 can implement phase shifts other than 0° or 180°.

[0044] Figure 4B A phase shifter circuit 406 is shown that can be used to phase shift a single phase-shifted signal. In some embodiments, the phase shifter circuit 406 can be used to implement... Figure 4A The phase shifter 404 shown is a phase shifting channel. In an embodiment, the phase shifter circuit 406 includes a multiplexer 410 and an inverter 412. During operation, the selection signal SEL causes the multiplexer 410 to select either the RF oscillator signal at node INJin (which represents a 0° phase shift) or an inverted version of the RF oscillator signal generated by the inverter 412 (which represents a 180° phase shift). In various embodiments, a total of n phase shifter circuits 406 can be used to implement... Figure 4A The phase shifter 404 is shown. It should be understood that the phase shifter circuit 406 is merely one of many exemplary phase shifter circuits that can be used to implement the phase shifting function of the embodiments.

[0045] Figure 5A An ILFD 500 according to another embodiment of the present invention is shown, which can be used to implement Figure 1 The prescaler 108 is shown. As shown, the ILFD 500 includes seven stages 504 coupled in a ring configuration. Each stage 504 includes a PMOS transistor M1 that performs the function of the tail injection circuit 202 as described in the above embodiments, an NMOS transistor M3 that performs the function of the direct injection circuit 204, and an NMOS transistor M2 that implements the function of the ring oscillator stage 206. In addition to the seven stages 504, a phase shifter 502 is also included to perform a 180° phase shift of the RF oscillator signal at node INJin. In some embodiments, the above-described... Figure 4B The phase shifter 406 described implements the phase shifter 502. The operation of the ILFD 500 is similar to that discussed above. Figure 2AThe operation of the ILFD 500 shown in FIG. 5 is similar to that of the ILFD 200 shown in FIG. 2, except that the ILFD 500 acts as a seven-division prescaler due to its seven stages, rather than the ILFD 200 having five stages acting as a five-division prescaler. In addition, the relationship between the RF oscillator signal at the node INJin and the peak shifts of the outputs o1, o2, o3, o4, o5, o6, and o7 is modified due to the phase shifter 502, as shown in the waveform diagram of FIG. 6. Figure 5B

[0046] Figure 5B A waveform diagram showing the relationship between the RF oscillator signal at the node INJin and the respective output voltages of the stages 504 of the ILFD 500 shown in FIG. 5 is shown in FIG. 7. Figure 5A Figure 2B Figure 2B As a result of the PMOS transistor M1 providing a lower impedance between the supply node and the ring oscillator outputs o1, o2, o3, o4, o5, o6, each positive peak of the RF oscillator signal at the node INJin corresponds to a positive peak of one of the ring oscillator output signals o1, o2, o3, o4, o5, o6, and o7. Because the phase shifter 502 inverts the phase of the RF oscillator signal before driving the gate of the PMOS transistor M1, the relationship between the peaks of the RF oscillator signal and the peaks of the output signals is different from that shown in the waveform diagram of FIG. 3, in which a positive peak of the output signal corresponds to a positive peak of the RF oscillator signal.

[0047] As shown in FIG. 5, at time tl, when the RF oscillator signal at the node INJin is at its peak voltage level, the output o1 is at its peak signal level due to the PMOS transistor M1 being turned on, and the outputs o4 and o5 have substantially equal voltage levels due to the NMOS transistor M3 being turned on. Similarly, at time t2, when INJin is at its peak voltage level, the output o3 is at its peak voltage level, and the outputs o6 and o7 have substantially equal voltage levels; at time t3, the output o5 is at its peak voltage level, and the outputs o1 and o2 have substantially equal voltage levels; at time t4, the output o7 is at its peak voltage level, and the outputs o3 and o4 have substantially equal voltage levels; at time t5, the output o2 is at its peak voltage level, and the outputs o5 and o6 have substantially equal voltage levels; at time t6, the output o4 is at its peak voltage level, and the outputs o7 and o1 have substantially equal voltage levels; at time t7, the output o6 is at its peak voltage level, and the outputs o2 and o3 have substantially equal voltage levels. Figure 5B

[0048] ​​​​In some implementations, phase shift circuit 502 can also be configured to selectively provide a 0-degree phase shift via selection signal SEL. Selectively changing the phase can be used to adjust or optimize the performance of IFLD 500, or to adjust the phase of the RF oscillator signal to suit a dual-mode prescaler. For example, in some implementations, two stages in stage 504 can be disabled (e.g., by routing output signal o5 instead of routing output signal o7 to the input of the first stage 504), and the phase shift of phase shift circuit 502 can be configured to have a 0° phase shift to selectively implement a divide-by-five prescaler. During operation as a divide-by-seven prescaler, all seven stages 504 are activated as shown, and phase shift circuit 502 is configured to have a 180-degree phase shift.

[0049] In addition to the direct injection circuit, side injection circuit, and tail injection circuit mentioned above, in situations such as Figures 6A-6B In the embodiments of the present invention shown, additional injection paths are possible. Figures 6A-6B Two instances of the aforementioned level 504 are shown that interact with the additional device interface.

[0050] As described above, stage 504 includes a PMOS transistor M1 implementing a tail injection circuit, an NMOS transistor M2 implementing a ring oscillator stage, and an NMOS transistor M3 implementing a direct injection circuit. The gate of transistor M1 is shown coupled to a first injection node INJ1, the gate of transistor M3 is shown coupled to a second injection node INJ2, and the gate of transistor M2 is shown coupled to the output of the preceding ring oscillator stage. In addition to these devices, an inverter stage 602 is included, the output of which is coupled to node o2 at the output of the first instance of stage 504 to provide additional tail injection. Inverter stage 602 includes a PMOS device M8 and an NMOS device M9, the gate of PMOS device M8 being connected to a third injection node INJ3, and the gate of NMOS device M9 being coupled to a fourth injection node INJ4. Therefore, each of the PMOS device M8 and the NMOS device M9 serves as an additional tail injection circuit. Another direct injection circuit 604 is coupled between node o1 at the input of the first instance of stage 504 and the output of the second instance of stage 504. This other injection circuit 604 includes an NMOS transistor M7, the gate of which is coupled to a fifth injection node INJ5. In some embodiments, one or more of transistors M1, M3, M7, M8, or M9 may be omitted. In other embodiments, as described above... Figures 3A to 3CAs described, side injection functionality can also be added by coupling the side injection circuits in series with either the PMOS transistor Ml or the NMOS transistor Ml. Thus, embodiments of the present application can include any combination of the injection circuits described above. In various embodiments, each of the injection nodes INJ1, INJ2, INJ3, INJ4, and INJ5 is configured to provide an RF oscillator signal with either a 0° phase shift or a 180° phase shift. These phase shifts can be generated, for example, using the phase shifter circuits described above with respect to Figure 4A and Figure 4B As described above, the injection circuits can be used to implement a pre- divider. Thus, in various embodiments, the pre-divider 108 can be implemented using the injection circuits described above. For example, the pre-divider 108 can be implemented using the injection circuits described above with respect to

[0051] Figure 6B It is shown that the ILFD 620 of the pre-divider 108 shown in Figure 1 FIG. 6 can also be used to implement a pre-divider. As shown, the ILFD 620 includes five stages 504, five inverter stages 602, and five additional direct injection circuits 604 arranged in a ring configuration. Thus, the ILFD can be used as a five-division pre- divider. Each stage 504 is coupled at its output to a respective inverter stage 602, and each additional direct injection circuit 604 is coupled between two adjacent stages 504.

[0052] Generally, the locking range of an embodiment ILFD is proportional to the number of injection paths present in the design. However, it should be appreciated that as the number of injection circuits increases, so does the parasitic loading. This increase in parasitic loading can increase the power consumption of the circuit. Thus, there is a trade-off between the number of injections used in a design and the power consumed by the design.

[0053] Figure 7 A radar system 700 utilizing a pre-divider in accordance with an embodiment of the present application is shown. As shown, the radar system 700 includes a PLL 702, a power amplifier 704, a transmit antenna 706, a receive antenna 708, a low noise amplifier (LNA) 710, a mixer 712, and a low pass filter 714. For example, the pre-divider 108 shown in Figure 1The illustrated PLL 100 including the embodiment prescaler 108 is implemented to realize a PLL 702. During operation, the output frequency of 702 is modulated using a modulation signal MOD. In some implementations, the modulation signal MOD includes a ramp signal so as to realize a series of frequency chirps to implement a frequency modulated continuous wave (FMCW) radar system. The PLL 702 thus generates a local oscillator signal LO having a ramping frequency. The local oscillator signal LO is then amplified by a power amplifier 704, the output of which is transmitted to one or more targets via a transmit antenna 706. RF signals reflected from the one or more targets are received by a receive antenna 708. The received signals are amplified by a LNA 710, mixed with the local oscillator signal LO using a mixer 712 to downconvert the amplified signals to an intermediate frequency (IF). The downconverted signals are then filtered using a low pass filter 714 to form an intermediate frequency signal IF. In implementations using FMCW radar technology, the frequency difference between the RF signals transmitted at the antenna 706 and the reflected signals received at the receive antenna 708 is proportional to the distance between the radar system and the one or more targets. It will be appreciated that Figure 7 The implementation of a FMCW radar system is merely one of many possible systems that can use the prescaler circuits described herein.

[0054] Figure 8 A method 800 of operating an injection-locked prescaler is shown in accordance with implementations of the present application. In step 802, an oscillator signal is injected in each of a plurality of ring oscillator stages using a respective direct injection circuit coupled between an input node and an output node of each of the plurality of ring oscillator stages. In some implementations, the ring oscillator stage 206 and direct injection circuit 204 described in the implementations herein can be used to implement each of the plurality of ring oscillator stages and the direct injection circuit.

[0055] In step 804, an oscillator signal is injected in each of the plurality of ring oscillator stages using a respective tail injection circuit coupled between a first power supply node and an output node of each of the plurality of ring oscillator stages. In some implementations, the tail injection circuit 202 can be used to implement the tail injection circuit.

[0056] Implementations of the present application are summarized here. Other implementations can be appreciated from a reading of the entire specification and claims presented herein.

[0057] Example 1. A circuit comprising: a ring oscillator comprising a plurality of stages coupled in a ring configuration, each stage of the plurality of stages comprising an input node coupled to an output node of a preceding stage of the plurality of stages, wherein each stage of the plurality of stages comprises: a ring oscillator transistor having a control node coupled to the input node and a load path coupled to the output node; a direct injection circuit having a load path coupled between the output node and the control node of the ring oscillator transistor and a control node coupled to a first oscillator input node; and a tail injection circuit having a load path coupled between the output node and a first supply node and a control node coupled to a second oscillator input node.

[0058] Example 2. The circuit of example 1, further comprising: a phase shifter circuit having a first output coupled to the first oscillator input node and a second output coupled to the second oscillator input node, wherein the phase shifter is configured to provide a first oscillator signal having a first phase at the first output and a second oscillator signal at the second output, wherein the first and second oscillator signals are 180 degrees out of phase with each other.

[0059] Example 3. The circuit of one of examples 1 or 2, wherein the ring oscillator transistor, the direct injection circuit, and the tail injection circuit each comprise a MOS transistor.

[0060] Example 4. The circuit of one of examples 1-3, wherein the plurality of stages comprises an odd number of stages.

[0061] Example 5. The circuit of one of examples 1-4, wherein each stage of the plurality of stages further comprises a side injection circuit having a load path coupled in series with the load path of the direct injection circuit.

[0062] Example 6. The circuit of one of examples 1-5, wherein each stage of the plurality of stages further comprises a side injection circuit having a load path coupled in series with the load path of the tail injection circuit.

[0063] Example 7. The circuit of one of examples 1-6, wherein the ring oscillator further comprises an additional direct injection circuit having a load path coupled between an input node of a first stage of the plurality of stages and an output node of a second stage of the plurality of stages.

[0064] Example 8. The circuit of one of Examples 1-7, wherein each stage of the plurality of stages further comprises a further tail injection circuit having a load path coupled between the output node and a second supply node and a control node coupled to the oscillator input node.

[0065] Example 9. A method of operating a circuit comprising an injection-locked frequency divider (ILFD) having a plurality of stages coupled in a ring configuration, the method comprising: injecting an oscillator signal in each stage of the plurality of stages using a respective direct injection circuit coupled between an input node and an output node of each stage of the plurality of stages; and injecting the oscillator signal at the output node of each stage of the plurality of stages using a respective tail injection circuit coupled between a first supply node and the output node of each stage of the plurality of stages.

[0066] Example 10. The method of Example 9, further comprising: injecting an input signal of each stage of the plurality of stages using a respective side injection circuit coupled in series with each respective direct injection circuit.

[0067] Example 11. The method of one of Examples 9 or 10, wherein injecting the oscillator signal at the output node of each stage further comprises using a respective further tail injection circuit coupled between a second supply node and the output node of each stage of the plurality of stages.

[0068] Example 12. The method of one of Examples 9-11, further comprising: injecting the oscillator signal between an input of a first stage of the plurality of stages and an output of a second stage of the plurality of stages using a further direct injection circuit coupled between the input of the first stage of the plurality of stages and the output of the second stage of the plurality of stages.

[0069] Example 13. The method of one of Examples 9-12, further comprising: generating the oscillator signal using a voltage-controlled oscillator; frequency dividing a frequency of an output of the ILFD using a frequency divider circuit to form a frequency divided signal; comparing a phase of the frequency divided signal to a phase of a reference clock using a phase detector to form a phase detection signal; filtering the phase detection signal using a loop filter to form a VCO control signal; and using the VCO control signal to control a frequency of the voltage-controlled oscillator.

[0070] Example 14. The method of one of Examples 9-13, wherein the ILFD is configured to divide a frequency of the oscillator signal by a predetermined number.

[0071] Example 15. The method of Example 14, wherein the predetermined number is odd.

[0072] Example 16. A phase-locked loop comprising: an injection-locked prescaler comprising a ring oscillator, wherein each respective stage of the ring oscillator comprises a respective direct injection circuit coupled between an input and an output of each respective stage, and a tail injection circuit coupled between the output of each respective stage and a supply node; a phase detector having an input coupled to an output of at least one stage of the ring oscillator; and a voltage-controlled oscillator having an oscillator signal output coupled to each respective direct injection circuit and each respective tail injection circuit, and a frequency control input coupled to an output of the phase detector.

[0073] Example 17. The phase-locked loop of example 16, further comprising: a frequency divider coupled between an output of at least one stage of the ring oscillator and an input of the phase detector; and a loop filter coupled between an output of the phase detector and the frequency control input of the voltage-controlled oscillator.

[0074] Example 18. The phase-locked loop of one of examples 16 or 17, wherein each respective stage of the ring oscillator further comprises a respective side injection circuit coupled in series with each respective direct injection circuit.

[0075] Example 19. The phase-locked loop of one of examples 16 to 18, wherein the injection-locked prescaler has a locking range of at least 30%; and the injection-locked prescaler has a power consumption of less than 10 mW.

[0076] Example 20. The phase-locked loop of one of examples 16 to 19, wherein the injection-locked prescaler, the phase detector, and the voltage-controlled oscillator are disposed on a single semiconductor substrate. While the application has been described with reference to illustrative implementations, the description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative implementations, as well as additional implementations of the application, will be apparent to those skilled in the art upon reference to the description. It is therefore intended that the appended claims shall cover any such modifications or implementations.

Claims

1. A ring configured circuit, comprising: a ring oscillator including a plurality of stages coupled in a ring configuration, each stage of the plurality of stages including an input node coupled to an output node of a preceding stage of the plurality of stages, wherein each stage of the plurality of stages includes: a ring oscillator transistor having a control node coupled to the input node and a load path coupled to the output node; a direct injection circuit having a load path coupled between the output node and the control node of the ring oscillator transistor and a control node coupled to a first oscillator input node configured to receive a first oscillation signal; and a tail injection circuit having a load path coupled between the output node and a first supply node and a control node coupled to a second oscillator input node configured to receive a second oscillation signal.

2. The circuit of claim 1, further comprising: a phase shifter circuit having a first output coupled to the first oscillator input node and a second output coupled to the second oscillator input node, wherein the phase shifter circuit is configured to provide the first oscillation signal having a first phase at the first output and the second oscillation signal at the second output, and wherein the first oscillation signal and the second oscillation signal are 180 degrees out of phase with each other.

3. The circuit of claim 1, wherein, the ring oscillator transistor, the direct injection circuit, and the tail injection circuit each include a MOS transistor.

4. The circuit of claim 1, wherein, the plurality of stages includes an odd number of stages.

5. The circuit of claim 1, wherein, each stage of the plurality of stages further includes a side injection circuit having a load path coupled in series with the load path of the direct injection circuit.

6. The circuit of claim 1, wherein, each stage of the plurality of stages further includes a side injection circuit having a load path coupled in series with the load path of the tail injection circuit.

7. The circuit of claim 1, wherein, the ring oscillator further includes an additional direct injection circuit having a load path coupled between an input node of a first stage of the plurality of stages and an output node of a second stage of the plurality of stages.

8. The circuit of claim 1, wherein, each stage of the plurality of stages further includes an additional tail injection circuit having a load path coupled between the output node and a second supply node and a control node coupled to the first oscillator input node or the second oscillator input node.

9. A method of operating a circuit including an injection-locked frequency divider (ILFD) having a plurality of stages coupled in a ring configuration, the method comprising: injecting a first oscillation signal in each stage of the plurality of stages through a respective direct injection circuit coupled between an input node and an output node of each stage of the plurality of stages; and injecting a second oscillation signal at the output node of each stage of the plurality of stages through a respective tail injection circuit coupled between a first supply node and the output node of each stage of the plurality of stages.

10. The method of claim 9, further comprising: injecting an input signal of each stage of the plurality of stages using a respective side injection circuit coupled in series with each respective direct injection circuit.

11. The method of claim 9, further comprising: injecting, using a respective further tail injection circuit coupled between a second power supply node and an output node of each stage of the plurality of stages, a further oscillating signal at the output node of each stage.

12. The method of claim 9, further comprising: injecting, using a further direct injection circuit coupled between an input of a first stage of the plurality of stages and an output of a second stage of the plurality of stages, a further oscillating signal between the input of the first stage of the plurality of stages and the output of the second stage of the plurality of stages.

13. The method of claim 9, further comprising: generating the first oscillating signal and the second oscillating signal using a voltage controlled oscillator (VCO); frequency dividing a frequency of an output of the ILFD using frequency divider circuitry to form a frequency divided signal; comparing a phase of the frequency divided signal to a phase of a reference clock using a phase detector to form a phase detection signal; filtering the phase detection signal using a loop filter to form a VCO control signal; and controlling a frequency of the voltage controlled oscillator using the VCO control signal. the ILFD is configured to divide a frequency of the first oscillating signal and the second oscillating signal by a predetermined number.

14. The method of claim 9, wherein, the predetermined number is an odd number.

15. The method of claim 14, wherein, 16. A phase-locked loop, comprising: an injection-locked prescaler including a ring oscillator, wherein each respective stage of the ring oscillator includes a respective direct injection circuit coupled between an input and an output of each respective stage, and a respective tail injection circuit coupled between the output of each respective stage and a power supply node, and wherein a first oscillating signal is injected in the each respective stage by the respective direct injection circuit, and a second oscillating signal is injected at the output of the each respective stage by the respective tail injection circuit; a phase detector having an input coupled to an output of at least one stage of the ring oscillator; and a voltage controlled oscillator having an oscillating signal output operatively coupled to each respective direct injection circuit and to each respective tail injection circuit, and a frequency control input coupled to an output of the phase detector.

17. The phase-locked loop of claim 16, further comprising: a frequency divider coupled between the output of at least one stage of the ring oscillator and the input of the phase detector; and a loop filter coupled between the output of the phase detector and the frequency control input of the voltage controlled oscillator. each respective stage of the ring oscillator further includes a respective side injection circuit coupled in series with each respective direct injection circuit.

19. The phase-locked loop of claim 16, wherein:

18. The phase-locked loop of claim 16, wherein, the injection-locked prescaler has a lock range of at least 30%; and the injection-locked prescaler has a power consumption of less than 10 mW. the injection-locked prescaler, the phase detector, and the voltage controlled oscillator are disposed on a single semiconductor substrate. ​ 20. The phase-locked loop of claim 16, wherein, ​

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