Assembling chips by rotational stacking

Abstract

A technique for assembling multiple chips is disclosed. A plurality of chip layers are prepared, each chip layer including at least one chip block. Each chip block includes a plurality of electrodes assigned the same function. The plurality of chip layers are sequentially rotationally stacked so as to configure at least one stack of overlapping chip blocks. Each stack holds a plurality of sets of vertically arranged electrodes having displacements in the horizontal plane. For at least one set, vias are at least partially formed within the plurality of chip layers so as to expose the surfaces of the vertically arranged electrodes in the set. The vias are filled with a conductive material.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a method for chip assembly, and more particularly to a method for assembling multiple chips, a chip structure for the method, and a stacked chip structure including multiple chips. SUMMARY OF THE INVENTION

[0002] With the increasing demand for higher performance and higher density integration of semiconductor devices, 3D integration technologies that enable broadband signal transmission and short wiring lengths have attracted attention to improve the performance of future computer systems.

[0003] Three-dimensional (3D) integration with through-silicon vias (TSVs) has been widely studied and developed. In the existing process of TSVs in 3D packaging, the TSVs formed in a silicon wafer are first filled with copper plating, and then the silicon wafer with TSVs is diced to obtain multiple singulated semiconductor chips. Finally, the singulated chips are stacked and bonded with the TSVs. The interconnection between stacked chips is usually achieved through solder bump bonding.

[0004] In the production process of 3D chip assembly, even if the chips have the same function (i.e., homogeneous integration), the via design sometimes requires different designs for each stacking level. Therefore, the pad design and mask pattern are unique for each stacking level, resulting in variations in the pad design and mask pattern. Therefore, it is necessary to assign a unique part number (P / N) to each stacking level, which complicates production control. In addition, when the yields of each stacking level are significantly different, many redundant components will be generated, thus reducing the efficiency of the production process.

[0005] Therefore, there is a need for a new chip assembly technology that can reduce the complexity of production control and improve the production efficiency of chip components.

[0006] According to an embodiment of the present invention, there is provided a method for assembling multiple chips. The method includes preparing multiple chip layers, each chip layer including at least one chip block. Each chip block includes multiple electrodes assigned the same function. The method further includes sequentially rotating and stacking the multiple chip layers to configure at least one stack of overlapping chip blocks, wherein each stack holds multiple groups of vertically arranged electrodes displaced in a horizontal plane. The method further includes forming vias at least partially within the multiple chip layers for at least one of the groups to expose the surface of the vertically arranged electrodes in the group. The method further includes filling the vias with a conductive material.

[0007] By using the method according to an embodiment of the present invention, the production control of the chip component can be simplified, and the production efficiency of the chip component can be improved. Since various chip designs, mask designs, and the number of components can be reduced regardless of the stack levels, the design workload, non-repetitive engineering costs, the complexity of production control, and production waste can be reduced.

[0008] In one embodiment, the at least one chip block includes an array of chip blocks arranged in a rotationally symmetric manner, performing the stacking of the plurality of chip layers such that each chip block in an array of one chip layer of the chip layers overlaps with a symmetrically positioned chip block in an array of another chip layer of the chip layers, and at least one stack of the overlapping chip blocks includes an array of stacks of the overlapping chip blocks. Thereby, multiple chip assemblies can be manufactured simultaneously, with a lower production control complexity and a higher production efficiency.

[0009] In a specific embodiment of the present invention, the stacking of the plurality of chip layers includes binding the plurality of chip layers by using one or more insulating adhesion layers, wherein each stack of the overlapping chip blocks holds a corresponding portion of each of the one or more insulating adhesion layers.

[0010] In another specific embodiment of the present invention, each corresponding portion of at least two of the one or more insulating adhesion layers has an opening as part of a via to be formed.

[0011] In another embodiment of the present invention, each electrode surface is configured to serve as a stopper for preventing hole formation and has a shape capable of forming a central portion of a via penetrating through the plurality of chip layers, wherein the central portion of the via is a portion not covered by any electrode surface. Thus, even if an opening is formed in the insulating adhesion layer by using a single mask design before stacking, the residual voids generated in the via at the space removed from the insulating adhesion layer can be minimized.

[0012] In a specific embodiment of the present invention, the rotational symmetry of the arrangement of the array is an n-fold rotational symmetry, and each rotation performed when stacking one of the chip layers onto another of the chip layers is a rotation of 360 / n*i (i = 1,..., n - 1) degrees around the center of the array with respect to the stacking basic position, and the number of the chip layers is n, each chip block has a checkerboard-like unit shape, and the via is formed through n or n - 1 chip layers.

[0013] In another embodiment of the present invention, n is 4, and each chip block has a square shape. Therefore, there is no need for design tools, lithography tools, and cutting tools to be applicable to special shapes other than rectangles. Standard design tools, lithography tools, and cutting tools can be used without any modification.

[0014] In another embodiment of the present invention, the fabrication of a plurality of chips, the stacking of the plurality of chips, and the formation of vias are repeatedly performed to obtain a plurality of stacked layer assemblies. Performing the formation of the vias causes the vias to partially penetrate each of the stacked layer assemblies. The method further includes stacking the plurality of stacked layer assemblies such that the vias of the stacked layer assemblies communicate with each other. The filling of the vias is performed once on the stacked plurality of stacked layer assemblies. Alternatively, the preparation and stacking of a plurality of chip layers are repeatedly performed to obtain a plurality of stacked layer assemblies. The method further includes stacking the plurality of stacked layer assemblies with a translational displacement. The formation of the vias and the filling of the vias are simultaneously performed on the plurality of stacked layer assemblies, respectively. Thus, the number of stacked levels can be two times, three times, etc.

[0015] In another embodiment of the present invention, each chip layer prepared has the form of a wafer or a panel, and the method further includes cutting the plurality of chip layers into a plurality of chip components, where each chip component corresponds to each stack of overlapping chip blocks. Interconnections can be established at the wafer level or the panel level rather than at the chip level.

[0016] In another embodiment of the present invention, the formation of the vias is performed by etching and / or laser processing, and the filling of the vias is performed by IMS (injection molding soldering) technology. Thereby, the manufacturing cost can be further reduced. A flexible and good ductility of an alloy composition of a conductive material can be obtained. It is applicable even when the number of layers increases and the aspect ratio of the vias correspondingly becomes higher.

[0017] In a specific embodiment of the present invention, each chip block has a semiconductor device or a thin-film battery.

[0018] According to another embodiment of the present invention, a chip structure is provided. The chip structure includes a chip layer, the chip layer includes at least one chip block, each chip block has a plurality of regions, and vias passing through the chip layer are allowed to be formed in the plurality of regions. The chip structure further includes a plurality of electrodes located at corresponding positions of the regions of each chip block. The plurality of electrodes are assigned the same function and have respective electrode surfaces, and the electrode surfaces are arranged such that when a rotation operation around the center of the chip block is applied to another electrode surface among the electrode surfaces, each electrode surface is configured to be adjacent to the other electrode surface among the electrode surfaces and has a displacement in a horizontal plane.

[0019] This chip structure can be used as a piece at any stacking level for assembling multiple chips. By using this chip structure, the production control of chip assembly can be simplified, and the production efficiency of chip assembly can be improved. Since it is independent of the stacking level and can reduce the types and the number of components of chip design and mask design, the design workload, non-repetitive engineering costs, the complexity of production control, and production waste can be reduced.

[0020] According to a further embodiment of the present invention, a stacked chip structure is provided. The stacked chip structure includes a plurality of rotationally stacked chip layers to form a stack of overlapping chip blocks. At least two overlapping chip blocks in each stack have corresponding via holes that communicate with each other to form through holes. The stacked chip structure further includes multiple groups of vertically arranged electrodes that are assigned the same function for each stack of the overlapping chip blocks. The vertically arranged electrodes in each group are arranged to have a displacement in the horizontal plane. The stacked chip structure further includes a conductive material filled in the through holes of each stack of the overlapping chip blocks. The conductive material filled in the through holes is in contact with the electrode surface of one of the groups of vertically arranged electrodes.

[0021] The stacked chip structure is low-cost and easy to manufacture, and has reliable connectivity.

[0022] Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the present invention are described in detail herein and are considered to be part of the claimed invention. Brief Description of the Drawings

[0023] The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the present invention are apparent from the following detailed description taken in conjunction with the accompanying drawings. Note that the dimensions and relative positions of the elements and layers in the drawings are not necessarily drawn to scale. Some of these elements or layers are arbitrarily enlarged and positioned to improve the readability of the drawings.

[0024] Figure 1A 、 1B 、1C and 1D show top views and cross-sectional views of stacked semiconductor chip assemblies with and without vertical conductors according to embodiments of the present invention.

[0025] Figure 2A 、 2B and 2C show enlarged top views and enlarged cross-sectional views of a chip assembly around a vertical conductor.

[0026] Figure 3A and 3BAn enlarged top view and perspective view of a chip component without vertical conductors around one vertical conductor are shown.

[0027] Figure 4 A schematic diagram of a semiconductor wafer that can be used to manufacture a chip assembly according to an embodiment of the present invention is shown.

[0028] Figure 5 A method of stacking a plurality of semiconductor wafers according to an embodiment of the present invention is shown.

[0029] Figure 6 Shown is a way of stacking wafers focusing on one stack of overlapping die.

[0030] Figures 7A - 7H Cross-sectional views are shown of the structure obtained at each step of the assembly process according to the embodiment of the present invention.

[0031] Figure 8 A top view of a stacked wafer assembly without vertical conductors is shown in accordance with an embodiment of the present invention.

[0032] Figure 9 A method of dicing a stacked wafer assembly into a plurality of stacked semiconductor chip assemblies according to an embodiment of the present invention is shown.

[0033] Figure 10 Various designs of vias and electrodes according to embodiments of the present invention are shown.

[0034] Figure 11 Techniques are described that can avoid the creation of voids in vias according to certain embodiments of the present invention.

[0035] Figure 12A , 12B 12C show cross-sectional views of structures obtained at each step of an assembly process for a stacked semiconductor chip assembly having eight layers according to a specific embodiment of the present invention.

[0036] Figure 13 An alternative assembly process for a stacked semiconductor chip assembly having eight layers is shown in accordance with another specific embodiment of the present invention.

[0037] Figure 14A and 14B Cross-sectional views of the structure obtained at each step of the alternative assembly process are shown.

[0038] Figure 15A , 15B , 15C and 15D illustrate a method of manufacturing a stacked semiconductor chip assembly having an equilateral triangle shape according to a specific embodiment of the present invention.

[0039] Figure 16A and16B Shows a way of manufacturing a stacked semiconductor chip assembly having a regular hexagon shape according to a specific embodiment of the present invention.

[0040] Figure 17A and 17B Shows a cross-sectional view of the structure obtained at each step of the assembly process having a regular hexagon shape according to a specific embodiment of the present invention.

[0041] Figure 18A and 18B Shows a cross-sectional view of a stacked semiconductor chip assembly having vertical conductors according to an alternative embodiment of the present invention.

[0042] Figure 19A 、 19B and 19C show a top view and a cross-sectional view of a stacked battery chip assembly having vertical conductors according to another embodiment of the present invention.

[0043] Figures 20A - 20C Shows a cross-sectional view of the structure obtained at each step of the related assembly process, which has a plurality of electrode layouts designed specifically for each stacked layer level. Detailed Description

[0044] Hereinafter, embodiments of the present invention will be described. However, those skilled in the art should understand that the embodiments described below are merely illustrative and do not limit the scope of the present invention.

[0045] Embodiments according to the present invention relate to a method of assembling a plurality of chips, a chip structure for the method, and a stacked chip structure manufactured by the method, wherein the plurality of chips are stacked in a novel manner.

[0046] Hereinafter, a series of Figure 1A 、 1B 、1C and 1D、 Figure 2A 、 2B and 2C and Figure 3A and 3B will be described to describe a stacked chip structure according to an embodiment of the present invention. The structure is a stacked semiconductor chip assembly 100 including a plurality of semiconductor chips.

[0047] Figure 1A and 1B Show a cross-sectional view and a top view of the stacked semiconductor chip assembly 100, respectively. Note that Figure 1B The cross-sectional view shown corresponds to Figure 1A The cross-section indicated by "A" in the top view of

[0048] As Figure 1A and 1BAs shown, the component 100 includes a plurality of semiconductor chip layers 110 stacked in sequence; and a plurality of vertical conductors 130 formed in the plurality of layers 110. The plurality of layers 110 can be bonded by an interlayer insulating adhesive, and each interlayer insulating adhesive is inserted between the upper layer and the lower layer 110. The interlayer insulating adhesive will be described in more detail later.

[0049] Each layer 110 corresponds to a semiconductor chip (also referred to as a "die"). Each layer 110 is made of a semiconductor material, such as silicon, silicon carbide, sapphire, and compound semiconductors (e.g., gallium phosphide (GaP), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN)), etc.

[0050] The layers 110 can have the same shape and have rotational symmetry. The shape of each layer 110 is the same as the unit shape of a checkerboard arrangement, and more specifically, the same as the unit shape of a regular checkerboard arrangement. In one or more specific embodiments, the shape of the layer 110 can be a square, an equilateral triangle, or a regular hexagon. In one embodiment, each layer 110 has an approximately square shape that has 4-fold rotational symmetry, as Figure 1A shown.

[0051] As Figure 1A and 1B shown, there are four layers 110A - 110D in the component 100. The number of layers in the component 100 corresponds to the order of rotational symmetry of the shape of the layer 110.

[0052] The layers 110 are rotationally stacked as indicated by the arrow symbols depicted in Figure 1B . The direction of the arrow represents the reference orientation of the layer 110 labeled by the arrow. The rotation applied to each layer 110 relative to a reference position (e.g., the bottom layer 110A) is a rotation around the center of the component 100 (and the layer 110) at an angle of 360 / n*i (i = 1,..., n - 1), where n represents the order of rotational symmetry of the shape of the layer 110. Note that the center of the component 100 is represented by two diagonal double-dashed lines. As Figures 1A - 1B shown, n is 4, and the rotation angles are 90, 180, and 270 degrees relative to the reference position (i.e., 0 degrees).

[0053] The vertical conductors 130 interconnect the plurality of layers 110. Each vertical conductor 130 is made of a conductive material, which can include metals, metal alloys, and / or other conductive materials. In one embodiment of the present invention, the conductive material is solder, which can be easily manufactured by IMS (injection molding soldering) technology, and the solder alloy composition can be flexibly adjusted. Each vertical conductor 130 has a stepped structure as Figure 1B shown.

[0054] The vertical conductors 130 are divided into groups. Different functions (denoted by the identifier "Px", where x represents the index of the function) can be assigned to each group. Multiple vertical conductors 130 within the same group are assigned the same function. Note that the function assigned to a particular vertical conductor means the role of the interconnection provided by the particular vertical conductor 130. For example, ground (GND), power supply (VCC), and specific input / output signals are types of functions.

[0055] As Figure 1A and 1B shown, the number of groups of vertical conductors 130 is two, corresponding to the number of functions of each layer 110 to be interconnected. The number of vertical conductors 130 in each group (i.e., each function) is four, which can correspond to the order of rotational symmetry. Thus, there are two groups of vertical conductors, including the first group of four vertical conductors 130 - P1I, 130 - P1II, 130 - P1III, 130P1IV (enclosed by the dashed circular line in Figure 1A ), and the second group of four vertical conductors 130 - P2I, 130 - P2II, 130 - P2III, 130 - P2IV (enclosed by the dotted circular line in Figure 1B ).

[0056] The top surface of the component 100 can be divided into multiple regions, in which a group of vertical conductors 130 with different functions are respectively fabricated. The number of regions corresponds to the order of rotational symmetry. As Figure 1A and 1B shown, there are four regions (I, II, III, IV) bounded by two double-dotted lines, and each region has a group of vertical conductors 130 with different functions (P1, P2). Note that there is no restriction on the way the surface of the component 100 is bounded, as long as the bounded regions have the same rotational symmetry as the shape of the layer 110.

[0057] The layout of the vertical conductors 130 also has the same rotational symmetry as the shape of the layer 110. More specifically, the positions of the vertical conductors within each group or function (e.g., 130 - P1I, 130 - P1II, 130 - P1III, 130 - P1IV) and the relative positional relationship between the vertical conductors 130 with different functions (e.g., the geometries of 130 - P1y and 130 - P2y; y = I, II, III, IV) have the same rotational symmetry, as shown by the dotted curved arrows in Figure 1A .

[0058] Note that the number of groups and the number of functions are Figures 1A - 1Bthe example shown in, and is not limited to a specific value (i.e., two). The number of groups and the number of functions may depend on the specifications of the semiconductor chip 110. In other specific embodiments of the present invention, there may be more than two groups and functions.

[0059] Figure 1C and 1D respectively show a top view and a cross-sectional view of the component 100 when the vertical conductor 130 is shown transparently. Note that Figure 1D the cross-sectional view shown corresponds to Figure 1C the cross-section represented by "A" in the top view shown.

[0060] As Figure 1C and 1D shown, for each vertical conductor 130, the component 100 further includes a plurality of electrodes (also referred to as pads) 112 formed on the surface of the layer 110; and vias 128 through which the surfaces of these electrodes 112 can be seen in the Figure 1C top view. The "through" holes 128 are holes that penetrate at least the chip layer 110. The vias 128 do not have to penetrate the entire layer 110. Note that the electrode surfaces at different levels are represented by different shadings. Each electrode 112 can be made of any one of metal materials (e.g., Cu, Al, etc.) and other conductive materials.

[0061] As Figure 1C and 1D shown, the number of electrodes 112 for each vertical conductor 130 is four, which corresponds to the order of rotational symmetry of the shape of the layer 110. Therefore, in the Figure 1C top view, the electrode surfaces of four electrodes 112A - 112D can be seen at each position of the vertical conductor 130. Note that the reference numerals are only labeled for one representative electrode group for the specific vertical conductor 130 - P1IV.

[0062] As Figure 1C shown, these four electrodes 112A - 112D constitute a group of vertically arranged electrodes 140 (more specifically, group 140 - P1IV because it corresponds to the vertical conductor 130 - P1IV). As Figure 1C shown, the vertically arranged electrodes 112A - 112D are displaced from each other in the horizontal plane such that when assuming no conductive material of the vertical conductor 130, the electrode surfaces of each of the vertically arranged electrodes 112A - 112D can be at least partially seen from the top. Each electrode surface of the vertically arranged electrodes 112A - 112D provides a bottom or a step, as Figure 1D shown, thus generating a stepped structure.

[0063] Note that the term "vertical" is defined as the direction perpendicular to the main surface (top surface or back surface) of the component 100 (and the layer 110), which matches the stacking direction. The vertical direction is indicated by the arrows marked "Z" in Figure 1B and 1D . The term "horizontal" is defined as the direction in a plane perpendicular to the vertical direction, which matches the plane of the main surface of the component 100 (and the chip layer 110). The horizontal plane is indicated by the arrows marked "X" and "Y" in Figure 1A and Figure 1C .

[0064] Furthermore, the electrode surfaces of the vertically arranged electrodes 112A to 112D in the group 140 are arranged to form a circle in the horizontal plane. Contrary to the vertical conductor 130, the geometry of the vertically arranged electrodes for each function (e.g., groups 140-P1I, 140-P1II, 140-P1III, 140-P1IV) does not have the same rotational symmetry as the shape of the layer 110, but has translational symmetry in the horizontal plane, as indicated by the dashed arrows in Figure 1C .

[0065] Note that in the described embodiments of the present invention, there are four vertical conductors 130-PxI to 130-PxI-IV for each function (e.g., x = 1, 2), where the vertical conductor 130 is located at the corresponding position of each group of vertically arranged electrodes 140-Pxy (x = 1, 2; y = I, II, III, IV). However, in other embodiments of the present invention, for each function (e.g., Px; x = 1, 2), there is at least one vertical conductor 130-Pxy (e.g., at least one of y = I, II, III, and IV).

[0066] Figure 2A An enlarged top view of the component 100 around a vertical conductor 130 is shown. The contours of the electrode surfaces of the four vertically arranged electrodes 112A to 112D are represented by double-dot dash lines (112A), dash lines (112B), dashed lines (112C), and dotted lines (112D), respectively.

[0067] Considering the placement accuracy of the stacking, the size of each electrode 112 is slightly larger than 1 / n of the size of the through hole 128 (and the vertical conductor 130). As shown in Figure 2AAs shown, the vertically arranged electrodes 112A to 112D are arranged such that each electrode surface is adjacent to, at least partially displaced from, and overlaps with another one of the vertically arranged electrodes 112A to 112D in the horizontal plane. For example, electrode 112A is adjacent to electrodes 112B and 112D, partially overlaps with electrodes 112B and 112D, and is slightly displaced from both electrodes 112B and 112D along the corresponding directions in the horizontal plane. The same applies to the other electrodes 112B to 112D.

[0068] Figure 2B and Figure 2C shows an enlarged cross-sectional view of the assembly 100 around a vertical conductor 130. Note that Figure 2B and Figure 2C the cross-sectional views shown respectively correspond to the cross-sections represented by "B" and "C" in the top view shown in Figure 2A It should also be noted that even for elements that do not intersect the corresponding cross-sections, the outlines of these elements are indicated by lines other than solid lines (such as dotted lines, dashed lines, etc.).

[0069] More specifically, in the cross-sectional views of Figure 2B and Figure 2C , the outlines of the vertical conductor 130 intersecting at the cross-sections represented by "C" and "B" are depicted by dotted lines 130a respectively. The outlines of the electrodes 112A and 112B intersecting at the cross-section indicated by "C" are depicted by dash-dotted lines and double dash-dotted lines in the cross-sectional view of Figure 2B . The outlines of the electrodes 112C and 112D intersecting at the cross-section indicated by "B" are depicted by dashed lines and dotted lines in the cross-sectional view of Figure 2C .

[0070] As Figure 2B and Figure 2C shown, the assembly 100 may further include one or more interlayer insulating adhesives 102B to 102D, each of which is inserted between the upper and lower layers (110A - 110B, 110B - 110C, 110C - 110D). Each interlayer insulating adhesive 102 may be made of any one of insulating resins such as PI (polyimide), BCB (benzocyclobutene), polybenzoxazole (PBO), or other polymers.

[0071] The vertically arranged electrodes 112A to 112D are located on respective levels of the surface of the layer 110. The vertically arranged electrodes 112A to 112D have respective electrode surfaces, and each electrode surface is in contact with the vertical conductor 130.

[0072] As Figure 2B and Figure 2CAs shown, the vertical conductor 130 penetrates at least partially through layers 110A to 110D. In the embodiment of the present invention, the number of layers forming the vertical conductor 130 is n, which corresponds to the order of rotational symmetry.

[0073] Figure 3A and Figure 3B respectively show an enlarged top view and a perspective view of the assembly 100 around a vertical conductor 130 when the vertical conductor 130 is shown transparently.

[0074] As Figure 3A and Figure 3B shown, the electrode surfaces of the vertically arranged electrodes 112A to 112D are arranged helically (or in a spiral shape) at respective levels associated with the layers 110A to 110D. More specifically, at the levels of the surfaces of the layers 110A to 110D, a spiral (or helical) stepped structure is formed.

[0075] As Figure 3B shown, the layers 110A to 110D respectively have through holes 128A to 128D formed therethrough. The through holes 128A to 128D of the layers 110A to 110D overlap and communicate with each other, and have different hole shapes to form a through hole 128 having a spiral or helical stepped structure. The electrode surfaces of the vertically arranged electrodes 112A to 112D are exposed within the through hole 128.

[0076] Note that, as shown in the series of Figure 1A , Figure 1B , Figure 1C and Figure 1D , Figure 2A , Figure 2B and Figure 2C as well as Figure 3A and Figure 3B , the number of layers 110 is 4. However, the number of layers 110 may not be limited. In a specific embodiment of the present invention, the number of layers 110 may be m multiplied by n, where m represents the number of units when assuming one unit includes n layers, which causes the electrode surfaces to circle around the center of the through hole 128 in a horizontal plane. When m is two or more, each vertically arranged electrode surface cannot be seen from the top. In this case, the vertically arranged electrodes 112 are arranged such that when assuming the absence of the conductive material of the vertical conductor 130 and the absence of the (multiple) upper units, the electrode surfaces of each vertically arranged electrode 112 of each unit can be at least partially seen from the top.

[0077] It is also noted that there may be other structural or functional elements, such as a base substrate on which the assembly 100 is stacked, a mother board on which the assembly 100 is mounted, and a surface wiring layer formed on the assembly 100, etc.

[0078] Component 100 can be assembled using a wafer-to-wafer stacking process. In the wafer-to-wafer stacking process, multiple semiconductor wafers are aligned and then bonded, and subsequently a single chip stack is diced.

[0079] Figure 4 A schematic diagram of a semiconductor wafer 250 that can be used to fabricate component 100 is shown. Figure 4 The illustrated wafer 250 corresponds to a chip structure according to an embodiment of the present invention.

[0080] As Figure 4 shown, the wafer 250 includes an array of semiconductor chip blocks 210, each semiconductor chip block corresponding to one semiconductor chip or die to be assembled in component 100 after dicing. Note that Figure 4 the illustrated wafer 250 may have been subjected to an appropriate thinning process, such as back grinding, so as to have an appropriate thickness. The wafer 250 corresponds to Figure 1B and 1D each layer 110 shown in, while including blocks 210 arranged in a novel manner, rather than including a single chip block.

[0081] Similar to component 100 and layer 110, the blocks 210 in the array are designed to have the same shape with rotational symmetry. The shape of each block 210 is the same as the shape of the tessellation unit, more specifically, the same as the regular tessellation unit shape, including a square, an equilateral triangle, and a regular hexagon. In one embodiment of the present invention, each block 210 has an approximately square shape with 4-fold rotational symmetry, as Figure 4 shown. Note that the shape of the block 210 has not been actually formed before dicing. However, it appears in the integrated circuit pattern of the block 210.

[0082] The array is two-dimensional. As Figure 4 shown, for convenience, both the number of columns and the number of rows in the array are 4. Thus, there are 16 blocks 210-ij (i = 1, 2, 3, 4; j = 1, 2, 3, 4). However, the size of the array is not limited to 4×4, and in other embodiments of the present invention, the size of the array can be 1×1, 2×2, 3×3, 6×6, 8×8, 16×16, etc., as long as the array exhibits the same rotational symmetry as the shape of the blocks 210 around the center of the array. Note that the center of the array is indicated by two intersecting dotted lines.

[0083] In Figure 4 also shown are a top view and a bottom view of a representative block 210. Each block 210 has a plurality of regions 214 in which vias passing through the wafer 250 are respectively allowed to be formed.

[0084] Each block 210 also includes a plurality of electrodes 212 formed thereon at corresponding positions in region 214. The plurality of electrodes 212 can be divided into a plurality of groups (e.g., P1 surrounded by the dashed circular line 222-P1). Different functions can be assigned to each group of electrodes 212, and the plurality of electrodes 212 in the same group are assigned the same function. Thus, there are 4 electrodes 212 for each function, and there are a total of 8 electrodes in the specific embodiment of the present invention shown in Figure 4 Note that for convenience, other conductive patterns such as wiring metals are omitted from the drawings. However, note that any conductive pattern can be kept outside the remaining portion of region 214 where the electrodes 212 are not formed. It should also be noted that, except for the electrodes 212, the conductive pattern does not need to have any symmetry.

[0085] Similar to component 100, the top and bottom surfaces of each block 210 can be divided into a plurality of regions, where a group of via regions (e.g., 214-P1I, 214-P2II) for different functions are respectively prepared. The number of regions corresponds to the order of rotational symmetry of the shape of block 210. As Figure 5 shown, there are four regions (y = I, II, III, IV) defined by the double-dashed lines. Note that the way of delimiting the surface of block 210 is not limited as long as the delimited regions have the same rotational symmetry as the shape of block 210.

[0086] The layout of the via regions 214 also has the same rotational symmetry as the shape of block 210. More specifically, the positions of the via regions 214 in each function and the relative positional relationship between the via regions 214 with different functions also have the same rotational symmetry as the shape of block 210. On the contrary, the positions of the electrode surfaces of the electrodes 212 in each function have translational symmetry, similar to Figure 1B the geometry of the vertically arranged electrodes 112A - 112D shown in

[0087] Although not shown in Figure 4 , the wafer 250 can also include an insulating adhesion layer formed on its top or bottom surface, and the insulating adhesion layer can be used for subsequent stacking processes. The insulating adhesion layer can be divided into a plurality of parts corresponding to the array of blocks 210.

[0088] In a specific embodiment of the present invention, when the via regions of the insulating adhesion layer are removed after stacking, each part of the insulating adhesion layer can have a flat form. In another specific embodiment of the present invention, each part of the insulating adhesion layer can have a plurality of openings located at the positions of the via regions 214 when the via regions of the insulating adhesion layer are removed before stacking.

[0089] Figure 5Shows the way of stacking the wafers 250. Figure 4 The illustrated wafers 250 can be used regardless of the wafer stack level. During the manufacturing process of the component 100, the wafers 250A - 250D are sequentially rotationally stacked as Figure 5 shown by their notches therein, which indicates the orientation of the wafers 250. Note that Figure 5 each semiconductor wafer 250 in Figure 4 is inverted compared to

[0090] In Figure 5 , the letters "A", "B", "C", and "D" are respectively marked to the 4 blocks 210 in each quadrant. The blocks 210 given the same letter in the 4 quadrants have a rotationally symmetric relationship around the array center. As Figure 5 shown, the blocks 210 of each wafer 250 are arranged in a rotationally symmetric manner such that when a rotation operation is performed around the array center, each block (one block in a quadrant is given the letter "A", "B", "C", or "D") overlaps with the other symmetrically arranged blocks (one block in another quadrant is given the same letter).

[0091] Therefore, a stack of one wafer (e.g., 250B) onto another wafer (e.g., 250A) can be performed such that each block 210 of one wafer (e.g., 210B - 41) overlaps with the symmetrically positioned blocks 210 of the other wafer (e.g., 210A - 11).

[0092] The rotation operation centered on the array center relative to a reference position (e.g., the lower wafer 250A) is to rotate by 360 / n*i (i = 1,..., n - 1) degrees centered on the array center, where n represents the order of rotational symmetry. As Figure 5 shown, n is 4, and the rotation angles are 90, 180, and 270 degrees relative to the reference position (i.e., 0 degrees).

[0093] By stacking the wafers 250A to 250D with appropriate rotation operations (90, 180, 270 degrees), for the position of each element in the array, four chip blocks (e.g., 210A - 11, 210B - 41, 210C - 44, 210D - 14) of different wafer levels are overlapped and stacked, generating a stacked array of overlapping blocks 210.

[0094] Figure 6 Shows the way of stacking the wafers 250, focusing on one stack 200 including the overlapping blocks 210A - 11, 210B - 41, 210C - 44, 210D - 14.

[0095] In Figure 6In [the figure], a top view of the entire stacked wafer assembly 260 and top views of each of the overlapping blocks 210A-11, 210B-41, 210C-44, 210D-14 are shown. Note that since the electrodes are formed on the back surfaces of each of the overlapping chip blocks 210, the outlines of the electrodes are shown by dotted lines.

[0096] As Figure 6 shown, in response to a rotation operation about the center of the array, the orientation of each block 210 is rotated as if it were subjected to a rotation operation about its center. Thus, focusing on the position of each element in the array, an array of stacks 200 of overlapping blocks having relative rotation angles is configured in the stacked wafer assembly 260. Each stack 200 corresponds to Figures 1A - 1D the assembly 100 shown in

[0097] In Figure 6 [the figure], a top view of the stack 200 of overlapping blocks 210 is further shown. Similar to the assembly 100, the top and bottom surfaces of the stack 200 can also be divided into multiple regions. There are four regions (I, II, III, IV) defined by double-dotted lines, and each region has a set of vertically arranged electrodes 210 having different functions (P1, P2).

[0098] Each stack 200 holds multiple groups 270 of vertically arranged electrodes 212A to 212D that are displaced in the horizontal plane (more specifically, the group 270-P1I composed of electrodes 212A-P1I, 212B-P1IV, 212C-P1III, 212D-P1II).

[0099] Thus, in combination with Figure 6 reference to Figure 4 For Figure 4 each block 210 shown in [the figure], the electrodes 212 are arranged such that each electrode surface (e.g., 212-P1I) is configured to be adjacent to another electrode surface (e.g., 212-P1IV) with a specific displacement in the horizontal plane when a rotation operation about the center of the block 210 is applied to another electrode surface (212-PIV). In response to a rotation operation about the center of the array, the position of each electrode 212 rotates as if it were subjected to a rotation operation about the center of the via region 214.

[0100] Although not shown in Figure 6 [the figure], each stack 200 of blocks 210 can also hold corresponding portions of one or more insulating adhesive layers inserted between the blocks 210, and each insulating adhesive layer defines two adjacent chip blocks 210. Each portion of the insulating adhesive layer can have a flat form or multiple openings, depending on the process flow.

[0101] Refer to a series of attached Figures 7A - 7H, describes an assembly process for manufacturing a stacked semiconductor chip assembly according to an embodiment of the present invention. Figures 7A - 7H Shows cross-sectional views of the structures obtained at each step of the assembly process. Note that Figure 7A , 7C , 7E, 7G (left side) and Figure 7B , 7D , 7F, 7H (right side) are cross-sectional views corresponding to different cross-sections similar to those marked "B" and "C" Figure 2A shown.

[0102] Referring to Figure 7A and 7B , the assembly process includes the step of preparing Figure 4 the wafers 250A - 250D shown, each wafer including an array of blocks 210. Each wafer 250 may have electrodes 212 formed on its surface.

[0103] Please refer to Figure 7C and Figure 7D , the assembly process further includes the step of sequentially stacking the wafers 250A to 250D in a rotational manner to form an array of stacks 200 of overlapping blocks 210 as shown in Figure 5 and Figure 6 shown. The upper wafer (e.g., 250B) is placed on the lower wafer (e.g., 250A) such that the top surface of the upper wafer (e.g., 250B) on which the electrode 212B is formed is joined to the back surface of the lower wafer (e.g., 250A). As referred to in Figure 6 , the step of stacking the wafers 250 can be performed such that the electrode surfaces of the vertically arranged electrodes (212A - P1I, 212B - P1IV, 212C - P1III, 212D - P1II) in each group are arranged to form a circle in a horizontal plane.

[0104] Further referring to Figure 7C and Figure 7D , the assembly process may include the step of bonding the wafers 250A to 250D with one or more interlayer insulating adhesive layers 202B to 202D inserted therebetween. In a particular embodiment of the present invention, an insulating adhesive is applied to the top surface of the upper wafer (e.g., 250B), and then the upper wafer (e.g., 250B) having the insulating adhesive layer (e.g., 202B) is placed on the lower wafer (e.g., 250A), which may or may not include an opening, and then cured.

[0105] Referring to the attached Figure 7E and 7F, The assembly process includes the step of forming vias 228 at least partially in wafers 250A to 250D to expose the electrode surfaces of vertically arranged electrodes 212A to 212D. The step of forming vias 228 is performed by etching (e.g., reactive ion etching (RIE) or other dry etching techniques) and / or laser processing.

[0106] In a specific embodiment of the present invention, the insulating adhesion layer 202 does not have an opening for the via 228 before stacking, and the wafers 250A to 250B and the insulating adhesion layers 202B to 202D can be effectively drilled by laser processing. In another specific embodiment of the present invention, the insulating adhesion layers 202B to 202D may have a plurality of openings, and the wafers 250 can be effectively drilled by etching. During hole formation, the electrode surface of each electrode 212A to 212D is configured to serve as a stopper to prevent hole formation.

[0107] Referring to Figure 7G and 7H , the assembly process includes the step of filling the vias 228 with a conductive material 230. The step of filling the vias 228 can be performed such that the conductive material 230 filled in each via contacts the corresponding electrode surface of the vertically arranged electrodes 212A to 212D. The step of filling the vias 228 can be performed by IMS (injection molding soldering) technology.

[0108] In the IMS process, molten solder is injected into the vias 228 under vacuum or reduced pressure conditions by using a filling head that traverses the surface of the component 260 and is cured in the vias 228. The filling head includes a reservoir for molten solder and a groove through which the molten solder is injected into the vias 228.

[0109] More specifically, the step of filling the vias 228 may include a plurality of sub-steps. As Figure 7C and Figure 7D shown, after the hole formation step, when viewed from the normal direction with respect to the wafer 250, all the electrodes 212A to 212D can be seen through the vias 228. When opening the vias 228 through the layers 250A - 250D, the inner surface of the vias 228 may be coated with an insulating material (e.g., polymer) to insulate the sidewalls of the wafer 250. The coating of the insulating material can be performed by using conventional techniques such as vapor deposition polymerization.

[0110] Then, the portion of the insulating material deposited on the electrodes 212A - 212D can be back-etched by conventional anisotropic etching to expose the electrode surface. At this time, the vias 228 may have a plurality of portions, each portion corresponding to each wafer 250 and having a mesa that exposes the corresponding electrode (e.g., the upper electrodes 212B to 212D) or an inner bottom surface that exposes the corresponding electrode (e.g., the lower electrode 212A).

[0111] The conductive material 230 is filled into the through - hole 228 to form a vertical conductor. Note that the filling step can be accomplished by injection - molded solder (IMS). In this case, expensive CMP (chemical - mechanical polishing) is not required. IMS is cost - effective. However, electroplating or other techniques can also be considered. In other embodiments where the filling step is completed by electroplating, subsequent seed sputtering, via - fill electroplating, and removal of the conductive material deposited on the surface by CMP are performed. The conductive material can be deposited on the inner surface of the hole 228 through a via - fill electroplating process to form the vertical conductor 130.

[0112] After the filling or deposition step, when viewed from above, the vertical conductor 230 can be seen while all the electrodes 212A - 212D are covered with the conductive material.

[0113] Attached Figures 7E - 7H This kind of spiral or spiral - stepped structure shown will enable the stacked chip assembly 100 to have reliable contact between the vertical conductor 230 and the electrodes 212A - 212D of the layers 250A - 250D.

[0114] Figure 8 A top view of the assembly 260 is shown when the vertical conductor 230 is shown transparently. An assembly 260 having an array of stacks 200 of overlapping chip blocks 210 in the form of wafers (or dies) as shown can be provided to the next in the production chain. Figure 8 A top view of the assembly 260 is shown when the vertical conductor 230 is shown transparently. An assembly 260 having an array of stacks 200 of overlapping chip blocks 210 in the form of wafers (or dies) as shown can be provided to the next in the production chain.

[0115] Figure 9 A method of cutting the assembly 260 is shown. As shown, the assembly process can also include the step of cutting the assembly 260 into a plurality of assemblies 100, each assembly corresponding to Figure 9 As shown, the assembly process can also include the step of cutting the assembly 260 into a plurality of assemblies 100, each assembly corresponding to Figure 6 one stack 200 of the overlapping blocks 210 as shown.

[0116] Since the blocks 210 are stacked without any additional horizontal displacement, the width of the cutting channel D can be minimized to the same extent as a single wafer, thus enabling the area of the wafer 250 to be utilized as effectively as possible. The manufacturing cost of the chip assembly 100 will decrease as the chips per wafer (CPW) increases.

[0117] Note that the cutting method can depend on the shape of each individual chip block 210. When n = 4 and each chip block has a square shape, no cutting tool is required for special shapes other than rectangular shapes. Standard cutting tools can be used without any special adjustment.

[0118] In other embodiments of the present invention, the assembly 100 separated from the assembly 260 by the cutting step can be provided to the next in the production chain.

[0119] Referring to Figure 10 , various designs of vias and electrodes according to embodiments of the present invention are shown. In Figure 10 , there are schematic diagrams of four exemplary designs 300, 320, 340, 360 and corresponding top views 310, 330, 350, 370, showing the arrangement of the electrode surface seen through the via when the vertical conductor is shown transparently.

[0120] The first exemplary design 300 and the top view 310 correspond to the above specific embodiment of the present invention, where n = 4. Both the via 302 and the electrode 304 have a square shape. The electrode 304 is partially formed within the via 302 and can have a size slightly larger than 1 / 4 of the size of the via 302, taking into account the placement accuracy of the stack. The whole of the via 302 is covered by at least any one of the electrodes 304A to 304D.

[0121] The second exemplary design 320 and the top view 330 show a variation where n = 4. Both the via 322 and the electrode 324 have a square shape, but their corners are rounded or notched. The size of the electrode 324 can also be slightly larger than 1 / 4 of the size of the via 322. The whole of the via 322 is covered by at least one of the electrodes 324A to 324D.

[0122] The third exemplary design 340 and the top view 350 show other variations. Both the via 342 and the electrode 344 have a circular shape. The electrode 344 can have a size slightly larger than 1 / 4 of the size of the via 342. The whole of the via 342 is covered by at least any one of the electrodes 344A to 344D.

[0123] The fourth exemplary design 360 and the top view 370 show another variation. Both the via 362 and the electrode 364 have a hollow circular shape. The electrode 344 can also have a size slightly larger than 1 / 4 of the size of the via 342. Contrary to the above designs 300, 320 and 340, the central portion 366 of the via 362 is not covered by any of the electrodes 364A to 364D.

[0124] As Figure 10 shown, the shape of the via and / or the electrode is not limited to a specific shape. It can be circular or other polygons having n-fold rotational symmetry (e.g., 90 degrees when n = 4). In addition, the shape of the electrode is not limited to a square. However, in each case, the electrode surfaces of the vertically arranged electrodes 304A to 304D, 324A to 324D, 344A to 344D, 364A to 364D are arranged to form a circle on the horizontal plane, i.e., covering 360 degrees.

[0125] As described above, regarding the manner of forming an opening in the insulating adhesive layer, there are mainly two cases. One is the case of fabricating an opening in the insulating adhesive layer 202 before the stacking step. The other case is the removal of the via region of the insulating adhesive layer 202 after the stacking step.

[0126] Compared with the third exemplary design 340, the fourth exemplary design 360 can be used in the latter case where the removal is performed before stacking. The third exemplary design is similar to design 360 in that it is based on a circle. The fourth exemplary design 360 is superior to the third exemplary design 340 in that, as described below, the generation of voids can be reduced.

[0127] Hereinafter, reference will be made to Figure 11 and in conjunction with Figure 10 to describe a technique capable of avoiding the generation of voids in the through - hole according to a specific embodiment of the present invention.

[0128] In Figure 11 there are a top - view of the electrode arrangement and two cross - sectional views around a vertical conductor for each of the exemplary designs 340 and 360. The cross - sectional view on the left - hand side corresponds to the cross - section represented by "L", while the cross - sectional view on the right - hand side corresponds to the cross - section represented by "R".

[0129] For the exemplary design 340, there are four wafers 352A - 352D; four electrodes 344A - 344D, each electrode being formed on the surface of each wafer 352; three insulating adhesive layers 354B - 354D inserted between the wafers 352A - 352D; and a vertical conductor 358 passing through the four wafers 352A - 352D.

[0130] As Figure 11 shown, since the removal of the through - hole portion in the insulating adhesive layer 354 is performed before stacking, there are removal spaces 356B - 356D in the insulating adhesive layers 354B - 354D. Because even when the hole - filling process is performed under vacuum or reduced - pressure conditions, such removal spaces 356 will cause void generation during the hole - filling process.

[0131] For the exemplary design 360, there are also four wafers 372A - 372D; four electrodes 364A - 364D, each electrode being formed on the surface of each wafer 372; three insulating adhesive layers 374B - 374D inserted between the wafers 372A - 372D; and a vertical conductor 378 passing through the four wafers 372A - 372D.

[0132] Contrary to the exemplary design 340, the vertical conductor 378 completely penetrates the four wafers 372A to 372D in the central portion. As described above, each electrode surface 364A to 364D serves as a stopper to prevent hole formation. However, the electrode surface 364 has a shape that can form a central portion 378A (which is also the central portion 377A of the via hole 377) of the vertical conductor 370 that penetrates the multiple wafers 372A to 372D. The central portion 378a (and also 377a) is the portion not covered by any electrode surface.

[0133] There are also removal spaces 376B to 376D in the insulating adhesion layers 374B to 374D. However, contrary to the exemplary design 340, the length (depth) of the removed spaces 376B - 376D can be shortened. Therefore, it is possible to expect a reduction in the generation of voids during the hole filling process.

[0134] In the case where a portion of the insulating adhesion layer 374 located at the position of the via hole 377 is removed before stacking, the shape of the adhesion opening can be optimized for each layer. However, in this case, different masks need to be prepared for each stacked layer level, which increases the cost and complexity of the production process. If all via hole regions are designed to be removed with a single mask, voids will be generated under the electrodes as described above. By adopting the exemplary design 360 in which a portion of the via hole region is not covered by any of the electrodes, the conductor filling process becomes easier, where the distance from the via hole to the edge of the vacant space under the electrode is uniform.

[0135] As described above, the number of layers 110 or wafers 250 may not be limited to 4. In a specific embodiment of the present invention, the number of layers 110 or wafers 250 to be stacked may be m times n, where m represents the number of units when assuming that one unit contains n layers 110 or wafers 250.

[0136] Reference Figure 12A 、 12B and 12C describe the assembly process of a stacked semiconductor chip assembly with eight layers according to a specific embodiment of the present invention. Figure 12A 、 12B and 12C show cross-sectional views of the structures obtained at each step of the assembly process.

[0137] In this assembly process, the exemplary design 360 is adopted. As Figure 12A shown, the assembly process may include by repeatedly performing Figures 7A~7FThe steps to obtain multiple stacked layer components 400A, 400B are as shown. Thus, the steps of preparing wafers (410A to 410D or 410E to 410H), stacking the wafers (410A to 410D or 410E to 410H) with insulating adhesive layers (412B to 412D or 412F to 412H), and forming vias 402A, 402B that completely penetrate the components 400A, 400B are repeated m times (in Figure 12A the specific embodiment of the present invention shown, m = 2).

[0138] As Figure 12B shown, the assembly process may further include the step of stacking the components 400A, 400B with an insulating adhesive layer (412E) such that the vias 402A, 402B of the components 400A, 400B communicate with each other to form a via 422 formed through the structure 420.

[0139] As Figure 12C shown, the assembly process may further include the step of filling the via 422 to form a vertical conductor 424 formed through the structure 420. In this process, the filling of each via 402A, 402B is performed simultaneously for multiple components 400A, 400B.

[0140] Referring to Figure 13 and Figure 14A and Figure 14B , an alternative assembly process for a stacked semiconductor chip component having eight layers according to a specific embodiment of the present invention is described. Figure 13 An alternative assembly process for eight layers is shown. Figure 14A and 14B show cross-sectional views of the structures obtained at each step of the alternative assembly process.

[0141] In the alternative assembly process, the design 450 shown in Figure 13 is adopted, where the electrode 454 has a tab or strip region 454a that extends outside the region of the original via 452.

[0142] Similar to the embodiment of the present invention shown in Figure 12A and 12B , the alternative assembly process may include the step of obtaining multiple components 440A, 440B by repeatedly performing the steps shown in Figures 7A~7D . However, the formation of vias is not performed for each component 440A, 440B. Thus, the steps of preparing wafers (460A to 460D or 460E to 460H) and stacking the wafers (460A to 460D or 460E to 460H) with insulating adhesive layers (462B to 462D or 462F to 462H) are repeated.

[0143] AsFigure 13 As shown, the obtained components 440A, 440B are stacked with a translational displacement (a horizontal displacement without rotation) S, and the amount of the displacement S can be the total size of the original vias 452 pulsating on the tab or strip region 454a. Note that in some embodiments, preferably, a sufficient pitch between adjacent vias is maintained.

[0144] As Figure 13 shown, the alternative assembly process may include the step of forming vias 464 that partially penetrate the components 440A, 440B such that each electrode surface of the electrodes 454A - 454H is exposed in the vias 464. The actual size (width) of the vias 464 is greater than twice the size of the original vias 452. Note that as Figure 13 shown, the surface of each of the electrodes 454A - 454H can be seen at least partially from the top.

[0145] As Figure 14A and 14B shown, the alternative assembly process may include the step of filling the vias 464 to form vertical conductors 468 formed through the structure 430. In this method, for a plurality of stacked layer components 440A, 440B, the filling of the vias 464A, 464B is performed at one time.

[0146] The assembly process shown in FIG. 12 is superior to Figure 13 and Figure 14A and Figure 14B shown alternative assembly processes in terms of cost per wafer (CPW) because the assembly process shown in FIG. 12 has no negative impact on the width of the dicing slots.

[0147] Referring Figure 15A , Figure 15B , Figure 15C and Figure 15D , a method of manufacturing a stacked semiconductor chip component having a regular triangular shape according to a specific embodiment of the present invention is described.

[0148] Figure 15A FIG. shows a schematic diagram of a semiconductor wafer 470 that can be used to manufacture a stacked semiconductor chip component having a regular triangular shape.

[0149] As Figure 15A shown, the wafer 470 includes an array of semiconductor chip blocks 472, each block corresponding to a single semiconductor chip or die after singulation. The blocks 472 in the array can have a regular triangle with three - fold rotational symmetry, as Figure 15A shown. Each block 472 includes three regions 474 that respectively allow the formation of vias through the wafer 470; and three electrodes 476. Note that for convenience, only one function of depicting the electrodes and via regions is present. However, there can be two or more functions.

[0150] In Figure 15A In the illustrated embodiment of the present invention, a total of 24 blocks 472 are tiled on a plane without overlap. The number of rows in the array is 4, and the number of triangles in each row is 5, 7, 7, and 5, respectively. However, the size of the array is not limited thereto. In other embodiments of the present invention, the number of rows may be 2 (e.g., 3 + 3), 6 (7 + 9 + 11 + 11 + 9 + 7), etc., as long as the array exhibits the same rotational symmetry of the third order.

[0151] Figure 15A Also shown is a manner of stacking a plurality of semiconductor wafers 470. Figure 15A The illustrated wafers 470 can be used regardless of the wafer stack hierarchy. During the manufacturing process, the wafers 470A - 470C are stacked in sequence with rotation. The rotation angles are 120 degrees and 240 degrees respectively relative to a reference position (i.e., 0 degrees).

[0152] By stacking the wafers 470A - 470C with appropriate rotational operations (120 degrees, 240 degrees), for the position of each element in the array, three chip blocks 472 of different wafer levels overlap and stack, resulting in Figure 15B an array of the stack 480 of overlapping chip blocks shown in.

[0153] Figure 15B Shown is a manner of stacking the wafers 470 concentrating on one stack 480 of overlapping chip blocks 472. As Figure 15B shown, in response to a rotational operation around the center of the array, the orientation of each block 472 is rotated as if it undergoes a rotational operation around its center. In Figure 15B shown is a top view of the stack 480 of overlapping chip blocks 472. Similar to the Figure 6 component 100 shown, the top surface and the bottom surface of the stack 480 can also be divided into multiple regions. There are three regions (I, II, III) defined by double-dashed lines, and each region has a set of vertically arranged electrode groups 210 with different functions ( Figure 15A and 15B only P1 is shown in). Each stack 480 holds multiple sets of vertically arranged electrodes 476A - 476C displaced in the horizontal plane.

[0154] Figure 15C and 15D shown is an enlarged cross-sectional view of the stack 480 around a vertical conductor. Note that the Figure 15C and Figure 15D shown cross-sectional views respectively correspond to the cross-sections represented by "H" and "G" in the Figure 15B shown top view.

[0155] As Figure 15C andFigure 15D As shown, the stack 480 may include three wafers 470A - 470C and two interlayer insulating adhesives 482B - 482C inserted therebetween. Vertically arranged electrodes 476A - 476C are located at respective levels on the surfaces of the wafers 470. The vertically arranged electrodes 476A - 476C have respective electrode surfaces, and each electrode surface is in contact with a vertical conductor 484, thereby creating a spiral or helical stepped structure.

[0156] Reference Figure 16A and Figure 16B as well as Figure 17A and Figure 17B , a method of manufacturing a stacked semiconductor chip assembly having a regular hexagon shape according to a specific embodiment of the present invention is described. Figure 16A A schematic view of a semiconductor wafer 490 that can be used to manufacture an assembly having a regular hexagon shape is shown.

[0157] As Figure 16A shown, the wafer 490 includes an array of semiconductor chip blocks 492. The blocks 492 in the array may have a regular hexagon shape with six - fold rotational symmetry. Each block 492 includes six via regions 494, in which vias passing through the wafer 490 are respectively allowed to be formed; and six electrodes 496. Note that, for convenience, only one function of depicting the electrodes and via regions is present. However, there may be two or more functions.

[0158] In Figure 16A the illustrated embodiment of the present invention, a total of seven blocks 492 form a tiled plane without overlap. The number of rows of hexagons in the array is 3, and the number of hexagons in each row is 2, 3, and 2 respectively. However, the size of the array is not limited thereto. In other embodiments of the present invention, the number of rows may be 1, 5 (3 + 4 + 5 + 4 + 3), etc., as long as the array exhibits the same six - fold rotational symmetry.

[0159] Figure 16A A method of stacking a plurality of semiconductor wafers 490 is also shown. Figure 16A The illustrated wafers 490 can be used regardless of the wafer stack levels. During manufacturing, wafers 490A - 490F are sequentially rotationally stacked. The rotation angles are 60, 120, 180, 240, and 300 degrees relative to a reference position (i.e., 0 degrees).

[0160] By stacking wafers 490A - 490F with appropriate rotational operations (60, 120, 180, 240, 300 degrees), for the position of each element in the array, six chip blocks at different wafer levels are overlapped and stacked, resulting in Figure 16B an array of stacks of overlapping chip blocks 500 as shown.

[0161] Figure 16B illustrates a way of stacking wafers 490 concentrating on one stack 500 of overlapping chip blocks 492. As Figure 16B shown, in response to a rotation operation about the center of the array, the orientation of each semiconductor chip block 492 is rotated as if it were subjected to a rotation operation about its center. In Figure 16B , a top view of the stack 500 is shown. Similar to Figure 6 the stacked semiconductor chip assembly 100 shown, the top and bottom surfaces of the stack 500 can also be divided into multiple regions. There are 6 regions (I, II, III, IV, V, VI) defined by double-dashed lines, and each region has a set of vertically arranged electrode groups 496A - 496F with different functions (only P1 is shown in Figure 16A and 16B ). Each stack 500 holds multiple sets of vertically arranged electrodes 476A - 476C that are displaced in the horizontal plane.

[0162] Figure 17A and 17B show an enlarged cross-sectional view of the stacked chip block 500 around a vertical conductor 504. Note that Figure 17A and 17B the cross-sectional views shown correspond to the cross-sections indicated by "I" and "J" in the top view shown in Figure 16B respectively.

[0163] As Figure 17A and 17B shown, the stack 500 can include 6 wafers 490A - 490F and 5 interlayer insulating adhesives 502B - 502F inserted therebetween. Vertically arranged electrodes 496A - 496F are located at each level on the surfaces of the wafers 490A - 490F. The vertically arranged electrodes 496A - 496F have their respective electrode surfaces, and each electrode surface contacts the vertical conductor 504, forming a spiral or spiral staircase-like structure.

[0164] In a regular checkerboard-shaped unit shape, a square is superior because there is no need for design tools, lithography tools, and cutting tools to be applicable to special shapes other than rectangles. Rectangular shapes are common in semiconductor processes. Therefore, standard design tools, lithography tools, and cutting tools can be used without any modification to process the chip shape.

[0165] In the above embodiment, the case of forming a through hole from the back side on the stacked wafers is illustrated. However, in other embodiments, the through hole can be formed from the front side into the stacked wafers. Figure 18A and 18B show a cross-sectional view of an assembly with a vertical conductor according to an alternative embodiment, where the through hole is formed from the front side of the stacked wafers. Note that Figure 18A and18B corresponds to different cross-sectional views similar to those shown in Figure 2A in which "B" and "C" are marked.

[0166] As Figure 18A and 18B shown, the stack 520 includes four wafers 530A - 530D and three interlayer insulating adhesives 522A - 522C inserted therebetween. Vertically arranged electrodes 532A - 532D are located at each level on the surface of the wafers 530. The vertically arranged electrodes 532A - 532D have their respective electrode surfaces, and each electrode surface is in contact with a vertical conductor 534, thereby forming a spiral or helical stepped structure. Contrary to Figure 2B , 2C and Figure 7G , 7H shown, the vertical conductor 534 penetrates a part of the wafers 530A - 530D. In the said embodiment, the number of wafers through which the vertical conductor 534 is formed is three, which corresponds to the order of rotational symmetry minus 1 (n - 1).

[0167] In the above embodiment, the components and wafers on which semiconductor devices are fabricated have been described. However, the stacked chip structure and chip structure according to the embodiments of the present invention are not limited to the structures related to semiconductor devices. In one embodiment, the stacked chip structure and chip structure can be structures related to thin - film batteries.

[0168] Hereinafter, with reference to Figure 19A , Figure 19B and Figure 19C , a stacked battery chip assembly 600 having a vertical conductor 630 according to another embodiment of the present invention will be described.

[0169] Figure 19A Show a top view and a cross - sectional view of the stacked battery chip assembly 600. Figure 19B and 19C Show a cross - sectional view of the stacked battery chip assembly 600. Note that Figure 19B and 19C the cross - sectional views shown respectively correspond to the cross - sections represented by "K" and "L" in the top view shown in Figure 19A .

[0170] As Figure 19A , Figure 19B and Figure 19CAs shown, the stacked battery chip assembly 600 includes a plurality of battery chip layers 610A - 610D; a plurality of vertical conductors 630 formed in the battery chip layers 610A - 610D; and a wiring layer 650. The wiring layer 650 constructed on top of the stacked battery chip layers 610A - 610D may have a wiring pattern connecting the vertical conductors 630 to external terminals, which may be connected to external devices such as a CPU (Central Processing Unit), memory, etc.

[0171] Each battery chip layer 610 may include a substrate 620, a solid thin - film battery element 626 fabricated on the substrate 620, and an insulator 628 formed on the solid thin - film battery element 626 and the substrate 620.

[0172] The substrate 620 may be made of any one of non - conductive substrate materials, such as silicon, alumina ceramic, glass, mica, etc., just to name a few. The insulator 628 may be made of a resin, such as BCB (benzocyclobutene) resin, etc. Each solid thin - film battery element 626 may include a cathode current collector (CCC) 624; a cathode; an electrolyte; an anode; and an anode current collector (ACC) 622.

[0173] The cathode current collector 624 and the anode current collector 622 may be formed on the substrate 620 corresponding to electrodes assigned different functions. In this embodiment, the functions include an anode and a cathode. The cathode current collector 624 and the anode current collector 622 may be made of any one of metals (e.g., Cu, Pt, Al, Au, etc.) and other conductive materials (e.g., graphite, carbon nanotubes, silicon, etc.).

[0174] The battery chip layers 610A - 610D may be bonded by the insulators 628A - 628C formed in the battery chip layers 610A - 610C.

[0175] As Figure 19B and 19C shown, vertically arranged electrodes 622A - 622D are located at each level of the surface of the substrate 620 of the battery pack layer 610. The vertically arranged electrodes 622A - 622D have respective electrode surfaces, and each electrode surface contacts the vertical conductor 630, thereby generating a spiral or spiral - stepped structure. The novel structure of the vertical conductor is beneficial for such thin - film solid - state batteries because the battery has only anode and cathode electrode assignments.

[0176] Figures 20A - 20C Cross - sectional views of the structures obtained at each step of the related assembly process are shown, where multiple electrode layouts are specifically designed for each stacked layer level.

[0177] Referring to Figure 20A, the related assembly process includes the step of preparing a plurality of wafers 710A to 710D, each wafer including an electrode layout specifically designed for a corresponding stack level. Refer to Figure 20B , the related assembly process further includes the steps of sequentially stacking a plurality of wafers 250A to 250D with adhesives 702B to 702D and forming vias 728 in wafers 710A to 710D to expose electrode surfaces 712A to 712D. Refer to Figure 20C , the related assembly process includes the step of filling the vias 728 with a conductive material 730.

[0178] As Figure 20A , Figure 20B and Figure 20C shown, when the method of drilling vias after stacking is adopted, the end electrodes for the vias are usually designed as a stepped structure to ensure sufficient contact with the conductive material. Therefore, it is required that the design of the vias is different for each stack level, even if the chips are homogeneous (i.e., homogeneous integration).

[0179] As Figure 20A , 20B and 20C shown, the electrode design and the mask pattern are unique for each stack level of the wafer. In this case, a unique part number (P / N) is assigned to each stack level of the wafer. Therefore, multiple P / Ns are required, which complicates production control. In addition, when the yields at each wafer level are significantly different, many remaining wafers will be produced, thus reducing the efficiency of the production process.

[0180] Contrary to the related assembly process, in the assembly process according to one or more embodiments of the present invention, the types of chip design, mask design, and the number of components can be reduced regardless of the stack level. Therefore, the design workload, non-recurring engineering costs, complexity of production control, and production waste can be reduced. Thereby, the production control of the chip assembly can be simplified, and the production efficiency of the chip assembly can be improved.

[0181] Stacked chip structures are generally low-cost and easy to manufacture, and have reliable connectivity. Note that some embodiments may not have these potential advantages, and these potential advantages are not required for all embodiments.

[0182] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, steps, layers, elements and / or components, but do not preclude the presence or addition of one or more other features, steps, layers, elements, components and / or combinations thereof.

[0183] If there are, all corresponding structures, materials, acts and equivalents of the means or step plus function elements in the following claims are intended to include any structure, material or act for performing the function in combination with other claimed elements specifically claimed. For purposes of illustration and description, a description of one or more aspects of the invention has been given, but is not intended to be exhaustive or to limit the invention to the disclosed form.

[0184] Without departing from the scope of the described embodiments of the invention, many modifications and variations will be apparent to one of ordinary skill in the art. The terms used herein have been chosen to best explain the principles of the embodiments, the practical application, or improvements made to the technology found in the marketplace, or to enable other ordinary skilled artisans in the art to understand the embodiments disclosed herein.

Claims

1. A method of assembling multiple chips, comprising: preparing multiple chip layers, each chip layer including at least one chip block, and each chip block including multiple electrodes assigned the same function; successively rotating and stacking the multiple chip layers to configure a stack of at least one overlapping chip block, with each stack maintaining multiple sets of vertically arranged electrodes displaced in a horizontal plane; for at least one set of the multiple sets, forming vias at least partially within the multiple chip layers to expose the surfaces of the vertically arranged electrodes in at least one of the multiple sets; and filling the vias with a conductive material.

2. The method according to claim 1, wherein the at least one chip block includes an array of chip blocks arranged in a rotationally symmetric manner, and the stacking of the multiple chip layers is performed such that each chip block in an array of one of the multiple chip layers overlaps with a symmetrically positioned chip block in an array of the other chip layers among the multiple chip layers, and at least one stack of the overlapping chip blocks includes an array of stacks of overlapping chip blocks.

3. The method according to claim 2, wherein each chip block has the same shape, the same shape having the same rotational symmetry as the arrangement of the array of chip blocks, and the multiple electrodes of each chip block have corresponding surfaces, the corresponding surfaces being arranged such that each surface is configured to be adjacent to and at least partially displaced from the other surfaces when a rotational operation is performed around the center of the chip block.

4. The method according to claim 2, wherein the stacking of the multiple chip layers is performed such that the surfaces of the vertically arranged electrodes in the set are arranged to form a circle in a horizontal plane.

5. The method according to claim 2, wherein the stacking of the multiple chip layers comprises: combining the multiple chip layers with one or more insulating adhesive layers, and each stack of the overlapping chip blocks holding a corresponding portion of each of the one or more insulating adhesive layers.

6. The method according to claim 5, wherein each corresponding portion of at least two of the one or more insulating adhesive layers has an opening as part of the via to be formed.

7. The method according to claim 6, wherein each electrode surface is configured to serve as a stopper for preventing hole formation and has a shape enabling the formation of a central portion of the via penetrating the multiple chips, the central portion of the via being the portion not covered by any of the electrode surfaces.

8. The method according to claim 2, wherein the rotational symmetry of the arrangement of the array is n-fold rotational symmetry, and each rotation performed when stacking one of the chip layers on another is a rotation of 360 / n*i (i = 1,..., n - 1) degrees around the center of the array relative to the stacking basic position, and the number of chip layers is n, each chip block has a unit shape arranged in a checkerboard pattern, and the via is formed through n or n - 1 chip layers.

9. The method according to claim 8, wherein n is 4, and each chip block has an approximately square shape.

10. The method according to claim 2, wherein the preparation of the plurality of chip layers, the stacking of the plurality of chip layers, and the formation of the vias are repeatedly performed to obtain a plurality of stacked layer assemblies, and the formation of the vias is performed such that the vias partially penetrate each stacked layer assembly, and the method further comprises: stacking the plurality of stacked layer assemblies such that the vias of the stacked layer assemblies communicate with each other, and simultaneously filling the vias of the plurality of stacked layer assemblies.

11. The method according to claim 2, wherein the preparation of the plurality of chip layers and the stacking of the plurality of chip layers are repeatedly performed to obtain a plurality of stacked layer assemblies, and the method further comprises: stacking the plurality of stacked layer assemblies with a translational displacement, and simultaneously performing the formation and filling of the vias for the plurality of stacked layer assemblies, respectively.

12. The method according to claim 2, wherein each chip layer prepared has the form of a wafer or a panel, and the method further comprises: cutting the plurality of chip layers into a plurality of chip components, each chip component corresponding to each stack of the overlapping chip blocks.

13. The method according to claim 1, wherein the formation of the vias is performed by etching and / or laser processing, and the filling of the vias is performed by injection molding welding (IMS) technology.

14. The method according to claim 1, wherein each chip block has a semiconductor device or a thin film battery.

15. A chip structure, comprising: a chip layer including at least one chip block, each chip block having a plurality of regions in which vias passing through the chip layer are allowed to be formed; and a plurality of electrodes located at corresponding positions of the regions of each chip block, the plurality of electrodes being assigned the same function and having corresponding electrode surfaces, the electrode surfaces being arranged such that when a rotation operation around the center of the chip block is applied to another electrode surface among the electrode surfaces, each electrode surface is configured to be adjacent to the other electrode surface among the electrode surfaces and has a displacement in a horizontal plane.

16. The chip structure according to claim 15, wherein the at least one chip block of the chip layer includes an array of chip blocks arranged in a rotationally symmetric manner such that when a rotation operation around the center of the array of the chip layer is applied to other symmetrically positioned chip blocks, each chip block in the array of the chip layer overlaps with the other symmetrically positioned chip blocks in the array of the chip layer.

17. The chip structure according to claim 16, wherein each chip block in the array of the chip layer has the same shape, and the same shape has the same rotational symmetry as the arrangement of the array of the chip blocks.

18. The chip structure according to claim 16, wherein the chip structure further comprises: an insulating adhesive layer formed on or in the chip layer, each insulating adhesive layer including a plurality of portions corresponding to the array of chip blocks.

19. The chip structure according to claim 18, wherein each portion of the insulating adhesion layer has a plurality of openings located at positions on the surface of the electrode.

20. The chip structure according to claim 17, wherein the rotational symmetry is an n-fold rotational symmetry, the rotation operation about the center of the array is a rotation of 360 / n degrees, the rotation operation about the center of the chip block is a rotation of 360 / n degrees, and each chip block in the array has a unit shape arranged in a checkerboard pattern.

21. A stacked chip structure comprising: a plurality of chip structures according to claim 15, providing a plurality of rotationally stacked chip layers so as to form a stack of overlapping chip blocks, at least two of the overlapping chip blocks in the stack having corresponding through holes communicating with each other to form through vias, and a plurality of vertically arranged electrode groups assigned the same function, for the stack of overlapping chip blocks, the vertically arranged electrodes in each group being arranged to have a displacement in a horizontal plane; and a conductive material filled in the through vias of the stack of the overlapping chip blocks, the conductive material filled in the through vias being in contact with the electrode surfaces of the vertically arranged electrodes of one of the groups.

22. The stacked chip structure according to claim 21, wherein each chip layer includes one chip block, the plurality of chip layers are stacked such that the chip block of one chip layer in the chip layers overlaps the chip block of another chip layer in a rotationally symmetric manner, and the stacked chip structure is a single chip component.

23. The stacked chip structure according to claim 21, wherein each chip layer includes an array of chip blocks arranged in a rotationally symmetric manner, the plurality of chip layers are stacked such that each chip block in the array of one chip layer in the chip layers overlaps a symmetrically positioned chip block in the array of another chip layer in the chip layers, so as to configure the stack of the overlapping chip blocks and one or more other stacks of overlapping chip blocks, the stack of the overlapping chip blocks and the other stacks being arranged in an array.

24. The stacked chip structure according to claim 23, wherein the electrode surfaces of the vertically arranged electrodes of one of the plurality of groups are arranged to form one or more circles around the center of the through via, and the plurality of chip layers include at least one unit of a stacked layer, each unit of the stacked layer corresponding to one circle.

25. The stacked chip structure according to claim 23, wherein the stacked chip structure further comprises: two or more insulating adhesion layers, each insulating adhesion layer bonding two adjacent chip layers, and including a plurality of portions corresponding to the array of the stack of the overlapping chip blocks, at least two corresponding portions related to the group having corresponding openings as parts of the through vias.

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