Method of processing a wafer

Abstract

A method of processing a wafer is provided, which is a technique for etching a silicon-containing film with a high aspect ratio. The method of processing a wafer according to an example embodiment includes a step of preparing a wafer having a substrate and a silicon-containing film provided on the substrate. The method also includes a step of forming a hard mask on the silicon-containing film. The method also includes a step of etching the silicon-containing film using the hard mask. The hard mask has a first film containing tungsten and provided on the silicon-containing film, and a second film containing zirconium or titanium and oxygen and provided on the first film.

Description

Technical Field

[0001] Exemplary embodiments of this disclosure relate to methods of processing wafers. Background Technology

[0002] In the manufacture of electronic devices such as semiconductor devices, plasma etching is performed on the silicon-containing film to form openings such as holes or trenches. A mask is placed on the silicon-containing film to form these openings. Etching resist masks are known as such masks.

[0003] In recent years, components within electronic devices have developed three-dimensional structures. This results in the formation of considerably deep openings in silicon-containing films. However, resist masks are largely consumed during plasma etching of silicon-containing films. Therefore, hard masks are used. As described in Patent Documents 1-4, hard masks formed of tungsten silicide or titanium nitride (TiN) are used.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2007-294836;

[0005] Patent Document 2: Japanese Patent Application Publication No. 2003-243526;

[0006] Patent document 3: Japanese Patent Application Publication No. 2005-150403;

[0007] Patent Document 4: U.S. Patent Application Publication No. 2019 / 0019675. Summary of the Invention

[0008] This disclosure provides a technique for etching silicon-containing films at high aspect ratios.

[0009] In one exemplary embodiment, a method for processing a wafer is provided. The method includes a step of preparing a wafer having a substrate and a silicon-containing film disposed on the substrate. The method further includes a step of forming a hard mask on the silicon-containing film. The method also includes a step of etching the silicon-containing film using the hard mask. The hard mask has a first film comprising tungsten disposed on the silicon-containing film, and a second film comprising zirconium or titanium and oxygen disposed on the first film.

[0010] Invention Effects

[0011] According to this disclosure, a technique for etching silicon-containing films at a high aspect ratio is provided. Attached Figure Description

[0012] Figure 1 This is a diagram illustrating a method for processing a wafer according to an exemplary embodiment.

[0013] Figure 2 It means execution Figure 1The diagram shows an example of the configuration of a film-forming apparatus that can be used with the method shown.

[0014] Figure 3 It means execution Figure 1 The diagram shows an example of the configuration of a coating apparatus that can be used with the method shown.

[0015] Figure 4 It means that with Figure 1 The diagram shows the multiple states of the wafer that can be achieved by executing the method shown.

[0016] Figure 5 This indicates that the evaluation has been implemented. Figure 1 A diagram showing the result of the second hard mask on the wafer using the method illustrated.

[0017] Figure 6 This indicates that the evaluation has been implemented. Figure 1 The figure shows the experimental results of the second hard mask of the wafer using the method shown.

[0018] Figure 7 It means that it has been executed. Figure 1 The figure shows the experimental results of etching the first hard mask using a second hard mask on a wafer using the method shown. Detailed Implementation

[0019] In recent years, with the increasing speed and density of electronic devices, it has become increasingly difficult to process tiny patterns. In particular, the formation of capacitors in memory devices (DRAM) requires a CD (critical dimension) of less than 20nm and an A / R (aspect ratio) of more than 50 with a depth of more than 1.0μm.

[0020] Currently, amorphous silicon is used as the hard mask for etching silicon-containing films. For example, a silicon oxide hard mask is used for etching amorphous silicon. With increasing A / R (Aspect Ratio), the amorphous silicon hard mask must be thickened. If the amorphous silicon hard mask becomes thicker, the silicon oxide hard mask used for etching the amorphous silicon must also become thicker. Increased mask thickness suppresses perpendicular ion incidence, leading to twisting. Therefore, a hard mask with higher plasma etching resistance than amorphous silicon is required for etching silicon-containing films. Furthermore, the hard mask used for etching with this higher plasma etching resistance also requires similarly higher plasma etching resistance.

[0021] The following describes various exemplary embodiments. In one exemplary embodiment, a method for processing a wafer is provided. The method includes a step of preparing a wafer having a substrate and a silicon-containing film disposed on the substrate. The method further includes a step of forming a hard mask on the silicon-containing film. The method includes a step of etching the hard mask to form a pattern on the hard mask. The method further includes a step of etching the silicon-containing film using the patterned hard mask. The hard mask has a first film containing tungsten and disposed on the silicon-containing film, and a second film containing zirconium or titanium and oxygen and disposed on the first film.

[0022] In another exemplary embodiment, a method for processing a wafer is provided. The method includes: a step of preparing a wafer having a substrate and a silicon-containing film disposed on the substrate. The method further includes: a step of forming a first film containing tungsten on the silicon-containing film. The method further includes: a step of forming a second film containing zirconium or titanium and oxygen on the first film. The method further includes: a step of using the second film as a mask and etching the first film to form a pattern on the first film. The method further includes: a step of using the patterned first film as a mask and etching the silicon-containing film.

[0023] In one exemplary embodiment described above, the silicon-containing film is etched using a hard mask having a first film containing tungsten disposed on the silicon-containing film and a second film containing zirconium or titanium disposed on the first film. The second film containing zirconium or titanium has sufficiently high etch resistance compared to the first film containing tungsten. Therefore, shape anomalies of the pattern are sufficiently suppressed during pattern formation on the hard mask having the first and second films. Thus, shape anomalies of the pattern formed on the silicon-containing film by etching the silicon-containing film having a pattern of sufficient shape anomaly suppression (and the hard mask) can also be sufficiently suppressed. Therefore, even when the pattern formed on the silicon-containing film has a high aspect ratio, twisting and the like are suppressed sufficiently well.

[0024] In one exemplary embodiment, the first film can be formed by sputtering onto a silicon-containing film during the process of forming the first film.

[0025] In one exemplary embodiment, in the process of forming the first film, the first film can be formed on a silicon-containing film by chemical vapor deposition.

[0026] In one exemplary embodiment, in the process of forming the second film, the second film can be formed on the first film by a coating process.

[0027] In one exemplary embodiment, the coating process may be a spin coating process.

[0028] In one exemplary embodiment, during the process of forming the second film, the second film can be formed on the first film by chemical vapor deposition or atomic layer deposition.

[0029] In one exemplary embodiment, the etching of the second film during the second film patterning process can be anisotropic etching using a plasma containing a gas containing halogen atoms. Similarly, the etching of the first film during the first film patterning process can be anisotropic etching using a plasma containing a gas containing halogen atoms.

[0030] In one exemplary embodiment, the first film and the second film may each be an amorphous film.

[0031] In one exemplary embodiment, the first film may also comprise silicon.

[0032] In one exemplary embodiment, the etching of the silicon-containing film in the process of etching the silicon-containing film can be anisotropic etching using plasma of fluorocarbon gas or plasma of hydrofluorocarbon gas.

[0033] In one exemplary embodiment, the silicon-containing film can be a single-layer film having any one of a monocrystalline silicon film, a polycrystalline silicon film, a silicon oxide film, and a silicon nitride film, or a multilayer film having any two or more of a monocrystalline silicon film, a polycrystalline silicon film, a silicon oxide film, and a silicon nitride film.

[0034] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the same reference numerals will be used to label the same or equivalent parts in the various drawings.

[0035] The following is for reference Figures 1-4 An exemplary embodiment of the method for processing a wafer will be described. Figure 1 This is a flowchart illustrating a method (referred to as method MT) for processing a wafer according to an exemplary embodiment. Figure 2 It means execution Figure 1 The diagram shows an example of the configuration of a film-forming device that can be used in the method MT. Figure 3 It means execution Figure 1 The diagram shows an example of the configuration of a coating apparatus that can be used with the method MT. Figure 4 It means that with Figure 1 The diagram shows the multiple states of the wafer W that can be achieved by the execution of the method MT.

[0036] First, refer to Figure 2 The configuration of a film-forming apparatus 10 according to an exemplary embodiment will be described. Figure 2The film-forming apparatus 10 shown is an apparatus for film formation by sputtering. The film-forming apparatus 10 includes a chamber body 12. The chamber body 12 has a generally cylindrical shape. The chamber body 12 provides its internal space as a chamber 12c. The chamber body 12 is formed, for example, from a conductor such as aluminum. The chamber body 12 is connected to a ground potential.

[0037] An exhaust device 14 for depressurizing chamber 12c is connected via an adapter 14a to the bottom of chamber body 12. The exhaust device 14 includes a pressure controller and a pressure-reducing pump such as a dry pump and / or a turbomolecular pump. Additionally, an opening 12t is formed on the side wall of chamber body 12 for the wafer W to be moved into and out of chamber 12c. This opening 12t can be opened and closed by a gate valve 12g.

[0038] A port 12p is provided in the chamber body 12. Port 12p provides a flow path for introducing gas into the chamber body 12. A gas supply unit is connected to port 12p. Gas is supplied from the gas supply unit to the chamber 12c via port 12p. The gas supplied to the chamber 12c can be a rare gas or an inert gas such as nitrogen.

[0039] A worktable 16 is provided inside chamber 12c. The worktable 16 is configured to support a wafer W disposed thereon. The worktable 16 may also have an electrostatic chuck for holding the wafer W. In addition, the worktable 16 may also have a temperature adjustment mechanism such as a heater.

[0040] The worktable 16 is connected to the drive mechanism 18. The drive mechanism 18 includes a support shaft 18a and a drive unit 18b. The support shaft 18a extends from directly below the worktable 16 through the bottom of the chamber body 12 to the outside of the chamber body 12. The central axis of the support shaft 18a coincides with the vertically extending axis AX. A sealing member 40 is provided between the support shaft 18a and the bottom of the chamber body 12. The sealing member 40 is configured to seal the space between the bottom of the chamber body 12 and the support shaft 18a in a manner that allows the support shaft 18a to rotate and move vertically. Such a sealing member 40 can be, for example, a magnetohydrodynamic seal.

[0041] A worktable 16 is attached to one end of the support shaft 18a, and a drive device 18b is connected to the other end of the support shaft 18a. The drive device 18b is configured to generate a driving force for rotating and moving the support shaft 18a vertically. The worktable 16 is configured to rotate along the axis AX center by rotating the support shaft 18a, and move vertically as the support shaft 18a moves vertically.

[0042] A bracket 20 and a bracket 22 are mounted on the top of the chamber body 12. Both brackets 20 and 22 are made of metal. The bracket 20 is supported on the top of the chamber body 12 via an insulating member 24. The bracket 22 is supported on the top of the chamber body 12 via an insulating member 26. The bracket 20 holds the target material 28 (first target material), and the bracket 22 holds the target material 30 (second target material).

[0043] Supports 20 and 22 hold targets 28 and 30 respectively, such that targets 28 and 30 are configured approximately symmetrically with respect to a virtual plane including axis AX. Additionally, supports 20 and 22 hold targets 28 and 30 such that targets 28 and 30 are tilted toward axis AX as they face upwards.

[0044] A power supply 32 is electrically connected to the support 20. The power supply 32 is configured to generate a voltage applied to the support 20. The voltage from the power supply 32 is applied to the target 28 via the support 20. The power supply 32 can be a DC power supply or a high-frequency power supply. If the power supply 32 is a high-frequency power supply, it is connected to the support 20 via a matching adapter to bring its load-side impedance close to or match the matching point.

[0045] A power supply 34 is electrically connected to the support 22. The power supply 34 is configured to generate a voltage applied to the support 22. The voltage from the power supply 34 can also be applied to the target 30 via the support 22. The power supply 34 can be a DC power supply or a high-frequency power supply. In the case that the power supply 34 is a high-frequency power supply, it is connected to the support 22 via a matching adapter to bring its load-side impedance close to or match the matching point.

[0046] The film-forming apparatus 10 may also include a cathode magnet 36 and a cathode magnet 38. The cathode magnet 36 is disposed on the outside of the chamber body 12 in a manner facing the target material 28 via a support 20. The cathode magnet 38 is disposed on the outside of the chamber body 12 in a manner facing the target material 30 via a support 22. A magnet driving unit 36a and a magnet driving unit 38a are respectively connected to the cathode magnet 36 and the cathode magnet 38.

[0047] During film deposition in the film deposition apparatus 10, a wafer W is moved into the chamber body 12, and the wafer W is placed on and supported by the stage 16. Furthermore, the vertical position of the stage 16 is adjusted by the drive mechanism 18, and the stage 16 rotates along the axis AX. Moreover, the rotation of the stage 16 continues during film deposition.

[0048] Next, gas is supplied to chamber 12c from the gas supply unit, and the pressure in chamber 12c is reduced by the exhaust device 14. Furthermore, voltage is applied to target 28 and target 30 via power supplies 32 and 34. Additionally, cathode magnets 36 and 38 are driven by magnet drive units 36a and 38a, respectively. As a result, plasma is concentrated near target 28 and target 30.

[0049] Furthermore, positive ions in the plasma collide with targets 28 and 30, thereby releasing their respective constituent materials from targets 28 and 30. The released constituent materials are deposited on the wafer W. Thus, a film is formed on the wafer W.

[0050] In one embodiment, target 28 and target 30 may be targets containing tungsten and silicon, respectively. In the targets 28 and 30 of this embodiment, the tungsten concentration and silicon concentration are adjusted such that the film formed on the wafer W is an amorphous film containing tungsten and silicon.

[0051] When the target material used in the film deposition apparatus 10 is a target material containing tungsten and silicon, at least one of the targets 28 and 30 can be used for film deposition. When only one of the targets 28 and 30 is used for film deposition, a voltage is applied only to the support holding that single target. Furthermore, only the cathode magnet corresponding to that single target is driven by the corresponding magnet drive unit.

[0052] In another embodiment, target 28 is formed of tungsten, and target 30 is formed of silicon. In this embodiment, both target 28 and target 30 are used for film formation. Furthermore, the voltage applied to target 28 and the voltage applied to target 30 are adjusted to form an amorphous film containing tungsten and silicon on wafer W.

[0053] Next, refer to Figure 3 The configuration of a coating apparatus PM2 according to an exemplary embodiment will be described. The coating apparatus PM2 includes a box station PM10, a processing station PM11, and an interface station PM13. The coating apparatus PM2 may have a configuration in which the box station PM10, the processing station PM11, and the interface station PM13 are integrally connected.

[0054] The cassette station PM10 is configured to house multiple wafers W in a cassette C for loading and unloading. The processing station PM11 has multiple processing devices configured to perform prescribed processing on the wafers W. The interface station PM13 is configured to transfer wafers W between itself and the exposure device PM12 adjacent to the processing station PM11.

[0055] A box-loading platform PM20 is provided at the box station PM10. Multiple box-loading plates PM21 are provided on the box-loading platform PM20 to hold the box C when it is moved in or out of the coating device PM2.

[0056] The PM10 station has such a setting Figure 3 The wafer transport device PM23 shown is capable of moving along a transport path PM22 extending in the X direction. The wafer transport device PM23 is also capable of moving in the vertical direction and about the vertical axis (θ direction). The wafer transport device PM23 is configured to transport wafers W between the cassette C on each cassette carrier PM21 and the transfer device of the third block G3 of the processing station PM11 described later.

[0057] The processing station PM11 is equipped with multiple, for example, four blocks (the first block G1, the second block G2, the third block G3, and the fourth block G4) containing various devices. For example, on the front side of the processing station PM11 ( Figure 3 The first G1 is located on the negative X-direction side. On the rear side of the PM11 processing station ( Figure 3 A second G2 is installed on the positive X-direction side. Additionally, on the PM10 side of the PM11 processing station (…). Figure 3 A third G3 is installed on the negative Y-direction side. On the interface station PM13 side of processing station PM11 ( Figure 3 A fourth G4 is set on the positive Y-direction side.

[0058] The first piece G1 is equipped with multiple liquid processing devices. These devices may include, for example, a developing device, an organic solvent supply device, an anti-reflective film forming device, a neutral layer forming device, a resist coating device, and a block copolymer coating device. The developing device, organic solvent supply device, anti-reflective film forming device, neutral layer forming device, resist coating device, and block copolymer coating device may be arranged, for example, stacked sequentially from below. Alternatively, the developing device, organic solvent supply device, anti-reflective film forming device, neutral layer forming device, resist coating device, and block copolymer coating device may be arranged in three parallel rows along a horizontal direction. The number and arrangement of the liquid processing devices can be arbitrarily selected.

[0059] The developing apparatus is configured to perform a developing process on the wafer W. The organic solvent supply apparatus is used as a polymer removal device configured to supply organic solvent to the wafer W. The antireflective film forming apparatus is configured to form an antireflective film on the wafer W. The neutral layer forming apparatus is configured to coat the wafer W with a neutralizing agent to form a neutral layer. The photoresist coating apparatus is configured to coat the wafer W with a photoresist solution to form a photoresist film. The block copolymer coating apparatus is configured to coat the wafer W with a block copolymer.

[0060] In the liquid processing apparatus described above, a spin coating process is performed to coat a pre-set coating liquid onto a wafer W. In the spin coating process, for example, the coating liquid is discharged from a coating nozzle onto the wafer W, and the wafer W is rotated using a coating machine, causing the coating liquid to spread onto the surface of the wafer W.

[0061] In the second unit G2, the heat treatment device, ultraviolet irradiation device, adhesion device, peripheral exposure device, and polymer separation device are arranged side by side in the vertical and horizontal directions. The number and configuration of the heat treatment device, ultraviolet irradiation device, adhesion device, peripheral exposure device, and polymer separation device can be arbitrarily selected.

[0062] The heat treatment apparatus is configured to perform heat treatment on a wafer W. The heat treatment apparatus includes a hot plate for holding and heating the wafer W, and a cooling plate for holding and cooling the wafer W, thus enabling both heating and cooling processes to be performed.

[0063] The ultraviolet irradiation device is configured to irradiate the wafer W with ultraviolet light. The adhesion device is configured to perform a hydrophobic treatment on the wafer W. The peripheral exposure device is configured to expose the outer periphery of the wafer W. The polymer separation device is configured to separate the block copolymer phase coated on the wafer W using the block copolymer coating device into a hydrophilic polymer and a hydrophobic polymer.

[0064] Multiple handover devices are arranged sequentially from below on the third G3 block. Multiple handover devices are arranged sequentially from below on the fourth G4 block.

[0065] A wafer handling area D is formed in the region enclosed by the first G1 to the fourth G4. Multiple wafer handling devices PM70 are arranged in the wafer handling area D.

[0066] The wafer handling device PM70 is configured to move within the wafer handling area D and is capable of handling wafers W to designated locations within the surrounding first G1, second G2, third G3, and fourth G4. Each of the multiple wafer handling devices PM70 has a handling arm PM70a. The handling arm PM70a is configured, for example, to be capable of moving along the Y-direction, X-direction, θ-direction, and vertical direction.

[0067] like Figure 3 As shown, a wafer transport device PM 90 is provided next to the positive X-direction side of the third block G3. The wafer transport device PM 90 has, for example, a transport arm PM 90a configured to move along the X-direction, the θ-direction, and the vertical direction. The wafer transport device PM 90 is configured to move vertically while supporting the wafer W, and is capable of transporting the wafer W to the various transfer devices within the third block G3.

[0068] Interface station PM13 is equipped with a wafer transport device PM91 and a transfer device PM92. The wafer transport device PM91 has a transport arm PM91a configured to move, for example, along the Y direction, the θ direction, and the vertical direction. The wafer transport device PM91 is configured, for example, to support the wafer W on the transport arm and to transport the wafer W between the transfer devices, the transfer device PM92, and the exposure device PM12 within the fourth block G4.

[0069] A control unit PM300 is connected to both the coating apparatus PM2 and the film-forming apparatus 10. The control unit PM300 is, for example, a computer, and has a program storage unit (not shown). The program storage unit stores a computer program for uniformly controlling the coating apparatus PM2 and the film-forming apparatus 10. The program storage unit also stores information for implementing… Figure 1 The method shown is a computer program for MT.

[0070] Such computer programs can also be recorded on computer-readable storage media such as hard disks, floppy disks, optical disks, magnetic optical arrays, and memory cards. In this case, the computer program recorded on the recording medium can be installed on the control unit PM300 for use.

[0071] return Figure 1 The method MT will be described in detail. Method MT consists of steps ST1 to ST6. In step ST1, preparation... Figure 4 The wafer W in state K1 is shown. The wafer W in state K1 has a substrate 101 and a silicon-containing film 102. The silicon-containing film 102 is disposed on the substrate 101. Furthermore, in... Figure 4 In the process, a silicon-containing film 102 is disposed in contact with the substrate 101, but other films with conductivity and insulation may also be disposed between the substrate 101 and the silicon-containing film 102. The silicon-containing film 102 may be a single-layer film having any one of a monocrystalline silicon film, a polycrystalline silicon film, a silicon oxide film, and a silicon nitride film, or a multilayer film having any two or more of the above films.

[0072] Then in process ST2, as Figure 4 As shown in state K2 of the wafer W, a hard mask is formed on the silicon-containing film 102. This hard mask includes a first hard mask 103 (first film) and a second hard mask 104 (second film) disposed on the first hard mask 103. More specifically, in process ST2, the first hard mask 103 and the second hard mask 104 are sequentially formed on the silicon-containing film 102. In process ST2, a carbon-containing film 105 may also be formed on the second hard mask 104.

[0073] In step ST2, firstly, a first hard mask 103 is formed on the silicon-containing film 102. The first hard mask 103 is a hard mask for plasma etching of the silicon-containing film 102. This plasma etching can be dry etching (anisotropic plasma etching) using plasma of halogen-based gases. The first hard mask 103 has high resistance to this plasma etching (step ST4 described later).

[0074] The first hard mask 103 comprises tungsten (W) and silicon (Si). The first hard mask 103 is an amorphous film comprising W and Si. For example, the first hard mask 103 comprises WSi. The concentration of W in the first hard mask 103 is within a range that maintains the amorphous state and achieves heat resistance (anti-crystallization). The film thickness of the first hard mask 103 can be in the range of 300–400 nm, but can be set according to the film thickness of the silicon-containing film 102 and etching selectivity.

[0075] The first hard mask 103 has high resistance to plasma etching (process ST4), so the film thickness of the first hard mask 103 can be thinner and the twisting is reduced.

[0076] The deposition of the first hard mask 103 can be performed, for example, by sputtering. The deposition of the first hard mask 103 can be performed using a film deposition apparatus 10, utilizing sputtering or co-sputtering with a single target or multiple targets. In the case of co-sputtering, the tungsten concentration can be arbitrarily set.

[0077] The material used for film deposition on the first hard mask 103 via sputtering, when the first hard mask 103 contains WSi, can be WSi in a monolithic system, or W and Si in a binary system. The temperature used for film deposition on the first hard mask 103 via sputtering can be room temperature. When sputtering is used for film deposition on the first hard mask 103, the tungsten concentration and crystallinity can be well controlled, and impurities can be reduced.

[0078] Furthermore, the first hard mask 103 can also be deposited using Chemical Vapor Deposition (CVD). In this case, the first hard mask 103 can be deposited using thermal or plasma-based vapor phase growth. In the CVD-based deposition of the first hard mask 103, the concentration of W can be arbitrarily set by adjusting the mixing ratio of the gases used for deposition.

[0079] In step ST2, after the first hard mask 103 is formed, the second hard mask 104 is formed. Through step ST2, the second hard mask 104 is formed on the first hard mask 103.

[0080] The second hard mask 104 is a hard mask used for plasma etching of the first hard mask 103. The plasma etching can be dry etching (anisotropic reactive ion etching) using plasma with halogen gas.

[0081] The second hard mask 104 exhibits high resistance to plasma etching (step ST4 described later). The second hard mask 104 comprises zirconium (Zr) or titanium (Ti) and oxygen (O). The second hard mask 104 is an amorphous film containing Zr or Ti and oxygen. For example, the second hard mask 104 can be zirconium oxide or titanium oxide. The concentration of Zr or Ti in the second hard mask 104 is within a range that maintains the amorphous state and achieves heat resistance (anti-crystallization). The film thickness of the second hard mask 104 can be in the range of 30–200 nm, but can be set according to the film thickness of the first hard mask 103 and etching selectivity.

[0082] The second hard mask 104 is formed on the first hard mask 103 by a coating process. More specifically, the formation (film formation) process of the second hard mask 104 can be performed by, for example, spin coating. The film formation of the second hard mask 104 is performed using a coating apparatus PM2.

[0083] The material used for forming the second hard mask 104 by spin coating includes a metal oxide carboxylate containing Zr or Ti, and an organic solvent. The organic solvent may be, for example, an ether, ester, ether ester, ketone, ketone ester, etc.

[0084] The temperature (drying temperature) used for film formation of the second hard mask 104 by spin coating can be in the range of 200 to 400 degrees Celsius. The temperature used for film formation of the second hard mask 104 by spin coating can be set to the temperature range within which the first hard mask 103 and the second hard mask 104 do not crystallize (maintain an amorphous state).

[0085] When the film formation of the second hard mask 104 is performed using spin coating, it is carried out in a non-vacuum system device. Therefore, compared with the case where it is performed in a vacuum system device, the film formation process becomes easier and the cost can be reduced.

[0086] Furthermore, the second hard mask 104 can also be formed using CVD or Atomic Layer Deposition (ALD). In this case, the second hard mask 104 can be formed through thermal or plasma-based vapor phase growth or interface growth.

[0087] In step ST2, after the second hard mask 104 is formed, a carbon-containing film 105 is formed. Through step ST2, the carbon-containing film 105 is formed on the second hard mask 104.

[0088] The carbon-containing film 105 can function as a mask for plasma etching of the first hard mask 103 and the second hard mask 104. The thickness of the carbon-containing film 105 can be in the range of 200 to 300 nm, and can be set according to the thickness of the first hard mask 103 and the second hard mask 104 and the etching selectivity.

[0089] The carbon-containing film 105 can be formed, for example, by spin coating. The carbon-containing film 105 can be formed, for example, using a coating apparatus PM2. The temperature (drying temperature) used for the carbon-containing film 105 formation by spin coating can be in the range of 400 to 600 degrees Celsius. The temperature (drying temperature) used for the carbon-containing film 105 formation by spin coating can be set to a temperature range within which the first hard mask 103 and the second hard mask 104 do not crystallize (maintain an amorphous state).

[0090] Then in process ST3, such as Figure 4 As shown in the wafer W in state K3, a pattern transferred to the silicon-containing film 102 is formed on the carbon-containing film 105. The pattern can be holes or grooves.

[0091] Then in process ST4, such as Figure 4 As shown in the state K4 of the wafer W, the first hard mask 103 and the second hard mask 104 are etched according to the pattern formed on the carbon film 105.

[0092] In step ST4, an etching apparatus (not shown) is used. In step ST4, firstly, the second hard mask 104 is etched. More specifically, in step ST4, the second hard mask 104 is etched using a carbon film 105 with a pattern transferred to the silicon film 102 as a mask, and the pattern is formed on the second hard mask 104.

[0093] The etching of the second hard mask 104 is anisotropic etching using a plasma containing a gas containing halogen atoms. More specifically, the etching of the second hard mask 104 can be heteroreactive ion etching using, for example, a plasma containing Cl2 gas, BCl3 gas, etc.

[0094] In step ST4, the first hard mask 103 is then etched. More specifically, in step ST4, the first hard mask 103 is etched using a second hard mask 104, on which a pattern transferred to the silicon-containing film 102 is formed, as a mask.

[0095] The etching of the first hard mask 103 is anisotropic etching using a plasma containing a gas containing halogen atoms. More specifically, the etching of the first hard mask 103 can be anisotropic reactive ion etching using a plasma such as Cl2 gas. At the end of process ST4, the second hard mask 104 may remain, but there are also cases where the second hard mask 104 is completely removed.

[0096] Then in process ST5, such as Figure 4 As shown in state K5 of the wafer W, a hard mask is used to etch the silicon-containing film 102. In step ST5, an etching apparatus (not shown) is used. More specifically, in step ST5, a first hard mask 103 (and possibly a second hard mask 104) with a pattern transferred to the silicon-containing film 102 is used as a mask to etch the silicon-containing film 102. Thus, the pattern is formed on the first hard mask 103. Therefore, through step ST5, holes or trenches reaching the substrate 101 can be formed on the silicon-containing film 102. At the end of step ST5, only the first hard mask 103 remains.

[0097] The etching of the silicon-containing film 102 performed in process ST5 can be a heteroelectrochemical etching using plasma of fluorocarbon gas (e.g., C4F6 gas) or hydrofluorocarbon gas (e.g., CH2F2 gas).

[0098] Next, in process ST6, as follows Figure 4 As shown in the state K6 of the wafer W, the first hard mask 103 is removed. If the second hard mask 104 remains at the end of process ST5, the first hard mask 103 and the second hard mask 104 are removed together in process ST6.

[0099] The removal of the first hard mask 103 performed in step ST6 can be performed by rotary cleaning. In this case, APM (ammonia peroxide mixture) solution, FPM (hydrofluoric acid-hydrogen peroxide mixture) solution, etc., can be used as the cleaning solution. The temperature (cleaning temperature) in step ST6 can be in the range of room temperature to 70 degrees Celsius.

[0100] The following describes the experiment conducted to evaluate the second hard mask 104. In the experiment, multiple hard masks with the same configuration as the second hard mask 104 were formed, and the surfaces of these multiple hard masks were analyzed by X-ray diffraction.

[0101] Figure 5 as well as Figure 6The results obtained through this experiment are shown. In the X-ray diffraction method of this experiment, the X-ray diffraction spectra inside multiple hard masks were obtained by 2θ-ω scanning. Figure 5 as well as Figure 6 In the diagram, the horizontal axis represents the diffraction angle 2θ [deg.], and the vertical axis represents the Log intensity [au].

[0102] Figure 5 This is a graph showing the results of X-ray diffraction analysis after heat-treating three zirconia hard masks at different temperatures. Figure 5 The graphs GPa1, GPa2, and GPa3 represent the X-ray diffraction results of the hard mask of zirconia subjected to heat treatment at temperatures of 400°C, 500°C, and 580°C, respectively.

[0103] Figure 6 This is a graph showing the results of X-ray diffraction analysis after heat-treating three titanium dioxide hard masks at different temperatures. Figure 6 The figures GPb1, GPb2, and GPb3 represent the X-ray diffraction results of the titanium oxide hard mask under heat treatment at temperatures of 400°C, 500°C, and 580°C, respectively.

[0104] like Figure 5 As shown, diffraction peaks were observed on the crystal planes at heat treatment temperatures above 500°C, confirming the presence of zirconium oxide crystals within the hard mask. Conversely, no diffraction peaks were observed on the crystal planes at a heat treatment temperature of 400°C, thus confirming the near absence of zirconium oxide crystals within the hard mask.

[0105] In addition, such as Figure 6 As shown, diffraction peaks were observed on the crystal planes at heat treatment temperatures above 500°C, confirming the presence of titanium oxide crystals within the hard mask. Conversely, no diffraction peaks were observed on the crystal planes at a heat treatment temperature of 400°C, thus confirming the near absence of titanium oxide crystals within the hard mask.

[0106] Next, the experimental results of etching the first hard mask 103 using the second hard mask 104 (step ST4) will be explained. In this experiment, a hard mask forming a tungsten-silicon film was used as the first hard mask 103, and a hard mask with the same zirconium oxide, titanium oxide, and silicon oxide as the second hard mask 104 was further formed as the second hard mask 104, and step ST4 was performed. In addition, as a comparative example, a silicon oxide hard mask was formed by plasma CVD (PE CVD) using TEOS (tetraethyl orthosilicate) as the feed gas, and step ST4 was performed.

[0107] In process ST4, during the etching of the first hard mask 103, the second hard mask 104 is also etched. Therefore, Figure 7 The calculation results show the etching selectivity, which is proportional to the etch film thickness of the first hard mask 103 and the etch film thickness of the second hard mask 104. This etch film thickness is the thickness removed by etching.

[0108] The etch thickness of the first hard mask 103 is represented by EA1. The etch thickness of the second hard mask 104 is represented by EA2.

[0109] Figure 7 The vertical axis represents the etch selectivity. This etch selectivity is EA1 / EA2.

[0110] like Figure 7 As shown, it was confirmed that after heat treatment at 400 degrees Celsius or above, the second hard mask 104, whether zirconium oxide or titanium oxide, exhibits extremely high etch selectivity compared to the silicon oxide hard mask. That is, it was confirmed that the second hard mask 104, whether zirconium oxide or titanium oxide, has higher resistance to etching performed in process ST4 compared to the first hard mask 103, which is made of tungsten silicon. Therefore, when the film thickness of the first hard mask 103 is set to, for example, 400 nm, the film thickness of the second hard mask 104 can be set to approximately 20–30 nm, enabling the second hard mask 104 to be thin-filmed.

[0111] Therefore, shape anomalies of the pattern formed on the first hard mask 103 by etching the first hard mask 103 can be sufficiently suppressed. Therefore, the shape of the high aspect ratio pattern formed on the silicon-containing film 102 by etching the silicon-containing film 102 located on the lower layer of the first hard mask 103 is also sufficiently suppressed to prevent twisting and other defects.

[0112] According to the method MT of an exemplary embodiment described above, the silicon-containing film 102 is etched using a hard mask on which a first hard mask 103 and a second hard mask 104 are sequentially disposed. The first hard mask 103 contains tungsten, and the second hard mask 104 contains zirconium or titanium. The second hard mask 104 has sufficiently high etch resistance compared to the first hard mask 103. Therefore, shape anomalies of the pattern are sufficiently suppressed during pattern formation on the hard mask having the first hard mask 103 and the second hard mask 104. Therefore, shape anomalies of the pattern formed on the silicon-containing film 102 by etching the silicon-containing film 102 using the first hard mask 103 (and the second hard mask 104) with a pattern on which shape anomalies are sufficiently suppressed can also be sufficiently suppressed. Therefore, even when the pattern formed on the silicon-containing film 102 has a high aspect ratio, twisting and the like are suppressed sufficiently well.

[0113] The above descriptions have illustrated various exemplary embodiments, but the embodiments are not limited to these exemplary embodiments. Various omissions, substitutions, and modifications are also possible. Furthermore, elements from different embodiments can be combined to form other embodiments.

[0114] Based on the above description, various embodiments of this disclosure have been described in this specification for illustrative purposes. It is understood that various modifications can be made without departing from the scope and spirit of this disclosure. Therefore, the various embodiments disclosed in this specification are not intended to be limiting, and the true scope and spirit are indicated by the appended claims.

[0115] Explanation of reference numerals in the attached figures

[0116] 10…film forming apparatus, 12…chamber body, 12c…chamber, 12g…gate valve, 12p…port, 12t…opening, 14…exhaust device, 14a…adapter, 16…worktable, 18…drive mechanism, 18a…support shaft, 18b…drive device, 20…support, 22…support, 24…insulating component, 26…insulating component, 28…target, 30…target, 32…power supply, 34…power supply, 36…cathode magnet, 36a…magnet drive, 38…cathode magnet, 38a…magnet drive, 40…sealing component, AX…axis, D…wafer transport area, G1…first wafer, G2…second wafer, G3…third wafer, G4…fourth wafer, MT…method, PM10…cassette station, PM11…processing station, PM12…exposure apparatus, PM13…interface station, PM2…coating apparatus, P M20…Case placement stage, PM21…Case placement plate, PM22…Transfer path, PM23…Wafer transfer device, PM300…Control unit, PM70…Wafer transfer device, PM70a…Transfer arm, PM90…Wafer transfer device, PM90a…Transfer arm, PM91…Wafer transfer device, PM91a…Transfer arm, PM92…Transfer device, W…Wafer, K1…State, K2…State, K3…State, K4…State, K5…State, K6…State, 101…Substrate, 102…Silicon-containing film, 103…First hard mask, 104…Second hard mask, 105…Carbon-containing film.

Claims

1. A method for processing a chip, comprising: A process for preparing a wafer, wherein the wafer has a substrate and a silicon-containing film disposed on the substrate; The process of forming a hard mask on the aforementioned silicon-containing film; The process of forming a carbon-containing film on the aforementioned hard mask; The process of etching a hard mask using the aforementioned carbon-containing film as a mask to form a pattern on the hard mask; and The process of etching the silicon-containing film using the hard mask with the above-described pattern. The aforementioned hard mask has a first film containing tungsten and a second film containing zirconium or titanium and oxygen. The first film is disposed on the silicon-containing film, and the second film is disposed on the first film. In the above-described process of forming a pattern on the hard mask, the first film and the second film have the same pattern transferred to the silicon-containing film.

2. The method according to claim 1, wherein, The etching of the silicon-containing film in the above-mentioned process of etching the silicon-containing film is anisotropic etching using plasma of fluorocarbon gas or plasma of hydrofluorocarbon gas.

3. The method according to claim 1, wherein, The aforementioned silicon-containing film is a single-layer film having any one of a monocrystalline silicon film, a polycrystalline silicon film, a silicon oxide film, and a silicon nitride film, or a multilayer film having any two or more of a monocrystalline silicon film, a polycrystalline silicon film, a silicon oxide film, and a silicon nitride film.

4. A method for processing a wafer, comprising: A process for preparing a wafer, wherein the wafer has a substrate and a silicon-containing film disposed on the substrate; The process of forming a first film containing tungsten on the aforementioned silicon-containing film; The process of forming a second film comprising zirconium or titanium and oxygen on the first film described above; The process of forming a carbon-containing film on the second film mentioned above; The process of etching the second film using the carbon-containing film as a mask to form a pattern on the second film; The process of etching the first film using the second film as a mask to form a pattern on the first film; and The process of etching the silicon-containing film by using the first film with the above-described pattern as a mask. In the above-described process of forming a pattern on the first film, the first film and the second film have the same pattern transferred onto the silicon-containing film.

5. The method according to claim 4, wherein, In the above-described process of forming the first film, the first film is formed on the silicon-containing film by sputtering.

6. The method according to claim 4, wherein, In the above-mentioned process of forming the first film, the first film is formed on the silicon-containing film by chemical vapor deposition.

7. The method according to any one of claims 4 to 6, wherein, In the above-described process of forming the second film, the second film is formed on the first film by a coating process.

8. The method according to claim 7, wherein, The above coating process is a spin coating process.

9. The method according to any one of claims 4 to 6, wherein, In the above-mentioned process of forming the second film, the second film is formed on the first film by chemical vapor deposition or atomic layer deposition.

10. The method according to any one of claims 4 to 6, wherein, The etching of the second film performed in the above-mentioned process of forming the second film pattern and the etching of the first film performed in the above-mentioned process of forming the first film pattern are respectively anisotropic etching using plasma containing a gas containing halogen atoms.

11. The method according to any one of claims 4 to 6, wherein, The etching of the silicon-containing film in the above-mentioned process of etching the silicon-containing film is anisotropic etching using plasma of fluorocarbon gas or plasma of hydrofluorocarbon gas.

12. The method according to any one of claims 4 to 6, wherein, The aforementioned silicon-containing film is a single-layer film having any one of a monocrystalline silicon film, a polycrystalline silicon film, a silicon oxide film, and a silicon nitride film, or a multilayer film having any two or more of a monocrystalline silicon film, a polycrystalline silicon film, a silicon oxide film, and a silicon nitride film.

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