Method for processing semiconductor wafer and wafer manufacturing system

Abstract

A method for processing a semiconductor wafer and a wafer manufacturing system are provided, the method for processing a semiconductor wafer comprising loading a semiconductor wafer on a top surface of a wafer carrier. The method also comprises supplying a gaseous material between the semiconductor wafer and the top surface of the wafer carrier via a first gas inlet port and a second gas inlet port, the first gas inlet port and the second gas inlet port being located below a fan-shaped section of the top surface. The method further comprises supplying a fluid medium to a fluid inlet port of the wafer carrier and guiding the fluid medium from the fluid inlet port to flow through a plurality of arc-shaped channels located below the fan-shaped section of the top surface. In addition, the method comprises supplying a plasma gas above the semiconductor wafer.

Description

Technical Field

[0001] The present disclosure relates to a method for processing a semiconductor wafer and a wafer manufacturing system. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, while geometry (i.e., the smallest component (or line) that can be produced using a process) has decreased, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of processing and manufacturing ICs.

[0003] Some of the process steps used in the manufacture of semiconductors include oxidation, diffusion, doping, annealing, etching, and film deposition. Film deposition is a reaction process used to produce or deposit thin films of materials on semiconductor wafers, including, but not limited to, metals, silicon dioxide, tungsten, silicon nitride, silicon oxynitride, and various dielectrics. Unsatisfactory uniformity of films deposited on semiconductor wafers by film deposition can adversely affect the function of semiconductor devices.

[0004] Although existing apparatus and methods for producing or depositing thin films of material on wafers are generally adequate for the intended purposes of these apparatus and methods, these apparatus and methods have not been completely satisfactory in all aspects. Therefore, it would be desirable to provide solutions for forming thin films for use in wafer manufacturing systems. Summary of the invention

[0005] According to some embodiments, a method for processing a semiconductor wafer is provided, including loading a semiconductor wafer on a top surface of a wafer carrier. The method also includes supplying a gaseous material between the semiconductor wafer and the top surface of the wafer carrier via a first gas inlet port and a second gas inlet port, the first gas inlet port and the second gas inlet port being located below a fan-shaped section of the top surface. The method further includes supplying a fluid medium to a fluid inlet port of the wafer carrier and directing the fluid medium from the fluid inlet port to flow through a plurality of arc-shaped channels located below the fan-shaped section of the top surface. Additionally, the method includes supplying a plasma gas above the semiconductor wafer.

[0006] According to some embodiments, a method for processing a semiconductor wafer is provided. The method includes loading a semiconductor wafer on a top surface of a wafer carrier. The method also includes supplying a gaseous material between the semiconductor wafer and the top surface of the wafer carrier via a gas inlet port of the wafer carrier. The method further includes supplying a fluid medium to the fluid inlet port of the wafer carrier and guiding the fluid medium from the fluid inlet port to flow through a first arc-shaped channel and a second arc-shaped channel, the first arc-shaped channel and the second arc-shaped channel being located at opposite sides of the gas inlet port. The second arc-shaped channel is positioned closer to the center of the wafer carrier than the first arc-shaped channel, and the fluid medium from the fluid inlet port flows through the first arc-shaped channel before flowing through the second arc-shaped channel. In addition, the method includes supplying a plasma gas above the semiconductor wafer.

[0007] According to some embodiments, a wafer manufacturing system for processing semiconductor wafers is provided. The wafer manufacturing system includes a wafer carrier having a top surface. Many holes are formed on the top surface. The wafer manufacturing system also includes a gas inlet port, which is formed in the wafer carrier and is located below the fan-shaped section of the top surface. The gas inlet port is fluidically connected to the hole. The wafer manufacturing system further includes a fluid inlet port, a first arc-shaped channel and a second arc-shaped channel formed in the wafer carrier. The first arc-shaped channel and the second arc-shaped channel are fluidically connected to the fluid inlet port. The first arc-shaped channel and the second arc-shaped channel are located below the fan-shaped section of the top surface and at opposite sides of the gas inlet port. In addition, the wafer manufacturing system includes a gas source and a source containing fluid. The gas source is fluidly connected to the gas inlet port, and the source containing fluid is fluidly connected to the fluid inlet port. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 A schematic diagram showing a wafer fabrication system according to some embodiments;

[0010] Figure 2 According to some embodiments, Figure 1 A cross-sectional view of the wafer carrier taken along line AA;

[0011] Figure 3 Show along Figure 2 A cross-sectional view of the wafer carrier taken along line BB;

[0012] Figure 4 Show along Figure 2 A cross-sectional view of the wafer carrier taken along line CC;

[0013] Figure 5 presenting experimental results of film thickness uniformity related to different factors according to some embodiments;

[0014] Figure 6 A cross-sectional view showing a wafer stage according to some embodiments;

[0015] Figure 7 A cross-sectional view showing a wafer stage according to some embodiments;

[0016] Figure 8 A top view showing some elements of a wafer fabrication system according to some embodiments;

[0017] Fig. 9 A flow chart illustrating a method for processing a semiconductor wafer in a wafer fabrication system is shown according to some embodiments;

[0018] Fig.10 A schematic diagram showing a stage of a method of forming a film on a semiconductor wafer, according to some embodiments, in which a fluid medium and a gaseous material are supplied into a wafer stage.

[0019]

Explanation of symbols

[0020] 1: Wafer manufacturing system

[0021] 5: Semiconductor wafer

[0022] 10: Chamber

[0023] 11: Lower shell

[0024] 12: Upper cover

[0025] 13: Dome structure

[0026] 20: Processing gas delivery module

[0027] 21: First Source

[0028] 22: First gas pipeline

[0029] 23: Nozzle

[0030] 25: Second Source

[0031] 26: Second gas pipeline

[0032] 27: Air Ring

[0033] 29: Gas nozzle

[0034] 30: Cleaning gas delivery module

[0035] 31: Source

[0036] 32: Gas pipeline

[0037] 34: Gas inlet port

[0038] 33: Remote plasma generator

[0039] 40,40a,40b: Wafer holding module

[0040] 41: Base

[0041] 42: Insulator

[0042] 421,422,423,424: Perforation

[0043] 43,43a,43b: Wafer carrier

[0044] 430,430a,430b: Periphery

[0045] 431: Top surface

[0046] 432: Bottom surface

[0047] 434,434a: sector section

[0048] 435: Internal annular groove

[0049] 436,438: Hole

[0050] 437: External annular groove

[0051] 45: Support pin

[0052] 46: O-ring

[0053] 460: annular recess

[0054] 49: Radio Frequency (RF) Power Supply

[0055] 50: Air source

[0056] 51: Gas inlet port

[0057] 55: Gas inlet port

[0058] 51a, 51b, 55a, 55b: Gas inlet ports

[0059] 52: First lower channel

[0060] 53: First upper channel

[0061] 54: First Ring Channel

[0062] 56: Second lower channel

[0063] 57: Second upper channel

[0064] 58: Second Ring Channel

[0065] 59: Gaseous materials

[0066] 60: Tank containing fluid

[0067] 61, 61b: Fluid inlet port

[0068] 62,62b: Fluid outlet port

[0069] 63,63b: Fluid guiding structure

[0070] 69: Fluid Medium

[0071] 70: RF module

[0072] 80: Gas exhaust module

[0073] 90: Control module

[0074] 91: Processor

[0075] 92: Memory

[0076] S100: Method

[0077] S110,S120,S130,S140,S150: Operation

[0078] A1, A1b: The first arc channel

[0079] A2, A2b: The second arc channel

[0080] A3, A3b: The third arc channel

[0081] A4, A4b: The fourth arc channel

[0082] A5b: The fifth arc channel

[0083] B1: First Boundary Line

[0084] B2: Second Boundary Line

[0085] C: Center

[0086] C1: First connection channel

[0087] C2: Second connection channel

[0088] C3: The third connecting channel

[0089] D: Depth

[0090] E1: First terminal channel

[0091] E2: Second terminal channel

[0092] L: Reference line

[0093] P0: Distance

[0094] P1: First spacing

[0095] P2: Second spacing

[0096] P3: The third spacing

[0097] W1,W2: Width

[0098] α1: Center angle

[0099] α2, α3, α5, α6: Angle DETAILED DESCRIPTION

[0100] The following disclosure provides many different embodiments or examples for implementing many different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these specific examples are only examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the subsequent description may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is only for the purpose of simplicity and clarity, and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0101] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0102] Semiconductor device manufacturing includes many different processes. One such process is performed in an environment with a high density plasma (HDP). For example, high-density plasma chemical vapor deposition (HDP-CVD) utilizes a high-density plasma directed toward a semiconductor wafer in a reaction chamber to perform a film deposition process. To form the high-density plasma, a gas is supplied through a number of nozzles, and a power supply utilizes RF or microwave power to excite the gas mixture and direct the plasma ions into a dense region above the surface of the semiconductor wafer. The main benefit of HDP-CVD is that HDP-CVD is able to deposit films to fill high aspect ratios. However, much of the challenge of using high-density plasma is related not only to the control of the flow rate of the gas discharged through the gas nozzle, but also to the control of the wafer temperature. The increased heat load to the semiconductor wafer can lead to high wafer temperatures and cause uneven sputtering rates across the semiconductor wafer. To address this problem, embodiments of the present disclosure provide a wafer stage having a fluid guiding structure to remove heat from a semiconductor wafer and the wafer stage. In one example, the fluid guiding structure is routed around the center of the wafer stage in such a way that heat accumulated over the entire area of ​​the wafer stage can be removed with substantially the same efficiency, thereby improving uniformity in the HDP process.

[0103] Figure 1 A schematic diagram of one embodiment of a wafer manufacturing system 1 for processing a semiconductor wafer 5 by high density plasma is shown according to some embodiments. The processes performed in the wafer manufacturing system 1 may include HDP-CVD, PECVD, etching or sputtering processes. However, the wafer manufacturing system 1 is not limited to performing the above processes, and can be used in the case of processing the semiconductor wafer 5 at a high temperature, and using a wafer stage for lowering the temperature.

[0104] The semiconductor wafer 5 may be made of silicon or other semiconductor materials. Additionally or alternatively, the semiconductor wafer 5 may include other basic semiconductor materials such as germanium (Ge). In some embodiments, the semiconductor wafer 5 is made of a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or indium phosphide (InP). In some embodiments, the semiconductor wafer 5 is made of an alloy semiconductor such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP) or gallium indium phosphide (GaInP). In some embodiments, the semiconductor wafer 5 includes an epitaxial layer. For example, the semiconductor wafer 5 has an epitaxial layer overlying a bulk semiconductor. In some other embodiments, the semiconductor wafer 5 may be a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI) substrate.

[0105] The semiconductor wafer 5 may have various device elements. Examples of device elements formed in the semiconductor wafer 5 include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and / or n-channel field-effect transistors (PFET / NFET), etc.), diodes, and / or other suitable elements. Various processes are performed to form the device elements, such as deposition, etching, implantation, photolithography, annealing, and / or other suitable processes.

[0106] In some embodiments, the wafer manufacturing system 1 includes a chamber 10, a process gas delivery module 20, a cleaning gas delivery module 30, a wafer holding module 40, a gas source 50, a tank containing a fluid 60, a radio frequency module 70, a gas exhaust module 80, and a control module 90. Additional features may be added to the wafer manufacturing system 1. For additional embodiments of the wafer manufacturing system 1, some of the features described below may be replaced or eliminated.

[0107] The chamber 10 is used to accommodate one or more semiconductor wafers 5 and to perform processing on the semiconductor wafers 5. In some embodiments, the chamber 10 includes a lower housing 11 and an upper cover 12, the upper cover 12 being hinged to the lower housing 11 and rotatable relative to the lower housing 11. In some embodiments, the upper cover 12 has a dome structure 13 formed therein. The inner wall of the lower housing 11 and the dome structure 13 respectively define the lower and upper boundaries of an airtight processing area in the chamber 10 for processing the semiconductor wafers 5. The lower housing 11 and the dome structure 13 may be made of a ceramic dielectric material such as aluminum oxide or aluminum nitride.

[0108] The process gas delivery module 20 is used to supply process gas into the chamber 10. In some embodiments, the process gas delivery module 20 supplies process gas into the chamber 10 via two different paths. For example, the process gas delivery module 20 includes a first gas line 22 and a second gas line 26. The first gas line 22 is connected to a showerhead 23, which is centrally arranged at the dome structure 13. Process gas from a first source 21 is supplied into the chamber 10 via the first gas line 22 and the showerhead 23. The second gas line 26 is connected to a gas ring 27, which extends circumferentially around the lower edge of the upper cover 12. A plurality of gas nozzles 29 extend radially from the gas ring 27 toward a processing area in the chamber 10. Process gas from a second source 25 is supplied into the chamber 10 via the second gas line 26, the gas ring 27, and the gas nozzles 29.

[0109] As can be appreciated by those skilled in the art, although the first gas line 22 and the second gas line 26 are connected to different sources such as the first source 21 and the second source 25, the actual connection of the gas lines to the chamber 10 varies depending on the deposition process performed in the chamber 10. According to some other embodiments, the first gas line 22 and the second gas line 26 may be connected to the same source. In some embodiments, at least one of the first gas line 22 and the second gas line 26 is connected to two or more sources, and different types of source gases are mixed before injecting the gases into the chamber 10. The supply of process gas from the first source 21 and the first gas line 22 may be regulated by the control module 90.

[0110] The cleaning gas delivery module 30 is used to supply cleaning gas into the chamber 10 after processing of the semiconductor wafer 5 is completed. In embodiments using flammable, toxic, or corrosive gases, it may be desirable to eliminate the gas remaining in the chamber 10 after processing. In some embodiments, the cleaning gas delivery module 30 includes a gas line 32 connected to a gas inlet port 34 formed on the top of the upper cover 12. In some embodiments, as shown in FIG. Figure 1As shown, the gas inlet port 34 is configured so that one end of the first gas line 22 is received in the gas inlet port, and the showerhead 23 is positioned to overlap with and be away from the exhaust end of the gas inlet port 34. The cleaning gas from the source 31 is supplied to the chamber 10 through the gas line 32, the gas inlet port 34, and the gap between the exhaust end of the gas inlet port 34 and the showerhead 23. Since the showerhead 23 is configured at the exhaust end of the gas inlet port 34, the cleaning gas can be uniformly distributed in the chamber 10. The cleaning gas may include molecular fluorine, nitrogen trifluoride, other carbonized fluorine, or equivalent.

[0111] In some embodiments, the cleaning gas delivery module 30 further includes a remote plasma generator 33. The remote plasma generator 33 excites the cleaning gas from the source 31 into a plasma and supplies the plasma to the chamber 10 via the gas inlet port 34. The remote plasma generator 33 may include a microwave generator. The remote plasma generator 33 and the gas inlet port 34 may be made of materials that resist attack by the plasma. The remote plasma generator 33 may be placed in close proximity to the gas inlet port 34 to avoid energy loss of the plasma. Generating the plasma in the remote plasma generator 33 allows the use of an efficient microwave generator without subjecting the components in the chamber 10 to the impact of temperature, radiation, or glow discharge that may be present in the plasma formed in situ. Therefore, relatively sensitive components such as the wafer holding module 40 do not need to be covered with a dummy wafer or otherwise protected, as may be required for the original plasma cleaning process.

[0112] The wafer holding module 40 is used to hold the semiconductor wafer 5 during processing. In some embodiments, the wafer holding module 40 includes a base 41, an insulator 42, a wafer carrier 43, and a number of support pins 45. In some embodiments, the base 41 is electrically connected to a radio frequency (RF) power source 49 and acts as an electrode for regulating the plasma in the chamber 10. The insulator 42 is disposed between the base 41 and the wafer carrier 43 to electrically isolate the base 41 from the wafer carrier 43. The wafer carrier 43 is used to fix or position the semiconductor wafer 5, for example, by electrostatic force. The wafer carrier 43 can be made of alumina or aluminum ceramic material. A thermal diode (not shown in the figure) can be mounted on the wafer carrier 43 to monitor the wafer temperature by detecting, for example, thermal radiation from the wafer carrier 43. These support pins 45 are used to support the semiconductor wafer 5 when the semiconductor wafer 5 is loaded or unloaded on the wafer carrier 43 by a robot arm (not shown in the figure). The supporting pins 45 return to the wafer stage 43 to place the semiconductor wafer 5 on the top surface of the wafer stage 43 .

[0113] Figure 2 Show along Figure 1AA. In some embodiments, the wafer carrier 43 includes a plurality of inlet ports or outlet ports for connecting a pipeline to the wafer carrier 43 or for facilitating the entry or exit of a fluid to the wafer carrier 43. For example, the wafer carrier 43 includes two gas inlet ports, such as a first gas inlet port 51 and a second gas inlet port 55. In addition, the wafer carrier 43 includes a fluid inlet port 61 and a fluid outlet port 62. In some embodiments, as Figure 1 As shown, the first gas inlet port 51 and the second gas inlet port 55 (only the first gas inlet port 51 is shown in the figure) Figure 1 The wafer carrier 43 is fluidly connected to the gas source 50 (in the figure). A gaseous material 59 such as helium is supplied to the wafer carrier 43 via the first gas inlet port 51 and the second gas inlet port 55. In addition, the fluid inlet port 61 and the fluid outlet port 62 are fluidly connected to the tank 60 containing the fluid. A fluid medium 69 such as ethylene glycol from the tank 60 containing the fluid is supplied to the fluid guide structure 63 formed in the wafer carrier 43 via the fluid inlet port 61, and circulated back to the tank 60 containing the fluid via the fluid outlet port 62. The tank 60 containing the fluid may include a heat exchanger (not shown in the figure) to cool or heat the fluid medium 69. The supply of the gaseous material from the gas source 50 and the supply of the fluid medium from the tank 60 containing the fluid may be regulated by the control module 90.

[0114] Figure 3 Show along Figure 2 A cross-sectional view of the wafer carrier 43 taken along line BB, and Figure 4 Show along Figure 2 FIG. 4 is a cross-sectional view of the wafer carrier 43 taken along line CC of FIG. In some embodiments, the wafer carrier 43 is placed on the insulator 42. An O-ring 46 is placed in an annular recess 460 formed on the bottom surface 432 of the wafer carrier 43. The O-ring 46 is used to prevent fluid or gas from leaking from the first gas inlet port 51 and the second gas inlet port 55, the fluid inlet port 61, and the fluid outlet port 62. The insulator 42 may also include a plurality of through holes, such as through holes 421 to 424. The through holes 421 to 424 are respectively connected to the lower ends of the first gas inlet port 51, the second gas inlet port 55, the fluid inlet port 61, and the fluid outlet port 62 to allow insertion of a gas line or a fluid line (not shown in the figure), which is connected to the first gas inlet port 51 and the second gas inlet port 55, the fluid inlet port 61, and the fluid outlet port 62.

[0115] According to some embodiments of the present disclosure, structural features of the wafer carrier 43 are described below.

[0116] In some embodiments, the two gas inlet ports 51 and 55 are located adjacent to the perimeter 430 of the wafer stage 43. A reference line L passes between the two gas inlet ports 51 and 55 and through the center C of the wafer stage 43. The reference line L may be perpendicular to a line connecting the two inlet ports 51 and 55.

[0117] In some embodiments, the two gas inlet ports 51 and 55 are fluidly connected to grooves formed on the top surface of the wafer stage 43. Figure 3 As shown, an inner annular groove 435 and an outer annular groove 437 are formed on the top surface 431 of the wafer stage 43. The inner annular groove 435 and the outer annular groove 437 are each formed in an annular shape and are concentrically arranged relative to the center C of the wafer stage 43. The outer annular groove 437 surrounds the inner annular groove 435 and is located farther from the center C of the wafer stage 43 than the inner annular groove 435.

[0118] The first gas inlet port 51 may be fluidly connected to the inner annular groove 435 via a plurality of gas channels formed in the wafer carrier 43. Figure 3 As shown, the wafer carrier 43 includes a first lower channel 52, a first upper channel 53 and a first annular channel 54. The first lower channel 52 extends vertically in the wafer carrier 43 in such a manner that the lower end is connected to the first gas inlet port 51. The first annular channel 54 is formed below the inner annular groove 435 and is fluidically connected to the inner annular groove 435 via a plurality of holes 436 formed on the bottom of the inner annular groove 435. The first upper channel 53 extends obliquely relative to the first lower channel 52 and connects the first lower channel 52 to the first annular channel 54. Therefore, when a gas line (not shown in the figure) is connected to the first gas inlet port 51, gaseous materials can be discharged between the semiconductor wafer 5 and the top surface 431 of the wafer carrier 43 via the first lower channel 52, the first upper channel 53, the first annular channel 54, the holes 436 and the inner annular groove 435.

[0119] The second gas inlet port 55 can be fluidly connected to the outer annular groove 437 via a plurality of gas channels formed in the wafer carrier 43. Figure 4As shown, the wafer carrier 43 includes a second lower channel 56, a second upper channel 57 and a second annular channel 58. The second lower channel 56 extends vertically in the wafer carrier 43 in such a manner that the lower end is connected to the second gas inlet port 55. The second annular channel 58 is formed below the outer annular groove 437 and is fluidly connected to the outer annular groove 437 via a plurality of holes 438 formed on the bottom of the outer annular groove 437. The second upper channel 57 extends obliquely relative to the second lower channel 56 and connects the second lower channel 56 to the second annular channel 58. Therefore, when a gas line (not shown in the figure) is connected to the second gas inlet port 55, gaseous materials can be discharged between the semiconductor wafer 5 and the top surface 431 of the wafer carrier 43 via the second lower channel 56, the second upper channel 57, the second annular channel 58, the holes 438 and the outer annular groove 437.

[0120] refer to Figure 2 In some embodiments, the wafer carrier 43 has a fluid guiding structure 63 formed in the wafer carrier for guiding the flow of the fluid medium in the wafer carrier 43. In some embodiments, the fluid guiding structure 63 extends at the same level as the wafer carrier 43 away from the top surface 431 of the wafer carrier 43. The fluid guiding structure 63 extends from the first end channel E1 and terminates at the second end channel E2. The first end channel E1 is fluidically connected to the fluid inlet port 61, and the second end channel E2 is fluidically connected to the fluid outlet port 62. Between the first end channel E1 and the second end channel E2 are many arc-shaped channels, such as the first arc-shaped channel A1, the second arc-shaped channel A2, the third arc-shaped channel A3 and the fourth arc-shaped channel A4, and many connecting channels, such as the first connecting channel C1, the second connecting channel C2 and the third connecting channel C3. Although Figure 2 Four arc-shaped channels and three connecting channels are shown, but the fluid guiding structure 63 may include any number of arc-shaped channels and connecting channels. In one embodiment, the number of arc-shaped channels is less than five.

[0121] In some embodiments, the upstream end of the first arc-shaped channel A1 is connected to the downstream end of the first end channel E1 and extends in the circumferential direction of the wafer stage 43. The arc angle of the first arc-shaped channel A1 relative to the center C of the wafer stage 43 is greater than 180 degrees, for example, the arc angle of the first arc-shaped channel A1 is in the range of about 330 degrees to about 355 degrees.

[0122] The second arc-shaped channel A2 is located at the inner side of the first arc-shaped channel A1 (i.e., the side closer to the center C of the wafer stage 43). The second arc-shaped channel A2 extends in the circumferential direction of the wafer stage 43. The arc angle of the second arc-shaped channel A2 may be smaller than the arc angle of the first arc-shaped channel A1. In an exemplary embodiment, the arc angle of the second arc-shaped channel A2 relative to the center C of the wafer stage 43 is greater than 180 degrees, for example, the arc angle of the second arc-shaped channel A2 is in the range of about 300 degrees to about 330 degrees.

[0123] In some embodiments, Figure 2 As can be seen from the top view shown in , the support pin 45 is located between the first arc-shaped channel A1 and the second arc-shaped channel A2, and is configured so that interference between the support pin 45 and the first arc-shaped channel A1 or the second arc-shaped channel A2 will not occur. Figure 2 As can be seen from the top view shown in , the first gas inlet port 51 and the second gas inlet port 55 are located between the first arc-shaped channel A1 and the second arc-shaped channel A2, and are configured so that heat from the area of ​​the wafer carrier 43 surrounding the first gas inlet port 51 and the second gas inlet port 55 can be efficiently dissipated. Fig. 9 Details of the process for cooling the wafer carrier are described in the method.

[0124] The third arc-shaped channel A3 is located at the inner side of the second arc-shaped channel A2. The third arc-shaped channel A3 extends in the circumferential direction of the wafer carrier 43. The arc angle of the third arc-shaped channel A3 may be smaller than the arc angle of the second arc-shaped channel A2. In an exemplary embodiment, the arc angle of the third arc-shaped channel A3 relative to the center C of the wafer carrier 43 is greater than 180 degrees, for example, the arc angle of the third arc-shaped channel A3 is in the range of about 200 degrees to about 230 degrees.

[0125] The fourth arc-shaped channel A4 is located at the inner side of the third arc-shaped channel A3. The fourth arc-shaped channel A4 extends in the circumferential direction of the wafer carrier 43. The arc angle of the fourth arc-shaped channel A4 may be greater than the arc angle of the third arc-shaped channel A3. In an exemplary embodiment, the arc angle of the fourth arc-shaped channel A4 relative to the center C of the wafer carrier 43 is greater than 180 degrees, for example, the arc angle of the fourth arc-shaped channel A4 is in the range of about 250 degrees to about 300 degrees.

[0126] The first connecting channel C1 connects the downstream end of the first arc-shaped channel A1 to the upstream end of the second arc-shaped channel A2. The second connecting channel C2 connects the downstream end of the second arc-shaped channel A2 to the upstream end of the third arc-shaped channel A3. The second connecting channel C2 can be located directly adjacent to the fluid inlet port 61. The third connecting channel C3 connects the downstream end of the third arc-shaped channel A3 to the upstream end of the fourth arc-shaped channel A4. The third connecting channel C3 can be located directly adjacent to the fluid outlet port 62. The downstream end of the fourth arc-shaped channel A4 is connected to one end of the second end channel E2.

[0127] The first connection channel C1, the second connection channel C2, and the third connection channel C3 may extend in a direction parallel to the radial direction of the wafer carrying table 43, or may be inclined relative to the radial direction of the wafer carrying table 43. Figure 2 In the illustrated exemplary embodiment, the first connecting channel C1 extends in a direction substantially parallel to the radial direction of the wafer stage 43. In this embodiment, the first connecting channel C1 is perpendicular to the first arc-shaped channel A1 and the second arc-shaped channel A2.

[0128] In addition, the second connecting channel C2 extends in a direction inclined relative to the radial direction of the wafer carrier 43. Specifically, the second connecting channel C2 forms an acute angle with respect to the second arc-shaped channel A2, and the second connecting channel C2 forms an obtuse angle with respect to the third arc-shaped channel A3. Therefore, the flow rate of the fluid medium when passing through the intersection of the second arc-shaped channel A2 and the second connecting channel C2 may be slower than the flow rate of the fluid medium through other channels. In addition, the flow rate of the fluid medium when passing through the intersection of the third arc-shaped channel A3 and the second connecting channel C2 may be faster than the flow rate of the fluid medium through other channels. The third connecting channel C3 may extend in the radial direction of the wafer carrier 43.

[0129] In some embodiments, in order to deliver the coolant for cooling the wafer stage 43, the coolant in the fluid inlet port 61 may have a lower temperature than the coolant in the fluid outlet port 62. Due to the different intersection angles of the connection channels, the fluid medium in the second connection channel C2 can be cooled by the lower temperature generated by the fluid inlet port 61, and the fluid medium in the third connection channel C3 cannot be heated by the higher temperature generated by the fluid outlet port 62.

[0130] In some embodiments, Figure 2As shown, as seen from the top view, the fan-shaped section 434 is defined on the wafer carrier 43. The fan-shaped section 434 is a circular section closed by the first boundary line B1, the second boundary line B2 and the arc located at the periphery 430 of the wafer carrier 43. The central angle α1 of the fan-shaped section 434 is about 270 degrees to about 300 degrees. The first gas inlet port 51 and the second gas inlet port 55 are located below the fan-shaped section 434 of the wafer carrier 43, and the reference line L passing between the first gas inlet ports 51 and 55 forms angles α2 and α3 with the first boundary line B1 and the second boundary line B2. Angle α2 is equal to angle α3. In an exemplary embodiment, angles α2 and α3 are in the range of about 120 degrees to about 150 degrees.

[0131] In some embodiments, all channels of the fluid guiding structure 63 located below the fan-shaped section 434 of the wafer stage 43 are formed in an arc shape and are part of a circle. For example, segments of each of the first arc-shaped channel A1, the second arc-shaped channel A2, the third arc-shaped channel A3, and the fourth arc-shaped channel A4 located below the fan-shaped section 434 are parts of circles with different radii.

[0132] In some embodiments, all channels of the fluid guiding structure 63 located below the fan-shaped section 434 of the wafer stage 43 are concentrically arranged relative to the center C of the wafer stage 43. For example, segments of each of the first arc-shaped channel A1, the second arc-shaped channel A2, the third arc-shaped channel A3, and the fourth arc-shaped channel A4 located below the fan-shaped section 434 are concentrically arranged relative to the center C of the wafer stage 43.

[0133] In some embodiments, all channels of the fluid guiding structure 63 located below the fan-shaped section 434 of the wafer stage 43 are symmetrically arranged with respect to a reference line L passing between the gas inlet ports 51 and 55. For example, segments of each of the first arc-shaped channel A1, the second arc-shaped channel A2, the third arc-shaped channel A3, and the fourth arc-shaped channel A4 located below the fan-shaped section 434 are symmetrically arranged with respect to the reference line L passing between the gas inlet ports 51 and 55. In other words, segments of each of the first arc-shaped channel A1, the second arc-shaped channel A2, the third arc-shaped channel A3, and the fourth arc-shaped channel A4 located on both sides of the reference line L have the same arc length from the reference line L to either the first boundary line B1 or the second boundary line B2.

[0134] In some embodiments, all channels that do not extend in the circumferential direction of the wafer stage 43 are located outside the fan-shaped section 434. For example, the first connecting channel C1, the second connecting channel C2, the third connecting channel C3, the first end channel E1, and the second end channel E2 are not located below the fan-shaped section 434. In addition, the fluid inlet port 61 and the fluid outlet port 62 are located outside the fan-shaped section 434.

[0135] In some embodiments, the first arc-shaped channel A1, the second arc-shaped channel A2, the third arc-shaped channel A3, and the fourth arc-shaped channel A4 are spaced apart from each other at different intervals. Figure 3 As shown, the first arc-shaped channel A1 is spaced apart from the second arc-shaped channel A2 by a first spacing P1, the second arc-shaped channel A2 is spaced apart from the third arc-shaped channel A3 by a second spacing P2, and the third arc-shaped channel A3 is spaced apart from the fourth arc-shaped channel A4 by a third spacing P3. The first spacing P1 is greater than the second spacing P2, and the second spacing P2 is greater than the third spacing P3. In an exemplary embodiment, the first spacing P1 is in a range of about 38 mm to about 45 mm, for example, the first spacing P1 is 42.14 mm. In an exemplary embodiment, the second spacing P2 is in a range of about 28 mm to about 35 mm, for example, the second spacing P2 is 28.84 mm. In an exemplary embodiment, the third spacing P3 is in a range of about 20 mm to about 25 mm, for example, the third spacing P3 is 23.86 mm.

[0136] In some embodiments, the outermost channel of the fluid guiding structure 63 is separated from the periphery 430 of the wafer support platform 43 by a distance greater than 0. Figure 3 As shown, the first arc-shaped channel A1 is away from the periphery 430 of the wafer carrier 43 by a distance P0. The distance P0 is in the range of about 10 mm to about 15 mm, for example, 12 mm. By configuring the first arc-shaped channel A1 spaced apart from the periphery 430 of the wafer carrier 43, the temperature uniformity in the peripheral area of ​​the wafer carrier 43 is improved. In some embodiments, as Figure 3 As shown, the first arc-shaped channel A1 is located below the vertical protrusion of the inner annular groove 435. Figure 3 As can be seen from the top view, the outer annular groove 437 is closer to the periphery 430 of the wafer supporting platform 43 than the first arc-shaped channel A1.

[0137] In some embodiments, each of the first connection channel C1, the second connection channel C2, and the third connection channel C3 has a length substantially the same as the spacing between the arc-shaped channels connected at the two ends of the arc-shaped channels. For example, the first connection channel C1 has a length equal to the first spacing P1, the second connection channel C2 has a length equal to the second spacing P2, and the third connection channel C3 has a length equal to the third spacing P3. In other words, the length of the first connection channel C1 is greater than the length of the second connection channel C2, and the length of the second connection channel C2 is greater than the length of the third connection channel C3.

[0138] In some embodiments, since the semiconductor wafer 5 in the central area has a higher temperature than the peripheral area of ​​the semiconductor wafer 5, due to the configuration in which the spacing gradually increases in the direction away from the center C of the wafer carrier 43, a higher heat exchange rate is exhibited in the area close to the center C of the wafer carrier 43 compared to the exchange rate in the area adjacent to the periphery 430 of the wafer carrier 43.

[0139] In some embodiments, the fluid inlet port 61 has a width W1 (see Figure 3 In one embodiment, the width W1 is in the range of about 25 mm to about 30 mm, for example, the width W1 is about 28 mm. The fluid outlet port 62 may have the same width as the fluid inlet port 61. In some embodiments, the fluid guiding structure 63 is used for each channel of uniform size and has a width (or diameter) greater than the depth. For example, Figure 3 As shown, the second end channel E2 has a depth D in the range of about 8 mm to about 12 mm, for example, the depth D is about 8 mm; and the second end channel E2 has a width (or diameter) W2 in the range of about 8 mm to about 12 mm, for example, the width W2 is about 12 mm.

[0140] According to the experimental results, Figure 5 As shown, when the channel has a depth D of about 8 mm and a width W2 of about 12 mm, the minimum film thickness uniformity is exhibited. The film thickness uniformity satisfies the following equation:

[0141] (T Max -T Min ) / 2*T avg *100%

[0142] Where T Max is the maximum thickness measured on the wafer surface, T Min is the minimum thickness measured on the wafer surface, and T avg It is the average thickness measured across the wafer surface. Lower film thickness uniformity indicates better performance of semiconductor devices.

[0143] Figure 6 A cross-sectional view of a wafer holding module 40a is shown according to some embodiments. The wafer holding module 40a is similar to Figure 2 The wafer holding module 40 shown in FIG. 4 is similar to the wafer holding module 40 , and similar components have similar reference numerals. The difference between the wafer holding module 40 a and the wafer holding module 40 includes that the wafer holding module 40 a replaces the two gas inlet ports 51 and 55 with two gas inlet ports 51 a and 55 a.

[0144] In some embodiments, the gas inlet port 51a and the gas inlet port 55a are located adjacent to the perimeter 430a of the wafer stage 43a. A reference line L passes between the two gas inlet ports 51a and 55a and through the center C of the wafer stage 43. The reference line L may be perpendicular to a line connecting the two inlet ports 51a and 55a. In some embodiments, the two gas inlet ports 51a and 55a are fluidly connected to grooves formed on the top surface of the wafer stage 43, such as Figure 3 43. The inner annular groove 435 and the outer annular groove 437 are shown in FIG. The gas inlet ports 51a and 55a are located below the fan-shaped section 434a of the wafer carrier 43a, and the reference line L passing between the gas inlet ports 51a and 55a forms angles α5 and α6 with the first boundary line B1 and the second boundary line B2. The angle α5 is different from the angle α6. In an exemplary embodiment, these angles α5 are in the range of about 120 degrees to about 150 degrees, and the angle α6 is in the range of about 30 degrees to about 60 degrees.

[0145] exist Figure 6 In the illustrated embodiment, segments of each of the first arcuate channel A1, the second arcuate channel A2, the third arcuate channel A3, and the fourth arcuate channel A4 located below the sector segment 434a are asymmetrically arranged relative to a reference line L passing between the gas inlet ports 51a and 55a. In other words, segments of each of the first arcuate channel A1, the second arcuate channel A2, the third arcuate channel A3, and the fourth arcuate channel A4 located on both sides of the reference line L have different arc lengths from the reference line L to the first boundary line B1 or from the reference line L to the second boundary line B2.

[0146] Figure 7 A cross-sectional view of a wafer holding module 40b is shown according to some embodiments. The wafer holding module 40b is similar to Figure 2 , and similar components have similar reference numerals. The differences between wafer holding module 40b and wafer holding module 40 include that wafer holding module 40b replaces fluid guiding structure 63 with fluid guiding structure 63b and replaces fluid inlet port 61 and fluid outlet port 62 with fluid inlet port 61b and fluid outlet port 62b.

[0147] The fluid inlet port 61b is positioned adjacent to the periphery 430b of the wafer stage 43b, and the fluid outlet port 62b is located at the center C of the wafer stage 43b. In some embodiments, the fluid guiding structure 63b is formed in a spiral shape and includes a plurality of arcuate channels, such as a first arcuate channel A1b, a second arcuate channel A2b, a third arcuate channel A3b, a fourth arcuate channel A4b, and a fifth arcuate channel A5b. The upstream end of the first arcuate channel A1b is connected to the fluid inlet port 61b, and the downstream end of the fifth arcuate channel A5b is connected to the fluid outlet port 62b. The second arcuate channel A2b, the third arcuate channel A3b, and the fourth arcuate channel A4b extend continuously from the first arcuate channel A1b to the fifth arcuate channel A5b.

[0148] In some embodiments, each of the first arc-shaped channel A1b, the second arc-shaped channel A2b, the third arc-shaped channel A3b, the fourth arc-shaped channel A4b, and the fifth arc-shaped channel A5b has a central angle of about 360 degrees. In addition, a segment of each of the first arc-shaped channel A1b, the second arc-shaped channel A2b, the third arc-shaped channel A3b, the fourth arc-shaped channel A4b, and the fifth arc-shaped channel A5b located below the fan-shaped section 434b of the wafer carrier 43 is formed in an arc shape. In addition, a segment of each of the first arc-shaped channel A1b, the second arc-shaped channel A2b, the third arc-shaped channel A3b, the fourth arc-shaped channel A4b, and the fifth arc-shaped channel A5b located below the fan-shaped section 434b of the wafer carrier 43 is asymmetrically arranged with respect to a reference line L passing between the gas inlet ports 51b and 55b. The gas inlet ports 51b and 55b may have a configuration similar to that of the first gas inlet ports 51 and 55.

[0149] Figure 8 A top view of some elements of a wafer manufacturing system is shown according to some embodiments. In some embodiments, the second gas line 26 includes an end section arranged concentrically with the gas ring 27 relative to the center C of the wafer stage 43, and the second gas line 26 is connected to the gas ring 27 via a tube 28. The end section of the second gas line 26 has a width D1, and the gas ring 27 has a width D2. In some embodiments, the width D1 is different from the width D2. For example, the width D1 is about 10 mm and the width D2 is about 12 mm, which significantly improves the velocity uniformity of the process gas supplied from the gas nozzle 29.

[0150] In some embodiments, Figure 8As shown, the extension line EL of the tube 28 passes through the center C of the wafer stage 43. The angle α7 between the extension line EL and the reference line L between the first gas inlet ports 51 and 55 is about 30 degrees to about 50 degrees. In some embodiments, the gas nozzle 29 located closer to the tube 28 supplies the process gas at a higher speed than the other gas nozzles 29 far from the tube 28. The difference in the speed of the process gas may cause non-uniform thickness uniformity. However, since the upstream section A1U of the first arc-shaped channel A1 that transfers the cooling medium that has just entered the fluid guiding structure 63 is located adjacent to the tube 28, the area of ​​the semiconductor wafer 5 located above the upstream section A1U of the first arc-shaped channel A1 may have a temperature slightly lower than the temperature in other areas. As a result, the film growth rate is optimally adjusted and the film thickness uniformity is improved.

[0151] refer to Figure 1 In some embodiments, the RF module 70 is used to generate an RF field to excite plasma in the chamber 10. In some embodiments, the RF module 70 includes a source RF 71, a top electrode 72, and a plurality of induction coils 73. The source RF 71 can be connected to a control module 90. The control module 90 can be operated to modulate the power output of the source RF 71 and deliver the correct amount of power to the top electrode 72 and the induction coils 73 for generating plasma. The wafer carrier 43 is also RF biased by the RF power supply 49. The RF power supply 49 can be connected to the control module 90. The control module 90 can be operated to modulate the power output of the RF power supply 49 and deliver the appropriate amount of power to the wafer carrier 43.

[0152] The gas exhaust module 80 is used to remove gaseous materials or plasma in the chamber 10. In some embodiments, the gas exhaust module 80 includes an exhaust pipe 81 and a pump 82. The exhaust pipe 81 is connected to the lower portion of the chamber 10. The exhaust pipe 81 can be made of quartz, SiC, Si or any other suitable material commonly used in the art. The pump 82 is connected to the exhaust pipe 81 and is used to generate an exhaust flow from the chamber 10. The flow rate of the exhaust flow in the exhaust pipe 81 can be adjusted by controlling the output power of the pump 82 according to the control signal sent from the control module 90. The pump 82 may include, but is not limited to, a turbomolecular pump.

[0153] The control module 90 controls and directs the manufacturing tools, such as the chamber 10, the process gas delivery module 20, the cleaning gas delivery module 30, the RF module 70, and the gas exhaust module 80, to start and stop the various processes involved in the film deposition process. The control module 90 also controls the supply of gaseous materials from the gas source 50 and the supply of fluid medium from the tank 60 containing the fluid.

[0154] In some embodiments, the control module 90 includes a processor 91 and a memory 92. The processor 91 is configured to execute and / or interpret one or more sets of instructions stored in the memory 92. In some embodiments, the processor 91 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC) and / or a suitable processing unit. The memory 92 includes a random access memory or other dynamic storage device for storing data and / or instructions for execution by the processor 91. In some embodiments, the memory 92 is used to store temporary variables or other intermediate information during the execution of instructions to be executed by the processor 91. In some embodiments, the memory 92 also includes a read-only memory or other static storage device for storing static information and instructions for the processor 91. In some embodiments, the memory 92 is an electronic, magnetic, optical, electromagnetic, infrared and / or semiconductor system (or device or apparatus). For example, memory 92 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In some embodiments using optical disks, memory 92 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0155] Fig. 9 is a flow chart illustrating a method S100 for processing a semiconductor wafer 5 according to some embodiments. Figures 1 to 8 and Fig.10 The attached Figure 1 Additional operations may be provided before, during, and after method S100, and some of the described operations may be replaced or eliminated for other embodiments of the method.

[0156] The method S100 starts with operation S110, in which a semiconductor wafer 5 is loaded on the top surface 43 of the wafer carrier 43. In some embodiments, the semiconductor wafer 5 is moved into the chamber 10 by a robot (not shown in the figure). The robot places the semiconductor wafer 5 on the support pins 45 and moves out of the chamber 200. After the semiconductor wafer 5 is placed on the support pins 45, these support pins 45 lower the semiconductor wafer 5, and then the semiconductor wafer 5 is fixed by the wafer carrier 43, as shown in FIG. Fig.10 shown.

[0157] The method S100 also includes an operation S120 in which a gaseous material is supplied between the semiconductor wafer 5 and the top surface 431 of the wafer stage 43. In some embodiments, the gaseous material is supplied to the wafer stage 43 via one or more gas pipelines connected to the first gas inlet port 51 and the second gas inlet port 55. The gaseous material 59 from the first gas inlet port 51 can be transported to the inner annular groove 435 via gas channels such as Figure 3 The first lower channel 52, the first upper channel 53, the first annular channel 54 and the hole 436 are shown. In addition, the gaseous material 59 from the second gas inlet port 55 can be supplied to the outer annular groove 437 through gas channels such as Figure 4 The second lower passage 56, the second upper passage 57, the second annular passage 58 and the hole 438 are shown.

[0158] like Fig.10 As shown, the gaseous material 59 filled in the inner annular groove 435 and the outer annular groove 437 will continue to flow into the gap formed between the semiconductor wafer 5 and the top surface 431 of the wafer stage 43. Most of the gaseous material 59 from the inner annular groove 435 is captured between the semiconductor wafer 5 and the top surface 431 of the wafer stage 43 by the gaseous material 59 from the outer annular groove 437. Therefore, a gas film is formed between the semiconductor wafer 5 and the top surface 431 of the wafer stage 43 and acts as a heat transfer medium between the semiconductor wafer 5 and the wafer stage 43. In some embodiments, the gaseous material 59 includes a gas with relatively high thermal conductivity, such as helium.

[0159] The method S100 also includes an operation S130 in which a fluid medium is supplied to the fluid guide structure 63 of the wafer carrier 43. In some embodiments, a fluid medium 69 such as ethylene glycol is supplied to the fluid guide structure 63 for cooling the wafer carrier 43. In some embodiments, the fluid medium 69 is supplied to the fluid guide structure 63 at a flow rate in the range of about 0.5 m / s to about 2.0 m / s. According to experimental results, as shown in FIG. Figure 5As shown, under the condition that the fluid medium 69 is controlled to have a flow rate of about 2.0 m / s, the minimum film thickness uniformity is exhibited.

[0160] In some embodiments, the fluid medium 69 is supplied to the fluid guide structure 63 via a pipeline connected to the fluid inlet port 61. After the fluid medium 69 enters the fluid guide structure 63, the fluid medium 69 may sequentially flow through the first end channel E1, the first arc-shaped channel A1, the first connecting channel C1, the second arc-shaped channel A2, the second connecting channel C2, the third arc-shaped channel A3, the third connecting channel C3, the fourth arc-shaped channel A4, and the second end channel E2. The fluid medium 69 is then removed from the fluid guide structure 63 via another pipeline connected to the fluid outlet port 62.

[0161] In some embodiments, the fluid medium 69 is guided by two arc-shaped channels located on both sides of the first gas inlet port 51 and the second gas inlet port 55, and the fluid medium 69 flows through the two arc-shaped channels in opposite circumferential directions around the center C of the wafer carrier 43. For example, Fig.10 As shown, the fluid medium 69 in the first arc-shaped channel A1 flows in a counterclockwise direction (designated as “X”) relative to the center C of the wafer stage 43, and the fluid medium 69 in the second arc-shaped channel A2 flows in a clockwise direction (designated as “˙”) relative to the center C of the wafer stage 43. The fluid medium 69 flows through the first arc-shaped channel A1 and the second arc-shaped channel A2 in opposite circumferential directions around the center C of the wafer stage 43. Due to this configuration, heat in the fan-shaped section 434 of the wafer stage 43 can be efficiently removed. In addition, the fluid medium 69 in the third arc-shaped channel A3 flows in a clockwise direction (designated as “X”) relative to the center C of the wafer stage 43, and the fluid medium 69 in the fourth arc-shaped channel A4 flows in a counterclockwise direction (designated as “˙”) relative to the center C of the wafer stage 43. The fluid medium 69 flows through the third arc-shaped channel A3 and the fourth arc-shaped channel A4 in opposite circumferential directions around the center C of the wafer stage 43.

[0162] In some embodiments, the fluid medium 69 is guided through arcuate channels, which are symmetrical about a reference line L passing between the first gas inlet port 51 and the second gas inlet port 55. For example, the fluid medium 69 is guided through a first arcuate channel A1, a second arcuate channel A2, a third arcuate channel A3, and a fourth arcuate channel A4, which are symmetrical about a reference line L passing between the first gas inlet port 51 and the second gas inlet port 55, as shown in FIG. Figure 2As shown. However, it will be appreciated that many variations and modifications may be made to the embodiments of the present disclosure. In some embodiments, the fluid medium 69 is directed through arcuate channels that are asymmetric about a reference line L passing between the first gas inlet port 51 and the second gas inlet port 55. For example, the fluid medium 69 is directed through a first arcuate channel A1, a second arcuate channel A2, a third arcuate channel A3, and a fourth arcuate channel A4 that are asymmetric about a reference line L passing between the first gas inlet port 51a and the second gas inlet port 55a, as shown in FIG. Figure 5 By configuring two arc-shaped channels passing through two opposite sides of the gas inlet port, heat from a portion of the wafer stage 43 positioned around the gas inlet port can be uniformly dissipated by the two adjacent arc-shaped channels.

[0163] In some embodiments, the fluid medium 69 is guided through arc-shaped channels, and these arc-shaped channels are arranged concentrically with respect to the center C of the wafer carrier 43. For example, the fluid medium 69 is guided through the first arc-shaped channel A1, the second arc-shaped channel A2, the third arc-shaped channel A3 and the fourth arc-shaped channel A4, and these arc-shaped channels are arranged concentrically with respect to the center C of the wafer carrier 43, such as Figure 2 As shown. Since the arc-shaped channels are concentrically arranged, the heat from a portion of the wafer stage 43 located between two arc-shaped channels can be uniformly dissipated through the two adjacent arc-shaped channels. As a result, a uniform temperature distribution is exhibited on the semiconductor wafer 5.

[0164] In some embodiments, the fluid medium 69 is guided through arc-shaped channels, and the arc-shaped channels are arranged concentrically with respect to the center C of the wafer carrier 43. For example, the fluid medium 69 is guided through the first arc-shaped channel A1, the second arc-shaped channel A2, the third arc-shaped channel A3 and the fourth arc-shaped channel A4. Figure 2 As shown. The arc angle of the first arc channel A1 is in the range of about 330 degrees to about 355 degrees, the arc angle of the second arc channel A2 is in the range of about 300 degrees to about 330 degrees, the arc angle of the third arc channel A3 is in the range of about 200 degrees to about 230 degrees, and the arc angle of the fourth arc channel A4 is in the range of about 250 degrees to about 300 degrees. Since the arc channels extend through most of the area of ​​the wafer carrier 43, the temperature in the wafer carrier 43 can be accurately adjusted.

[0165] In some embodiments, the fluid medium 69 is guided through an arcuate channel located below the vertical protrusion of the inner annular groove 435. For example, Fig.10 As shown, the fluid medium 69 is guided through the first arc-shaped channel A1, and the first arc-shaped channel A1 is located below the vertical protrusion of the inner annular groove 435.

[0166] In some embodiments, the fluid medium 69 from the fluid inlet port 61 first flows through an arc-shaped channel farthest from the center C of the wafer stage 43, and flows to another arc-shaped channel located closer to the center C of the wafer stage 43. For example, the fluid medium 69 from the fluid inlet port 61 flows through the first arc-shaped channel A1 before flowing through the second arc-shaped channel A2.

[0167] The method S100 also includes an operation S140 in which a plasma gas is supplied above the semiconductor wafer 5. In some embodiments, RF power is applied to the dome structure 13 and the wafer stage 43 through the RF module 70 and the RF power supply 49, and plasma is excited between the dome structure 13 and the wafer stage 43. In some embodiments, as Fig.10 As shown, the plasma gas 15 is directed toward the semiconductor wafer 5 to form a thin film on the semiconductor wafer 5 in an HDP-CVD process or to trench a material formed on the semiconductor wafer 5 in an etching process.

[0168] The method S100 also includes an operation S150 in which the semiconductor wafer 5 is unloaded from the wafer stage 43. In some embodiments, after the process in the chamber 10 is completed, the semiconductor wafer 5 is raised by the support pins 45 and removed from the chamber 10 by a robot (not shown).

[0169] It will be appreciated that the semiconductor wafer manufactured according to the presently disclosed method undergoes more processes. For example, after the semiconductor wafer 5 formed with the thin film is removed from the wafer manufacturing system 1, the semiconductor wafer 5 is sent to a chemical-mechanical polishing (CMP) system for a planarization process. It will be appreciated that since the thin film formed on the semiconductor wafer 5 has a higher uniformity than the thin film handled by the known wafer carrier, the process parameters used in the planarization process can be set according to a conventional recipe without spending extra time for re-creation. As a result, the tool availability of the CMP system is improved, and the use of slurry in the CMP system is reduced.

[0170] The semiconductor wafer 5 may undergo additional processes including material deposition, implantation or etching operations to form various features such as field effect transistors, capping insulating layers, contacts / vias, silicide layers, interconnect metal layers, dielectric layers, passivation layers, metallization layers with signal lines, or the like. In some embodiments, one or more layers of conductive, semiconductive and insulating materials are formed over the substrate, and a pattern is formed in one or more of these layers.

[0171] An embodiment of a wafer manufacturing system uses a wafer carrier to cool a semiconductor wafer. A fluid guiding structure for guiding a heat exchange medium in the wafer carrier includes a plurality of arc-shaped channels that are configured adjacent to a gas inlet port for receiving helium gas. Since heat accumulated at an area of ​​the wafer carrier around the gas inlet port can be efficiently removed, more uniform processing may occur on the semiconductor wafer being processed. According to an experimental result in an HDP-CVD process, film thickness uniformity is reduced by about 0.8% from 1.57% to 0.78% compared to a semiconductor wafer cooled by a known wafer carrier.

[0172] According to some embodiments, a method for processing a semiconductor wafer is provided. The method includes loading a semiconductor wafer on a top surface of a wafer carrier. The method also includes supplying a gaseous material between the semiconductor wafer and the top surface of the wafer carrier via a first gas inlet port and a second gas inlet port, the first gas inlet port and the second gas inlet port being located below a fan-shaped section of the top surface. The method further includes supplying a fluid medium to a fluid inlet port of the wafer carrier and guiding the fluid medium from the fluid inlet port to flow through a plurality of arc-shaped channels located below the fan-shaped section of the top surface. In addition, the method includes supplying a plasma gas above the semiconductor wafer. According to some embodiments, the fluid medium is guided through these arc-shaped channels, which are symmetrical about a reference line passing between the first gas inlet port and the second gas inlet port. According to some embodiments, the fluid medium is guided through these arc-shaped channels, which are asymmetrical about a reference line passing between the first gas inlet port and the second gas inlet port, as seen from a top view, the angle between the reference line and the boundary of the fan-shaped section is greater than 30 degrees. According to some embodiments, the fluid medium is guided through the arc-shaped channels, which are arranged concentrically relative to the center of the wafer carrier. According to some embodiments, the fluid medium is guided through the arc-shaped channels, which have an arc angle greater than 180 degrees relative to the center of the wafer carrier. According to some embodiments, the first arc-shaped channel of the arc-shaped channels, the second arc-shaped channel of the arc-shaped channels, and the third arc-shaped channel of the arc-shaped channels are arranged in sequence along the direction toward the center of the wafer carrier, and the method for processing a semiconductor wafer further includes the following steps. The fluid medium is guided from the first arc-shaped channel of the arc-shaped channels to the second arc-shaped channel of the arc-shaped channels via the first connecting channel, and the fluid medium is guided from the second arc-shaped channel of the arc-shaped channels to the third arc-shaped channel of the arc-shaped channels via the second connecting channel, and the second connecting channel has a length less than a length of the first connecting channel. According to some embodiments, the gaseous material supplied through the first gas inlet port is guided to the inner annular groove formed on the top surface of the wafer carrier. The gaseous material supplied through the second gas inlet port is guided to an outer annular groove formed on the top surface of the wafer carrier, the outer annular groove surrounding the inner annular groove. According to some embodiments, the fluid medium is guided through one of the arc-shaped channels located below the vertical protrusion of the inner annular groove. According to some embodiments, the method of processing a semiconductor wafer further includes the step of discharging the fluid medium through a fluid outlet port, the fluid inlet port and the fluid outlet port being located outside the fan-shaped section of the wafer carrier.

[0173] According to some embodiments, a method for processing a semiconductor wafer is provided. The method includes loading a semiconductor wafer on a top surface of a wafer carrier. The method also includes supplying a gaseous material between the semiconductor wafer and the top surface of the wafer carrier via a gas inlet port of the wafer carrier. The method further includes supplying a fluid medium to the fluid inlet port of the wafer carrier and guiding the fluid medium from the fluid inlet port to flow through a first arc-shaped channel and a second arc-shaped channel, the first arc-shaped channel and the second arc-shaped channel being located at opposite sides of the gas inlet port. The second arc-shaped channel is positioned closer to the center of the wafer carrier than the first arc-shaped channel, and the fluid medium from the fluid inlet port flows through the first arc-shaped channel before flowing through the second arc-shaped channel. In addition, the method includes supplying a plasma gas above the semiconductor wafer. According to some embodiments, the fluid medium is guided through the first arc-shaped channel and the second arc-shaped channel, and the first arc-shaped channel and the second arc-shaped channel are concentrically arranged relative to the center of the wafer carrier. According to some embodiments, the fluid medium is guided through a first arcuate channel and a second arcuate channel, and the first arcuate channel and the second arcuate channel have an arc angle greater than 180 degrees relative to the center of the wafer carrier. According to some embodiments, the method for processing a semiconductor wafer further includes the following steps. The fluid medium from the second arcuate channel is guided through a third arcuate channel, wherein the first arcuate channel, the second arcuate channel and the third arcuate channel are sequentially arranged along a direction toward the center of the wafer carrier. The fluid medium is guided from the first arcuate channel to the second arcuate channel via a first connecting channel. The fluid medium is guided from the second arcuate channel to the third arcuate channel via a second connecting channel, and the second connecting channel has a length less than a length of the first connecting channel. According to some embodiments, the fluid medium is guided through the first arcuate channel and the second arcuate channel, and the fluid medium flows in opposite circumferential directions around the center of the wafer carrier. According to some embodiments, gaseous material supplied through a gas inlet port is directed to an inner annular groove formed on a top surface of a wafer carrier, and fluid medium is directed through a first arcuate channel located below a vertical protrusion of the inner annular groove.

[0174] According to some embodiments, a wafer manufacturing system for processing semiconductor wafers is provided. The wafer manufacturing system includes a wafer carrier having a top surface. Many holes are formed on the top surface. The wafer manufacturing system also includes a gas inlet port, which is formed in the wafer carrier and is located below the fan-shaped section of the top surface. The gas inlet port is fluidly connected to these holes. The wafer manufacturing system further includes a fluid inlet port, a first arc-shaped channel and a second arc-shaped channel formed in the wafer carrier. The first arc-shaped channel and the second arc-shaped channel are fluidly connected to the fluid inlet port. The first arc-shaped channel and the second arc-shaped channel are located below the fan-shaped section of the top surface and at opposite sides of the gas inlet port. In addition, the wafer manufacturing system includes a gas source and a source containing fluid. The gas source is fluidly connected to the gas inlet port, and the source containing fluid is fluidly connected to the fluid inlet port. According to some embodiments, the arc-shaped channel is concentrically configured relative to a center of the wafer carrier. According to some embodiments, the arc-shaped channels have an arc angle greater than 180 degrees relative to a center of the wafer carrier. According to some embodiments, the wafer manufacturing system further includes a third arc-shaped channel, a first connecting channel, and a second connecting channel. The first arc-shaped channel, the second arc-shaped channel, and the third arc-shaped channel are sequentially arranged along a direction toward the center of the wafer carrier. The first connecting channel connects the first arc-shaped channel to the second arc-shaped channel. The second connecting channel connects the second arc-shaped channel to the third arc-shaped channel, and the second connecting channel has a length less than a length of the first connecting channel.

[0175] The foregoing content summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that such equivalent constructions may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for processing a semiconductor wafer, characterized in that: Include: Loading a semiconductor wafer on a top surface of a wafer carrier; supplying a gaseous material between the semiconductor wafer and the top surface of the wafer carrier through a first gas inlet port and a second gas inlet port, the first gas inlet port and the second gas inlet port being located below a fan-shaped section of the top surface; Supplying a fluid medium to a fluid inlet port of the wafer carrier and guiding the fluid medium from the fluid inlet port to flow through a plurality of arc-shaped channels located below the fan-shaped section of the top surface, guiding the fluid medium through the plurality of arc-shaped channels, the plurality of arc-shaped channels being concentrically arranged relative to a center of the wafer carrier; and A plasma gas is supplied above the semiconductor wafer.

2. The method according to claim 1, characterized in that The fluid medium is guided through the plurality of arcuate channels, and the plurality of arcuate channels are symmetrical about a reference line passing between the first gas inlet port and the second gas inlet port.

3. The method according to claim 1, characterized in that: wherein the fluid medium is guided by the plurality of arc-shaped channels, the plurality of arc-shaped channels being asymmetric with respect to a reference line passing between the first gas inlet port and the second gas inlet port; Wherein, an angle between the reference line and a boundary of the fan-shaped section is greater than 30 degrees.

4. The method according to claim 1, characterized in that: The plurality of arc-shaped channels include a first arc-shaped channel and a second arc-shaped channel. A distance between the first arc-shaped channel and the center of the wafer carrier is greater than a distance between the second arc-shaped channel and the center of the wafer carrier.

5. The method according to claim 1, characterized in that The fluid medium is guided through the plurality of arc-shaped channels, and the plurality of arc-shaped channels have an arc angle greater than 180 degrees relative to the center of the wafer supporting platform.

6. The method according to claim 1, characterized in that A first arc-shaped channel among the plurality of arc-shaped channels, a second arc-shaped channel among the plurality of arc-shaped channels, and a third arc-shaped channel among the plurality of arc-shaped channels are sequentially arranged along a direction toward the center of the wafer carrier, and the method further comprises: guiding the fluid medium from the first arc-shaped channel among the plurality of arc-shaped channels to the second arc-shaped channel among the plurality of arc-shaped channels via a first connecting channel; and The fluid medium is guided from the second arc-shaped channel among the plurality of arc-shaped channels to the third arc-shaped channel among the plurality of arc-shaped channels via a second connecting channel, wherein the second connecting channel has a length smaller than a length of the first connecting channel.

7. The method according to claim 1, characterized in that The fluid medium is guided through a first arc-shaped channel among the plurality of arc-shaped channels and a second arc-shaped channel among the plurality of arc-shaped channels, the first arc-shaped channel and the second arc-shaped channel being located on both sides of the first and second gas inlet ports, wherein the fluid medium flows through the first arc-shaped channel among the plurality of arc-shaped channels and the second arc-shaped channel among the plurality of arc-shaped channels in opposite circumferential directions around the center of the wafer carrier.

8. The method according to claim 1, characterized in that directing the gaseous material supplied through the first gas inlet port to an inner annular groove formed on the top surface of the wafer stage; The gaseous material supplied through the second gas inlet port is guided to an outer annular groove formed on the top surface of the wafer carrier, and the outer annular groove surrounds the inner annular groove.

9. The method according to claim 8, characterized in that The fluid medium is guided through an arc-shaped channel among the plurality of arc-shaped channels located below a vertical protrusion of the inner annular groove.

10. The method according to claim 1, characterized in that The method further comprises the step of discharging the fluid medium through a fluid outlet port, wherein the fluid inlet port and the fluid outlet port are located outside the fan-shaped section of the wafer carrier.

11. A method for processing a semiconductor wafer, characterized in that: Include: Loading a semiconductor wafer on a top surface of a wafer carrier; supplying a gaseous material between the semiconductor wafer and the top surface of the wafer carrier through a gas inlet port of the wafer carrier; supplying a fluid medium to a fluid inlet port of the wafer carrier and directing the fluid medium from the fluid inlet port to flow through a first arcuate channel and a second arcuate channel located at opposite sides of the gas inlet port, the second arcuate channel being located closer to a center of the wafer carrier than the first arcuate channel, wherein the fluid medium from the fluid inlet port flows through the first arcuate channel before flowing through the second arcuate channel; and A plasma gas is supplied above the semiconductor wafer.

12. The method according to claim 11, characterized in that The fluid medium is guided through the first arc-shaped channel and the second arc-shaped channel, and the first arc-shaped channel and the second arc-shaped channel are concentrically arranged relative to the center of the wafer supporting platform.

13. The method according to claim 11, characterized in that The fluid medium is guided through the first arc-shaped channel and the second arc-shaped channel, and the first arc-shaped channel and the second arc-shaped channel have an arc angle greater than 180 degrees relative to the center of the wafer supporting platform.

14. The method according to claim 11, characterized in that Further including: guiding the fluid medium from the second arc-shaped channel to pass through a third arc-shaped channel, wherein the first arc-shaped channel, the second arc-shaped channel and the third arc-shaped channel are sequentially arranged along a direction toward the center of the wafer carrier; guiding the fluid medium from the first arc-shaped channel to the second arc-shaped channel via a first connecting channel; and The fluid medium is guided from the second arc-shaped channel to the third arc-shaped channel via a second connecting channel, wherein the second connecting channel has a length smaller than a length of the first connecting channel.

15. The method according to claim 11, characterized in that The fluid medium is guided through the first arc-shaped channel and the second arc-shaped channel, and the fluid medium flows in opposite circumferential directions around the center of the wafer supporting platform.

16. The method according to claim 11, characterized in that The gaseous material supplied through the gas inlet port is guided to an inner annular groove formed on the top surface of the wafer carrier, and the fluid medium is guided through the first arcuate channel, which is located below a vertical protrusion of the inner annular groove.

17. A wafer manufacturing system, characterized in that: Include: A wafer carrier having a top surface, wherein a plurality of holes are formed on the top surface; a gas inlet port formed in the wafer carrier and located below a fan-shaped section of the top surface, wherein the gas inlet port is in fluid communication with the plurality of holes; a fluid inlet port formed in the wafer carrier; a first arcuate channel and a second arcuate channel fluidly connected to the fluid inlet port, wherein the first arcuate channel and the second arcuate channel are located below the fan-shaped section of the top surface and at opposite sides of the gas inlet port; a gas source fluidly connected to the gas inlet port; and A source containing a fluid is fluidly connected to the fluid inlet port.

18. The wafer manufacturing system according to claim 17, characterized in that: The arc-shaped channel is concentrically arranged relative to a center of the wafer supporting platform.

19. The wafer manufacturing system according to claim 17, characterized in that: The arc-shaped channels have an arc angle greater than 180 degrees relative to a center of the wafer supporting platform.

20. The wafer manufacturing system according to claim 17, characterized in that: Further including: a third arc-shaped channel, wherein the first arc-shaped channel, the second arc-shaped channel and the third arc-shaped channel are sequentially arranged along a direction toward a center of the wafer supporting platform; a first connecting channel, connecting the first arc-shaped channel to the second arc-shaped channel; and A second connecting channel connects the second arc-shaped channel to the third arc-shaped channel, wherein the second connecting channel has a length that is smaller than a length of the first connecting channel.

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