A capacitive coupled output buffer circuit of a voltage controlled oscillator and a control method thereof

Abstract

The present invention provides a capacitor-coupled output buffer circuit of a voltage-controlled oscillator and a control method thereof. A voltage-controlled oscillator, a first capacitor, a first inverter and a second inverter are sequentially arranged between an input end and an output end; the first inverter comprises: a first P-channel MOS transistor and a first N-channel MOS transistor, the first P-channel MOS transistor and the first N-channel MOS transistor are connected in series between a power supply end and a ground end, and a MOS transistor group is bridged between the first P-channel MOS transistor and the first N-channel MOS transistor, the gate of the MOS transistor group is connected to an EN signal end and an ENN signal end; and a third N-channel MOS transistor is also included, the gate of the third N-channel MOS transistor is connected to the ENN signal end, the source of the third N-channel MOS transistor is grounded, and the drain of the third N-channel MOS transistor is connected to the gate of the first N-channel MOS transistor. The output buffer circuit in the enable shutdown mode can achieve zero power consumption.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a capacitive coupling output buffer circuit of a voltage-controlled oscillator and a control method thereof. Background Art

[0002] like Figure 1 As shown, a DC blocking capacitor C1, a first inverter and a second inverter connected in series are sequentially arranged between the input and the output of the capacitor-coupled output buffer circuit of the existing voltage-controlled oscillator, wherein the first inverter comprises a first P-channel MOS transistor MP1 and a first N-channel MOS transistor MN1, the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1 are connected in series between a power supply terminal and a ground terminal, and a first resistor R1 is bridged between the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1, wherein the second inverter comprises a second P-channel MOS transistor MP2 and a second N-channel MOS transistor MN2, the second P-channel MOS transistor MP2 and the second N-channel MOS transistor MN2 are connected in series between the power supply terminal and the ground terminal;

[0003] Since a first inverter connected across the first resistor R1 is provided between the input and output of the capacitive coupling output buffer circuit, the capacitive coupling output buffer circuit cannot be turned off when the enable control is turned off, that is, the existence of the first resistor R1 will keep the output of the first inverter composed of the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1 at an intermediate potential. This intermediate potential is likely to keep the second inverter of the next stage in a conducting state, so that a direct current flows from the power supply to the ground. In this case, even if the enable control is turned off, the power consumption will be abnormally large because the output buffer circuit is not turned off. Summary of the invention

[0004] In view of the above problems existing in the prior art, a capacitive coupled output buffer circuit of a voltage controlled oscillator and a control method thereof are provided, which are intended to add a switching factor in the buffer circuit so that the output buffer circuit can also be turned off when the enable control is turned off.

[0005] The specific technical solutions are as follows:

[0006] A capacitor-coupled output buffer circuit of a voltage-controlled oscillator, wherein a voltage-controlled oscillator, a first capacitor, a first inverter and a second inverter are sequentially arranged between an input end and an output end, the input end includes an EN signal end (EN) and an input control voltage, and the input control voltage is a control voltage of a voltage-controlled oscillator (VCO);

[0007] The first inverter comprises: a first P-channel MOS transistor and a first N-channel MOS transistor, the first P-channel MOS transistor and the first N-channel MOS transistor are connected in series between a power supply terminal and a ground terminal, and a MOS transistor group is connected between the first P-channel MOS transistor and the first N-channel MOS transistor, and the MOS transistor group is between an input and an output of the first inverter;

[0008] The first capacitor is connected between the voltage controlled oscillator and the gate of the first N-channel MOS transistor;

[0009] A gate of the first N-channel MOS transistor is connected to a gate of the first P-channel MOS transistor, and a drain of the first N-channel MOS transistor and a drain of the first P-channel MOS transistor are both connected to a second inverter;

[0010] The gate of the second N-channel MOS transistor is connected to the gate of the second P-channel MOS transistor, and the drain of the second N-channel MOS transistor and the drain of the first P-channel MOS transistor are connected to the output terminal;

[0011] It also includes a third N-channel MOS transistor, wherein the gate of the third N-channel MOS transistor is connected to the ENN signal terminal, the source of the third N-channel MOS transistor is grounded, and the drain of the third N-channel MOS transistor is connected to the gate of the first N-channel MOS transistor;

[0012] The second inverter includes a second P-channel MOS transistor and a second N-channel MOS transistor, and the second P-channel MOS transistor and the second N-channel MOS transistor are connected in series between the power supply terminal and the ground terminal.

[0013] Preferably, in the capacitor-coupled output buffer circuit of the voltage-controlled oscillator, the MOS transistor group includes a plurality of MOS transistors connected in series.

[0014] Preferably, in the capacitor-coupled output buffer circuit of the voltage-controlled oscillator, the MOS transistor group includes at least one sub-P-channel MOS transistor and at least one sub-N-channel MOS transistor, and the number of sub-P-channel MOS transistors and sub-N-channel MOS transistors in the MOS transistor group is the same.

[0015] Preferably, in the capacitor-coupled output buffer circuit of the voltage-controlled oscillator, the gate of the sub-N-channel MOS transistor is connected to the EN signal terminal, and the gate of the sub-P-channel MOS transistor is connected to the ENN signal terminal.

[0016] Preferably, in the capacitive coupled output buffer circuit of the voltage controlled oscillator, when the MOS transistor group includes a sub-P channel MOS transistor and a sub-N channel MOS transistor;

[0017] A source of the sub-N-channel MOS transistor is connected to a gate of the first N-channel MOS transistor, and a drain of the sub-N-channel MOS transistor is connected to a drain of the first N-channel MOS transistor;

[0018] A source or a drain of the sub P-channel MOS transistor is connected to the gate of the first N-channel MOS transistor, and a drain or a source of the sub P-channel MOS transistor is connected to the drain of the first N-channel MOS transistor.

[0019] Preferably, the capacitive coupling output buffer circuit of the voltage-controlled oscillator includes in the MOS transistor group:

[0020] at least two sub-N-channel MOS transistors, wherein the two sub-N-channel MOS transistors are denoted as a first sub-N-channel MOS transistor and a second sub-N-channel MOS transistor, a source of the first sub-N-channel MOS transistor is connected to a gate of the first N-channel MOS transistor, a drain of the second sub-N-channel MOS transistor is connected to a drain of the first N-channel MOS transistor,

[0021] When the first sub-N-channel MOS transistor and the second sub-N-channel MOS transistor are adjacent to each other, the drain of the first sub-N-channel MOS transistor is connected to the source of the second sub-N-channel MOS transistor;

[0022] When the first sub-N-channel MOS transistor and the second sub-N-channel MOS transistor are not adjacent to each other, the drain of the first sub-N-channel MOS transistor is connected to the source of the sub-N-channel MOS transistor adjacent to the first sub-N-channel MOS transistor, and the source of the second sub-N-channel MOS transistor is connected to the drain of the sub-N-channel MOS transistor adjacent to the second sub-N-channel MOS transistor;

[0023] At least two sub-P-channel MOS transistors, wherein the two sub-P-channel MOS transistors are denoted as a first sub-P-channel MOS transistor and a second sub-P-channel MOS transistor, the first sub-P-channel MOS transistor is connected to a gate of the first N-channel MOS transistor, and the second sub-P-channel MOS transistor is connected to a drain of the first N-channel MOS transistor;

[0024] When the first sub-P-channel MOS transistor and the second sub-P-channel MOS transistor are adjacent to each other, the first sub-P-channel MOS transistor is connected to the second sub-P-channel MOS transistor;

[0025] When the first sub-P-channel MOS transistor and the second sub-P-channel MOS transistor are not adjacent, the first sub-P-channel MOS transistor is connected to the sub-P-channel MOS transistor adjacent to the first sub-P-channel MOS transistor, and the second sub-P-channel MOS transistor is connected to the sub-P-channel MOS transistor adjacent to the second sub-P-channel MOS transistor.

[0026] Preferably, the capacitor-coupled output buffer circuit of the voltage-controlled oscillator further includes an inverting amplifier, wherein the input end of the inverting amplifier is connected to one end of the MOS transistor group, and the output end of the inverting amplifier is connected to the other end of the MOS transistor group.

[0027] Preferably, in the capacitor-coupled output buffer circuit of a voltage-controlled oscillator, the first capacitor is an AC coupling capacitor, which is used to couple the signal generated by the voltage-controlled oscillator to the output buffer stage.

[0028] A control method for a capacitively coupled output buffer circuit of a voltage-controlled oscillator is also provided, wherein the method is applied to any of the capacitively coupled output buffer circuits of the voltage-controlled oscillator described above, and specifically comprises the following steps:

[0029] When the enable control signal outputted from the EN signal terminal is '1', the voltage-controlled oscillator works normally and the MOS transistor group is turned on;

[0030] When the enable control signal outputted from the EN signal terminal is '0', the voltage controlled oscillator is turned off, the third N-channel MOS transistor pulls the drain voltage to the ground, and the MOS transistor group is turned off.

[0031] The above technical solution has the following advantages or beneficial effects:

[0032] In the above embodiment, the implementation method of the resistor is modified based on the capacitor-coupled output buffer circuit of the voltage-controlled oscillator in the prior art, and a third N-channel MOS transistor is added, so that the output buffer circuit can achieve zero power consumption in the enable shutdown mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The embodiments of the present invention will be described more fully with reference to the attached drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0034] Figure 1 A circuit diagram of a capacitive coupled output buffer circuit of a voltage controlled oscillator of the prior art of the present invention;

[0035] Figure 2 A circuit diagram of a first embodiment of a capacitive coupling output buffer circuit of a voltage controlled oscillator of the present invention;

[0036] Figure 3 A circuit diagram of a second embodiment of a capacitive coupling output buffer circuit of a voltage controlled oscillator of the present invention;

[0037] Figure 4 It is a circuit diagram of Embodiment 3 of the capacitive coupling output buffer circuit of the voltage controlled oscillator of the present invention. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0040] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0041] The present invention includes a capacitive coupling output buffer circuit of a voltage-controlled oscillator VCO, wherein a voltage-controlled oscillator VCO, a first capacitor C1, a first inverter and a second inverter are sequentially arranged between an input end and an output end, the input end includes an EN signal end EN and an input control voltage V, and the input control voltage V is a control voltage of the voltage-controlled oscillator VCO;

[0042] The first inverter includes a first P-channel MOS transistor MP1 and a first N-channel MOS transistor MN1, the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1 are connected in series between a power supply terminal Vdd and a ground terminal GND, and a MOS transistor group is connected across the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1, and the MOS transistor group is connected in series between an input and an output of the first inverter;

[0043] The first capacitor C1 is connected between the voltage controlled oscillator VCO and the gate of the first N-channel MOS transistor MN1;

[0044] A gate of the first N-channel MOS transistor MN1 is connected to a gate of the first P-channel MOS transistor MP1, and a drain of the first N-channel MOS transistor MN1 and a drain of the first P-channel MOS transistor MP1 are both connected to the second inverter;

[0045] The gate of the second N-channel MOS transistor MN2 is connected to the gate of the second P-channel MOS transistor MP2, and the drain of the second N-channel MOS transistor MN2 and the drain of the first P-channel MOS transistor MP1 are connected to the output terminal;

[0046] It also includes a third N-channel MOS transistor MN3, a gate of the third N-channel MOS transistor MN3 is connected to the ENN signal terminal ENN, a source of the third N-channel MOS transistor MN3 is grounded, and a drain of the third N-channel MOS transistor MN3 is connected to the gate of the first N-channel MOS transistor MN1;

[0047] The second inverter includes a second P-channel MOS transistor MP2 and a second N-channel MOS transistor MN2. The second P-channel MOS transistor MP2 and the second N-channel MOS transistor MN2 are connected in series between the power supply terminal Vdd and the ground terminal GND.

[0048] In the above embodiment, the implementation method of the resistor is modified based on the capacitor-coupled output buffer circuit of the voltage-controlled oscillator VCO in the prior art, and a third N-channel MOS transistor MN3 is added, so that the output buffer circuit can achieve zero power consumption in the enable shutdown mode.

[0049] In the above embodiment, a MOS transistor group with controllable gate voltage is used between the input and output in the capacitive coupled output buffer circuit of the voltage controlled oscillator VCO, wherein controllable gate voltage means that it can be turned off, and combined with a pull-down NMOS, the output buffer circuit can be truly turned off, thereby saving power consumption.

[0050] In the above embodiment, by connecting the MOS transistor group between the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1, the MOS transistor group is in a linear region during normal operation, so that the MOS transistor group exhibits a resistance characteristic, and the effect of a high resistance value can be achieved relatively easily through the MOS transistor group.

[0051] When the enable is turned off, the MOS transistor group is in the off state, and the input and output of the first inverter are disconnected; at this time, because ENN of MN6 is high level, that is, the enable control signal EN is equal to '0' at this time, the output through the inverter ENN is '1', so MN6 is in the linear region, which will pull down the gate voltage of the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1 in the first inverter, so that the first N-channel MOS transistor MN1 is in the off state, and there will be no current path from the power supply to the ground. At the same time, the outputs of the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1 in the first inverter are high level, so that the second P-channel MOS transistor MP2 in the second inverter of the next stage is in the off state, and there will be no current path from the power supply to the ground. Therefore, when the enable is turned off, the output buffer circuit can achieve zero power consumption.

[0052] In the above embodiment, it should be noted that the function of the third N-channel MOS transistor MN3 is to pull the drain voltage down to the ground voltage when the enable control signal is equal to '0';

[0053] The function of the MOS transistor group is that when the enable control signal is equal to '1', the MOS transistor group is in the linear region, and at this time the MOS transistor group can be equivalent to a resistor, so that an appropriate static operating point is established between the input and output of the first inverter including the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1, so that the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1 are in the saturation region, so that the input signal of the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1 will be amplified by the circuit composed of the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1; at this time, the second inverter including the second P-channel MOS transistor MP2 and the second N-channel MOS transistor MN2 amplifies and shapes the output of the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1 to become a standard digital square wave signal.

[0054] In the above embodiment, the specific control method is:

[0055] When the enable control signal outputted by the EN signal terminal EN is '1', the voltage controlled oscillator VCO and the like work normally. At this time, the third N-channel MOS transistor MN3 will not pull the drain voltage to the ground because the gate voltage control signal is '0', and the transistors in the MOS transistor group are in the on mode because the gate voltages are respectively '1' and '0'.

[0056] When the enable control signal is '0', the voltage-controlled oscillator VCO and the like are in shutdown mode. At this time, the third N-channel MOS transistor MN3 pulls the drain voltage to ground because the gate voltage control signal is '1', and the transistors in the MOS transistor group are in cut-off mode because the gate voltages are respectively at '0' and '1', thereby achieving zero power consumption in the output buffer circuit when the enable is turned off.

[0057] Furthermore, in the above embodiment, the MOS transistor group includes a plurality of MOS transistors connected in series.

[0058] In the above embodiment, when working normally, that is, the enable control signal is equal to '1', all MOS transistors in the MOS transistor group are in the linear region, so that the MOS transistor group can present a resistance characteristic. Through multiple MOS transistors connected in series, the MOS transistor group can easily achieve the effect of high resistance.

[0059] Furthermore, in the above embodiment, a gate voltage controllable MOS transistor group is used between the input and the output in the capacitive coupled output buffer circuit of the voltage controlled oscillator VCO, wherein the MOS transistor group is a series CMOS including at least one sub-P-channel MOS transistor and at least one sub-N-channel MOS transistor, and the number of sub-P-channel MOS transistors and sub-N-channel MOS transistors in the MOS transistor group is the same.

[0060] In the above embodiment, the greater the number of sub-P-channel MOS transistors and sub-N-channel MOS transistors connected in series, the greater the resistance of the MOS transistor group.

[0061] In the above embodiment, a gate voltage-controllable series CMOS is used between the input and output in the capacitive-coupled output buffer circuit of the voltage-controlled oscillator VCO, and the output buffer circuit can be truly turned off by combining the series CMOS with a pull-down NMOS, thereby saving power consumption.

[0062] Furthermore, in the above embodiment, the gate of the sub-N-channel MOS transistor is connected to the input terminal of the first inverter, and the input terminal of the first inverter is the EN signal terminal EN at this time, and the gate of the sub-P-channel MOS transistor is connected to the output terminal of the first inverter, and the output terminal of the first inverter is connected to the ENN signal terminal ENN at this time.

[0063] In the above embodiment, when the enable control signal outputted by the EN signal terminal EN is '1', the sub-N-channel MOS transistor in the MOS transistor group is also in the on-mode because the gate voltage is at '1', and the sub-P-channel MOS transistor in the MOS transistor group is also in the linear region because the gate voltage is at '0', so that the entire MOS transistor group is in the on-mode, and the entire MOS transistor group is also in the linear region, at this time, the entire MOS transistor group can be equivalent to a resistor;

[0064] When the enable control signal is '0', the sub-N-channel MOS transistor in the MOS transistor group is in the cut-off mode because the gate voltage is at '0' and the sub-P-channel MOS transistor in the MOS transistor group is in the cut-off mode because the gate voltage is at '1', so that when the enable is turned off, the output buffer circuit achieves zero power consumption.

[0065] Furthermore, in the above embodiment, when the MOS transistor group includes a sub-P-channel MOS transistor and a sub-N-channel MOS transistor;

[0066] A source of the sub N-channel MOS transistor is connected to a gate of the first N-channel MOS transistor MN1, and a drain of the sub N-channel MOS transistor is connected to a drain of the first N-channel MOS transistor MN1;

[0067] A source or a drain of the sub P-channel MOS transistor is connected to the gate of the first N-channel MOS transistor MN1 , and a drain or a source of the sub P-channel MOS transistor is connected to the drain of the first N-channel MOS transistor MN1 .

[0068] Furthermore, in the above embodiment, an inverting amplifier is further included, wherein the input end of the inverting amplifier is connected to the EN signal end EN, and the output end of the inverting amplifier is connected to the ENN signal end ENN.

[0069] Furthermore, in the above embodiment, the first capacitor C1 is an AC coupling capacitor, which is used to couple the signal generated by the voltage controlled oscillator VCO to the output buffer stage.

[0070] As a specific embodiment 1: Figure 2 As shown, a voltage-controlled oscillator VCO, a first capacitor C1, a first inverter and a second inverter are arranged between the input end and the output end of the capacitive-coupled output buffer circuit of the voltage-controlled oscillator VCO, and the input end includes an EN signal end EN and an input control voltage V;

[0071] The first inverter includes a first P-channel MOS transistor MP1 and a first N-channel MOS transistor MN1, and the second inverter includes a second P-channel MOS transistor MP2 and a second N-channel MOS transistor MN2;

[0072] The source of the first P-channel MOS transistor MP1 is connected to the power supply terminal Vdd, the drain of the first P-channel MOS transistor MP1 is connected to the gate of the second P-channel MOS transistor MP2, the gate of the first P-channel MOS transistor MP1 is connected to the output end of the first capacitor C1, and the input end of the first capacitor C1 is connected to the voltage-controlled oscillator VCO;

[0073] A source of the first N-channel MOS transistor MN1 is grounded, a drain of the first N-channel MOS transistor MN1 is connected to a gate of the second P-channel MOS transistor MP2, and a gate of the first N-channel MOS transistor MN1 is connected to an output end of the first capacitor C1;

[0074] The source of the second P-channel MOS transistor MP2 is connected to the power supply terminal Vdd, the drain of the second P-channel MOS transistor MP2 is connected to the output terminal, and the gate of the second P-channel MOS transistor MP2 is respectively connected to the drain of the first P-channel MOS transistor MP1, the drain of the first N-channel MOS transistor MN1MP1 and the MOS transistor group;

[0075] The source of the second N-channel MOS transistor MN2 is grounded, the drain of the second N-channel MOS transistor MN2 is connected to the output terminal, and the gate of the second N-channel MOS transistor MN2 is respectively connected to the drain of the first P-channel MOS transistor MP1, the drain of the first N-channel MOS transistor MN1MP1 and the MOS transistor group;

[0076] A MOS transistor group is connected between the first P-channel MOS transistor MP1 and the first N-channel MOS transistor MN1, and the MOS transistor group includes a sub-P-channel MOS transistor and a sub-N-channel MOS transistor.

[0077] The gate of the sub-N-channel MOS transistor is connected to the EN signal terminal EN, the source of the sub-N-channel MOS transistor is connected to the gate of the first N-channel MOS transistor MN1, and the drain of the sub-N-channel MOS transistor is connected to the gate of the second P-channel MOS transistor MP2.

[0078] The gate of the sub-P-channel MOS transistor is connected to the ENN signal terminal ENN, the source or drain of the sub-P-channel MOS transistor is connected to the gate of the first N-channel MOS transistor MN1, and the drain or source of the sub-P-channel MOS transistor is connected to the gate of the second P-channel MOS transistor MP2;

[0079] A gate of the first N-channel MOS transistor MN1 is connected to a gate of the first P-channel MOS transistor MP1, and a drain of the first N-channel MOS transistor MN1 and a drain of the first P-channel MOS transistor MP1 are both connected to the second inverter;

[0080] The gate of the second N-channel MOS transistor MN2 is connected to the gate of the second P-channel MOS transistor MP2, and the drain of the second N-channel MOS transistor MN2 and the drain of the first P-channel MOS transistor MP1 are connected to the output terminal;

[0081] It also includes a third N-channel MOS transistor MN3, a gate of the third N-channel MOS transistor MN3 is connected to the ENN signal terminal ENN, a source of the third N-channel MOS transistor MN3 is grounded, and a drain of the third N-channel MOS transistor MN3 is connected to the gate of the first N-channel MOS transistor MN1;

[0082] It also includes an inverting amplifier, wherein the input end of the inverting amplifier is connected to one end of the MOS transistor group, and the output end of the inverting amplifier is connected to the other end of the MOS transistor group.

[0083] As a preferred implementation, one end of the MOS transistor group is the EN signal terminal EN, and the other end is the ENN signal terminal ENN, that is, the input end of the inverting amplifier can be connected to the EN signal terminal EN, and the output end of the inverting amplifier can be connected to the ENN signal terminal ENN.

[0084] As a preferred embodiment, when the source of the sub P-channel MOS transistor is connected to the gate of the first N-channel MOS transistor MN1 , the drain of the sub P-channel MOS transistor is connected to the gate of the second P-channel MOS transistor MP2 .

[0085] As a preferred embodiment, when the drain of the sub P-channel MOS transistor is connected to the gate of the first N-channel MOS transistor MN1 , the source of the sub P-channel MOS transistor may be connected to the gate of the second P-channel MOS transistor MP2 .

[0086] Furthermore, in the above embodiment, the MOS transistor group includes:

[0087] at least two sub-N-channel MOS transistors, wherein the two sub-N-channel MOS transistors are denoted as a first sub-N-channel MOS transistor MN4 and a second sub-N-channel MOS transistor MN5, a source of the first sub-N-channel MOS transistor MN4 is connected to a gate of the first N-channel MOS transistor MN1, a drain of the second sub-N-channel MOS transistor MN5 is connected to a drain of the first N-channel MOS transistor MN1,

[0088] When the first sub-N-channel MOS transistor MN4 and the second sub-N-channel MOS transistor MN5 are adjacent to each other, the drain of the first sub-N-channel MOS transistor MN4 is connected to the source of the second sub-N-channel MOS transistor MN5;

[0089] When the first sub-N-channel MOS transistor MN4 and the second sub-N-channel MOS transistor MN5 are not adjacent to each other, the drain of the first sub-N-channel MOS transistor MN4 is connected to the source of the sub-N-channel MOS transistor adjacent to the first sub-N-channel MOS transistor MN4, and the source of the second sub-N-channel MOS transistor MN5 is connected to the drain of the sub-N-channel MOS transistor adjacent to the second sub-N-channel MOS transistor MN5;

[0090] At least two sub-P-channel MOS transistors, wherein the two sub-P-channel MOS transistors are denoted as a first sub-P-channel MOS transistor MP4 and a second sub-P-channel MOS transistor MP5, the first sub-P-channel MOS transistor MP4 is connected to a gate of the first N-channel MOS transistor MN1, and the second sub-P-channel MOS transistor MP5 is connected to a drain of the first N-channel MOS transistor MN1;

[0091] When the first sub-P-channel MOS transistor MP4 and the second sub-P-channel MOS transistor MP5 are adjacent to each other, the first sub-P-channel MOS transistor MP4 is connected to the second sub-P-channel MOS transistor MP5;

[0092] When the first sub-P-channel MOS transistor MP4 and the second sub-P-channel MOS transistor MP5 are not adjacent to each other, the first sub-P-channel MOS transistor MP4 is connected to the sub-P-channel MOS transistor adjacent to the first sub-P-channel MOS transistor MP4, and the second sub-P-channel MOS transistor MP5 is connected to the sub-P-channel MOS transistor adjacent to the second sub-P-channel MOS transistor MP5.

[0093] As a specific embodiment 2: Figure 3 As shown, the technical solution different from the first embodiment is that the MOS transistor group includes: a first sub-N-channel MOS transistor MN4, a second sub-N-channel MOS transistor MN5, a first sub-P-channel MOS transistor MP4 and a second sub-P-channel MOS transistor MP5;

[0094] The source of the first sub-N-channel MOS transistor MN4 is connected to the gate of the first N-channel MOS transistor MN1, the drain of the second sub-N-channel MOS transistor MN5 is connected to the drain of the first N-channel MOS transistor MN1, the first sub-N-channel MOS transistor MN4 and the second sub-N-channel MOS transistor MN5 are adjacent, and the drain of the first sub-N-channel MOS transistor MN4 is connected to the source of the second sub-N-channel MOS transistor MN5.

[0095] The first sub-P-channel MOS transistor MP4 is connected to the gate of the first N-channel MOS transistor MN1, the second sub-P-channel MOS transistor MP5 is connected to the drain of the first N-channel MOS transistor MN1, the first sub-P-channel MOS transistor MP4 and the second sub-P-channel MOS transistor MP5 are adjacent, and the first sub-P-channel MOS transistor MP4 is connected to the second sub-P-channel MOS transistor MP5.

[0096] As a specific embodiment 3: Figure 4 As shown, the technical solution different from the first embodiment is that: the MOS transistor group includes more than three sub-N-channel MOS transistors and more than three P-channel MOS transistors. Here, three are taken as an example, and two of the sub-N-channel MOS transistors are recorded as the first sub-N-channel MOS transistor MN4 and the second sub-N-channel MOS transistor MN5, and two of the sub-P-channel MOS transistors are recorded as the first sub-P-channel MOS transistor MP4 and the second sub-P-channel MOS transistor MP5;

[0097] The source of the first sub-N-channel MOS transistor MN4 is connected to the gate of the first N-channel MOS transistor MN1, the drain of the second sub-N-channel MOS transistor MN5 is connected to the drain of the first N-channel MOS transistor MN1, the first sub-N-channel MOS transistor MN4 and the second sub-N-channel MOS transistor MN5 are not adjacent, a third sub-N-channel MOS transistor MN6 is also present between the first sub-N-channel MOS transistor MN4 and the second sub-N-channel MOS transistor MN5, the drain of the first sub-N-channel MOS transistor MN4 is connected to the source of the third sub-N-channel MOS transistor MN6, and the source of the second sub-N-channel MOS transistor MN5 is connected to the drain of the third sub-N-channel MOS transistor MN6;

[0098] The first sub-P-channel MOS transistor MP4 and the second sub-P-channel MOS transistor MP5 are not adjacent to each other, and there is a third sub-P-channel MOS transistor MP6 between the first sub-P-channel MOS transistor MP4 and the second sub-P-channel MOS transistor MP5. The first sub-P-channel MOS transistor MP4 is connected to the third sub-P-channel MOS transistor MP6, and the second sub-P-channel MOS transistor MP5 is connected to the third sub-P-channel MOS transistor MP6.

[0099] Also included is a control method for a capacitively coupled output buffer circuit of a voltage-controlled oscillator VCO, wherein the method is applied to any of the capacitively coupled output buffer circuits of the voltage-controlled oscillator VCO described above, and specifically comprises the following steps:

[0100] When the enable control signal outputted by the EN signal terminal EN is '1', the voltage-controlled oscillator VCO works normally and the MOS transistor group is turned on;

[0101] When the enable control signal outputted by the EN signal terminal EN is '0', the voltage controlled oscillator VCO is turned off, the third N-channel MOS transistor MN3 pulls the drain voltage to the ground, and the MOS transistor group is turned off.

[0102] It should be noted that the various embodiments of the control method of the capacitive coupling output buffer circuit of the voltage controlled oscillator VCO in this embodiment are consistent with the various embodiments of the capacitive coupling output buffer circuit of the voltage controlled oscillator VCO mentioned above, and will not be elaborated herein.

[0103] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A capacitive coupled output buffer circuit of a voltage controlled oscillator, characterized in that: A voltage-controlled oscillator (VCO), a first capacitor (C1), a first inverter and a second inverter are sequentially arranged between the input end and the output end, the input end includes an EN signal end (EN) and an input control voltage (V), and the input control voltage (V) is a control voltage of the voltage-controlled oscillator (VCO); The first inverter comprises: a first P-channel MOS transistor (MP1) and a first N-channel MOS transistor (MN1), wherein the first P-channel MOS transistor (MP1) and the first N-channel MOS transistor (MN1) are connected in series between a power supply terminal (Vdd) and a ground terminal (GND), and a MOS transistor group is bridged between the first P-channel MOS transistor (MP1) and the first N-channel MOS transistor (MN1), and a gate of the MOS transistor group is connected to an EN signal terminal (EN) and an ENN signal terminal (ENN); The first capacitor (C1) is connected between the voltage-controlled oscillator (VCO) and the gate of the first N-channel MOS transistor (MN1); It also includes a third N-channel MOS transistor (MN3), wherein the gate of the third N-channel MOS transistor (MN3) is connected to the ENN signal terminal (ENN), the source of the third N-channel MOS transistor (MN3) is grounded, and the drain of the third N-channel MOS transistor (MN3) is connected to the gate of the first N-channel MOS transistor (MN1); The second inverter comprises a second P-channel MOS transistor (MP2) and a second N-channel MOS transistor (MN2), wherein the second P-channel MOS transistor (MP2) and the second N-channel MOS transistor (MN2) are connected in series between a power supply terminal (Vdd) and a ground terminal (GND); The MOS transistor group includes at least one sub-P-channel MOS transistor and at least one sub-N-channel MOS transistor, and the number of the sub-P-channel MOS transistors and the sub-N-channel MOS transistors in the MOS transistor group is the same; When the enable control signal output by the EN signal terminal (EN) is '1', the voltage controlled oscillator (VCO) works normally and the MOS transistor group is turned on; When the enable control signal output by the EN signal terminal (EN) is '0', the voltage controlled oscillator (VCO) is turned off, the third N-channel MOS transistor (MN3) pulls the drain voltage to ground, and the MOS transistor group is turned off.

2. The capacitive coupled output buffer circuit of the voltage controlled oscillator as claimed in claim 1, characterized in that: The MOS transistor group includes a plurality of MOS transistors connected in series.

3. The capacitive coupled output buffer circuit of the voltage controlled oscillator according to claim 1, characterized in that: The gate of the sub-N-channel MOS transistor is connected to the EN signal terminal (EN), and the gate of the sub-P-channel MOS transistor is connected to the ENN signal terminal (ENN).

4. The capacitive coupled output buffer circuit of the voltage controlled oscillator as claimed in claim 3, characterized in that: When the MOS transistor group includes a sub-P-channel MOS transistor and a sub-N-channel MOS transistor; The source of the sub-N-channel MOS transistor is connected to the gate of the first N-channel MOS transistor (MN1), and the drain of the sub-N-channel MOS transistor is connected to the drain of the first N-channel MOS transistor (MN1); The source or drain of the sub-P-channel MOS transistor is connected to the gate of the first N-channel MOS transistor (MN1), and the drain or source of the sub-P-channel MOS transistor is connected to the drain of the first N-channel MOS transistor (MN1).

5. The capacitive coupled output buffer circuit of the voltage controlled oscillator as claimed in claim 3, characterized in that: The MOS transistor group includes: at least two sub-N-channel MOS transistors, wherein the two sub-N-channel MOS transistors are denoted as a first sub-N-channel MOS transistor (MN4) and a second sub-N-channel MOS transistor (MN5), wherein a source of the first sub-N-channel MOS transistor (MN4) is connected to a gate of the first N-channel MOS transistor (MN1), and a drain of the second sub-N-channel MOS transistor (MN5) is connected to a drain of the first N-channel MOS transistor (MN1), When the first sub-N-channel MOS transistor (MN4) and the second sub-N-channel MOS transistor (MN5) are adjacent to each other, the drain of the first sub-N-channel MOS transistor (MN4) is connected to the source of the second sub-N-channel MOS transistor (MN5); When the first sub-N-channel MOS transistor (MN4) and the second sub-N-channel MOS transistor (MN5) are not adjacent to each other, the drain of the first sub-N-channel MOS transistor (MN4) is connected to the source of the sub-N-channel MOS transistor adjacent to the first sub-N-channel MOS transistor (MN4), and the source of the second sub-N-channel MOS transistor (MN5) is connected to the drain of the sub-N-channel MOS transistor adjacent to the second sub-N-channel MOS transistor (MN5); At least two sub-P-channel MOS transistors, wherein the two sub-P-channel MOS transistors are denoted as a first sub-P-channel MOS transistor (MP4) and a second sub-P-channel MOS transistor (MP5), the first sub-P-channel MOS transistor (MP4) being connected to a gate of the first N-channel MOS transistor (MN1), and the second sub-P-channel MOS transistor (MP5) being connected to a drain of the first N-channel MOS transistor (MN1); When the first sub-P-channel MOS transistor (MP4) and the second sub-P-channel MOS transistor (MP5) are adjacent to each other, the first sub-P-channel MOS transistor (MP4) is connected to the second sub-P-channel MOS transistor (MP5); When the first sub-P-channel MOS transistor (MP4) and the second sub-P-channel MOS transistor (MP5) are not adjacent to each other, the first sub-P-channel MOS transistor (MP4) is connected to the sub-P-channel MOS transistor adjacent to the first sub-P-channel MOS transistor (MP4), and the second sub-P-channel MOS transistor (MP5) is connected to the sub-P-channel MOS transistor adjacent to the second sub-P-channel MOS transistor (MP5).

6. The capacitive coupled output buffer circuit of the voltage controlled oscillator as claimed in claim 1, characterized in that: It also includes an inverting amplifier, wherein the input end of the inverting amplifier is connected to one end of the MOS transistor group, and the output end of the inverting amplifier is connected to the other end of the MOS transistor group.

7. The capacitive coupled output buffer circuit of a voltage controlled oscillator as claimed in claim 1, characterized in that: The first capacitor (C1) is an AC coupling capacitor, used to couple the signal generated by the voltage controlled oscillator (VCO) to the output buffer stage.

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