Bias current generating circuit

Abstract

The bias current generating circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper end and a lower end connected in the current path, and a well contact through which a reverse leakage current of the resistor flows. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a drive transistor to provide a drive voltage to the well contact of the resistor, and to cause the reverse leakage current of the resistor to flow into the leakage control circuit.

Description

TECHNICAL FIELD

[0001] The present invention relates to a circuit for generating a bias current. In particular, the present invention relates to a bias current generation circuit having reduced leakage. BACKGROUND

[0002] Various circuits use bias current generation circuits to receive a bias current from the bias current generation circuit for adjusting a parameter of a signal they provide. For example, a current controlled oscillator (CCO) that generates a clock signal adjusts the frequency of the clock signal based on a bias current provided by a bias current generation circuit.

[0003] Figure 1 is a circuit diagram of a bias current generation circuit. The bias current generation circuit includes a first current path 102 and a second current path 104. The first current path 102 and the second current path 104 are connected in parallel between a supply voltage V DD and a ground level. The first current path 102 includes a first transistor 106, a second transistor 108, and a third transistor 110 connected in series. The second current path 104 includes a fourth transistor 112, a fifth transistor 114, a diffusion resistor 116, and a polysilicon resistor 118 connected in series. Here, the polysilicon resistor is an integrated passive device formed as part of an integrated circuit, typically including a thin film or strip of polysilicon material having a defined resistance between the ends of two contact points. Similarly, here, the diffusion resistor is an integrated passive device formed as part of an integrated circuit, typically including a thin film or strip of material having a defined resistance between the ends of two contact points, to be described in connection with Figure 2The integrated non-active device is further described in detail below. The integrated non-active device differs from a conventional discrete resistor in that it has a "well contact." Unlike a conventional discrete resistor, the integrated resistor can be connected to an existing voltage level in an integrated circuit on one of its two terminals, or at another point, or even a distributed area. Specifically, the first transistor 106, the second transistor 108, and the third transistor 110 each have a current path between two main terminals and a control terminal. The current paths of the first transistor 106, the second transistor 108, and the third transistor 110 are connected in series in the first current path 102. Similarly, the fourth transistor 112 and the fifth transistor 114 each have a current path between two main terminals and a control terminal. The current paths of the fourth transistor 112 and the fifth transistor 114, the diffusion resistor 116, and the polysilicon resistor 118 are connected in series in the second current path 104. The control terminals of the first transistor 106 and the fourth transistor 112 are connected together, and the control terminals of the second transistor 108 and the fifth transistor 114 are connected together. The mirror transistor 120 is connected as a mirror of the fourth transistor 112 to provide a mirror current of the current flowing through the current path of the fourth transistor 112 as a bias current of the bias current generation circuit 100.

[0004] The diffusion resistor 116 has two current terminals connected in the second current path 104 and a well contact connected to a supply voltage V DD . Similarly, the polysilicon resistor 118 has two current terminals connected in the second current path 104 and a well contact connected to a supply voltage V DD . Figure 2 A more detailed structure diagram of an example of the diffusion resistor 116 and the polysilicon resistor 118 in a manufacturing process is shown. Both the diffusion resistor 116 and the polysilicon resistor 118 are manufactured on a substrate 202, which is a P-type doped substrate according to the present example. The diffusion resistor 116 is disposed in a first N-well 204 on the substrate 202, and the polysilicon resistor 118 is disposed on a second N-well 206 on the substrate 202.

[0005] In the first N-well 204, a diffusion region 208 is formed to provide the diffusion resistor 116. The diffusion region 208 has a doping concentration higher than the P-type substrate 202, and thus can be referred to as a P+ doped region 208. The diffusion region 208 provides the current terminals of the diffusion resistor 116 at its lateral ends. An N-type doped region 210 having a doping concentration higher than the first N-well 204 is formed next to the diffusion region 208. The N+ doped region 210 provides the well contact of the diffusion resistor 116. A polysilicon layer 212 disposed on the second N-well 206 provides the current terminals of the polysilicon resistor 118 at its lateral ends. An N-type doped region 214 having a doping concentration higher than the second N-well 206 is formed at the edge portion of the second N-well 206. The N+ doped region 214 provides the well contact of the polysilicon resistor 118.

[0006] like Figure 2 As shown, a first junction diode D1 is formed at the interface between the P+ diffusion region 208 and the first N-well 204, and a second junction diode D2 is formed at the interface between the P-type substrate 202 and the first N-well 204. For the first junction diode D1, its equivalent anode is located in the P+ diffusion region 208, and its equivalent cathode is located in the first N-well 204. For the second junction diode D2, its equivalent anode is located in the P-type substrate 202, and its equivalent cathode is located in the first N-well 204. However, during operation, the well contact of the diffusion resistor 116, i.e., the N+ doped region 210, is coupled to the supply voltage V. DD The equivalent cathodes of the first and second junction diodes D1 and D2 are placed at a high voltage level, causing the first and second junction diodes D1 and D2 to be reverse biased. As is known, such reverse-biased diodes, especially under high-temperature conditions, exhibit significantly high leakage current I0. leak1 and I leak2 Since the diffusion region 208, which acts as the diffusion resistor 116, is coupled in the second current path 104, the reverse leakage current I of the first junction diode D1... leak1 That is, the current flowing into the diffusion region 208 also flows into the second current path 104, thereby changing the current flowing through the current path of the fourth transistor 112. As a result, the bias current of the bias current generating circuit 100, which mirrors the current of the fourth transistor 112, will deviate from its desired value, reducing the accuracy of the bias current generating circuit 100, especially in ultra-low power applications.

[0007] Figure 3 A cross-sectional schematic diagram of another connected diffusion resistor 116 is shown. Figure 3 In the middle, the N+ doped region 210 is connected in the second current path 104, and connected to the upper end of the diffusion resistor 116. The well contact of the diffusion resistor 116 is therefore not connected to the supply voltage V. DD The reverse leakage currents of both the first junction diode D1 and the second junction diode D2 are reduced. However, the N+ doped region 210 is connected to the left lateral end of the P+ diffusion region 208, thus the well contact of the diffusion resistor 116 is connected to the second current path 104. Therefore, the reverse leakage currents of the first junction diode D1 and the second junction diode D2 flowing through the well contact of the diffusion resistor 116 will affect the second current path 104, causing the current in the current channel of the fourth transistor 112 to deviate, and further causing the bias current generated by the bias current generating circuit 100 to deviate. Therefore, it is still necessary to separate the reverse leakage current from the second current path 104. Summary of the Invention

[0008] This Summary is provided to introduce a selection of concepts, in simplified form, that are further described below in the DETAILED DESCRIPTION section. This Summary is not intended to identify key or essential features of the claims, nor define any limitations for the claims.

[0009] According to one embodiment, a bias current generating circuit includes:

[0010] a first current path between a supply voltage terminal and a ground level, including a series connection of respective main terminals of a first transistor, a second transistor, and a third transistor;

[0011] a second current path between the supply voltage terminal and the ground level, including a series connection of respective main terminals of a fourth transistor and a fifth transistor, and a diffusion resistance;

[0012] wherein the diffusion resistance has a top terminal connected to the fifth transistor, a bottom terminal connected to the second current path, and a well contact, the diffusion resistance having a reverse leakage current responsive to a voltage on the well contact being higher than a voltage on the top terminal;

[0013] a leakage control circuit including a series connection of a sixth transistor and a seventh transistor; wherein the sixth transistor is connected to the supply voltage, and the seventh transistor has a source connected to the well contact of the diffusion resistance to:

[0014] apply a drive voltage to the well contact of the diffusion resistance of the second current path; and

[0015] cause the reverse leakage current of the diffusion resistance to flow through the well contact of the diffusion resistance into the leakage control circuit.

[0016] In one or more embodiments, the diffusion resistance is disposed in an N-well on a P-type substrate, and includes:

[0017] a P-type diffusion region in the N-well to provide the top terminal and the bottom terminal of the diffusion resistance; and

[0018] an N+ doped region adjacent to the diffusion region to provide the well contact to receive the drive voltage;

[0019] wherein the reverse leakage current of the diffusion resistance flows through a PN junction at an interface of the P-type diffusion region and the N-well.

[0020] In one or more embodiments, the sixth transistor of the leakage control circuit is a PMOS transistor connected as a diode, having a source connected to the supply voltage, a drain connected to the seventh transistor, and a gate connected to the drain of the sixth transistor.

[0021] In one or more embodiments, the seventh transistor of the leakage control circuit is an NMOS transistor having a gate connected to the drain of the sixth transistor and a source connected to the upper end of the diffusion resistance of the second current path.

[0022] In one or more embodiments, the seventh transistor is an intrinsic NMOS transistor having a negative gate-source voltage such that a drive voltage provided at the source of the seventh transistor is higher than a voltage at the upper end of the diffusion resistance.

[0023] In one or more embodiments:

[0024] the fifth transistor of the second current path is an NMOS transistor having a drain connected to the fourth transistor and a source connected to the upper end of the diffusion resistance;

[0025] the seventh transistor of the leakage control circuit is an NMOS transistor having a gate connected to the drain of the sixth transistor and a source connected to the gate of the fifth transistor.

[0026] In one or more embodiments, the gate-source voltage drop of the seventh transistor is lower than the gate-source voltage drop of the fifth transistor such that a drive voltage provided at the source of the seventh transistor is higher than a voltage at the upper end of the diffusion resistance.

[0027] In one or more embodiments, the leakage control circuit further comprises an eighth transistor connected between the source of the seventh transistor and a ground level, the eighth transistor being connected as a diode to provide a load for the seventh transistor.

[0028] In one or more embodiments, the bias current generation circuit further comprises a mirror transistor connected as a mirror of the fourth transistor to generate a mirror current mirroring a current of the fourth transistor as a bias current provided as an output of the bias current generation circuit.

[0029] According to an embodiment, a bias current generation circuit comprises:

[0030] a current path connected between a supply voltage and a ground level, the current path comprising a transistor having a current channel connected in the current path and a resistance having an upper end and a lower end connected in the current path and a well contact configured to cause a reverse leakage current of the resistance to flow through the well contact; and

[0031] a leakage control circuit connected to the supply voltage, wherein the leakage control circuit comprises a drive transistor configured to provide a drive voltage to the well contact of the resistance and to cause the reverse leakage current of the resistance to flow into the leakage control circuit.

[0032] In one or more embodiments, the resistance of the current path is a diffusion resistance comprising:

[0033] diffusion regions on the ends of the resistor providing upper and lower ends of the resistor; and

[0034] doped regions alongside the diffusion regions providing well contacts of the resistor.

[0035] In one or more embodiments, the diffusion regions and the doped regions are disposed in a well, the diffusion regions and the well having opposite dopant types to generate a reverse leakage current at an interface of the well and the diffusion regions in response to a drive voltage applied to the well being higher than a voltage of the diffusion regions.

[0036] In one or more embodiments, the drive transistor is an intrinsic NMOS transistor having a gate connected to a gate of the transistor of the current path, a drain connected to the supply voltage, and a source connected to a well contact of the resistor.

[0037] In one or more embodiments, the intrinsic NMOS transistor has a negative gate-source voltage to cause a drive voltage of the well contact of the resistor to be higher than a voltage of the upper end of the resistor.

[0038] In one or more embodiments, a current of a current channel of the transistor is mirrored by a mirror transistor to generate a mirror current to be provided as a bias current of the bias current generation circuit.

[0039] In one or more embodiments, the transistor is a PMOS transistor having a source connected to the supply voltage, a drain connected in the current path, and a gate connected to the drain.

[0040] In one or more embodiments:

[0041] the transistor is a PMOS transistor having a source and a drain connected in the current path;

[0042] the current path further includes an NMOS transistor having a drain connected to the drain of the PMOS transistor, a source connected to the upper end of the resistor; and

[0043] the drive transistor has a gate connected to a gate of the NMOS transistor of the current path, a drain connected to the supply voltage, and a source connected to a well contact of the resistor.

[0044] In one or more embodiments, the drive transistor is an NMOS transistor having a gate-source voltage drop lower than a gate-source voltage drop of the NMOS transistor of the current path to cause a drive voltage on the source of the drive transistor to be higher than a voltage of the source of the NMOS transistor of the current path.

[0045] In one or more embodiments, the leakage control circuit further includes a transistor connected as a diode connected between the supply voltage and the drive transistor.

[0046] In one or more embodiments, the leakage control circuit further comprises a transistor connected as a diode between the drive transistor and a ground level. BRIEF DESCRIPTION OF DRAWINGS

[0047] So that the present application can be more completely understood, further detailed description of the application can be had by reference to one or more embodiments, some of which are set forth in the appended figures. In the appended figures, the use of like reference numerals in different figures indicates similar elements, and:

[0048] Figure 1 is a circuit schematic of a bias current generation circuit;

[0049] Figure 2 is a structural schematic of a diffusion resistance and a poly resistance in Figure 1

[0050] Figure 3 is a structural schematic of a diffusion resistance and a poly resistance in Figure 1

[0051] Figure 4 is a circuit schematic of a bias current generation circuit according to an embodiment;

[0052] Figure 5 is a structural schematic of a diffusion resistance and a poly resistance in Figure 4

[0053] Figure 6 is a circuit schematic of a bias current generation circuit according to another embodiment; and

[0054] Figure 7 is a structural schematic of a diffusion resistance and a poly resistance in Figure 6 DETAILED DESCRIPTION

[0055] Figure 4 shows a circuit schematic of a bias current generation circuit according to an embodiment. As with the bias current generation circuit in Figure 1 Figure 4 The bias current generation circuit 400 in embodiments of DD ​​​​​Between and ground level. The first current path 402 includes a first transistor 406, a second transistor 408, and a third transistor 410 connected in series. The second current path 404 includes a fourth transistor 412, a fifth transistor 414, a diffusion resistor 416, and a polycrystalline resistor 418 connected in series.

[0056] In the illustrated embodiment, the first transistor 406 is a PMOS transistor, and the second transistor 408 and the third transistor 410 are NMOS transistors. The source of the first transistor 406 is connected to the supply voltage V. DD The drain of the first transistor 406 is connected to the drain of the second transistor 408. The source of the second transistor 408 is connected to the drain of the third transistor 410. The source of the third transistor 410 is connected to ground. The gate or control terminal of the first transistor 406 is connected to the gate or control terminal of the fourth transistor 412. The gate or control terminal of the second transistor 408 is connected to its drain, and the gate or control terminal of the second transistor 408 is connected to the gate or control terminal of the fifth transistor 414. The gate or control terminal of the third transistor 410 is connected to its drain.

[0057] In the second current path 404, the fourth transistor 412 is a PMOS transistor, and the fifth transistor 414 is an NMOS transistor. The source of the fourth transistor 412 is connected to the supply voltage V. DD The drain of the fourth transistor 412 is connected to the drain of the fifth transistor 414. The source of the fifth transistor 414 is connected to the diffusion resistor 416. The gate or control terminal of the fourth transistor 412 is connected to its drain.

[0058] The diffusion resistor 416 and the polycrystalline resistor 418 each have an upper terminal, a lower terminal, and a well contact. The upper terminal of the diffusion resistor 416 is connected to the source of the fifth transistor 414. The lower terminal of the diffusion resistor 416 is connected to the upper terminal of the polycrystalline resistor 418. The lower terminal of the polycrystalline resistor 418 is connected to ground. The well contact of the polycrystalline resistor 418 is connected to receive the supply voltage V. DD When the bias current generating circuit 400 is operating, the current in the second current path 404, i.e., the current in the current channel of the fourth transistor 412, is used to generate a bias current using a mirror transistor 420 connected as a mirror of the fourth transistor 412. The diffusion resistor 416 and the polycrystalline resistor 418 adjust the temperature coefficient of the second current path 404, and thus adjust the bias current generated by the bias current generating circuit 400.

[0059] exist Figure 4 In the embodiment, the bias current generating circuit 400 further includes a circuit connected to the supply voltage V. DDand the well contact of the diffusion resistance 416. The leakage control circuit 422 includes a sixth transistor 424 and a seventh transistor 426 connected in series. In the present embodiment, the sixth transistor 424 is a PMOS transistor and the seventh transistor 426 is an NMOS transistor. The source of the PMOS transistor 424 is connected to the supply voltage V DD , the drain of the PMOS transistor 424 is connected to the drain of the NMOS transistor 426. The gate or control terminal of the PMOS transistor 424 is connected to its drain. The PMOS transistor 424 is thereby connected as a diode. The PMOS transistor 424 connected as a diode is connected between the supply voltage V DD and the NMOS transistor 426 to protect the NMOS transistor 426 from electrostatic discharge (ESD) risks. The PMOS transistor 424 can thereby be referred to as a protection transistor. The source of the NMOS transistor 426 is connected to the well contact of the diffusion resistance 416 and the gate or control terminal of the NMOS transistor 426 is connected to the source of the fifth transistor 414 and to the upper end of the diffusion resistance 416. The source of the NMOS transistor 426 provides a drive voltage to the diffusion resistance 416 at the well contact of the diffusion resistance 416, and the seventh NMOS transistor 426 can thereby be referred to as a drive transistor.

[0060] Figure 5 A cross-sectional view showing the structure of the diffusion resistance 416 and the poly resistance 418 is shown. Similar to that shown in Figure 2 , the diffusion resistance 416 and the poly resistance 418 are arranged on a substrate 502. According to the present embodiment, the substrate 502 is a P-doped substrate. The diffusion resistance 416 is arranged in a first N-well 504 on the P-substrate 502 and the poly resistance 418 is arranged on a second N-well 506 on the P-substrate 502. A diffusion region 508 is formed in the first N-well 504 to provide the diffusion resistance 416. A poly layer 512 is formed on the second N-well 506 to provide the poly resistance 418. In the present embodiment, the diffusion region 508 and the poly layer 512 are both P+ doped but not silicided. As such, the diffusion resistance 416 and the poly resistance 418 have relatively high sheet resistances (a typical sheet resistance of the diffusion resistance 416 is about 226.6 ohm / sq and a typical sheet resistance of the poly resistance 418 is about 601.0 ohm / sq). The P+ doped diffusion region 508 has a positive temperature coefficient (TC) and the P+ doped poly layer 512 has a negative TC.

[0061] The diffusion region 508 has a higher doping concentration than the P-type substrate 502, and is therefore referred to as the P+ diffusion region 508. An N-type doped region 510 is disposed adjacent to the diffusion region 508. In this embodiment, the N-type doped region 510 has a higher doping concentration than the first N-well 504, and is therefore referred to as the N+ doped region 510. The N+ doped region 510 is used to apply a relatively high voltage to the first N-well 504, thereby reverse-biasing the PN junction between the P+ diffusion region 508 and the first N-well 504, preventing the PN junction from forward conducting and preventing leakage current from the P+ diffusion region 508.

[0062] In this embodiment, the N+ doped region 510 is connected to the source of the NMOS transistor 426 in the leakage control circuit 422. According to this embodiment, the NMOS transistor 426 is an intrinsic device that has a negative gate-source threshold voltage V under typical process and room temperature conditions. th . refer to Figure 4 During operation, the source of the NMOS transistor 426, connected to the well contact of the diffusion resistor 416, is provided with a voltage slightly higher than its gate or control terminal, which is connected to the upper end of the diffusion resistor 416. Figure 5 In the N+ doped region 510, the voltage V _lnw Only compare the voltage V of the P+ diffusion region 508 s2 Slightly higher, for example, tens of millivolts (mV), therefore the reverse leakage current I of the first junction diode D1 at the interface between the P+ diffusion region 508 and the first N-well 504 is... leak1 It is negligible. Furthermore, the reverse leakage current I... leak1 The current primarily flows through the leakage control circuit 422, namely the PMOS transistor 424 connected as a diode and the intrinsic NMOS transistor 426, without affecting the second current path 404. The stability and robustness of the bias current generated by the mirror diode 420 relative to temperature and leakage current are thus improved.

[0063] Figure 6 This is a circuit diagram of a bias current generating circuit 600 according to another embodiment. This bias current generating circuit 600 is... Figure 4 The bias current generating circuit 400 is similar, including a first current path 602 and a second current path 604. However, in this embodiment, the voltage difference between the upper end of the diffusion resistor 616 and the well contact is driven by a different leakage control circuit 622. The first current path 602 includes a series connection at the supply voltage V DD A first PMOS transistor 606, a second NMOS transistor 608, and a third NMOS transistor 610 are connected between the supply voltage V and ground. The second current path 604 includes a series connection at the supply voltage V. DDThe circuit includes a fourth PMOS transistor 612, a fifth NMOS transistor 614, a diffusion resistor 616, and a polysilicon resistor 618, which are connected between the ground level and the ground level. The bias current generating circuit 600 includes a mirror PMOS transistor 620 connected as a mirror of the fourth PMOS transistor 612 to generate a mirror current as the bias current provided by the bias current generating circuit 600.

[0064] The bias current generating circuit 600 includes a circuit connected to the supply voltage V. DD A leakage control circuit 622 is provided between the leakage level and ground. The leakage control circuit 622 includes a sixth transistor 624, a seventh transistor 626, and an eighth transistor 628 connected in series. In this embodiment, the sixth transistor 624 is a PMOS transistor connected as a diode to protect the seventh transistor 626 from ESD risks, and the eighth transistor 628 is an NMOS transistor connected as a diode to provide a load to the seventh transistor 626 and stabilize its output voltage. The sixth transistor 626 can thus be referred to as a protection transistor, and the eighth transistor as a load transistor. The seventh transistor 626 is an NMOS transistor with a drain connected to the sixth PMOS transistor 624, a gate or control terminal connected to the gate or control terminal of the second transistor 608 and the fifth transistor 614, and a source connected to the eighth NMOS transistor 628. The source of the seventh NMOS transistor 626 provides a drive voltage to the diffusion resistor 616 by applying a drive voltage to the well contact of the diffusion resistor 616, thus the seventh NMOS transistor 626 can be referred to as a drive transistor.

[0065] Figure 7 yes Figure 6 A schematic cross-sectional view of the diffusion resistor 616 and the polycrystalline resistor 618 is shown in the diagram. Both the diffusion resistor 616 and the polycrystalline resistor 618 are disposed on a P-type substrate 702, in the first N-well 704 and the second N-well 706, respectively. Both resistors have a cross-sectional view of the diffusion resistor 616 and the polycrystalline resistor 618. Figure 5 The resistors in the same configuration are similar and will not be described in detail here. The N+ doped region 710 is connected to the source of the seventh NMOS transistor 626. The left lateral end of the diffusion region 708, that is, the upper end of the diffusion resistor 616, is connected to the source of the fifth transistor 614.

[0066] refer to Figure 6 As shown, a driving voltage V is applied from the source of the seventh NMOS transistor 626 to the well contact of the diffusion resistor 616. _lnwSince the gates or control terminals of the fifth NMOS transistor 614 and the seventh NMOS transistor 626 are connected together, the source voltages of the fifth NMOS transistor 614 and the seventh NMOS transistor 626 depend on their respective gate-source voltage drops. A larger gate-source voltage drop results in a lower source voltage. Because there is a positive correlation between the gate-source voltage drop of a transistor and the current flowing through it, the voltage V across the well contact of the diffusion resistor 616... _lnw Slightly higher than the voltage V at the upper end of the diffusion resistor 616 s2 This is because it mainly includes the reverse leakage current I of the first junction diode D1. leak1 The current I of the leakage control circuit 622 and the current of the eighth transistor 628. _leak The current I below the second current path 604 _bias In one example, at a temperature of 140°C, the current I in the second current path 604 is... _bias It is the current I of the leakage control circuit 622. _leak 1.36 times, thus providing the source voltage V of the seventh NMOS transistor 626 as the drive voltage to the well contact of the diffusion resistor 616. _lnw Compared to the source voltage V of the fifth transistor 614 s2 16.4mV.

[0067] exist Figure 7 In this implementation, the reverse leakage current of the first junction diode D1 flows through the N+ doped region 710 connected in the leakage control circuit 622, having almost no effect on the second current path 604. As previously mentioned, the voltage at the well contact of the diffusion resistor 616 is only about tens of millivolts higher than the voltage at its upper end. In the first junction diode D1, the reverse bias voltage is low enough to generate a negligible reverse leakage current, further reducing the deviation of the bias current from its desired value.

[0068] An embodiment of the bias current generating circuit includes a second current path comprising a fourth transistor. The current of the fourth transistor is used by a current mirror transistor to generate a bias current. The second current path further includes a diffusion resistor and a polycrystalline resistor connected in series with the fourth transistor. The diffusion resistor has an upper end connected to the fourth transistor via a fifth transistor, a lower end connected to the polycrystalline resistor, and a well contact. The bias current generating circuit further includes a leakage control circuit that provides a control voltage to the well contact of the diffusion resistor. The reverse leakage current of the diffusion resistor flows through the leakage control circuit. The control voltage is higher than the voltage at the upper end of the diffusion resistor. In an alternative embodiment, the polycrystalline resistor and the diffusion resistor can be interchanged by connecting the polycrystalline resistor between the diffusion resistor and the fifth transistor.

[0069] Reference is made herein to specific illustrated examples that are described in considerable detail to facilitate a clear understanding of various illustrative implementations. The illustrated examples are not meant to limit the scope of the system, structure, and device that can be constructed in accordance with one or more implementations, and the methods implemented in accordance with one or more implementations, but rather are intended to be illustrative thereof. Rather, the scope of the system, structure, and device that can be constructed in accordance with one or more implementations, and the methods implemented in accordance with one or more implementations, will be defined only in light of the claims that follow, and equivalents thereof. To the extent that specific examples are discussed herein, they are provided only to assist in understanding the present disclosure and are not intended to limit the scope of the system, structure, and device that can be constructed in accordance with one or more implementations, and the methods implemented in accordance with one or more implementations.

[0070] It will be understood that, with respect to various positional indications used in the foregoing description of the present application, such as top, bottom, upper, lower, those indications are given with reference to the respective drawings and can instead have other positional relationships when the orientation of the device is changed in manufacture or operation. As noted above, those positional relationships are described for clarity only and are not limiting.

[0071] The foregoing description of the present application is with reference to particular implementations and particular drawings, but the present application should not be limited thereto, but should only be as set forth in the claims. The various drawings described are illustrative and not limiting. In the drawings, the size of the elements can be exaggerated and can not be drawn to scale for illustrative purposes. The present description should also include discontinuous variations in the elements, manner of operation, and properties of the application. Various attenuated implementations of the present application should also be included.

[0072] The word "comprising" as used in the description and claims of the present application does not exclude other elements or steps. Unless otherwise specified, the use of singular terms such as "a", "an" and "the" can include the plural. The word "comprising" does not exclude other elements or steps. The indefinite article "a" or "an" does not exclude a plurality. The scope of the expression "means for" can include hardware and software means. The word "coupling" or "connected to" means that there is a link of any kind between the elements in question, and does not necessarily mean a direct link. The word "coupling" or "connected to" does not exclude the presence of intermediate elements between the elements being coupled or connected, unless otherwise specified. In describing a transistor and its connections, the words gate, drain, and source are interchangeable with gate terminal, drain terminal, and source terminal.

[0073] Many modifications can be made to the specific implementations described herein without departing from the scope of the claims that follow.

Claims

1. A bias current generating circuit characterized by comprising: comprises a series connection of current channels of the first transistor, the second transistor, and the third transistor; a second current path between the supply voltage terminal and the ground level, comprising a series connection of current channels of the fourth transistor and the fifth transistor, and a diffusion resistance; wherein the diffusion resistance has an upper end connected to the fifth transistor, a lower end connected in the second current path, and a well contact, the diffusion resistance having a reverse leakage current in response to a voltage on the well contact being higher than a voltage on the upper end; a leakage control circuit comprising a series connection of a sixth transistor and a seventh transistor; wherein one of a source and a drain of the sixth transistor is connected to the supply voltage, and the other of the source and the drain of the sixth transistor is connected to a drain of the seventh transistor; the seventh transistor further has a source connected to the well contact of the diffusion resistance to: apply a drive voltage to the well contact of the diffusion resistance of the second current path; and cause the reverse leakage current of the diffusion resistance to flow through the well contact of the diffusion resistance into the leakage control circuit. the diffusion resistance is arranged in an N-well on a P-substrate, and comprises: a P-type diffusion region in the N-well to provide the upper end and the lower end of the diffusion resistance; and 2. The bias current generating circuit according to claim 1, wherein an N+ doped region next to the diffusion region to provide the well contact to receive the drive voltage; wherein the reverse leakage current of the diffusion resistance flows through a PN junction at an interface of the P-type diffusion region and the N-well. the seventh transistor of the leakage control circuit is an NMOS transistor having a gate connected to the drain of the sixth transistor, and a gate connected to the upper end of the diffusion resistance of the second current path. the seventh transistor is an intrinsic NMOS transistor having a negative gate-source voltage to cause the drive voltage provided at the source of the seventh transistor to be higher than a voltage at the upper end of the diffusion resistance.

3. The bias current generation circuit according to claim 1, characterized by:

5. The bias current generation circuit according to claim 1, wherein:

4. The bias current generating circuit according to claim 3, characterized in that: the fifth transistor of the second current path is an NMOS transistor having a source connected to the drain of the fourth transistor, and a source connected to the upper end of the diffusion resistance; the seventh transistor of the leakage control circuit is an NMOS transistor having a gate connected to the drain of the sixth transistor, and a gate connected to the gate of the fifth transistor. comprises a current path connected between a supply voltage terminal and a ground level, the current path comprising a transistor having a current channel connected in the current path, and a resistance having an upper end and a lower end connected in the current path, and a well contact configured to cause a reverse leakage current of the resistance to flow through the well contact; and a leakage control circuit connected to the supply voltage, wherein the leakage control circuit comprises a drive transistor configured to provide a drive voltage to the well contact of the resistance, and to cause the reverse leakage current of the resistance to flow into the leakage control circuit; 6. A bias current generating circuit characterized by comprising: wherein the drive transistor is an intrinsic NMOS transistor having a gate connected to the upper end of the resistance of the current path, a drain connected to the supply voltage, and a source connected to the well contact of the resistance. the resistance of the current path is a diffusion resistance comprising: a diffusion region providing the upper end and the lower end of the resistance on a lateral end; and a doped region next to the diffusion region to provide the well contact of the resistance.

7. The bias current generation circuit according to claim 6, wherein the diffusion resistance is arranged in an N-well on a P-substrate, and comprises: a P-type diffusion region in the N-well to provide the upper end and the lower end of the diffusion resistance; and an N+ doped region next to the diffusion region to provide the well contact to receive the drive voltage; wherein the reverse leakage current of the diffusion resistance flows through a PN junction at an interface of the P-type diffusion region and the N-well.

8. The bias current generation circuit according to claim 7, characterized by: A diffusion region and a doped region are disposed in a well, the diffusion region and the well having opposite dopant types to generate a reverse leakage current at an interface of the well and the diffusion region in response to a drive voltage applied to the well being higher than a voltage of the diffusion region.

9. A bias current generating circuit characterized by comprising: Comprise: a current path connected between a supply voltage and a ground level, the current path including a transistor having a current channel connected in the current path, and a resistance having an upper end and a lower end connected in the current path, and a well contact configured to cause a reverse leakage current of the resistance to flow therethrough; and a leakage control circuit connected to the supply voltage, wherein the leakage control circuit includes a drive transistor configured to provide a drive voltage to the well contact of the resistance, and to cause the reverse leakage current of the resistance to flow into the leakage control circuit; wherein: the transistor is a PMOS transistor having a source and a drain connected in the current path; the current path further includes an NMOS transistor having a drain connected to the drain of the PMOS transistor, a source connected to the upper end of the resistance; and the drive transistor has a gate connected to a gate of the NMOS transistor of the current path, a drain connected to the supply voltage, and a source connected to the well contact of the resistance.

10. The bias current generation circuit according to claim 9, characterized by: the drive transistor is an NMOS transistor having a gate-source voltage drop lower than a gate-source voltage drop of the NMOS transistor of the current path, to cause the drive voltage on the source of the drive transistor to be higher than a voltage of the source of the NMOS transistor of the current path.

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