A chip packaging method, a chip and an electronic device

Abstract

The present application relates to the field of intelligent power module technology, and discloses a chip packaging method, a chip and an electronic device, the packaging method comprising: providing a cut wafer to prepare a power semiconductor chip, the power semiconductor chip comprising a gate, a first emitter and a second emitter; attaching a high-temperature adhesive film to the surface of the gate and the first emitter; installing the power semiconductor chip on an electronic packaging substrate; assembling the electronic packaging substrate with a lead frame to achieve electrical connection between the components; installing a drive control chip on the lead frame and achieving electrical connection; removing the high-temperature adhesive film; achieving connection between the drive electrode of the drive control chip and the gate, and connection between the first emitter and the lead frame; performing plastic sealing, post-curing, degumming, electroplating and rib cutting. The packaging method disclosed in the present application can prevent the problem of gate contamination generated during the combination of the lead frame and the chip, and enhance the reliability of the gate welding wire.

Description

Technical Field

[0001] The present application relates to the technical field of intelligent power modules, and in particular to a chip packaging method, a chip and an electronic device. Background Art

[0002] The intelligent power module not only integrates the power switch device and the drive circuit, but also has built-in fault detection circuits such as overvoltage, overcurrent and overheating, and can send detection signals to the CPU. It is composed of a high-speed, low-power die, an optimized gate drive circuit and a fast protection circuit, which can ensure that the intelligent power module itself is not damaged even if a load accident or improper use occurs. With the further increase in the current density of power devices, higher requirements are placed on the heat dissipation capacity of devices and modules, and the market's requirements for increasingly light, thin, short, small and low-priced products have brought greater challenges to the miniaturization of power devices or modules.

[0003] In intelligent power modules, in order to improve the heat dissipation and overcurrent capacity of the module, it has become a trend to replace aluminum wires with copper frame connections, which not only reduces the risk of damaging the chip during the cold pressure welding process of aluminum wires, but also improves packaging efficiency and reliability. Since the intelligent power module contains a driver IC chip, high speed and reliability are required when driving the IGBT (connecting the gate), and currently the gold wire or copper wire hot pressure welding process is basically used. During the high-temperature bonding process of the bonding material on the chip surface and the copper frame, contaminants will splash onto the gate. In addition, secondary pollution may also occur during the cleaning process using chemicals, causing the quality of the intelligent power module to decline. Summary of the invention

[0004] The present invention provides a chip packaging method, which can prevent the problem of grid contamination generated during the process of combining a lead frame with a chip and enhance the reliability of grid bonding wires.

[0005] In order to achieve the above object, the present application provides a chip packaging method, comprising:

[0006] Providing a cut wafer to prepare a power semiconductor chip, wherein the power semiconductor chip includes a gate, a first emitter and a second emitter;

[0007] Attaching a high temperature adhesive film on the surface of the gate and the first emitter;

[0008] Mounting the power semiconductor chip on an electronic packaging substrate;

[0009] Assembling the electronic packaging substrate and the lead frame to achieve electrical connection between the electronic packaging substrate and the power semiconductor chip, between the electronic packaging substrate and the lead frame, and between the power semiconductor chip and the lead frame;

[0010] Installing a drive control chip on the lead frame and achieving electrical connection between the drive control chip and the lead frame;

[0011] Removing the high temperature adhesive film on the gate and the first emitter;

[0012] Welding metal leads between the electronic packaging substrate and the lead frame to achieve connection between the driving electrode of the driving control chip and the gate, and to achieve connection between the first emitter and the lead frame;

[0013] The electronic packaging substrate and the lead frame are plastic-sealed, post-cured, debonded, electroplated and rib-cut.

[0014] In the above-mentioned packaging method, before the power semiconductor chip is installed on the electronic packaging substrate, a high-temperature adhesive film is attached to the surface of the gate and the first emitter. When the electronic packaging substrate and the lead frame are assembled and electrically connected, the high-temperature adhesive film can ensure that the gate and the first emitter are not contaminated during the installation of the lead frame and the high-temperature reflow process, and the high-temperature adhesive film is removed after the electrical connection is completed, thereby enhancing the reliability of the gate bonding wire and ensuring the reliability of the product.

[0015] In addition, since the above-mentioned packaging method adopts the assembly of the lead frame and the electronic packaging substrate, the lead frame is used for the interconnection on the chip surface, replacing the aluminum wire, which can make the heat dissipation effect of the chip better and can also improve the reliability and current density of the chip; and the connection between the driving electrode and the gate of the driving control chip and the connection between the first emitter and the lead frame are realized through metal leads. The technology is simple and reliable, easy to implement, and can also ensure good connection.

[0016] Therefore, the packaging method provided by the present invention prevents the problem of gate contamination generated during the assembly of the lead frame and the electronic packaging substrate by covering the gate and the first emitter with a high-temperature adhesive film, thereby enhancing the reliability of the gate bonding wire; in addition, it also improves the heat dissipation capacity, reliability and current density of the chip.

[0017] Preferably, the electrical connection between the electronic packaging substrate and the power semiconductor chip, the electrical connection between the electronic packaging substrate and the lead frame, and the electrical connection between the power semiconductor chip and the lead frame include:

[0018] Printing a bonding material between the electronic packaging substrate and the power semiconductor chip;

[0019] printing a bonding material on the second emitter on each of the power semiconductor chips;

[0020] Printing a bonding material on a portion where the electronic packaging substrate is connected to the lead frame;

[0021] The bonding material is subjected to high temperature reflow curing.

[0022] Preferably, the step of achieving electrical connection between the drive control chip and the lead frame comprises:

[0023] A bonding material is printed between the lead frame and the drive control chip, and the bonding material is subjected to high-temperature reflow curing.

[0024] Preferably, a groove is provided on the electronic packaging substrate, and when the electronic packaging substrate is assembled with the lead frame, the pins of the lead frame are embedded in the groove.

[0025] Preferably, the step of removing the high temperature adhesive film on the gate and the first emitter includes:

[0026] Using ultraviolet light to irradiate the high temperature adhesive film attached to the gate and the first emitter;

[0027] The high temperature adhesive film attached to the gate electrode and the first emitter electrode is adsorbed by a suction nozzle.

[0028] Preferably, the present application further provides a chip, comprising a vertically interconnected electronic packaging substrate and a lead frame, wherein:

[0029] The electronic packaging substrate is electrically connected to the lead frame;

[0030] A plurality of power semiconductor chips are mounted on the electronic packaging substrate, each of the power semiconductor chips comprises: a gate, a first emitter and a second emitter, and each of the power semiconductor chips is electrically connected to the electronic packaging substrate;

[0031] A plurality of drive control chips are mounted on the lead frame, and each of the drive control chips is electrically connected to the lead frame;

[0032] The driving electrode of each driving control chip is connected to the gate on the corresponding power semiconductor chip through a metal wire.

[0033] Preferably, the surface passivation layer material of the gate electrode and the surface passivation layer material of the first emitter electrode are aluminum or aluminum alloy, and the surface passivation layer material of the second emitter electrode is silver or silver alloy.

[0034] Preferably, the electronic packaging substrate and the lead frame have a plastic packaging layer, and the material of the plastic packaging layer is epoxy resin.

[0035] Preferably, the electronic packaging substrate is a copper-clad ceramic substrate.

[0036] Preferably, the present application also provides an electronic device, comprising any one of the chips described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of a step flow of a chip packaging method in this application;

[0038] Figure 2 A schematic diagram of a cross-sectional structure of a chip in this application;

[0039] Figure 3 A schematic diagram of a top view of the chip structure before rib cutting in this application;

[0040] Figure 4 A schematic diagram of a top view of the structure of the chip after rib cutting in this application;

[0041] Figure 5 This is a schematic diagram of the top view of the power semiconductor chip in this application without a high-temperature adhesive film attached;

[0042] Figure 6 This is a schematic diagram of the top view of the structure of the power semiconductor chip attached with a high-temperature adhesive film in this application.

[0043] In the figure:

[0044] 1-electronic packaging substrate; 2-lead frame; 3-power semiconductor chip; 31-gate; 32-first emitter; 33-second emitter; 4-drive control chip; 5-metal lead; 6-binding material; 7-groove; 8-epoxy resin; 9-high temperature adhesive film. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] like Figure 1 Combination Figure 3 and Figure 5-Figure 6 As shown, the present application provides a chip packaging method for solving the problem of contaminated gate 31 generated during the bonding process of lead frame 2 and chip, and the specific steps are as follows:

[0047] S1: providing a cut wafer to prepare a power semiconductor chip 3, wherein the power semiconductor chip 3 includes a gate 31, a first emitter 32 and a second emitter 33;

[0048] S2: attaching a high temperature adhesive film 9 to the surfaces of the gate electrode 31 and the first emitter electrode 32;

[0049] S3: installing the power semiconductor chip 3 on the electronic packaging substrate 1;

[0050] S4: Assembling the electronic packaging substrate 1 and the lead frame 2 to achieve electrical connection between the electronic packaging substrate 1 and the power semiconductor chip 3, between the electronic packaging substrate 1 and the lead frame 2, and between the power semiconductor chip 3 and the lead frame 2;

[0051] S5: installing the driving control chip 4 on the lead frame 2, and realizing electrical connection between the driving control chip 4 and the lead frame 2;

[0052] S6: removing the high temperature adhesive film 9 on the gate 31 and the first emitter 32;

[0053] S7: welding the metal lead 5 between the electronic packaging substrate 1 and the lead frame 2 to achieve the connection between the driving electrode of the driving control chip 4 and the gate 31, and to achieve the connection between the first emitter 32 and the lead frame 2;

[0054] S8: performing plastic encapsulation, post-curing, debonding, electroplating and rib cutting on the electronic packaging substrate 1 and the lead frame 2.

[0055] The above chip includes a power semiconductor chip 3 and a drive control chip 4. The power semiconductor chip 3 is mounted on an electronic packaging substrate 1, and the drive control chip 4 is mounted on a lead frame 2. The electronic packaging substrate 1 and the lead frame 2 are assembled and electrically connected to realize chip packaging. In order to realize this process, first, before the power semiconductor chip 3 is installed on the electronic packaging substrate 1, a high-temperature adhesive film 9 is attached to the gate 31 and the first emitter 32 on the power semiconductor chip 3, which can ensure that the gate 31 will not be contaminated during the assembly and electrical connection. After the assembly and electrical connection are realized, the high-temperature adhesive film 9 is removed, which will not affect the normal use of the chip. The above packaging method prevents the problem of contaminating the gate 31 generated during the combination of the lead frame 2 and the electronic packaging substrate 1 by covering the gate 31 with the high-temperature adhesive film 9, and enhances the reliability of the gate 31 welding wire.

[0056] In addition, since the above packaging method uses the assembly of the lead frame 2 and the electronic packaging substrate 1, the chip surface interconnection uses the lead frame 2 instead of the aluminum wire, which can make the heat dissipation effect of the chip better and improve the reliability and current density of the chip. The connection between the driving electrode of the driving control chip 4 and the gate 31 and the connection between the first emitter 32 and the lead frame 2 are realized by the metal lead 5. The technology is simple and reliable, easy to implement, and can also ensure good connection.

[0057] Specifically, in order to realize the electrical connection between the electronic packaging substrate 1 and the power semiconductor chip 3, the electrical connection between the electronic packaging substrate 1 and the lead frame 2, and the electrical connection between the power semiconductor chip 3 and the lead frame 2, the following method can be used:

[0058] Before the power semiconductor chip 3 is mounted on the electronic packaging substrate 1, a bonding material 6 is printed on the electronic packaging substrate 1, and then the power semiconductor chip 3 is mounted on the electronic packaging substrate 1; thereafter, the bonding material 6 is printed on the second emitter 33; then, the lead frame 2 is mounted on the electronic packaging substrate 1; thereafter, the bonding material 6 is printed on the portion where the lead frame 2 is connected to the electronic packaging substrate 1; and thereafter, the bonding material 6 is cured at high temperature to achieve electrical connection between the components.

[0059] Similarly, in order to achieve electrical connection between the driving control chip 4 and the wire frame 2, after the above-mentioned binding material 6 is cured at high temperature, the binding material 6 can be printed on the position where the driving control chip 4 is installed on the wire frame 2, and the driving control chip 4 is installed on the wire frame 2, and then the binding material 6 is cured at high temperature to achieve electrical connection between the driving control chip 4 and the wire frame 2.

[0060] Furthermore, a groove 7 is provided on the electronic packaging substrate 1. When the electronic packaging substrate 1 is assembled with the lead frame 2, the pins of the lead frame 2 are embedded in the groove 7, which can ensure the parallelism between the electronic packaging substrate 1 and the lead frame 2, prevent the resin overflow on the heat dissipation surface caused by the tilt of the electronic packaging substrate 1, and ensure better heat dissipation function.

[0061] Specifically, when removing the high-temperature adhesive film 9 on the gate 31 and the first emitter 32, the step includes: using ultraviolet light to irradiate the high-temperature adhesive film 9 attached to the gate 31 and the first emitter 32, and then adsorbing the high-temperature adhesive film 9 attached to the gate 31 and the first emitter 32 through a suction nozzle. This step is simple, reliable and easy to implement.

[0062] Based on the same inventive idea, Figure 2 as well as Figure 4 As shown, the present application also provides a chip prepared by the above-mentioned packaging method, the chip includes a vertically interconnected electronic packaging substrate 1 and a lead frame 2, wherein the electronic packaging substrate 1 is electrically connected to the lead frame 2; a plurality of power semiconductor chips 3 are mounted on the electronic packaging substrate 1, each of the power semiconductor chips 3 includes: a gate 31, a first emitter 32 and a second emitter 33, and each of the power semiconductor chips 3 is electrically connected to the electronic packaging substrate 1; a plurality of drive control chips 4 are mounted on the lead frame 2, each of the drive control chips 4 is electrically connected to the lead frame 2; a drive electrode of each drive control chip 4 is connected to the gate 31 on the corresponding power semiconductor chip 3 via a metal lead 5.

[0063] The above-mentioned chip includes a power semiconductor chip 3 and a drive control chip 4. The chip is vertically interconnected by an electronic packaging substrate 1 and a lead frame 2. The electronic packaging substrate 1 is a carrier of the power semiconductor chip 3, and the lead frame 2 is a carrier of the drive control chip 4. The lead frame 2 not only realizes the electrical connection of the power semiconductor chip 3, but also realizes the high heat dissipation performance of the chip.

[0064] In addition, the above-mentioned chip is prepared by the packaging method in the present application, and the electrical connection between the power semiconductor chip 3 and the electronic packaging substrate 1, the electrical connection between the power semiconductor chip 3 and the lead frame 2, and the electrical connection between the lead frame 2 pins and the electronic packaging substrate 1 are achieved by printing the bonding material 6 and high-temperature curing. In this process, contamination of the gate 31 is avoided, thereby enhancing the reliability of the gate 31 welding wire.

[0065] Specifically, the surface passivation layer material of the gate 31 included in the above-mentioned power semiconductor chip 3 and the surface passivation layer material of the first emitter 32 are aluminum or aluminum alloy. Since aluminum material is easily corroded, the chip packaging is achieved by attaching a high-temperature adhesive film 9, which effectively avoids the problem of contaminating the gate 31 during the assembly process and enhances the reliability of the gate 31 welding wire; the surface passivation layer material of the second emitter 33 is silver or silver alloy, which is convenient for connection with the bonding material 6.

[0066] Furthermore, the above chip is encapsulated with epoxy resin 8. After the epoxy resin 8 is cured at high temperature, the epoxy resin 8 film is fully reacted, the internal stress is reduced and the resin hardness is increased. The epoxy resin 8 wraps the chip and the internal structure in a molten state, providing physical and electrical protection, and can effectively prevent the impact of the external environment. It should be noted that the back of the electronic packaging substrate 1 does not need to be wrapped with epoxy resin 8.

[0067] Furthermore, the electronic packaging substrate 1 of the above chip adopts a copper-clad ceramic substrate, which has the advantages of high thermal conductivity, high electrical insulation, low expansion, high conductivity and excellent weldability, and can better ensure the product stability of the chip.

[0068] Based on the same inventive concept, the present application also provides an electronic device, including the above-mentioned chip. Since the above-mentioned chip has good heat dissipation performance and overcurrent capability, the reliability is improved and the functional stability of the electronic device is ensured.

[0069] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A chip packaging method, characterized in that: include: Providing a cut wafer to prepare a power semiconductor chip, wherein the power semiconductor chip includes a gate, a first emitter and a second emitter; Attaching a high temperature adhesive film on the surface of the gate and the first emitter; Mounting the power semiconductor chip on an electronic packaging substrate; Assembling the electronic packaging substrate and the lead frame to achieve electrical connection between the electronic packaging substrate and the power semiconductor chip, between the electronic packaging substrate and the lead frame, and between the power semiconductor chip and the lead frame; Installing a drive control chip on the lead frame and achieving electrical connection between the drive control chip and the lead frame; Removing the high temperature adhesive film on the gate and the first emitter; Welding metal leads between the electronic packaging substrate and the lead frame to achieve connection between the driving electrode of the driving control chip and the gate, and to achieve connection between the first emitter and the lead frame; The electronic packaging substrate and the lead frame are plastic-sealed, post-cured, debonded, electroplated and rib-cut.

2. The chip packaging method according to claim 1, characterized in that: The method of realizing the electrical connection between the electronic packaging substrate and the power semiconductor chip, the electrical connection between the electronic packaging substrate and the lead frame, and the electrical connection between the power semiconductor chip and the lead frame comprises: Printing a bonding material between the electronic packaging substrate and the power semiconductor chip; printing a bonding material on the second emitter on each of the power semiconductor chips; Printing a bonding material on a portion where the electronic packaging substrate is connected to the lead frame; The bonding material is subjected to high temperature reflow curing.

3. The chip packaging method according to claim 1, characterized in that: The method of realizing electrical connection between the drive control chip and the lead frame includes: A bonding material is printed between the lead frame and the drive control chip, and the bonding material is subjected to high-temperature reflow curing.

4. The chip packaging method according to claim 1, characterized in that: The electronic packaging substrate is provided with a groove, and when the electronic packaging substrate is assembled with the lead frame, the pins of the lead frame are embedded in the groove.

5. The chip packaging method according to claim 1, characterized in that: The step of removing the high temperature adhesive film on the gate electrode and the first emitter electrode comprises: Using ultraviolet light to irradiate the high temperature adhesive film attached to the gate and the first emitter; The high temperature adhesive film attached to the gate electrode and the first emitter electrode is adsorbed by a suction nozzle.

6. A chip prepared by the packaging method according to any one of claims 1 to 5, characterized in that: An electronic package substrate and lead frame comprising vertical interconnections, wherein: The electronic packaging substrate is electrically connected to the lead frame; A plurality of power semiconductor chips are mounted on the electronic packaging substrate, each of the power semiconductor chips comprises: a gate, a first emitter and a second emitter, and each of the power semiconductor chips is electrically connected to the electronic packaging substrate; A plurality of drive control chips are mounted on the lead frame, and each of the drive control chips is electrically connected to the lead frame; The driving electrode of each driving control chip is connected to the gate on the corresponding power semiconductor chip through a metal wire.

7. The chip according to claim 6, characterized in that: The surface passivation layer material of the gate electrode and the surface passivation layer material of the first emitter electrode are aluminum or aluminum alloy, and the surface passivation layer material of the second emitter electrode is silver or silver alloy.

8. The chip according to claim 6, characterized in that: The electronic packaging substrate and the lead frame have a plastic packaging layer, and the material of the plastic packaging layer is epoxy resin.

9. The chip according to claim 6, characterized in that: The electronic packaging substrate is a copper-clad ceramic substrate.

10. An electronic device, characterized in that: Comprising a chip as described in any one of claims 6-9.

Images