Die yield assessment based on pattern-failure rate simulation

Abstract

The present application discloses a computing system to identify structures of an integrated circuit that can be manufactured using a lithographic mask described by mask layout data, and to generate a process window for the identified structure based at least in part on the mask layout data and a failure definition for the identified structure. The computing system uses the process window for the identified structure to determine a failure rate for the identified structure based on a distribution of manufacturing parameters. The computing system determines a frequency of occurrence of the identified structure based on the mask layout data, and generates a die yield metric for the integrated circuit by aggregating the failure rate of the identified structure based on the frequency of occurrence of the identified structure in the integrated circuit. These increases in integrated circuit production enable manufacturers to produce more units per unit of fixed wafer processing cost.

Description

[0001] Related Applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 62 / 803,090, filed on February 8, 2019, which is incorporated herein by reference. Technical Field

[0003] The present application relates generally to electronic design automation, and more particularly to die yield assessment based on pattern-failure rate simulation. Background Art

[0004] In the design process for manufacturing integrated circuits, the physical design of the integrated circuit can describe specific geometric elements, which is often referred to as a "layout" design. Geometric elements (usually polygons) define shapes that are created with various materials to manufacture the integrated circuit. Typically, the designer will select multiple groups of geometric elements representing circuit device components (e.g., contacts, gates, etc.) and place them in the design area. These multiple groups of geometric elements can be custom designed, selected from a previously created design library, or some combination of the two. After placing the multiple groups of geometric elements representing the circuit device components, geometric elements representing connecting lines are placed between these geometric elements according to predetermined routes. These lines will form the wiring for interconnecting electronic devices.

[0005] Descriptions of circuit layouts can be provided in a variety of different formats. The Graphic Data System II (GDSII) format is a popular format for transmitting and archiving two-dimensional graphical circuit layout data. Among other features, it contains a hierarchical structure, each of which contains layout elements (e.g., polygons, paths or polylines, circles, and text boxes). Other formats include open source formats called Open Access, Milkyway, EDDM, and Open Artwork System Interchange Standard (OASIS). These different industry formats are used to define geometric information in layout designs for manufacturing integrated circuits. Once the design is complete, the layout portion of the design can be used by manufacturing tools to manufacture circuits using photolithography processes.

[0006] There are many different manufacturing processes to make circuits, but most processes include a series of steps of depositing layers of different materials on a substrate, exposing specific portions of each layer to radiation, and then etching away the exposed (or unexposed) portions of the layer. For example, a simple semiconductor device component can be made by the following steps. First, a positive epitaxial layer is grown on a silicon substrate by chemical vapor deposition. Next, a nitride layer is deposited on the epitaxial layer. Specific areas of the nitride layer are then exposed to radiation, and the exposed areas are etched away, leaving exposed areas on the epitaxial layer (i.e., areas no longer covered by the nitride layer). The exposed areas are then subjected to a diffusion or ion implantation process so that dopants (e.g., phosphorus) enter the exposed epitaxial layer and form charged wells. This process of depositing material layers on a substrate or subsequent material layers, then exposing specific patterns to radiation, etching, and dopants or other diffused materials is repeated many times, allowing different physical layers of the circuit to be made.

[0007] Each time a material layer is exposed to radiation, a mask needs to be created to expose only the desired areas to the radiation and protect other areas from exposure. The mask is created based on the circuit layout data. That is, the geometric elements described in the layout design define the relative positions or relative areas of the circuit that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create a mask based on the layout design, which can then be used in the photolithography process.

[0008] As designers and manufacturers continue to increase the number of circuit components in a given area and / or reduce the size of circuit components, the shapes reproduced on the substrate (and therefore in the mask) become smaller and more closely spaced together. This reduction in feature size increases the difficulty of accurately reproducing the image intended by the layout design on the substrate. The diffraction effects of light often result in defects in the intended image not being accurately printed onto the substrate during the photolithography process, thereby producing defects in the manufactured device. One or more resolution enhancement techniques (RETs) are often used to improve the resolution of the image formed by the mask on the substrate during the photolithography process.

[0009] One of these techniques, "optical proximity correction" or "optical process correction" (OPC), adjusts the amplitude of light transmitted through a lithography mask by modifying the mask layout design data used to create the mask. For example, margins in the mask layout design can be adjusted to make certain portions of a geometric element larger or smaller, depending on how much extra exposure (or lack of exposure) is needed at certain points on the substrate. When these adjustments are properly calibrated, overall pattern fidelity can be improved.

[0010] During the manufacturing process, semiconductor manufacturers may use photolithography masks created based on mask layout design data to manufacture integrated circuits. However, the manufacturing process used by the semiconductor manufacturer may have parameters that change during the manufacturing process of the integrated circuit, such as exposure dose and focus depth of the transmitted light through the photolithography mask, which may change the size and / or shape of some integrated circuit structures. In some examples, such as when the structure exceeds the error tolerance of a critical critical dimension of the integrated circuit, these changes in size and / or shape may cause defects in the integrated circuit.

[0011] To address these defects based on manufacturing variability, designers and manufacturers use intuition or experience to identify structures that may have a lithographic response to changes in dose and focus that can cause defects. The identified structures can then be tested empirically, for example, by repeatedly manufacturing the identified structures with different combinations of dose and focus and measuring the dimensions of the resulting structures. These empirical tests can identify which combinations of dose and focus will allow the manufacture of defect-free structures.

[0012] As feature size reduction increases, the number of structures affected by manufacturing variability also increases, making it impractical to empirically test the increasing number of structures. Many designers and manufacturers have instead turned to validation of photolithography mask design data generated by optical proximity correction tools to perform empirical testing by utilizing simulation to identify a reduced set of problematic structures or hot spots in the integrated circuit.

[0013] Designers and manufacturers typically use the results of empirical testing to subjectively determine whether the defect risk of a structure is low enough for integrated circuit manufacturing or whether to redesign the structure. Some designers and manufacturers have attempted to quantify defect risk, for example, by performing Monte Carlo simulations using various combinations of dose and focus, but this is a time-consuming and resource-intensive process given the number of Monte Carlo simulations performed for each structure and the number of structures to be analyzed in an integrated circuit. Summary of the invention

[0014] The present application discloses a computing system to identify structures of integrated circuits that can be manufactured using photolithography masks described by mask layout data, and to generate a process window for the identified structure based at least in part on the mask layout data and the failure definition of the identified structure. The computing system can determine the failure rate of the identified structure based on the distribution of manufacturing parameters using the process window for the identified structure. The computing system can determine the frequency of occurrence of the identified structure based on the mask layout data, and generate a die yield metric for the integrated circuit by summarizing the failure rate of the identified structure based on the frequency of occurrence of the identified structure in the integrated circuit. The embodiments will be described in more detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 and Figure 2 An example of a computer system of the type that may be used to implement various embodiments is shown.

[0016] Figure 3 An example of an optical proximity correction (OPC) verification tool that implements die yield assessment according to various embodiments is shown.

[0017] Figure 4 Example target wafer images and corresponding process windows for integrated circuit structures in the target wafer images are shown according to various embodiments.

[0018] Figure 5 An example process window with manufacturing variability distribution for an integrated circuit structure according to various embodiments is shown.

[0019] Figures 6A to 6D Example process windows with manufacturing variability distributions for integrated circuit structures according to various examples are shown.

[0020] Figure 7 A flow chart showing an example of die yield assessment utilizing an optical proximity correction (OPC) verification tool according to various examples is shown. DETAILED DESCRIPTION

[0021] Various examples may be implemented by executing software instructions by a computing device 101 (e.g., a programmable computer). Figure 1 An illustrative example of a computing device 101 is shown. As can be seen from the figure, computing device 101 includes a computing unit 103 having a processor unit 105 and a system memory 107. Processor unit 105 can be any type of programmable electronic device for executing software instructions, but will typically be a microprocessor. System memory 107 can include read-only memory (ROM) 109 and random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both read-only memory (ROM) 109 and random access memory (RAM) 111 can store software instructions for execution by processor unit 105.

[0022] The processor unit 105 and the system memory 107 are directly or indirectly connected to one or more peripheral devices 115-123 via the bus 113 or an alternative communication structure. For example, the processor unit 105 or the system memory 107 can be directly or indirectly connected to one or more additional storage devices, such as a hard disk drive 117 (which can be magnetic and / or removable), a removable optical drive 119, and / or a flash memory card. The processor unit 105 and the system memory 107 can also be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input device 121 can include, for example, a keyboard, a pointing device (such as a mouse, a touchpad, a stylus, a trackball, or a joystick), a scanner, a camera, and a microphone. The output device 123 can include, for example, a monitor display, a printer, and a speaker. For various examples of the computing device 101, one or more of the peripheral devices 115-123 can be housed internally with the computing unit 103. Alternatively, one or more of peripheral devices 115 - 123 may be external to the housing of computing unit 103 and connected to bus 113 via, for example, a universal serial bus (USB) connection.

[0023] In some implementations, the computing unit 103 may be directly or indirectly connected to a network interface 115 for communicating with other devices constituting the network. The network interface 115 may convert data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the Transmission Control Protocol (TCP) and the Internet Protocol (IP). In addition, the network interface 115 may employ any suitable connection agent (or combination of agents) to connect to the network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art and therefore will not be discussed in more detail here.

[0024] It should be understood that computing device 101 is shown as an example only and is not intended to be limiting. Various embodiments may be implemented using one or more computing devices, including Figure 1 The components of computing device 101 shown include only Figure 1 A subset of the components shown, or it includes components (including those not shown Figure 1 For example, various embodiments may be implemented using a multi-processor computer, multiple single-processor computers arranged in a network, and / or multiple multi-processor computers arranged in a network, or some combination of the two.

[0025] In some implementations, processor unit 105 may have more than one processor core. Figure 2An example of a multi-core processor unit 105 that can be used with various embodiments is shown. As can be seen in the figure, the processor unit 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B, respectively, and a memory cache 205A and 205B, respectively. As known to those of ordinary skill in the art, the computing engines 203A and 203B may include logic devices for performing various computing functions, such as obtaining software instructions and then performing the operations specified in the instructions obtained. These operations may include, for example, adding, subtracting, multiplying and comparing numbers, performing logical operations, such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203A and 203B may then use its corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and / or instructions for execution.

[0026] Each processor core 201A and 201B is connected to an interconnect 207. The specific configuration of interconnect 207 may vary depending on the architecture of processor unit 105. For some processor cores 201A and 201B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation, and IBM Corporation, interconnect 207 may be implemented as an interconnect bus. However, for other processor units 201A and 201B, such as the Opteron XT microprocessor available from Advanced Micro Devices of Sunnyvale, California, interconnect 207 may be implemented as an interconnect bus. TM and Athlon TM In a dual-core processor, interconnect 207 may be implemented as a system request interface device. In any case, processor cores 201A and 201B communicate with input / output interface 209 and memory controller 210 via interconnect 207. Input / output interface 209 provides a communication interface to bus 113. Similarly, memory controller 210 controls information exchange with system memory 107. In some implementations, processor unit 105 may include additional components, such as an advanced cache memory that may be shared by processor cores 201A and 201B. It should also be understood that Figure 1 and Figure 2 The depiction of a computer network is provided by way of example only and is not intended to imply any limitation as to the scope of use or functionality of alternative embodiments.

[0027] Die yield assessment based on pattern-failure rate simulation

[0028] Figure 3 An example of an optical proximity correction (OPC) verification tool 300 that implements die yield assessment according to various embodiments is shown. Figure 3, the OPC verification tool 300 can receive a mask design layout 301 describing a lithography mask having a pattern that allows portions of a material layer to be exposed to light during a lithography process used to manufacture an integrated circuit. The lithography mask can be generated from the mask design layout 301, for example using a reticle writing tool, and the lithography mask can manufacture a target wafer image corresponding to a layout design of an integrated circuit. The layout design can define geometric information that can be used to manufacture the integrated circuit, which can be specified in a Graphic Data System II (GDSII) format, an open access format, a Milkyway format, an EDDM format, an Open Artifact System Interaction Standard (OASIS) format, etc. In some embodiments, the mask design layout 301 can have been subjected to optical proximity correction, which can adjust the mask design layout 301 to change the amplitude of transmitted light through the mask generated according to the mask design layout 301 and increase the overall pattern fidelity printed on the integrated circuit.

[0029] The OPC verification tool 300 may receive a process model 302, which may describe a manufacturing process used by a semiconductor manufacturer to manufacture an integrated circuit corresponding to a circuit design layout. The process model 302 may identify a critical dimension (CD) used for the manufacturing process and a type of operation performed to manufacture the integrated circuit. The process model 302 may also identify a factory value of a manufacturing parameter, such as a light focus, an exposure dose, or an exposure duration during a photolithography process.

[0030] The OPC verification tool 300 may receive a failure definition 303 that describes a manufacturing variability that causes a portion of an integrated circuit to fail. The failure definition 303 may identify an error tolerance of a manufactured structure or feature compared to a critical dimension, for example, the error tolerance may be expressed as a positive or negative percentage of the critical dimension. When a structure or feature is manufactured at a size that exceeds the error tolerance of the critical dimension, the manufactured structure or feature may be considered to have failed. In some embodiments, the failure definition 303 may identify a state that would also constitute a failure, for example, a squeeze state, a bridge state, etc. The failure definition 303 may also include a target wafer image corresponding to a circuit design layout of the integrated circuit.

[0031] The OPC verification tool 300 may receive a parameter distribution 304 to identify which manufacturing parameters may vary during the manufacturing process of the integrated circuit, such as light focus, exposure dose or exposure time period during the photolithography process, critical dimension mask error, random effects, etc. The parameter distribution 304 may also identify the distribution type of the manufacturing parameters during the manufacturing process and define how the manufacturing parameters vary in the distribution. For example, when the manufacturing parameters vary according to a Gaussian distribution, the parameter distribution 304 may include a mean value and a standard deviation for each manufacturing parameter.

[0032] The OPC verification tool 300 may include a pre-classification system 310 for identifying patterns in the mask layout data 301 that have a higher risk of forming a failed structure in the integrated circuit due to changes in manufacturing parameters during the manufacturing process. These identified patterns in the mask layout data 301 may correspond to candidate "hot spots" to be studied. In some embodiments, the pre-classification system 310 may simulate the manufacture of the integrated circuit based on the mask layout data 301 to identify which patterns in the mask layout data 301 correspond to hot spots. For example, the pre-classification system 310 may compare the simulated integrated circuit with the target wafer image, and determine the deviation of the simulated integrated circuit from the target wafer image based on the comparison. When the deviation between the simulated integrated circuit and the target wafer image exceeds a predetermined threshold, the pre-classification system 310 may identify the simulated integrated circuit and the portion corresponding to the deviation in the mask design layout 301 as a hot spot. The pre-classification system 310 may also perform a pattern matching operation on the mask layout data 301 to identify candidate hot spots based on previously known hot spot patterns.

[0033] The OPC verification tool 300 may include a process window system 320 for generating a process window for one or more patterns identified as corresponding to hot spots in the mask design layout 301 based at least in part on the failure definition 303. The process window may correspond to a range of manufacturing parameter values ​​that allows a semiconductor manufacturer to manufacture failure-free structures using the pattern. In some embodiments, the process window system 320 may simulate the manufacture of structures associated with the hot spots identified according to the mask design layout 301, for example, using different manufacturing parameter values ​​for simulation. The process window system 320 may identify those manufacturing parameter values ​​that do not cause structural failure based on the failure definition 303. For example, when the failure definition 303 specifies an error tolerance of + / - 10% with respect to a critical dimension of 90nm, the process window system 320 may determine manufacturing parameter values ​​for simulating structures having a width between 81nm and 99nm. Reference will be made to Figure 4 Embodiments of process window generation are described.

[0034] Figure 4 An example target wafer image 410 and a corresponding process window 430 for an integrated circuit structure are shown in accordance with various embodiments. Figure 4 , target wafer image 410 may correspond to a structure, such as structure 411, manufactured from at least one lithography mask in a lithography process. The lithography process may include exposing a layer of material disposed on a substrate using a pattern defined by a lithography mask to form the structure of an integrated circuit. Due to manufacturing variability in the lithography process, such as variations in exposure focus and / or exposure dose, the structure manufactured on the substrate may be different from target wafer image 410.

[0035] In this example, the structure 411 can be characterized for different combinations of manufacturing parameters (e.g., dose and focus) to determine a lithographic response 420 for potential manufacturing variability. The lithographic response 420 can be represented as a set of curves (e.g., Poisson curves) in an image having an x-axis corresponding to changes in focus 422 and a y-axis corresponding to changes in a resulting line width 421 of the structure 411. Each curve can correspond to a different dose provided during the characterization process. In some embodiments, the lithographic response 420 can be determined by simulation using design data for a lithographic mask used to manufacture the target wafer image 410.

[0036] The lithographic response 420 for various combinations of dose and focus 422 can be used to generate a process window 430 for the structure 422. The process window 430 can correspond to a combination of dose 431 and focus 432 that will allow the fabrication of the structure 411 having a range of line widths that are considered defect-free. In some embodiments, an integrated circuit can have a critical dimension (CD) corresponding to an idealized width of its structures, and have an acceptable error tolerance to determine a range of line widths about the critical dimension that will keep the fabricated structures defect-free. The process window 430 can correspond to a combination of dose and focus from the lithographic response 420 that will fabricate the structure 411 having a line width that is within the acceptable error tolerance of the critical dimension.

[0037] Return to reference Figure 3, the OPC verification tool 300 may include a failure prediction system 330 for generating a failure presentation 305 having one or more failure metrics and / or die yield metrics associated with the mask design layout 301. The failure prediction system 330 may determine a failure rate on a per-structure or per-feature basis, and then utilize the feature failure rates, for example, based in part on the frequency of features or structures in the mask design layout 301, to determine an overall chip failure rate or die yield metric. In some embodiments, the failure prediction system 330 may provide the pre-classification system 310 with a failure rate per feature, which may allow the pre-classification system 310 to select a subset of hotspot structures to include in the hotspot report 306. For example, the pre-classification system 310 may exclude previously identified hotspots from the conclusions of the hotspot report 306 when the failure rate of a feature is below a preset threshold failure level. Since semiconductor manufacturers can perform metrology on the hot spot structures included in the failure presentation 305, such as bright field inspection (BFI) metrology, scanning electron microscope (SEM) metrology, etc., reducing the number of hot spot structures in the failure presentation 305 can allow semiconductor manufacturers to reduce metrology and overall turnaround time.

[0038] The failure prediction system 330 may include a feature failure unit 332 for determining a feature failure rate on a per-structure basis or on a per-feature basis based on the process window 503 for the structure or feature and the parameter distribution 304. Figure 5 An embodiment of a characteristic failure rate is described below.

[0039] refer to Figure 3 and Figure 5 The feature failure unit 332 can identify which manufacturing parameters will change during the manufacturing process of the integrated circuit based on the parameter distribution 304, such as the light focus, exposure dose, critical dimension mask error, random effects, etc. during the photolithography process. Figure 5 In the example shown, the fabrication parameters may be dose 501 and focus 502 , and the process window 503 may correspond to a combination of dose 501 and focus 502 that will allow fabrication of structures or features having a range of line widths that are considered defect-free based on the failure definition 303 .

[0040] The feature failure unit 332 can generate a manufacturing variability distribution 504 (e.g., a probability density function) of the manufacturing parameters based on the parameter distribution 304. For example, when the parameter distribution 304 specifies the variability of two manufacturing parameters - dose and focus - as Gaussian, the feature failure unit 332 can generate a two-dimensional probability density function with a Gaussian distribution based on the variability described in the parameter distribution 304. In some embodiments, the parameter distribution 304 can include an average value or mean and a standard deviation of the manufacturing parameters.

[0041] Feature failure unit 332 may determine a feature failure rate for a feature in an integrated circuit based on manufacturing variability distribution 504 and process window 503 for the feature. In some embodiments, feature failure unit 332 may determine the feature failure rate using Equation 1:

[0042] p fail =1-∮< 工艺窗口 PDF 2D (E,F)dEdF (1)

[0043] In Equation 1, the characteristic failure probability p fail The probability of a feature not failing due to manufacturing parameter variability can be determined by calculating the manufacturing variability distribution PDF for the range of manufacturing parameters - dose E and focus F - based on the process window 503 for the feature. 2D The two-dimensional probability density function of is integrated to find .

[0044] refer to Figure 3 , the failure prediction system 330 may include a yield prediction unit 334 for determining a die yield metric of an integrated circuit that can be manufactured according to the mask design layout 301. The yield prediction unit 334 may determine the die yield metric using characteristic failure rates of different types of structures and the frequencies of these structures in the integrated circuit. For example, the yield prediction unit 334 may determine the die yield using a Poisson model as shown in Equation 2:

[0045] DY=e -AD0 (2)

[0046] In Equation 2, the die yield metric DY may be equal to an exponential function having a value corresponding to the die area A and the average defect density D in the integrated circuit. 0 The average defect density D of the integrated circuit is the negative exponential of the product of 0 It may be equal to the sum of the defect densities of the individual features in the integrated circuit. A single feature defect density may be equal to the product of the feature failure rate determined by the feature failure unit 332 and the frequency of the feature in the integrated circuit.

[0047] The yield prediction unit 334 may determine the frequency of each feature to be manufactured in the integrated circuit, for example, by analyzing the mask design layout 301 for the integrated circuit or the target wafer image. The yield prediction unit 334 may determine the die yield metric DY using the frequency of each feature to be manufactured in the integrated circuit and the feature failure rate determined by the feature failure unit 332.

[0048] In some embodiments, the failure prediction system 330 can provide the failure presentation 305 to the design system, or the failure prediction system 330 is implemented in a design system for generating the mask design layout 301 or the layout design of the integrated circuit. The failure presentation 305 can include characteristic failure rates and / or die yield metrics, which can inform the design system about the potential impact of design features on die yield or failure rate. The design system can utilize the characteristic failure rates and / or die yield metrics in the failure presentation 305 in modifying the layout design of the integrated circuit or modifying the mask design layout 301.

[0049] The OPC verification tool 300 may include a parameter setting system 340 for determining which values ​​of manufacturing parameters (e.g., dose and focus) the semiconductor manufacturer should set based on the die yield metric. In some embodiments, the parameter setting system 340 may determine the die yield metric for multiple different combinations of manufacturing parameter values, and then select one of the manufacturing parameter value combinations for the semiconductor manufacturer to set for the manufacturing process, for example, the manufacturing parameter value combination that provides the highest die yield or the lowest chip failure rate. Figures 6A to 6D Embodiments are described for setting foundry values ​​for manufacturing parameters based on die yield metrics.

[0050] refer to Figures 6A to 6C , a graph shows a plurality of process windows 603A-603C associated with different structures that can be fabricated in a lithography process. The process windows 603A-603C may correspond to combinations of manufacturing parameters - dose 601 and focus 602 - that will allow fabrication of structures having a range of line widths that are considered defect-free based on a failure definition. The graph may also include a manufacturing variability distribution 604 (e.g., a probability density function) of the manufacturing parameters, which may be centered around a set combined value of dose 601 and focus 602.

[0051] refer to Fig.6D, a graph showing overlapping combinations of process windows 603A to 603C associated with structures that can be manufactured in a lithography process. The OPC verification tool can utilize die yield metric generation techniques to determine a factory value 605 that corresponds to a combination of settings for dose 601 and focus 602 to be used in the manufacture of structures associated with process windows 603A to 603C. For example, the OPC verification tool can determine die yield metrics for multiple different combinations of dose 601 and focus 602 values ​​that center the manufacturing variability distribution 604. The combination of dose 601 and focus 602 that corresponds to the highest yield or lowest failure rate for multiple die yield metrics can be selected as the factory value 605.

[0052] When structures corresponding to process windows 603A to 603C appear in the integrated circuit with the same frequency, the factory value 605 can be positioned toward the center of the overlapping portion of process windows 603A to 603C. However, when the structures have a non-uniform distribution, the OPC verification tool can set the factory value 605 to be more biased toward the more frequent structures. In this example, the factory value 605 has its focus moved to the right due to the higher frequency of the structure associated with process window 603B relative to the structures associated with process windows 603A and 603C.

[0053] Return to reference Figure 3 , the values ​​set by parameter setting system 340 may be included in failure representation 305, which a semiconductor manufacturer may utilize to manufacture integrated circuits using mask design layout 301. In some embodiments, failure representation 305 may be utilized by automatic process control (APC) equipment during the manufacture of integrated circuits. APC equipment may dynamically compensate for process drift during the manufacturing process, for example, by adjusting exposure dose. APC equipment may receive failure representation 305, or include parameter setting functionality, to determine adjustments to dose or other manufacturing parameters that may be used to improve die yield.

[0054] The OPC verification tool 300 may include a fault tolerance system 350 to determine an error tolerance for a critical dimension based on the die yield metric determined by the yield prediction unit 334. In determining the die yield metric, the failure definition includes a critical dimension error tolerance to determine the amount of deviation from the critical dimension that the semiconductor manufacturer will allow and still consider the structure to be defect-free. The fault tolerance system 350 may vary the critical dimension error tolerance and determine multiple different die yield metrics for each critical dimension error tolerance, rather than having a static critical dimension error tolerance. The fault tolerance system 350 may determine an allowable variation of a manufacturing parameter (e.g., dose and focus) for each different critical dimension error tolerance based on the die yield metric. The fault tolerance system 350 may include critical dimension error tolerances for manufacturing parameters and allowable variations of manufacturing parameters associated therewith within the failure presentation 305, which may allow the semiconductor manufacturer to set critical dimension error tolerances based at least in part on how much these error tolerances will allow the manufacturing parameters to vary during the manufacturing process.

[0055] Figure 7 A flow chart showing an example of die yield assessment using an optical proximity correction (OPC) verification tool according to various examples is shown. Figure 7 In block 701, a computing system implementing an OPC verification tool may identify structures of an integrated circuit that can be manufactured using a lithography mask described by mask layout data. The OPC verification tool may identify patterns in the mask layout data that have a higher risk of forming a failed structure in the integrated circuit due to changes in manufacturing parameters during the manufacturing process. These patterns in the identified mask layout data may correspond to candidate "hot spot" structures to be studied. In some embodiments, the OPC verification tool may simulate the manufacture of the integrated circuit based on the mask layout data to identify which patterns in the mask layout data correspond to hot spot structures. The OPC verification tool may also perform pattern matching operations on the mask layout data to identify candidate hot spots based on previously known hot spot patterns.

[0056] In block 702, a computing system implementing an OPC verification tool may generate a process window for the identified structure based on the mask layout data and the failure definition of the identified structure. The process window may correspond to a range of values ​​of manufacturing parameters (e.g., dose and focus) that will allow a semiconductor manufacturer to manufacture a failure-free structure with the pattern. In some embodiments, the OPC verification tool may simulate the manufacture of structures associated with the hot spot structures identified according to the mask design layout, for example, using different manufacturing parameter values ​​for simulation. The OPC verification tool may identify those manufacturing parameter values ​​that do not cause structural failure based on a failure definition that specifies an acceptable error tolerance of the manufacturing parameter relative to a critical dimension of the integrated circuit.

[0057] In block 703, a computing system implementing an OPC verification tool may determine a failure rate for the identified structure based on a process window and a distribution of manufacturing parameters. The OPC verification tool may generate a manufacturing variability distribution (e.g., a probability density function) for the manufacturing parameters based on the distribution of the manufacturing parameters. For example, when two manufacturing parameters - dose and focus - change during the manufacturing process of an integrated circuit, the OPC verification tool may generate a two-dimensional probability density function based on the distribution of the manufacturing parameters. In some embodiments, the distribution of the manufacturing parameters may include an average value or mean and a standard deviation of the manufacturing parameters. The OPC verification tool may determine the failure rate by applying the manufacturing variability distribution to the process window of the identified structure (e.g., integrating the probability density function over an area defined by the process window of the identified structure).

[0058] In block 704, a computing system implementing the OPC verification tool may determine a frequency of occurrence of the identified structure in the integrated circuit. The OPC verification tool may determine the frequency of each structure to be fabricated in the integrated circuit, for example, by analyzing mask layout data or a target wafer image for the integrated circuit. The frequency of each structure may correspond to a plurality of patterns of the mask layout data corresponding to the structure per unit area (e.g., specified as square centimeters) of the integrated circuit.

[0059] In block 705, a computing system implementing an OPC verification tool may generate a die yield metric for an integrated circuit based on the failure rate and frequency of occurrence of the identified structures. The OPC verification tool may determine the die yield metric using the failure rates of different types of structures and the frequencies of these structures in the integrated circuit. In some embodiments, the die yield metric may be equal to an exponential function having an exponent corresponding to the negative of the product of the die area in the integrated circuit and the average defect density in the integrated circuit. The average defect density of the integrated circuit may be equal to the sum of the defect densities of the individual features in the integrated circuit. A single feature defect density may be equal to the product of the feature failure rate and the frequency of the feature in the integrated circuit.

[0060] The above-described systems and apparatus may use a dedicated processor system, a microcontroller, a programmable logic device, a microprocessor, or any combination thereof to perform some or all of the operations described herein. Some of the operations described above may be implemented in software, and other operations may be implemented in hardware. Any operations, processes, and / or methods described herein may be performed by an apparatus, device, and / or system substantially similar to those described herein and to the accompanying drawings illustrated with reference thereto.

[0061] The processing device may execute instructions or "code" stored in the memory. The memory may also store data. The processing device may include, but is not limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interact with a networked system locally or remotely via wireless transmission.

[0062] The processor memory can be integrated with the processing device (e.g., RAM or FLASH memory provided within an integrated circuit microprocessor, etc.). In other examples, the memory may include independent devices, such as external disk drives, memory arrays, portable FLASH key cards, etc. The memory and the processing device may be operably coupled together, or communicate with each other, such as through I / O ports, network connections, etc., and the processing device can read files stored on the memory. By setting permissions, the relevant memory may be designed as "read-only" (ROM) or not. Other examples of memory may include, but are not limited to, WORM, EPROM, EEPROM, FLASH, etc., which may be implemented in solid-state semiconductor devices. Other memories may include moving parts, such as known rotating disk drives. All such memories may be "machine-readable" and readable by the processing device.

[0063] The operating instructions or commands may be implemented or embodied in a tangible form of stored computer software (also referred to as a "computer program" or "code"). The program, or code, may be stored in a digital memory and may be read by a processing device. "Computer-readable storage media" (or alternatively, "machine-readable storage media") may include all of the above types of memory as well as new technologies of the future, as long as the memory may be able to store digital information having the properties of a computer program or other data at least temporarily, and as long as the stored information may be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, minicomputer, desktop, or even laptop computer. Instead, "computer-readable" may include storage media that can be read by a processor, a processing device, or any computing system. Such media may be any available media that can be accessed locally and / or remotely by a computer or processor, and may include volatile media and non-volatile media, as well as removable media and non-removable media, or any combination thereof.

[0064] Programs stored in computer-readable storage media may include computer program products. For example, storage media may be used as a convenient means for storing or transmitting computer programs. For convenience, operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be situations where these functional blocks or diagrams may be equivalently integrated into a single logical device, program or operation with unclear boundaries.

[0065] in conclusion

[0066] Although this application describes specific examples of implementing embodiments of the present disclosure, those skilled in the art will appreciate that there are many variations and permutations of the above systems and techniques that fall within the spirit and scope of the present disclosure as described in the appended claims. For example, although specific terms have been used above to refer to electronic design automation processes, it should be understood that any desired combination of electronic design automation processes may be used to implement various examples of the present disclosure.

[0067] Those skilled in the art will also recognize that the concepts taught herein can be adapted to specific applications in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are only one of a number of alternative implementations that will become apparent after reading this disclosure.

[0068] Although the specification may refer to "one", "another", or "some" examples in multiple places, this does not necessarily mean that each such reference is to the same example or examples, or that the feature applies to only a single example.

Claims

1. A method for evaluating die yield, comprising: identifying, by a computing system, structures of an integrated circuit that can be fabricated using photolithography masks described by the mask layout data; The failure rate of the identified structure is determined by the computing system in the following manner: generating a process window for the identified structure based at least in part on a lithographic response of the mask layout data and a failure definition for the integrated circuit, wherein the failure definition describes manufacturing variability that causes failure of a portion of the integrated circuit and includes identifying conditions that will constitute a failure or includes a target wafer image corresponding to a circuit design layout of the integrated circuit; as well as integrating a distribution of a manufacturing parameter during the manufacturing process over the process window for the identified structure; determining, by the computing system, a frequency of occurrence of the identified structure in the integrated circuit based on the mask layout data; as well as A die yield metric is generated, by the computing system, for the integrated circuit based at least in part on the failure rate of the identified structure and a frequency of occurrence of the identified structure in the integrated circuit.

2. The method according to claim 1, further comprising: A probability density function corresponding to the distribution of the manufacturing parameter in a manufacturing process is applied, by the computing system, to the process window of the identified structure to generate the failure rate of the identified structure.

3. The method according to claim 1, wherein: Generating the die yield metric for the integrated circuit further includes aggregating the failure rates of the identified structures based at least in part on the frequencies of occurrence of the identified structures in the integrated circuit.

4. The method according to claim 1, further comprising: A value for the manufacturing parameter used in manufacturing the integrated circuit is set by the computing system based at least in part on the die yield metric for the integrated circuit. 5 . The method of claim 1 , further comprising predicting, by the computing system, an error margin from a critical dimension of the structure in the integrated circuit based at least in part on the die yield metric.

6. The method according to claim 1, wherein: The manufacturing parameters correspond to a focus of light exposed onto the integrated circuit through the photolithography mask and an exposure dose of the light.

7. A system for die yield assessment, comprising: a storage device configured to store machine-readable instructions; and A computing system comprising one or more processing devices, the one or more processing devices being configured, in response to executing the machine-readable instructions, to: identifying structures of integrated circuits that can be fabricated using photolithography masks described by the mask layout data; The failure rate of the identified structure is determined by: generating a process window for the identified structure based at least in part on a lithographic response of the mask layout data and a failure definition for the integrated circuit, wherein the failure definition describes manufacturing variability that causes failure of a portion of the integrated circuit and includes identifying conditions that will constitute a failure or includes a target wafer image corresponding to a circuit design layout of the integrated circuit; as well as integrating a distribution of a manufacturing parameter during the manufacturing process over the process window for the identified structure; determining a frequency of occurrence of the identified structure in the integrated circuit based on the mask layout data; as well as A die yield metric for the integrated circuit is generated based at least in part on the failure rate of the identified structure and a frequency of occurrence of the identified structure in the integrated circuit.

8. The system according to claim 7, wherein: The one or more processing devices, in response to executing the machine-readable instructions, are configured to apply a probability density function corresponding to the distribution of the manufacturing parameter in a manufacturing process to the process window of the identified structure to generate the failure rate of the identified structure.

9. The system according to claim 7, wherein: The one or more processing devices, in response to executing the machine-readable instructions, are configured to generate the die yield metric for the integrated circuit by aggregating the failure rates of the identified structures based at least in part on the frequencies of occurrence of the identified structures in the integrated circuit.

10. The system according to claim 7, wherein: The one or more processing devices, in response to executing the machine-readable instructions, are configured to set a value for the manufacturing parameter used in a manufacturing process of the integrated circuit based at least in part on the die yield metric for the integrated circuit.

11. The system according to claim 7, wherein: The one or more processing devices, in response to executing the machine-readable instructions, are configured to predict an error margin from a critical dimension of the structure in the integrated circuit based at least in part on the die yield metric.

12. An apparatus comprising a storage device storing instructions, the instructions being configured to cause one or more processing devices to perform operations comprising: identifying structures of integrated circuits that can be fabricated using photolithography masks described by the mask layout data; The failure rate of the identified structure is determined by: generating a process window for the identified structure based at least in part on a lithographic response of the mask layout data and a failure definition for the integrated circuit, wherein the failure definition describes manufacturing variability that causes failure of a portion of the integrated circuit and includes identifying conditions that will constitute a failure or includes a target wafer image corresponding to a circuit design layout of the integrated circuit; as well as integrating a distribution of a manufacturing parameter during the manufacturing process over the process window for the identified structure; determining a frequency of occurrence of the identified structure in the integrated circuit based on the mask layout data; as well as A die yield metric for the integrated circuit is generated based at least in part on the failure rate of the identified structure and a frequency of occurrence of the identified structure in the integrated circuit.

13. The device according to claim 12, wherein: The instructions are configured to cause one or more processing devices to perform operations, the operations also including: applying a probability density function corresponding to the distribution of the manufacturing parameters in a manufacturing process to the process window of the identified structure to generate the failure rate of the identified structure.

14. The device according to claim 12, wherein: Generating the die yield metric for the integrated circuit further includes aggregating the failure rates of the identified structures based at least in part on the frequencies of occurrence of the identified structures in the integrated circuit.

15. The device according to claim 12, wherein: The instructions are configured to cause one or more processing devices to perform operations further comprising setting a value for the manufacturing parameter used in a manufacturing process of the integrated circuit based at least in part on the die yield metric for the integrated circuit.

16. The device according to claim 12, wherein: The instructions are configured to cause one or more processing devices to perform operations further comprising predicting an error margin from a critical dimension of the structure in the integrated circuit based at least in part on the die yield metric.

17. The device according to claim 12, wherein: The manufacturing parameters correspond to a focus of light exposed onto the integrated circuit through the photolithography mask and an exposure dose of the light.

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