Semiconductor devices

Abstract

The semiconductor device comprises a semiconductor portion, a first electrode on the back side of the semiconductor portion, a second electrode on the surface side, and a control electrode between the semiconductor portion and the second electrode. The second electrode comprises a first contact portion extending in the semiconductor portion and a second contact portion in contact with the surface of the semiconductor portion. The semiconductor portion comprises a first layer of a first conductivity type, a second layer of a second conductivity type, and a third layer of a first conductivity type. The second layer is arranged between the first layer and the second electrode. The third layer is arranged between the second layer and the second electrode, and is in contact with the first contact portion and the second contact portion. The first contact portion has a first width in the second direction and a second width in the second direction at a first position and a second position arranged in a first direction, respectively, the first position is located between the first electrode and the second position, the first width is wider than the second width, the first direction is from the first electrode toward the second electrode, and the second direction is from the control electrode toward the first contact portion along the surface of the semiconductor portion.

Description

[0001] This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-46499 (filing date: March 17, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments relate to a semiconductor device. Background Art

[0003] Power semiconductor devices are required to have reduced on-resistance. Summary of the invention

[0004] Embodiments provide a semiconductor device having reduced on-resistance.

[0005] A semiconductor device according to an embodiment of the present invention comprises a semiconductor portion, a first electrode provided on the back side of the semiconductor portion, a second electrode provided on the front side of the semiconductor portion, and a control electrode provided between the semiconductor portion and the second electrode. The second electrode comprises a first contact portion extending in the semiconductor portion and a second contact portion in contact with the front side of the semiconductor portion. The control electrode is arranged inside a groove provided in the semiconductor portion, is electrically insulated from the semiconductor portion by a first insulating film, and is electrically insulated from the second electrode by a second insulating film. The semiconductor portion comprises a first layer of a first conductivity type, a second layer of a second conductivity type, and a third layer of the first conductivity type. The first layer extends between the first electrode and the second electrode, and the groove has a depth from the front side of the semiconductor portion to the first layer. The second layer is provided between the first layer and the second electrode, and faces the control electrode via the first insulating film. The first contact portion extends from the front side of the semiconductor portion into the second layer. The third layer is provided between the second layer and the second electrode, is in contact with the first insulating film, the first contact portion, and the second contact portion, and is electrically connected to the second electrode. The first contact portion has a first width in the second direction and a second width in the second direction at a first position and a second position arranged in the first direction, respectively, the first position is located between the first electrode and the second position, the first width is wider than the second width, the first direction is from the first electrode toward the second electrode, and the second direction is along the front side of the semiconductor portion from the control electrode toward the first contact portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment.

[0007] Figure 2It is a schematic cross-sectional view showing characteristics of a semiconductor device according to an embodiment.

[0008] Figure 3 (a)~ Figure 7 (b) is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment.

[0009] Figure 8 (a) and (b) are schematic cross-sectional views showing semiconductor devices according to modified examples of the embodiment.

[0010] Fig. 9 (a) and (b) are schematic cross-sectional views showing a semiconductor device according to another modified example of the embodiment.

[0011] Fig.10 (a) and (b) are schematic cross-sectional views showing semiconductor devices according to comparative examples. DETAILED DESCRIPTION

[0012] The following is a description of the embodiments with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and their detailed description is appropriately omitted, and the different parts are described. In addition, the accompanying drawings are schematic or conceptual drawings, and the relationship between the thickness and width of each part, the ratio of the dimensions between the parts, etc. are not necessarily the same as the actual situation. Moreover, even when representing the same part, there is a case where the mutual dimensions and ratios are represented differently according to the drawings.

[0013] In addition, the configuration and structure of each part are described using the X-axis, Y-axis, and Z-axis shown in each drawing. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X direction, Y direction, and Z direction, respectively. Also, sometimes the Z direction is set as the upper direction and the opposite direction is set as the lower direction for description.

[0014] Figure 1 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is, for example, a trench gate MOSFET.

[0015] like Figure 1 As shown, the semiconductor device 1 includes a semiconductor portion 10, a first electrode (hereinafter referred to as a drain electrode 20), a second electrode (hereinafter referred to as a source electrode 30), and a control electrode (hereinafter referred to as a gate electrode 40). The semiconductor portion 10 is, for example, silicon.

[0016] The drain electrode 20 is provided on the back surface side of the semiconductor portion 10. The drain electrode 20 is a metal layer containing aluminum, gold, or the like.

[0017] The source electrode 30 is provided on the front surface side of the semiconductor portion 10 . That is, the semiconductor portion 10 is provided between the drain electrode 20 and the source electrode 30 .

[0018] The source electrode 30 is a metal layer having a stacked structure including, for example, a first metal layer 31, a second metal layer 33, and a third metal layer 35. The first metal layer 31, the second metal layer 33, and the third metal layer 35 are stacked in this order on the front surface side of the semiconductor unit 10.

[0019] The first metal layer 31 includes, for example, titanium nitride (TiN) and is located between the semiconductor portion 10 and the second metal layer 33 .

[0020] The second metal layer 33 includes, for example, tungsten (W). The second metal layer 33 is located between the first metal layer 31 and the third metal layer 35 .

[0021] The third metal layer 35 includes, for example, aluminum (Al). The third metal layer 35 is provided to be thicker than the thickness obtained by adding the thickness of the first metal layer 31 and the thickness of the second metal layer 33, for example.

[0022] The source electrode 30 includes a first contact portion 30 P and the second contact portion 30 F The first contact portion 30 P The second contact portion 30 extends in the semiconductor portion 10. F It is in contact with the front surface of the semiconductor portion 10 exposed between adjacent interlayer insulating films 45 .

[0023] The gate electrode 40 is disposed between the semiconductor portion 10 and the source electrode 30, inside a gate trench GT provided in the semiconductor portion 10. The gate electrode 40 is electrically insulated from the semiconductor portion 10 by a first insulating film (hereinafter referred to as a gate insulating film 43). Furthermore, the gate electrode 40 is electrically insulated from the source electrode 30 by a second insulating film (hereinafter referred to as an interlayer insulating film 45).

[0024] The semiconductor portion 10 includes a first layer of a first conductivity type (hereinafter referred to as an n-type drift layer 11), a second layer of a second conductivity type (hereinafter referred to as a p-type diffusion layer 13), a third layer of a first conductivity type (hereinafter referred to as an n-type source layer 15), a fourth layer of a second conductivity type (hereinafter referred to as a p-type contact layer 17) and a fifth layer of a first conductivity type (hereinafter referred to as an n-type buffer layer 19).

[0025] The n-type drift layer 11 extends between the drain electrode 20 and the source electrode 30. The gate trench GT has a depth reaching the n-type drift layer 11 from the front surface of the semiconductor portion 10.

[0026] The p-type diffusion layer 13 is provided between the n-type drift layer 11 and the source electrode 30 , and faces the gate electrode 40 via the gate insulating film 43 .

[0027] The n-type source layer 15 is disposed between the p-type diffusion layer 13 and the source electrode 30. The n-type source layer 15 is located at the first contact portion 30P The n-type source layer 15 is disposed between the side surface of the gate insulating film 43 and the first contact portion 30. P and the second contact portion 30 F The n-type source layer 15 is electrically connected to the source electrode 30 . The n-type source layer 15 contains n-type impurities having a higher concentration than that of the n-type impurities of the n-type drift layer 11 .

[0028] The p-type contact layer 17 is selectively disposed between the p-type diffusion layer 13 and the source electrode 30. The p-type contact layer 17 is disposed between the p-type diffusion layer 13 and the first contact portion 30. P The p-type contact layer 17 is provided in the p-type diffusion layer 13 , for example. The p-type contact layer 17 contains a p-type impurity having a higher concentration than that of the p-type impurity in the p-type diffusion layer 13 .

[0029] The p-type contact layer 17 and the first contact portion 30 P The p-type diffusion layer 13 is in contact with the source electrode 30 and is electrically connected to the source electrode 30 . The p-type diffusion layer 13 is electrically connected to the source electrode 30 via the p-type contact layer 17 .

[0030] The n-type buffer layer 19 is provided between the n-type drift layer 11 and the drain electrode 20. The n-type buffer layer 19 contains n-type impurities having a higher concentration than the n-type impurities of the n-type drift layer 11. The drain electrode 20 is in contact with the n-type buffer layer 19 and is electrically connected to the n-type buffer layer 19, for example.

[0031] like Figure 1 As shown, the source electrode 30 is connected via the first contact portion 30 P and the second contact portion 30 F The source electrode 30 is electrically connected to the n-type source layer 15 via the first contact portion 30 P Electrically connected to the p-type contact layer 17 .

[0032] The p-type diffusion layer 13 has a convex region that bulges toward the n-type drift layer 11 between two adjacent gate electrodes 40 among the plurality of gate electrodes 40 arranged in the X direction. P and between convex regions.

[0033] First contact portion 30 P The first contact portion 30 is provided so as to expand in front end as extending from the source electrode 30 into the semiconductor portion 10. P In a first direction (hereinafter referred to as Z direction) from the drain electrode 20 toward the source electrode 30, for example, there is a first position P 1 and the second position P 2 Along the front surface of the semiconductor portion 10 from the gate electrode 40 toward the first contact portion 30 PIn the second direction (hereinafter referred to as the X direction), the first contact portion 30 P With the first position P 1 The first width W C1 and the second position P 2 The second width W C2 . First position P 1 Located at the drain electrode 20 and the second position P 2 The first width W C1 Than the second width W C2 Width.

[0034] P-type diffusion layer 13 includes a portion between p-type contact layer 17 and gate insulating film 43. P-type diffusion layer 13 has a width in the X direction narrower than the width of n-type source layer 15 in the X direction at the portion between p-type contact layer 17 and gate insulating film 43.

[0035] Second contact portion 30 F Located at the first contact portion 30 P The n-type source layer 15 is in contact with the front surface of the semiconductor portion 10 (the front surface of the n-type source layer 15 ) between the ends of the interlayer insulating film 45 in the X direction.

[0036] Figure 2 It is a schematic cross-sectional view showing the characteristics of the semiconductor device 1 according to the embodiment. Figure 2 Schematic diagram showing the distribution of n-type impurities in the n-type source layer 15 .

[0037] like Figure 2 As shown in FIG. 1 , the n-type impurity concentration in the n-type source layer 15 has a distribution that is highest at the front surface and decreases in the depth direction. Therefore, the first contact portion 30 in contact with the n-type source layer 15 P and the second contact portion 30 F The contact resistance of the second contact portion 30 in contact with the front surface of the n-type source layer 15 is different. F The contact resistance of the first contact portion 30 in contact with the side surface of the n-type source layer 15 is greater than that of the first contact portion 30 in contact with the side surface of the n-type source layer 15. P That is, the larger the second contact portion 30 is, the lower the contact resistance is. F The larger the area, the lower the contact resistance between the n-type source layer 15 and the source electrode 30 can be.

[0038] For example, for Fig.10 The semiconductor device E1 shown in (a) has a first contact portion 30 P The first position P is configured to be narrower as it extends toward the semiconductor portion 10. 1 The first width W in the X direction C1 Than the second position P 2 The second width W C2 narrow.

[0039] If the p-type contact layer 17 of the semiconductor device E1 is set to the same size as the p-type contact layer 17 of the semiconductor device 1, for example, the second contact portion 30 F The area ratio of the second contact portion 30 of the semiconductor device 1 is F Therefore, in the semiconductor device E1, the contact resistance between the n-type source layer 15 and the source electrode 30 increases, and the on-resistance increases.

[0040] In addition, for Fig.10 (b) shows a semiconductor device E2, wherein the first contact portion 30 P The semiconductor device E2 is also configured to be narrower as it extends into the semiconductor portion 10. Compared with the semiconductor device E1, the arrangement interval of the gate electrodes 40 in the X direction is increased, and the width W of the semiconductor portion 10 between adjacent gate electrodes 40 is increased. DM Thus, the second contact portion 30 can be enlarged. F The area of ​​the n-type source layer 15 is reduced, thereby reducing the contact resistance between the n-type source layer 15 and the source electrode 30.

[0041] However, by increasing the width W of the semiconductor portion 10 DM , the width W of the p-type contact layer 17 and the gate insulating film 43 PG Therefore, in the process of turning off the semiconductor device E2, the avalanche breakdown tolerance is reduced. That is, the discharge path of holes generated by the avalanche breakdown phenomenon caused by the electric field concentration at the lower end of the gate electrode 40 is extended, and the resistance to the hole current is increased. In addition, by increasing the width W of the semiconductor portion 10 DM , the density of the inversion trenches induced at the interface between the p-type diffusion layer 13 and the gate insulating film 43 decreases, and the trench resistance increases.

[0042] In contrast, in the semiconductor device 1, the first contact portion 30 is provided so as to expand toward the semiconductor portion 10. P The second contact portion 30 can be enlarged without reducing the avalanche breakdown withstand capacity and the trench density. F Thus, the on-resistance of the semiconductor device 1 can be reduced.

[0043] Below, refer to Figure 3 (a)~ Figure 7 (b) A method for manufacturing the semiconductor device 1 will be described. Figure 3 (a)~ Figure 7 (b) is a schematic cross-sectional view showing a manufacturing process of the semiconductor device 1 according to the embodiment.

[0044] like Figure 3As shown in (a), after forming the gate trench GT on the front surface FS side of the semiconductor wafer 100, the gate insulating film 43 is formed. The semiconductor wafer 100 is, for example, an n-type silicon wafer containing n-type impurities at the same concentration as that of the n-type drift layer 11.

[0045] The gate trench GT is formed by selectively etching the semiconductor wafer 100 using, for example, anisotropic RIE (Reactive Ion Etching). The gate insulating film 43 is, for example, a silicon oxide film formed by thermal oxidation. The gate insulating film 43 is formed to a thickness sufficient to leave a space SP inside the gate trench GT.

[0046] like Figure 3 As shown in (b), a conductive layer 40f is formed on the front surface FS side of the semiconductor wafer 100. The conductive layer 40f is, for example, polysilicon. The conductive layer 40f is formed to fill the space SP in the gate trench GT. The conductive layer 40f is formed, for example, using CVD (Chemical Vapor Deposition).

[0047] like Figure 4 As shown in (a), the conductive layer 40f is removed while the portion formed inside the gate trench GT is left. The conductive layer 40f is removed using, for example, isotropic dry etching. The portion remaining inside the gate trench GT becomes the gate electrode 40.

[0048] like Figure 4 As shown in (b), after the p-type diffusion layer 13 is formed on the front surface FS side of the semiconductor wafer 100, the n-type source layer 15 is formed.

[0049] The p-type diffusion layer 13 is formed by ion implanting p-type impurities such as boron (B) into the semiconductor wafer 100 and activating them by heat treatment. Furthermore, the p-type impurities are diffused by heat treatment to form the p-type diffusion layer 13. The p-type diffusion layer 13 is formed to face the gate electrode 40 via the gate insulating film 43.

[0050] The n-type source layer 15 is formed by ion implanting n-type impurities such as phosphorus (P) into the semiconductor wafer 100 and activating them by heat treatment. The n-type source layer 15 is formed to be shallower than the p-type diffusion layer 13 from the front surface FS of the semiconductor portion 10.

[0051] like Figure 5 As shown in (a), after forming an etching mask EM1 on the front surface FS side of the semiconductor wafer 100, a contact trench CT is formed. For example, the contact trench CT is formed by selectively etching the semiconductor wafer 100 through the opening ST of the etching mask EM1. The etching mask EM1 is, for example, a silicon oxide film.

[0052] The contact trench CT is formed, for example, to a depth reaching the p-type diffusion layer 13 from the front surface FS of the semiconductor wafer 100. The bottom surface of the contact trench CT is located in the p-type diffusion layer 13, for example.

[0053] For example, the semiconductor wafer 100 is selectively etched by anisotropic RIE to form the contact trench CT. At this time, the width W of the bottom surface of the contact trench CT in the X direction is BT The width W of the opening ST in the X direction is ST The etching conditions such as high frequency power and vacuum degree can be set in a wide range.

[0054] like Figure 5 As shown in (b), while the etching mask EM1 is retained, p-type impurities such as boron (B) are ion-implanted into the front surface FS side of the semiconductor wafer 100. As a result, an implantation region IR is formed at the bottom surface of the contact trench CT. The implantation region IR contains p-type impurities. Next, after the etching mask EM1 is removed, the p-type impurities in the implantation region IR are activated by heat treatment.

[0055] like Figure 6 As shown in (a), after forming the p-type contact layer 17 under the contact trench CT, the interlayer insulating film 45 is formed. The p-type contact layer 17 is formed by activating the p-type impurities implanted into the region IR.

[0056] The interlayer insulating film 45 is, for example, a silicon oxide film formed by CVD. The interlayer insulating film 45 is formed to cover the front surface FS side of the semiconductor wafer 100. The interlayer insulating film 45 may be formed to fill the inside of the contact trench CT, or may be formed to leave a gap inside the contact trench CT.

[0057] like Figure 6 As shown in (b), after forming an etching mask EM2 on the interlayer insulating film 45, the interlayer insulating film 45 is selectively removed. The interlayer insulating film 45 is removed while leaving the portion covering the gate electrode 40. The interlayer insulating film 45 is removed by dry etching, for example. The etching mask EM2 is, for example, a resist mask.

[0058] like Figure 7 As shown in (a), a first metal layer 31 and a second metal layer 33 are formed to cover the front surface FS side of the semiconductor wafer 100. The first metal layer 31 is, for example, a titanium nitride layer formed by sputtering, and the second metal layer 33 is, for example, a tungsten layer formed by CVD.

[0059] The first metal layer 31 is formed to cover the n-type source layer 15 and the interlayer insulating film 45 exposed on the front surface FS side of the semiconductor portion 10 and to cover the inner surface of the contact trench CT. The second metal layer 33 is formed to fill the inside of the contact trench CT.

[0060] like Figure 7 As shown in (b), the third metal layer 35 is formed on the second metal layer 33. The third metal layer 35 is, for example, an aluminum layer formed by sputtering. Then, the back side of the semiconductor wafer 100 is ground to be thinned to a predetermined thickness.

[0061] Then, n-type impurities such as phosphorus (P) are ion-implanted into the back side of the semiconductor wafer 100 to form an n-type buffer layer 19 (see Figure 1 ). In addition, a drain electrode 20 is formed on the back surface, thereby completing the semiconductor device 1. The portion between the n-type buffer layer 19 and the p-type diffusion layer 13 of the semiconductor wafer 100 becomes the n-type drift layer 11.

[0062] Figure 8 (a) and (b) are schematic cross-sectional views showing a semiconductor device 2 according to a modification of the embodiment. Figure 8 (b) is along Figure 8 (a) is a cross-sectional view taken along line AA. Hereinafter, description of the same structure as that of the semiconductor device 1 will be appropriately omitted.

[0063] like Figure 8 As shown in (a), the source electrode 30 of the semiconductor device 2 has a first contact portion 30 P and the second contact portion 30 F The first contact portion 30 P The second contact portion 30 has a shape in which the front end expands as it extends in the semiconductor portion 10. F area and reduce the on-resistance.

[0064] The semiconductor device 2 further includes a third electrode (hereinafter referred to as a field plate 50) configured inside the gate trench GT together with the gate electrode 40. The field plate 50 is provided between the drain electrode 20 and the gate electrode 40. The field plate 50 is electrically insulated from the n-type drift layer 11 by a third insulating film (hereinafter referred to as an insulating film 53). Furthermore, the field plate 50 is electrically insulated from the gate electrode 40 by a fourth insulating film (hereinafter referred to as an insulating film 55). The field plate 50 is, for example, polycrystalline silicon having conductivity. The insulating film 53 and the insulating film 55 are, for example, silicon oxide films.

[0065] like Figure 8 As shown in (b), the gate electrode 40 extends in the direction along the front surface of the semiconductor portion 10, for example, in the Y direction, inside the gate trench GT. The gate electrode 40 has, for example, a gate connection portion 40 located at an end in the Y direction. C and is electrically connected to the gate wiring 60 .

[0066] The gate line 60 has a stacked structure including, for example, a first metal layer 61, a second metal layer 63, and a third metal layer 65. The first metal layer 61 is, for example, a titanium nitride layer. The second metal layer 63 is, for example, a tungsten layer. The third metal layer 65 is, for example, an aluminum layer.

[0067] The gate wiring 60 includes a contact portion 60 extending in the contact hole CH1 of the interlayer insulating film 45. P . Contact part 60 P The gate connection portion 40 C The contact portion 60 electrically connects the gate electrode 40 to the gate wiring 60. P The contact hole CH1 includes a portion of the first metal layer 61 in contact with the gate electrode 40 and a portion of the second metal layer 63 buried in the contact hole CH1 .

[0068] The field plate 50 extends in the Y direction inside the gate trench GT. The field plate 50 has a connection portion 50 at an end portion in the Y direction. C . Connecting portion 50 C The gate connection portion 40 is provided along the gate electrode 40 C Extending in the Z direction. Connecting portion 50 C The extension portion 30 of the source electrode 30 B Electrical connection.

[0069] The source electrode 30 includes a main portion 30 electrically connected to the n-type source layer 15 and the p-type contact layer 17. A , and from the main unit 30 A The extension portion 30 extending along the front surface of the interlayer insulating film 45 B Extension 30 B The contact portion 30 is provided BP .

[0070] Contact part 30 BP The contact hole CH2 of the interlayer insulating film 45 extends to the connection portion 50. C Contact. Contact portion 30 BP The contact portion 30 includes a portion of the first metal layer 31 in contact with the field plate 50 and a portion of the second metal layer 33 buried in the contact hole CH2. BP The field plate 50 is electrically connected to the source electrode 30 .

[0071] Fig. 9 (a) and (b) are schematic cross-sectional views showing a semiconductor device 3 according to another modified example of the embodiment. Fig. 9 (b) is along Fig. 9 (a) is a cross-sectional view taken along line BB. Hereinafter, description of the same structure as that of the semiconductor device 1 will be appropriately omitted.

[0072] like Fig. 9As shown in (a), the source electrode 30 of the semiconductor device 3 has a first contact portion 30 P and the second contact portion 30 F The first contact portion 30 P The second contact portion 30 has a shape in which the front end expands as it extends in the semiconductor portion 10. F area and reduce the on-resistance.

[0073] The semiconductor device 3 further includes a field plate 50 disposed inside the gate trench GT together with the gate electrode 40. The gate electrode 40 includes a first gate electrode 40 arranged in the X direction. A and the second gate electrode 40 B The field plate 50 includes a first portion 50 A and Part 2 50 B .

[0074] Part 150 A The first portion 50 is arranged closer to the drain electrode 20 than the gate electrode 40 in the Z direction. A The n-type drift layer 11 is electrically insulated by the insulating film 53 .

[0075] Part 250 B On the first gate electrode 40 A and the second gate electrode 40 B The second part 50 B The first gate electrode 40 is connected to the insulating film 55. A and the second gate electrode 40 B Electrical insulation.

[0076] like Fig. 9 As shown in (b), a gate connection portion 40 of the gate electrode 40 is provided between the field plate 50 and the gate wiring 60. C . Gate electrode 40 A and the gate electrode 40 B At the ends of the respective Y directions and at the gate connection portion 40 C connect.

[0077] The contact portion 60 of the gate wiring 60 P The gate connection portion 40 C contact, the gate electrode 40 A and the gate electrode 40 B Electrically connected to the gate wiring 60 .

[0078] The field plate 50 extends in the Y direction inside the gate trench GT. The field plate 50 has a connection portion 50 at an end portion in the Y direction. C . Connecting portion 50 C Through the extension portion 30 of the source electrode 30B Contact portion 30 BP With extension 30 B Electrical connection. Contact portion 30 BP The field plate 50 is electrically connected to the source electrode 30 .

[0079] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, changes, etc. can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device comprising: Semiconductor Division; A first electrode is provided on the back side of the semiconductor portion; a second electrode disposed on the front side of the semiconductor portion, comprising a first contact portion extending in the semiconductor portion and a second contact portion in contact with the front side of the semiconductor portion; a control electrode disposed in the semiconductor portion between the first electrode and the second electrode, electrically insulated from the semiconductor portion by a first insulating film, and opposed to the second electrode via a second insulating film; and another control electrode, adjacent to the control electrode, The semiconductor portion includes a first layer of a first conductivity type, a second layer of a second conductivity type, and a third layer of the first conductivity type, The first layer extends between the first electrode and the second electrode, and the control electrode has a length from the second insulating film to the first layer. The second layer is disposed between the first layer and the second electrode, and faces the control electrode via the first insulating film. The third layer is provided between the second layer and the second electrode, and is in contact with the first insulating film, the first contact portion, and the second contact portion. The first contact portion has a first width in the second direction and a second width in the second direction at a first position and a second position arranged in the first direction, respectively; the first position is located between the first electrode and the second position; a contact surface of the second contact portion contacting the third layer is adjacent to the second position in the second direction; the first direction is from the first electrode toward the second electrode; and the second direction is from the control electrode toward the first contact portion. The first width at the first position is wider than the second width at the second position, Between the control electrode and the other control electrode, a full width in the second direction of the contact surface of the second contact portion in contact with the third layer is wider than the second width.

2. The semiconductor device according to claim 1, wherein The third layer of the semiconductor portion includes a first conductivity type impurity, and a concentration of the first conductivity type impurity on the front side in contact with the second contact portion is higher than a concentration of the first conductivity type impurity on an interface side between the second layer and the third layer.

3. The semiconductor device according to claim 1 or 2, wherein: The semiconductor portion also includes a fourth layer of the second conductivity type, which is arranged between the second layer and the first contact portion and contacts the first contact portion, contains second conductivity type impurities with a concentration higher than that of the second conductivity type impurities in the second layer, and is electrically connected to the second electrode.

4. The semiconductor device according to claim 3, wherein: The fourth layer of the semiconductor portion is located in the second layer, and the second layer is electrically connected to the second electrode via the fourth layer.

5. The semiconductor device according to any one of claims 1, 2 and 4, wherein: The third layer of the semiconductor portion includes a portion located between a side surface of the first contact portion and the first insulating film and in contact with the side surface of the first contact portion.

6. The semiconductor device according to any one of claims 1, 2 and 4, wherein: The second contact portion is provided between an end portion of the second insulating film in the second direction and the first contact portion.

7. The semiconductor device according to any one of claims 1, 2 and 4, wherein: The semiconductor device further includes a third electrode, which is provided in the first layer of the semiconductor portion via a third insulating film, faces the control electrode via a fourth insulating film, and is arranged at a position closer to the first electrode than the control electrode in the first direction. The third electrode is electrically connected to the second electrode.

8. The semiconductor device according to claim 7, wherein: The control electrode includes a first portion and a second portion arranged along the second direction, The third electrode extends between the first portion and the second portion.

9. The semiconductor device according to claim 7, wherein: The third electrode is located between the first electrode and the control electrode.

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