UART Extended Receiver Circuit Capable of Enabling Control of Power Supply

Abstract

The present invention relates to a UART extended receiving circuit capable of enabling control of a power supply. The circuit includes a power input pin (1), a charge-discharge module (2) and a voltage regulation module (3) sequentially arranged on the power input pin (1), a UART receiving open-drain input pin (4) and a UART transmitting open-drain output pin (5). The circuit further includes a switch module (6) that is respectively connected to the power input pin (1), the UART receiving open-drain input pin (4) and the enable terminal (EN) of the voltage regulation module (3), and can pull down the enable terminal (EN) to turn off the voltage regulation module (3) according to a signal when the UART receiving open-drain input pin (4) continuously outputs the same signal. Without changing the original UART interface definition, the present invention realizes the quick power-off and quick restart of the communication module, and improves the working efficiency of the electric meter.

Description

Technical Field

[0001] The invention relates to the technical field of electric energy meters, and in particular to a UART expansion receiving circuit capable of realizing enable control of a power supply. Background Art

[0002] Smart meters all have a communication module that enables remote unattended meter reading. Usually, the communication module is pluggable, so there is a hardware interface UART between the meter and the communication module. From the communication module end, the interface has three pin definitions: power input, UART receive open-drain input, and UART transmit open-drain output. Figure 1 shown.

[0003] According to the existing hardware interface design, when the "power input" is powered normally, the supercapacitor or battery will be charged through the "supercapacitor / battery-charge and discharge" circuit. Since the charging target voltage is lower than the input voltage of the power supply, VD1 is cut off at this time, and the input power supply supplies power to the back-end "voltage regulator" circuit, outputting a stable voltage for use by the back-end circuit; when there is no voltage at the "power input", VD1 is turned on, and the "supercapacitor / battery-charge and discharge" starts to discharge for the "voltage regulator" to work, and VD2 is cut off to avoid discharging to the front end and wasting the energy of the supercapacitor or battery.

[0004] This structure has a disadvantage. When the communication module crashes, or the electric meter needs to actively restart the communication module, the communication module needs to have a power-on process, that is, the electric meter must first turn off the "power input" end of the communication power supply, wait for a certain period of time, and then reopen the "power input" end. However, due to the effect of the supercapacitor or battery, even if the "power input" end is turned off, the communication module will not lose power immediately, resulting in a long waiting time (more than 5 minutes).

[0005] Currently, a common solution is to add a pin definition to the interface circuit to control the on or off of the "regulator" circuit through the pin definition. However, the actual situation is that more often than not, designers do not want to change the pin interface definition, but hope to achieve fast power-off and fast restart of the communication module without changing the original definition. Summary of the invention

[0006] In view of the above problems, the purpose of the present invention is to provide a UART extended receiving circuit that can realize power enable control and control the communication module to quickly power off and quickly restart the communication module without changing the pin definition through a UART input signal.

[0007] In order to achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a UART extended receiving circuit that can realize power enable control, the circuit includes a power input pin, a charging and discharging module and a voltage stabilizing module arranged on the power input pin in sequence, a UART receiving open drain input pin and a UART transmitting open drain output pin, characterized in that: the circuit also includes a switch module that is respectively connected to the power input pin, the UART receiving open drain input pin and the enable end of the voltage stabilizing module and can pull down the enable end according to the signal to turn off the voltage stabilizing module when the UART receiving open drain input pin continuously outputs the same signal.

[0008] Furthermore, the signal is a low level signal.

[0009] Further, the switch module includes a first switch module which is respectively connected to the power input pin and the UART receiving open-drain input pin and is not turned on when the UART receiving open-drain input pin continuously outputs a low level, and a second switch module which is respectively connected to the power input pin and the enable end of the voltage regulator module;

[0010] The first switch module is connected to the second switch module to ensure that the second switch module is turned on by turning itself off to pull down the enable terminal.

[0011] Furthermore, the first switch module includes a first resistor voltage-dividing network and a first switch tube connected to the first resistor voltage-dividing network and the second switch module respectively, and the voltage-dividing part of the first resistor voltage-dividing network is connected to the UART receiving open-drain input pin.

[0012] Furthermore, the second switch module includes a second resistor divider network, a second switch tube connected to the second resistor divider network and the enable end of the voltage stabilizing module respectively, and a capacitor that cooperates with the second resistor divider network to determine the conduction speed of the second switch tube.

[0013] Further, the first resistor voltage divider network includes a first resistor and a second resistor, one end of the first resistor is connected to the power input pin and the other end is connected to the second resistor and the UART receiving open drain input pin, and the other end of the second resistor is grounded;

[0014] The first switch tube is a MOS tube whose gate is connected to the other end of the first resistor, whose drain is connected to the voltage dividing point of the second resistor voltage dividing network, and whose source is grounded.

[0015] Furthermore, the second resistor voltage divider network includes a third resistor and a fourth resistor, one end of the third resistor is connected to the power input pin and the other end is connected to the drain of the first switch tube and the fourth resistor, and the other end of the fourth resistor is grounded;

[0016] The second switch tube is a MOS tube whose gate is connected to the other end of the third resistor, whose drain is connected to the enable end of the voltage regulator module, and whose source is grounded;

[0017] The capacitor is connected in parallel across the fourth resistor.

[0018] Furthermore, the circuit also includes a first diode arranged at the other end of the first resistor to prevent the input voltage from being input into the back-end circuit through the first resistor and causing the input voltage of the back-end circuit to exceed an upper limit.

[0019] Furthermore, the circuit also includes a second diode for preventing backflow when the charge and discharge module discharges.

[0020] Furthermore, the circuit also includes a third diode for realizing the selection of power supply modes of the charging and discharging module and the power input pin to supply power to the voltage stabilizing module when the power input pin works normally.

[0021] Compared with the prior art, the advantages of the present invention are: by utilizing the pin signal output characteristics when the hardware interface circuit transmits information, the UART receiving open-drain input pin continuously outputs a low level, the second switch module is turned on, and the enable end of the voltage stabilizing module is pulled low, so that the communication module is quickly powered off by turning off the voltage stabilizing module. It is well achieved that the relationship between the pin signal information and the voltage stabilizing module is cleverly utilized without changing the hardware interface pin definition, so that the communication module is quickly restarted and the working efficiency of the electric energy meter is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Define the circuit schematic for the existing UART pins.

[0023] Figure 2 This is the improved UART pin circuit schematic diagram of this application. DETAILED DESCRIPTION

[0024] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0025] like Figure 2As shown, the UART extended receiving circuit capable of realizing power enable control of the present application includes a power input pin 1, a charge and discharge module 2 and a voltage stabilizing module 3 sequentially arranged on the power input pin 1, a UART receiving open drain input pin 4 and a UART transmitting open drain output pin 5. The circuit also includes a switch module 6 which is respectively connected to the power input pin 1, the UART receiving open drain input pin 4 and the enable end of the voltage stabilizing module 3 and can pull down the enable end according to the signal to turn off the voltage stabilizing module 3 when the UART receiving open drain input pin 4 continuously outputs the same signal. In the present application, the charge and discharge module 2 is composed of a super capacitor or a battery.

[0026] In normal UART communication, the UART receive open-drain input pin 4 is at a high level when idle, and there will be a high-level end bit after each transmission. In other words, the UART receive open-drain input pin 4 is at a low level only when transmitting signals. In other situations, including when the meter is powered off and not working, it will be in a high-impedance state and no low level will appear, so the UART communication line will not remain in a low level state for a long time.

[0027] When it is transmitting signals, it is only in a low level state for a short time. The short low level state time cannot pull the enable end of the voltage regulator low. Therefore, in the current UART hardware interface circuit design, the voltage regulator module therein is always in working state.

[0028] Now, the present application makes the UART receive open-drain input pin 4 continuously in the same signal state, uses the signal to pull down the enable end of the voltage regulator module, turns off the voltage regulator module, and thus cuts off the connection between the charging module and the back-end communication module, cleverly solving the problem that the existing communication module cannot be quickly powered off and restarted.

[0029] In the present application, the signal is a low-level signal. That is, the present application makes full use of the characteristic that the signal line is in a low-level state during transmission to perform the shutdown operation. Of course, the characteristic that the signal line is in a high-level state for a long time can also be used to design the circuit. However, in this case, it is necessary to make full use of the characteristic of signal jump, and it will also make the circuit design more complicated. Although the design in this case is easy to know, as a preferred embodiment, the present application preferably adopts the characteristic that the output signal is at a low level for improvement.

[0030] Specifically, the switch module 6 includes a first switch module 61 which is respectively connected to the power input pin 1 and the UART receive open-drain input pin 4 and is not conductive when the UART receive open-drain input pin 4 continuously outputs a low level, and a second switch module 62 which is respectively connected to the power input pin 1 and the enable end EN of the voltage regulator module 3; the first switch module 61 is connected to the second switch module 62 to ensure that the second switch module 62 is conductive by shutting down itself to pull down the enable end.

[0031] like Figure 2 As shown, the first switch module 61 includes a first resistor divider network 611 and a first switch tube 612 connected to the first resistor divider network 611 and the second switch module 62 respectively, and the voltage dividing point of the first resistor divider network 611 is connected to the UART receiving open drain input pin 4.

[0032] The second switch module 62 includes a second resistor divider network 621 , a second switch tube 622 connected to the second resistor divider network 621 and the enable terminal EN of the voltage stabilizing module 3 , and a capacitor 623 that cooperates with the second resistor divider network 621 to determine the conduction speed of the second switch tube 622 .

[0033] In this embodiment, the resistor divider network 611 includes a first resistor R3 and a second resistor R6, one end of the first resistor R3 is connected to the power input pin 1 and the other end is connected to the second resistor R6 and the UART receiving drain open input pin 4, and the other end of the second resistor R6 is grounded; at the same time, the first switch tube 612 is a MOS tube M3 whose gate is connected to the other end of the first resistor R3 and the drain is connected to the voltage dividing point of the second resistor divider network 621 and the source is grounded.

[0034] The second resistor divider network 621 includes a third resistor R4 and a fourth resistor R5, one end of the third resistor R4 is connected to the power input pin 1 and the other end is connected to the drain of the first switch tube 612 and the fourth resistor R5, and the other end of the fourth resistor R5 is grounded; the second switch tube 622 is a MOS tube M2 whose gate is connected to the other end of the third resistor R4 and the drain is connected to the enable end EN of the voltage regulator module 3 and the source is grounded, and the capacitor C1 is connected in parallel to both ends of the fourth resistor R5.

[0035] Continue to see Figure 2 The circuit also includes a first diode VD4 arranged at the other end of the first resistor R3 to prevent the input voltage from being input to the back-end circuit through the first resistor R3 and causing the input voltage of the back-end circuit to exceed the upper limit, a second diode VD2 to prevent backflow when the charge and discharge module 2 is discharged, and a third diode VD1 to realize the selection of the power supply mode between the charge and discharge module 2 and the power input pin 1 to supply power to the voltage stabilizing module 3 when the power input pin 1 is working normally.

[0036] The working mode of the circuit is as follows: when the UART receiving open-drain input pin 4 maintains a low level, M3 is turned off, and the input voltage of the voltage regulator module 3 is divided by R4 and R5 to charge the gate of M2. Due to the existence of C1, the gate voltage of M2 rises slowly, which is equivalent to continuing to extend the duration of the low level on the UART receiving open-drain input pin 4 in disguise. When the gate-source voltage Vgs of M2 exceeds the threshold value, M2 starts to turn on, and the enable terminal EN of the voltage regulator module 3 starts to discharge. When the voltage of the enable terminal EN of the voltage regulator module 3 is lower than the lower limit, the voltage regulator module 3 stops working and the communication module is powered off. In this way, the voltage regulator module is turned off by the enable terminal EN.

[0037] When the UART receiving open-drain input pin 4 is in a high-impedance state, the voltage divided by R3 and R6 is given to the gate of M3, M3 is turned on, the gate of M2 is quickly discharged through the drain of M3, M2 is turned off, and the voltage regulator module 3 is in a normal working state.

[0038] That is, in this application, the voltage regulator module leads to an enable control terminal "EN" to the outside. When the external input of "EN" is in a high-impedance state, the bias voltage inside the voltage regulator module circuit ensures that the voltage regulator module circuit is in a normal working state. When the "EN" input is at a low level, the voltage regulator module circuit can be turned off. In this circuit design, compared with the existing design ( Figure 1 As shown in the figure, R3, R4, R5, R6, C1, M2, M3 and VD4 are added. Among them, VD4 is used to cut off the excessive voltage coming through R3 to prevent the voltage of the input signal from exceeding the upper limit of the MCU IO. The remaining devices are used to realize the function of the enable control terminal "EN" input of the voltage regulator module to ensure that when a long time (no longer than 5s) of low level appears on the UART receiving drain open input pin, M2 can be triggered to output a low level to turn off the voltage regulator module, thereby realizing the shutdown of the working power of the communication module.

[0039] The present application utilizes the pin signal output characteristics when the hardware interface circuit transmits information, so that the UART receive open-drain input pin continuously outputs a low level, the second switch module is turned on, and the enable end of the voltage regulator module is pulled low, so that the communication module is quickly powered off by turning off the voltage regulator module. This well implements the relationship between the pin signal information and the voltage regulator module without changing the hardware interface pin definition, thereby achieving a fast restart of the communication module and improving the working efficiency of the electric energy meter.

[0040] Although embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A UART extended receiving circuit capable of enabling control of a power supply. The circuit includes a power input pin (1), a charge and discharge module (2) and a voltage stabilization module (3) sequentially arranged on the power input pin (1), a UART receiving drain open input pin (4), and a UART transmitting drain open output pin (5). It is characterized in that: The circuit further includes a switch module (6) respectively connected to the power input pin (1), the UART receiving drain open input pin (4), and the enable terminal (EN) of the voltage stabilization module (3), and can pull down the enable terminal (EN) to turn off the voltage stabilization module (3) according to this signal when the UART receiving drain open input pin (4) continuously outputs the same signal; wherein, this signal is a low-level signal; and, by keeping the UART receiving drain open input pin in the same signal state continuously, the enable terminal of the voltage stabilization module is pulled down by using this signal to turn off the voltage stabilization module, thereby cutting off the connection between the charging module and the backend communication module to achieve rapid power-off of the communication module.

2. The UART extended receiving circuit capable of enabling control of a power supply according to claim 1, It is characterized in that: The switch module (6) includes a first switch module (61) respectively connected to the power input pin (1) and the UART receiving drain open input pin (4) and not conducting when the UART receiving drain open input pin (4) continuously outputs a low level, and a second switch module (62) respectively connected to the power input pin (1) and the enable terminal (EN) of the voltage stabilization module (3); The first switch module (61) is connected to the second switch module (62) to ensure that the second switch module (62) conducts to pull down the enable terminal (EN) by its own turn-off.

3. The UART extended receiving circuit capable of enabling control of a power supply according to claim 2, It is characterized in that: The first switch module (61) includes a first resistor voltage division network (611) and a first switch tube (612) respectively connected to the first resistor voltage division network (611) and the second switch module (62). The voltage division point of the first resistor voltage division network (611) is connected to the UART receiving drain open input pin (4).

4. The UART extended receiving circuit capable of enabling control of a power supply according to claim 3, It is characterized in that: The second switch module (62) includes a second resistor voltage division network (621), a second switch tube (622) respectively connected to the second resistor voltage division network (621) and the enable terminal (EN) of the voltage stabilization module (3), and a capacitor (623) cooperating with the second resistor voltage division network (621) to determine the conduction speed of the second switch tube (622).

5. The UART extended receiving circuit capable of enabling control of a power supply according to claim 4, It is characterized in that: The first resistor voltage division network (611) includes a first resistor (R3) and a second resistor (R6). One end of the first resistor (R3) is connected to the power input pin (1), and the other end is connected to the second resistor (R6) and the UART receive drain open input pin (4). The other end of the second resistor (R6) is grounded; The first switching transistor (612) is a MOS transistor (M3) whose gate is connected to the other end of the first resistor (R3), whose drain is connected to the voltage division point of the second resistor voltage division network (621), and whose source is grounded.

6. The UART extended receive circuit capable of enabling control of the power supply according to claim 5, characterized in that: The second resistor voltage division network (621) includes a third resistor (R4) and a fourth resistor (R5). One end of the third resistor (R4) is connected to the power input pin (1), and the other end is connected to the drain of the first switching transistor (612) and the fourth resistor (R5). The other end of the fourth resistor (R5) is grounded; The second switching transistor (622) is a MOS transistor (M2) whose gate is connected to the other end of the third resistor (R4), whose drain is connected to the enable terminal (EN) of the voltage regulator module (3), and whose source is grounded; The capacitor (C1) is connected in parallel across the two ends of the fourth resistor (R5).

7. The UART extended receive circuit capable of enabling control of the power supply according to claim 5, characterized in that: The circuit further includes a first diode (VD4) provided at the other end of the first resistor (R3) to prevent the input voltage from being input to the subsequent circuit through the first resistor (R3) and causing the input voltage of the subsequent circuit to exceed the upper limit.

8. The UART extended receive circuit capable of enabling control of the power supply according to claim 5, characterized in that: The circuit further includes a second diode (VD2) for preventing backflow when the charge and discharge module (2) discharges.

9. The UART extended receive circuit capable of enabling control of the power supply according to claim 5, characterized in that: The circuit further includes a third diode (VD1) that, when the power input pin (1) is operating normally, enables one of the power supply modes of the charge and discharge module (2) and the power input pin (1) to supply power to the voltage regulator module (3).

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