Reducing the Sensitivity of Integrated Circuits and Sensors to Radio Frequency Interference

Abstract

A device includes a ground plane (2), an integrated circuit chip (1) disposed on the ground plane (2), the integrated circuit chip (1) including one or more conductive layers (10) surrounding the periphery of the integrated circuit chip (1), and a plurality of bonding wires (9) that electrically couple the one or more conductive layers (10) to the ground plane (2).

Description

Technical Field

[0001] The present invention relates to reducing the susceptibility of integrated circuits and sensors (such as analog circuits and sensors) to radio frequency interference. Background Art

[0002] When adjacent RF antennas communicate with a base station, analog integrated circuits are affected by strong magnetic and electric fields. Analog circuits are also affected by strong fields when being evaluated for Electro-Magnetic Compatibility (EMC), such as in a Transverse Electro-Magnetic (TEM) cell where a transmission line is parallel to the surface of the integrated circuit. The TEM cell test can generate a magnetic field (H) in the side of the die and a vertical electric field (E) in the top of the die. The TEM cell test is described in IEC 62132-8, which specifies a method for measuring the immunity of an integrated circuit (IC) to radio frequency (RF) electromagnetic interference in the frequency range of 150 KHz to 3 GHz.

[0003] This exposure to strong magnetic and electric fields can cause serious errors in analog integrated circuits and communication circuits, resulting in incorrect outputs or complete communication failures.

[0004] Providing a metal box around an integrated circuit is a known shielding technique. However, for optical circuits (e.g., circuits including color sensors, optical proximity sensors, or other optical sensors), this technique may be impossible, for example, because the integrated circuit needs to sense external light. Summary of the Invention

[0005] A first aspect of the present invention provides an apparatus that includes a ground plane and an integrated circuit chip disposed on the ground plane. The integrated circuit chip includes one or more conductive layers surrounding the periphery of the integrated circuit chip and a plurality of bonding wires that electrically couple the one or more conductive layers to the ground plane.

[0006] In the context of an optical sensor, the embodiments described herein are intended to block RF interference from entering the integrated circuit or package, or at least significantly reduce RF interference, without blocking the light that will be sensed by the integrated circuit. These techniques can be used to reduce analog circuit failures and communication errors, particularly light-to-digital conversion errors caused by RF interference.

[0007] In an embodiment, the integrated circuit chip may include one or more optical sensors.

[0008] In an embodiment, an integrated circuit chip may have a bottom surface attached to a ground plane and a top surface on which one or more conductive layers define four corners, wherein each corner is electrically coupled to the ground plane by one or more of a plurality of bonding wires. For each corner, a first wire of the plurality of bonding wires may electrically couple the corner to the ground plane, and a second bonding wire of the plurality of wires may electrically couple the corner to the ground plane. The first bonding wire may be in a first plane, the second bonding wire may be in a second plane, and the first plane may be orthogonal to the second plane. The first and second planes may be parallel to respective planes of the side surfaces of the chip that meet at the corresponding corner. The plurality of bonding wires may follow a curved path in their respective planes.

[0009] In addition to the plurality of bonding wires first mentioned, the device may include a plurality of operational bonding wires, and the plurality of bonding wires first mentioned may extend further from the integrated circuit chip than the operational bonding wires.

[0010] One or more conductive layers may include a plurality of stacked metal layers. One or more conductive layers may include a scribe seal of the integrated circuit chip. The ground plane may be conductive and may include copper.

[0011] The integrated circuit chip may include a substrate layer and an epitaxial layer. The substrate layer may be located between the epitaxial layer and the ground plane.

[0012] In an embodiment, the substrate layer and the epitaxial layer may be located between one or more conductive layers and the ground plane.

[0013] The device may include a wireless transmitter near the integrated circuit chip, wherein the wireless transmitter induces a magnetic field during operation, and wherein the magnitude of the magnetic field impinging on the integrated circuit chip may be reduced at least in part by one or more conductive layers and a plurality of bonding wires.

[0014] The device may include a metal layer on the top surface of the integrated circuit chip, which may be coupled to the ground plane by a bonding wire and may have an opening to expose an optical sensor of the integrated circuit chip.

[0015] According to a second aspect of the present invention, there is provided a device comprising: an integrated circuit chip and means for reducing radio frequency interference to one or more components of the integrated circuit chip, the integrated circuit chip including one or more optical sensors and one or more conductive layers surrounding the periphery of the integrated circuit chip.

[0016] In an embodiment, one or more conductive layers may include a scribe seal of the integrated circuit chip. Description of the Drawings

[0017] Figure 1Shows an integrated circuit chip mounted on a metal ground plane, having a metal shield including an opening and eight additional corner bonding wires;

[0018] Figure 2 Shows Figure 1 a front view of the integrated circuit chip;

[0019] Figure 3 Shows an optical test chip having a metal shield including an opening and eight additional corner bonding wires;

[0020] Figure 4 Shows an optical test chip having a metal shield including an opening and no additional bonding wires;

[0021] Figure 5 Shows an optical test chip without a shield and having eight additional corner bonding wires;

[0022] Figure 6 Shows an optical test chip without a metal shield and without additional bonding wires; and

[0023] Figure 7 Shows the Δ count (absolute difference between RF on and RF off) during a TEM test of the test chip shown in Figures 3 to 6 Detailed Description

[0024] A varying magnetic field (e.g., H x , H y ) intersects one or more conductive loops, with a vector component perpendicular to the loops (i.e., entering one side of the IC chip). The varying magnetic field induces a voltage in the loops, and the voltage in turn generates a current, thereby generating a magnetic field.

[0025] According to Faraday's law, the induced electromotive force (EMF) generated in the loop by the perpendicular component of the H field is:

[0026]

[0027] where φ is the magnetic flux, A is the area where the loop intersects the field, B is the magnetic flux density, ω is the frequency of the magnetic field in radians per second, μ r is the relative permeability, μ o is the permeability of free space, and H is the magnetic field strength.

[0028] According to Lenz's law, the induced EMF always generates a current whose magnetic field is opposite to the original change in magnetic flux, thereby canceling and mitigating the magnetic field entering the loop.

[0029] ​The EMF induced in a loop is proportional to the area, frequency, and H-field strength of the loop. Thus, an H-field of 3 GHz and 20 A / m will generate 1000 times more EMF than an H-field of 3 MHz and 20 A / m. The increase in EMF with frequency indicates the importance of keeping the loop impedance low to form an opposing magnetic field at high frequencies.

[0030] Providing additional bond wires on the chip can utilize these principles to help reduce the RF interference that would otherwise occur.

[0031] Embodiments will now be described with reference to a device such as an integrated circuit chip or "chip" for example. Figure 1 Such a chip 1 is shown, as well as a ground plane 2 on which the chip is located. The ground plane can be a metal (e.g., copper) substrate, and the chip is mounted on the ground plane. Standard bond wires 3 are provided on the sides of the chip. These standard bond wires can be operational bond wires connected to, for example, the input, output, power, or control pins / pads 4 of the chip. A metal shield 5 is also provided, connected to the VSSA and VSSD pins 6, 7 of the chip. The shield is provided with an opening 8 to allow light to be sensed by an optical sensor (not shown) of the chip. It is assumed that the chip is subject to, for example, varying levels of a magnetic field H x and H y and a varying vertical electric field E z effects.

[0032] Additional bond wires 9 are provided, which are electrically coupled together and connected to the ground plane 2. Specifically, the additional bond wires 9 are electrically coupled by one or more conductive (e.g., metal) layers 10 provided along or adjacent to the edge of the chip. The conductive layer can include a plurality of stacked metal layers such that they completely surround the interior of the chip together. The conductive layer 10, the ground plane 2, and the additional bond wires 9 together form a low-impedance electrical loop. It is the changing magnetic fields in these loops that induce EMF, thereby generating opposing magnetic fields.

[0033] The additional bond wires 9 are provided at one or more corners of the chip. In Figure 1 the example shown, there are a total of eight additional bond wires, with two bond wires at each corner of the chip. This arrangement provides optimal H-field mitigation on all four sides of the chip.

[0034] In Figure 2 the front view, a low-impedance electrical loop can be seen, formed by a first additional bond wire 9a, a conductive layer 10a, a second bond wire 9b, and a metal substrate / ground plane 2a. Also as Figure 2 shown, each additional bond wire 9 preferably extends outward beyond the standard bond wires on the same chip face. This maximizes the RF interference protection not only for the chip itself but also for the standard bond wires.

[0035] For example, the conductive layer electrically connected to the additional bonding wire 9 can be a scribe seal layer. Scribe seals are typically included in the chip to prevent the propagation of cracks during the separation of individual die from the wafer. The upper layer of the scribe seal can provide dedicated interconnection and electrical coupling for the additional bonding wire. Typically, the metal scribe seal around the chip is not exposed and is, for example, surrounded by a residual silicon layer. However, access to this metal layer can be obtained through a cut in the passivation layer on the chip. By using the scribe seal to provide dedicated interconnection, the amount of chip modification, production time, and cost required are reduced.

[0036] (As described in IEC 62132-8) TEM cell testing can be used to subject the test chip to a horizontal H field and a vertical E field. As described above, the additional bonding wire can mitigate the H field on the horizontal plane. By covering the device with a top metal shield formed using the top-side metal of the IC and then connecting this shield to ground, it can be used to prevent the vertical E field from entering the IC. The additional bonding wire and the metal layer combined can form an effective shield for TEM cell measurements for EMC testing of non-optical ICs. For optical ICs, it may be necessary to have a cut in the top metal shield, for example, to allow light to reach the photodiode. The larger the size of the cut, the lower the shielding effectiveness against the vertical E field.

[0037] Performance data has been collected on the test chip using a TEM cell. Figures 3 to 6 It is shown that test chips were fabricated in four different configurations. Two test chips were fabricated, one without a shield and the other with a top metal shield with VSSA and VSSD pins connected to opposite ends of the chip. These pins are shorted to ground. There are two bonding schemes, one without corner bonding wires and the other with eight grounded corner bonding wires.

[0038] Figure 7 The TEM cell test results are shown. The Δ count, which is the absolute difference in counts (counts of the least significant bit (LSB) of an Analog-to-Digital Converter (ADC)) between the RF-on state and the RF-off state, is plotted as a function of frequency. Compared to the unprotected chip (trace 11), the Δ count is reduced due to the presence of the additional bonding wire alone (trace 12) and the presence of the shield alone (trace 13). For the test chip with both the shield and the additional bonding wire (trace 14), the Δ count is particularly reduced. The raw count at the high light level used for testing was approximately 6,000,000. Thus, the absolute (RF-on - RF-off) count difference for the test case with the shield plus eight corner bonding wires is approximately 0.1% or less of the raw count.

[0039] The foregoing techniques can be used in a wide range of applications, including, for example, the market for mobile device analog circuits for sensors. A host device (e.g., a smart phone) can include a module or package that can contain an integrated circuit (IC) chip (e.g., a die) that includes an optical sensor (e.g., a color sensor, an optical proximity sensor, or other optical sensor) and associated electronics that are operable to process signals from the sensor and to control other components (e.g., a display screen) of the host device in response to signals from the sensor. The sensor can include, for example, one or more photodiodes. A controller (e.g., a microprocessor on the chip or in the host device) can use signals from the optical sensor to, for example, adjust the brightness of the display screen of the host device or to adjust the color temperature of the display screen based on ambient light.

[0040] Effective shielding is provided to prevent fluctuating fields, particularly near-field horizontal magnetic field planes, originating from adjacent antennas. This helps reduce communication errors due to RF interference. In some cases, the techniques described herein can significantly reduce (e.g., by a factor of 10) the impact of RF interference within an analog integrated circuit or package. Thus, the disclosed subject matter can help improve RF immunity within an integrated circuit and / or package.

[0041] For example, these techniques are particularly beneficial for analog circuits and optical sensors operating near an RF antenna or a WiFi antenna. For example, the techniques can be effective even when the antenna is separated from an IC circuit mounted on a flexible cable or printed circuit board by 1 millimeter or less. These techniques also have the advantage of not requiring an expensive metal enclosure around the IC.

[0042] Those skilled in the art will appreciate that various modifications can be made to the above embodiments without departing from the scope of the invention.

Claims

1. An apparatus, comprising: A ground plane; An integrated circuit chip disposed on the ground plane, the integrated circuit chip including one or more conductive layers surrounding the periphery of the integrated circuit chip; and A plurality of bonding wires electrically coupling the one or more conductive layers to the ground plane, And including a metal layer on the top surface of the integrated circuit chip, coupled to the ground plane by a bonding wire, and an optical sensor having an opening to expose the integrated circuit chip.

2. The device according to claim 1, wherein The integrated circuit chip includes one or more optical sensors.

3. The device according to claim 1 or 2, wherein The integrated circuit chip has a bottom surface attached to the ground plane and a top surface on which the one or more conductive layers define four corners, and wherein each corner is electrically coupled to the ground plane by one or more of the plurality of bonding wires.

4. The device according to claim 3, wherein For each corner, a first bonding wire of the plurality of bonding wires electrically couples the corner to the ground plane, and a second bonding wire of the plurality of bonding wires electrically couples the corner to the ground plane.

5. The apparatus according to claim 4, wherein The first bonding wire is in a first plane, the second bonding wire is in a second plane, and the first plane is orthogonal to the second plane.

6. The device according to claim 5, wherein The first plane and the second plane are parallel to the respective planes of the side surfaces of the chip meeting at the corresponding corner.

7. The apparatus according to claim 6, wherein, The plurality of bonding wires follow a curved path in their respective planes.

8. The apparatus according to claim 1 or 2, further comprising a plurality of operational bonding wires in addition to the plurality of bonding wires, wherein the plurality of bonding wires extend further from the integrated circuit chip than the operational bonding wires.

9. The device according to claim 1 or 2, wherein The one or more conductive layers include a plurality of stacked metal layers.

10. The device according to claim 1 or 2, wherein, The one or more conductive layers include a scribe seal of the integrated circuit chip.

11. The device according to claim 1 or 2, wherein, The ground plane is conductive.

12. The device according to claim 11, wherein, The ground plane includes copper.

13. The device according to claim 1 or 2, wherein, The integrated circuit chip includes a substrate layer and an epitaxial layer.

14. The apparatus according to claim 13, wherein, The substrate layer is located between the epitaxial layer and the ground plane.

15. The apparatus according to claim 14, wherein, The substrate layer and the epitaxial layer are located between the one or more conductive layers and the ground plane.

16. The apparatus according to claim 1 or 2, including a wireless transmitter near the integrated circuit chip, wherein the wireless transmitter induces a magnetic field during operation, and wherein the magnitude of the magnetic field impinging on the integrated circuit chip is reduced at least in part by the one or more conductive layers and the plurality of bonding wires.

17. A device, comprising: an integrated circuit chip, the integrated circuit chip including one or more optical sensors and one or more conductive layers surrounding a periphery of the integrated circuit chip; a ground plane; Components for reducing radio frequency interference to one or more components of the integrated circuit chip; And a plurality of bonding wires electrically coupling the one or more conductive layers to the ground plane, And including a metal layer on the top surface of the integrated circuit chip, coupled to the ground plane by a bonding wire, and an optical sensor having an opening to expose the integrated circuit chip.

18. The apparatus according to claim 17, wherein the one or more conductive layers include a scribe seal of the integrated circuit chip.

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