A switch and data access method

Abstract

The embodiment of the present invention provides a switch and a data access method, which relates to the field of communication technology, and can improve the efficiency of CPU access to I2C devices and reduce the occupancy of CPU by accessing I2C devices. The switch of the embodiment of the present invention includes: a central processing unit CPU, a complex programmable logic device CPLD chip and multiple integrated circuit bus I2C devices. The CPU is connected to the CPLD chip through a serial peripheral interface SPI; the CPLD chip includes multiple I2C analog interfaces, each of which is implemented by two I / O pins; each I2C analog interface included in the CPLD chip is connected to a different I2C device. The CPU is used to send an access instruction to the CPLD chip through the SPI; the CPLD chip is used to perform read and write operations on the I2C device through the I2C analog interface based on the access instruction.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a switch and a data access method. Background Art

[0002] The central processing unit (CPU) on the switch board can access the I2C devices on the board, such as the electrically erasable programmable read only memory (EEPROM), temperature sensor, real-time clock (RTC), optical module, etc., through the Inter-Integrated Circuit (I2C) bus. I2C is a low-speed serial bus consisting of two lines: the serial clock line (SCL) and the serial data line (SDA).

[0003] like Figure 1 As shown in the figure, different types of I2C devices on the switch board can be connected to different I2C interfaces of the CPU, such as Figure 1 The temperature sensing chip, RTC chip and EEPROM are connected to the I2C1 interface of the CPU; the power supply and fan are connected to the I2C2 interface of the CPU; one end of the analog switch is connected to the business interface modules 0~N, and the other end is connected to the I2C3 interface of the CPU, and the remaining I2C devices are connected to the I2C4 interface of the CPU.

[0004] There are many I2C devices on the switch board. The CPU needs to access these I2C devices through the I2C bus at regular intervals. Since the rate of the I2C bus is low, the CPU accessing a large number of I2C devices will take up a lot of CPU time, resulting in low access efficiency. In addition, the CPU cannot perform other services when accessing I2C devices. Summary of the invention

[0005] The purpose of the embodiment of the present invention is to provide a switch and a data access method to improve the efficiency of CPU access to I2C devices and reduce the CPU occupancy of access to I2C devices. The specific technical solution is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a switch, comprising: a central processing unit CPU, a complex programmable logic device CPLD chip and a plurality of integrated circuit bus I2C devices;

[0007] The CPU is connected to the CPLD chip via a serial peripheral interface SPI; the CPLD chip includes a plurality of I2C analog interfaces, each of which is implemented by two I / O pins; each of the I2C analog interfaces included in the CPLD chip is connected to a different I2C device;

[0008] The CPU is used to send an access instruction to the CPLD chip through the SPI;

[0009] The CPLD chip is used to perform read and write operations on the I2C device through the I2C analog interface based on the access instruction.

[0010] Optionally, the first I2C analog interface of the CPLD chip is connected to a plurality of I2C devices with different physical addresses; and / or,

[0011] The second I2C analog interface of the CPLD chip is connected to an analog switch, the analog switch is connected to a plurality of I2C devices with the same physical address, and the analog switch is used to select to open or close the access channel of each I2C device connected to the analog switch.

[0012] Optionally, the CPU includes an I2C interface, and the CPU is connected to a specified I2C device via the I2C interface; or,

[0013] One of the I2C analog interfaces of the CPLD chip is connected to the designated I2C device.

[0014] Optionally, the designated I2C device includes a power supply and a fan.

[0015] In a second aspect, an embodiment of the present invention provides a data access method, which is applied to a CPU, wherein the CPU is located in the switch according to any one of the first aspects, and the method includes:

[0016] The CPU sends an access instruction to the CPLD chip through the SPI, wherein the access instruction includes a physical address and a register address of the I2C device to be accessed, so that the CPLD chip performs a read and write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction to obtain a read and write result;

[0017] The CPU obtains the reading and writing results of the CPLD chip on the I2C device to be accessed through the SPI.

[0018] Optionally, the access instruction is a write instruction, and the write instruction carries data to be written;

[0019] The CPU obtains the reading and writing results of the CPLD chip on the I2C device to be accessed through the SPI, including:

[0020] The CPU obtains a writing result of the data to be written from the CPLD chip through the SPI, and the writing result is used to indicate a writing success or a writing failure.

[0021] Optionally, the access instruction is a read instruction; the CPU obtains the read and write results of the CPLD chip on the I2C device to be accessed through the SPI, including:

[0022] The CPU obtains the data to be read from the CPLD chip through the SPI, and the data to be read is the data read from the register corresponding to the register address in the I2C device to be accessed by the CPLD chip through the I2C analog interface.

[0023] In a third aspect, an embodiment of the present invention provides a data access method, which is applied to a CPLD chip, wherein the CPLD chip is located in the switch according to any one of the first aspects, and the method includes:

[0024] Receive an access instruction sent by the CPU through the SPI, wherein the access instruction includes a physical address and a register address of the I2C device to be accessed;

[0025] Based on the access instruction, the I2C device to be accessed is read and written through the I2C analog interface, and the read and write results are stored, so that the CPU can obtain the read and write results of the CPLD chip on the I2C device to be accessed through the SPI.

[0026] Optionally, the access instruction is a write instruction, and the write instruction carries data to be written;

[0027] The step of performing read and write operations on the I2C device to be accessed through the I2C analog interface based on the access instruction and storing the read and write results includes:

[0028] Sending an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, wherein the address signal includes a physical address of the I2C device to be accessed;

[0029] Receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent by the I2C device to be accessed after receiving the address signal and confirming that the physical address in the address signal is the same as the physical address of the device itself;

[0030] Writing the data to be written into a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the register address;

[0031] A write response sent by the I2C device to be accessed is received through an I2C analog interface between the I2C device to be accessed, and a write result of the data to be written is stored based on the write response, wherein the write result is used to indicate a write success or a write failure.

[0032] Optionally, the access instruction is a read instruction; and performing read and write operations on the I2C device to be accessed through an I2C analog interface based on the access instruction and storing the read and write results includes:

[0033] Sending an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, wherein the address signal includes a physical address of the I2C device to be accessed;

[0034] Receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent by the I2C device to be accessed after receiving the address signal and confirming that the physical address in the address signal is the same as the physical address of the device itself;

[0035] Reading the data to be read from the register corresponding to the register address in the I2C device to be accessed through the I2C analog interface between the device and the I2C device to be accessed;

[0036] The data to be read is stored so that the CPU can obtain the data to be read from the CPLD chip through the SPI.

[0037] Optionally, the method further includes:

[0038] If a recovery command of the CPU for the designated I2C analog interface is received through the SPI bus, the SCL clock signal of the designated I2C analog interface is pulled down continuously for 9 times.

[0039] In a fourth aspect, an embodiment of the present invention provides a data access device, applied to a CPU, wherein the CPU is located in the switch according to the first aspect, and the device includes:

[0040] A writing module is used to send an access instruction to the CPLD chip through the SPI, wherein the access instruction includes the physical address and register address of the I2C device to be accessed, so that the CPLD chip performs a read and write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction to obtain a read and write result;

[0041] The acquisition module is used to obtain the reading and writing results of the CPLD chip on the I2C device to be accessed through the SPI.

[0042] Optionally, the access instruction is a write instruction, and the write instruction carries data to be written; and the acquisition module is specifically used to:

[0043] The writing result of the data to be written is obtained from the CPLD chip through the SPI, and the writing result is used to indicate whether the writing is successful or failed.

[0044] Optionally, the access instruction is a read instruction; and the acquisition module is specifically used to:

[0045] The data to be read are obtained from the CPLD chip through the SPI, wherein the data to be read are data read from the register corresponding to the register address in the I2C device to be accessed by the CPLD chip through the I2C analog interface.

[0046] In a fifth aspect, an embodiment of the present invention provides a data access device, which is applied to a CPLD chip, wherein the CPLD chip is located in the switch described in the first aspect, and the device includes:

[0047] A receiving module, used for receiving an access instruction sent by the CPU via SPI, wherein the access instruction includes a physical address and a register address of the I2C device to be accessed;

[0048] The access module is used to perform read and write operations on the I2C device to be accessed through the I2C analog interface based on the access instruction, and store the read and write results so that the CPU can obtain the read and write results of the CPLD chip on the I2C device to be accessed through the SPI.

[0049] Optionally, the access instruction is a write instruction, and the write instruction carries data to be written;

[0050] The access module is specifically used for:

[0051] Sending an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, wherein the address signal includes a physical address of the I2C device to be accessed;

[0052] Receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent by the I2C device to be accessed after receiving the address signal and confirming that the physical address in the address signal is the same as the physical address of the device itself;

[0053] Writing the data to be written into a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the register address;

[0054] A write response sent by the I2C device to be accessed is received through an I2C analog interface between the I2C device to be accessed, and a write result of the data to be written is stored based on the write response, wherein the write result is used to indicate a write success or a write failure.

[0055] Optionally, the access instruction is a read instruction;

[0056] The access module is specifically used for:

[0057] Sending an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, wherein the address signal includes a physical address of the I2C device to be accessed;

[0058] Receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent by the I2C device to be accessed after receiving the address signal and confirming that the physical address in the address signal is the same as the physical address of the device itself;

[0059] Reading the data to be read from the register corresponding to the register address in the I2C device to be accessed through the I2C analog interface between the device and the I2C device to be accessed;

[0060] The data to be read is stored so that the CPU can obtain the data to be read from the CPLD chip through the SPI.

[0061] Optionally, the device further comprises: a pull-down module;

[0062] The pull-down module is used to pull down the SCL clock signal of the specified I2C analog interface for 9 consecutive times if a recovery command for the specified I2C analog interface is received from the CPU through the SPI bus.

[0063] In the switch and data access method provided by the embodiment of the present invention, the CPU is connected to the CPLD chip via SPI, and the CPLD chip can be connected to the I2C device via the I2C analog interface. When the CPU needs to access the I2C device, it sends an access instruction to the CPLD chip via SPI, and the CPLD chip performs read and write operations on the I2C device based on the access instruction. Since the process of accessing the I2C device is executed by the CPLD, the CPU only needs to send the access instruction to the CPLD chip via SPI, and the rate of SPI is higher than the rate of the I2C bus, thereby reducing the occupancy of the CPU by accessing the I2C device and improving the access efficiency.

[0064] Of course, it is not necessary to achieve all of the advantages described above at the same time to implement any product or method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0066] Figure 1 It is a structural diagram of a switch in the related art;

[0067] Figure 2 A schematic diagram of the structure of a switch provided by an embodiment of the present invention;

[0068] Figure 3 A flow chart of a data access method provided by an embodiment of the present invention;

[0069] Figure 4 Another data access method flow chart provided by the embodiment of the present invention;

[0070] Figure 5 A flow chart of a data writing method provided by an embodiment of the present invention;

[0071] Figure 6 A flow chart of a data reading method provided by an embodiment of the present invention;

[0072] Figure 7 A schematic diagram of the structure of a data access device provided by an embodiment of the present invention;

[0073] Figure 8 A schematic diagram of the structure of another data access device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0074] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field based on this application belong to the scope of protection of the present invention.

[0075] In order to improve the efficiency of a central processing unit (CPU) accessing an integrated circuit bus (Inter-Integrated Circuit, I2C) device and reduce the CPU occupancy of accessing I2C devices, an embodiment of the present invention provides a switch, wherein the switch may be a box switch or a frame switch, etc., and the embodiment of the present invention does not specifically limit this.

[0076] like Figure 2 As shown, the switch provided by the embodiment of the present invention includes: a CPU 201, a CPLD (Complex Programmable Logic Device) chip 202 and multiple I2C devices.

[0077] The CPU 201 is connected to the CPLD chip 202 via a serial peripheral interface (SPI); the CPLD chip 202 includes a plurality of I2C analog interfaces, each of which is implemented by two input / output (I / O) pins; each I2C analog interface included in the CPLD chip 202 is connected to a different I2C device. The CPLD chip 202 includes a certain storage space, and part of the storage space of the CPLD chip 202 can be used as a logic register of the CPLD chip 202. The logic register can store the access instruction sent by the CPU 201, and can also store the read and write results of the I2C device to be accessed.

[0078] The CPU 201 is used to send access instructions to the CPLD chip 202 through the SPI; the CPLD chip 202 is used to perform read and write operations on the I2C device through the I2C analog interface based on the access instructions.

[0079] In the embodiment of the present invention, the connection relationship between the I2C analog interface of the CPLD chip 202 and the I2C device can be set according to actual needs.

[0080] For example, when there are fewer I2C devices, each I2C analog interface of the CPLD chip 202 can be connected to one I2C device.

[0081] When there are many I2C devices, each I2C analog interface of the CPLD chip 202 can be connected to multiple I2C devices. In one embodiment, the I2C devices can be classified, and the classification basis can be the importance of the I2C devices. For example, the I2C devices inside the switch can be divided into two categories, one of which is important I2C devices and the other is non-important I2C devices, and then the I2C devices (such as business port optical modules) connected to the switch are taken as one category. Accordingly, an I2C analog interface of the CPLD chip 202 is connected to important I2C devices, another I2C analog interface is connected to non-important I2C devices, and another I2C analog interface is connected to multiple business port optical modules through an analog switch. Alternatively, the I2C devices inside the switch are taken as one type of I2C devices, and the I2C devices connected to the switch are taken as another type of I2C devices. Accordingly, an I2C analog interface of the CPLD chip 202 is connected to the I2C devices inside the switch, and another I2C analog interface is connected to the I2C devices connected to the switch through an analog switch. The embodiment of the present application does not limit the classification method of I2C devices, and the I2C devices connected to each I2C analog interface can be set according to actual needs.

[0082] For example, Figure 2 The temperature sensing chip, RTC chip and EEPROM are a type of I2C devices, which are commonly connected to the I2C2 analog interface of the CPLD chip 202. Figure 2 The service port optical modules 0 to N are external modules, and the service port optical modules 0 to N are a type of I2C devices, which are connected to the I2C3 analog interface of the CPLD chip 202 through an analog switch.

[0083] The CPLD chip 202 includes a plurality of I / O pins. For some of the I / O pins of the CPLD chip 202, the SCL signal and the SDA signal transmitted by the I2C interface can be respectively simulated at two I / O pins of the CPLD chip 202 through logic code, thereby simulating the two I / O pins as one I2C interface. The embodiment of the present invention realizes the function of simulating the I2C interface through some of the I / O pins of the CPLD chip. Since the CPLD chip itself has a plurality of I / O pins, the embodiment of the present invention does not increase the hardware cost of the CPLD chip.

[0084] In the switch provided by the embodiment of the present invention, the CPU is connected to the CPLD chip via SPI, and the CPLD chip can be connected to the I2C device via the I2C analog interface. When the CPU needs to access the I2C device, it sends an access instruction to the CPLD chip via SPI, and the CPLD chip performs read and write operations on the I2C device based on the access instruction. Since the process of accessing the I2C device is executed by the CPLD, the CPU only needs to send the access instruction to the CPLD chip via SPI, and the rate of SPI is higher than the rate of the I2C bus, thereby reducing the occupancy of the CPU by accessing the I2C device and improving the access efficiency.

[0085] For example, the rate of the I2C bus that transmits data between I2C interfaces is generally below 100 kiloHertz (kHz), while the rate of the SPI bus that transmits data between SPI interfaces is generally above 2 megaHertz (MHz), so the rate of the SPI is much higher than the rate of the I2C bus.

[0086] In the embodiment of the present invention, the first I2C analog interface of the CPLD chip 202 is connected to a plurality of I2C devices with different physical addresses; and / or, the second I2C analog interface of the CPLD chip 202 is connected to an analog switch, and the analog switch is connected to a plurality of I2C devices with the same physical address. The analog switch is used to select to open or close the access channel of each I2C device connected to the analog switch.

[0087] Optionally, the first I2C analog interface of the CPLD chip 202 can be connected to an I2C device.

[0088] The “first” in the first I2C analog interface and the “second” in the second I2C analog interface are only used to distinguish I2C analog interfaces connected to different devices, and are not used to limit the properties of the I2C analog interface itself.

[0089] For example, Figure 2 As shown, the I2C2 analog interface of the CPLD chip 202 is connected to the temperature sensing chip, EEPROM and RTC chip. Among them, the temperature sensing chip, EEPROM and RTC chip are a type of I2C devices, and their physical addresses are different from each other.

[0090] Optionally, since the physical addresses of the service port optical modules are usually the same, each service port optical module can be connected to an I2C analog interface of the CPLD chip 202. Figure 2As shown, the service port optical modules 0-N can be connected to the I2C3 analog interface of the CPLD chip 202 through an analog switch. The CPLD chip 202 accesses different service port optical modules by selecting different access channels through the analog switch. The analog switch selects different access channels based on the control signal of the CPLD chip 202.

[0091] In the embodiment of the present invention, the CPU 201 includes an I2C interface, and the CPU 201 is connected to a specified I2C device via the I2C interface; or, one of the I2C analog interfaces of the CPLD chip 202 is connected to the specified I2C device.

[0092] Optionally, specified I2C devices include power supplies and fans.

[0093] For example, Figure 2 As shown, the power supply and the fan are connected to the I2C1 interface of the CPU 201 .

[0094] Since the CPU generally has an I2C interface, directly connecting more important I2C devices to the I2C interface of the CPU can improve the reliability of the CPU accessing these more important I2C devices.

[0095] Optionally, in addition to the power supply, fan, temperature sensor chip, EEPROM, RTC chip and service port optical module, there may be other I2C devices, such as a power monitoring module, a clock phase-locked loop, etc.

[0096] For example, Figure 2 As shown, other I2C devices can be connected to the I2C4 analog interface of the CPLD chip 202.

[0097] The embodiment of the present invention can connect all I2C devices in the switch to the CPLD chip to reduce the occupation of CPU resources for accessing the I2C devices as much as possible, thereby preventing the CPU from being unable to perform other operations due to being occupied by the I2C interface.

[0098] At the same time, in the related art, all I2C devices are directly connected to the I2C interface of the CPU. In order to classify and manage the I2C devices, each type of I2C device is connected to an I2C interface, so that the CPU needs to have a large number of I2C interfaces, which has certain restrictions on the selection of the CPU in the switch and increases the cost of the CPU.

[0099] The embodiment of the present invention can select some I2C devices to directly connect to the I2C interface of the CPU, or set all the I2C devices in the switch to connect to the CPLD chip instead of the CPU. In this way, a CPU with fewer I2C interfaces can be selected, thereby reducing the restrictions on the selection of CPUs in the switch and reducing the cost of the CPU.

[0100] In addition, in the related art, the I2C interface is simulated through a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) interface or a universal serial bus (Universal Serial Bus, USB) interface. These solutions all require adding additional chips to the switch board where the CPU and I2C devices are located, increasing the hardware cost of the switch.

[0101] The switch board where the CPU and I2C devices are located generally includes a CPLD chip. The embodiment of the present invention utilizes the CPLD chip on the switch board to implement the function of converting the SPI protocol to the I2C protocol. At the same time, the CPLD chip on the switch board can generally implement this function. Therefore, the embodiment of the present invention has no additional restrictions on the selection of the CPLD chip on the switch board and does not increase additional hardware costs.

[0102] The conventional switch structure is as follows Figure 1 As shown, the temperature sensing chip, RTC chip and EEPROM are connected to the I2C1 interface of the CPU; the power supply and fan are connected to the I2C2 interface of the CPU; one end of the analog switch is connected to the business interface modules 0 to N, and the other end is connected to the I2C3 interface of the CPU, and other I2C devices are connected to the I2C4 interface of the CPU. Among them, the I2C devices connected to the same I2C interface are distinguished by different physical addresses. If the physical addresses of the I2C devices connected to the same I2C interface are the same, the analog switch selects different channels to distinguish them.

[0103] When the CPU needs to access an I2C device, the CPU sends an address signal to all I2C devices connected to the CPU through each I2C interface, where the address signal includes the physical address of the I2C device to be accessed. After each I2C device receives the address signal, if the physical address included in the address signal is the same as its own physical address, it will feedback an Acknowledge character (ACK) signal to the CPU to inform the CPU that further operations can be performed. After receiving the ACK signal, the CPU reads data from the I2C device that sent the ACK signal, or writes data to the I2C device that sent the ACK signal.

[0104] Among them, if multiple I2C devices with the same physical address are connected to an I2C interface of the CPU, or the load capacitance of the I2C device connected to an I2C interface of the CPU exceeds the maximum capacitance supported by the I2C protocol (400pF, where pF represents picofarads), the CPLD chip controls the analog switch to open the corresponding channel, so that the CPU can access the corresponding I2C device.

[0105] In addition to regular access to I2C devices, the CPU also needs to complete a read and write operation in some I2C devices at regular intervals, that is, poll some I2C devices. Since the CPU accesses I2C devices through the I2C interface, and the rate of the I2C interface is low, that is, the CPU sends address signals, receives ACK messages, and reads or writes data to the I2C device slowly, it takes up a lot of CPU time and resources, making it difficult for the CPU to handle other services.

[0106] In order to improve the access efficiency of the CPU and reduce the occupation of CPU resources by accessing the I2C device. Figure 2 In the switch shown, Figure 3 As shown, the method comprises the following steps:

[0107] S301, the CPU sends an access instruction to the CPLD chip via SPI.

[0108] The access instruction includes the physical address and register address of the I2C device to be accessed, so that the CPLD chip performs read and write operations on the I2C device to be accessed through the I2C analog interface based on the access instruction to obtain read and write results.

[0109] In the embodiment of the present invention, the CPLD chip has a certain storage space, and part of the storage space of the CPLD chip can be used as the logic register of the CPLD chip. The CPU can access the logic register of the CPLD chip through the state machine of the internal logic code of the CPLD chip to send an access instruction to the CPLD chip.

[0110] S302, the CPU obtains the read and write results of the CPLD chip on the I2C device to be accessed through the SPI.

[0111] The data access method provided by the embodiment of the present invention is that the CPU is connected to the CPLD chip through SPI, and the CPLD chip is connected to the I2C device through the I2C analog interface. When the CPU needs to access the I2C device, it sends an access instruction to the CPLD chip through SPI, and the CPLD chip performs read and write operations on the I2C device based on the access instruction. Since the process of accessing the I2C device is executed by the CPLD chip, the CPU only needs to send an access instruction to the CPLD chip. When the CPLD chip performs read and write operations on the I2C device, the CPU can handle other services. And because the rate of SPI is higher than the rate of the I2C bus, the CPU obtains the read and write results of the I2C device to be accessed from the CPLD chip through SPI. Compared with the CPU accessing the I2C device through the I2C interface in the prior art, the CPU time occupied by accessing the I2C device can be reduced, the data access efficiency is improved, and the time for the CPU to process other services is increased.

[0112] In the embodiment of the present invention, the CPU can write data to the I2C device through the CPLD chip. In this case, the access instruction is a write instruction, and the write instruction carries the data to be written.

[0113] Based on this, the method in which the CPU obtains the read and write results of the CPLD chip on the I2C device to be accessed through SPI in the above S302 can be implemented as follows: the CPU obtains the write result of the data to be written from the CPLD chip through SPI. Wherein, the write result is used to indicate a write success or a write failure. Optionally, when the write result is a write failure, the write result may also include the reason for the write failure.

[0114] In an embodiment of the present invention, after the CPLD chip writes the data to be written to the I2C device, if the CPLD chip receives an ACK message fed back by the I2C device within a specified time period, it is determined that the writing is successful; or, if the CPLD chip does not receive an ACK message fed back by the I2C device within a specified time period after writing the data to be written to the I2C device, it is determined that the writing has failed.

[0115] After receiving the ACK message indicating that the write is successful, the CPLD chip stores the write result indicating that the write is successful. If the CPLD chip does not receive the ACK message indicating that the write is successful within the specified time after writing the data to be written to the I2C device, the write result indicating that the write fails is stored. This allows the CPU to obtain the write result from the CPLD chip, thereby improving the reliability of data writing.

[0116] When the CPU in the embodiment of the present invention needs to write data into the register of the I2C device, it can send a write instruction to the CPLD chip, and the CPLD chip completes the data writing work. During the process of the CPLD writing data, the CPU can handle other services. Since the CPU and the CPLD chip communicate via SPI, the data transmission speed of SPI is much higher than the transmission speed of I2C. Compared with the CPU directly writing data to the I2C device through the I2C interface, the embodiment of the present invention can improve the data writing speed of the CPU, and avoid the situation where the CPU cannot handle other services because of writing data to the I2C device.

[0117] In an embodiment of the present invention, the CPU can read data from the I2C device through the CPLD chip. In this case, the access instruction is a read instruction. The method in which the CPU obtains the read and write results of the CPLD chip on the I2C device to be accessed through the SPI in S302 can be implemented as follows: the CPU obtains the data to be read from the CPLD chip through the SPI. The data to be read is the data read from the register corresponding to the register address of the I2C device to be accessed by the CPLD chip through the I2C analog interface.

[0118] The data to be read belongs to the reading result of the CPLD chip on the I2C device to be accessed. The reading result is used to indicate a successful read or a failed read. When the reading result is a successful read, the reading result includes the data to be read read by the CPLD chip. When the reading result is a failed read, the reading result also includes the reason for the failure.

[0119] In the embodiment of the present invention, if the CPLD chip can read the data to be read from the I2C device, it is determined that the reading is successful, and the CPLD chip can store the reading result, at which time the reading result is used to indicate that the reading is successful, and the reading result includes the data to be read. Alternatively, if the CPLD chip cannot read the data to be read from the I2C device, that is, after sending a read signal to the I2C device, if an ACK message fed back by the I2C signal is not received within a specified time, it is determined that the reading fails, and the CPLD chip can store the reading result, at which time the reading result is used to indicate that the reading fails.

[0120] Accordingly, the CPU can obtain the reading result from the CLPD chip via SPI.

[0121] When the CPU in the embodiment of the present invention needs to read data from the register of the I2C device, it can send a read instruction to the CPLD chip, and the CPLD chip completes the data reading work, and the CPU can process other services at this time. Because the CPU and the CPLD chip communicate through SPI, the data transmission speed of SPI is much higher than the transmission speed of I2C. Compared with the CPU directly reading data through the I2C interface, the embodiment of the present invention can improve the reading speed and avoid the situation where the CPU cannot process other services because of reading data in the I2C device.

[0122] In another embodiment of the present invention, when there are multiple access instructions, the CPU can send multiple access instructions to the CPLD chip via SPI, so that the CPLD chip performs read and write operations on the I2C device targeted by each access instruction through the I2C analog interface, and stores the read and write results of each read and write operation.

[0123] Accordingly, in the above S302, the CPU obtains the read and write results of the CPLD chip on the I2C device to be accessed through SPI, which can be implemented as follows:

[0124] The CPU obtains the read and write results of the CPLD chip for each I2C device targeted by the access instruction through the SPI.

[0125] It can be seen that after the CPU sends multiple access instructions to the CPLD chip, it can continue to process other services. After the CPLD chip completes the read and write operations on the I2C devices targeted by the multiple access instructions, the CPU can read multiple read and write results from the CPLD chip at one time. Compared with the CPU accessing each I2C device through each I2C interface, the embodiment of the present invention can reduce the occupancy of CPU resources, which is equivalent to improving the data access efficiency of the CPU.

[0126] The embodiment of the present invention also provides a data access method, which is applied to a CPLD chip, wherein the CPLD chip is located in the above Figure 2 In the switch shown. Figure 4 As shown, the method comprises the following steps:

[0127] S401, receiving an access instruction sent by the CPU via SPI, wherein the access instruction includes a physical address and a register address of the I2C device to be accessed.

[0128] The CPLD chip has a certain storage space, and part of the storage space of the CPLD chip can be used as the logic register of the CPLD chip. The CPU can access the logic register of the CPLD chip through the state machine of the internal logic code of the CPLD chip to send access instructions to the CPLD chip.

[0129] S402, performing read and write operations on the I2C device to be accessed through the I2C analog interface based on the access instruction, and storing the read and write results so that the CPU can obtain the read and write results of the CPLD chip on the I2C device to be accessed through the SPI.

[0130] The CPLD chip 202 includes multiple I / O pins. For some I / O pins of the CPLD chip 202, the SCL signal and the SDA signal transmitted by the I2C interface can be simulated at two I / O pins of the CPLD chip through logic code, thereby simulating the two I / O pins into one I2C interface.

[0131] The data access method provided by the embodiment of the present invention is that the CPU is connected to the CPLD chip through SPI, and the CPLD chip is connected to the I2C device through the I2C analog interface. When the CPU needs to access the I2C device, it sends an access instruction to the CPLD chip through SPI, and the CPLD chip performs read and write operations on the I2C device based on the access instruction. Since the process of accessing the I2C device is executed by the CPLD chip, the CPU only needs to send an access instruction to the CPLD chip through SPI. When the CPLD chip performs read and write operations on the I2C device, the CPU can handle other services. And because the rate of SPI is higher than the rate of the I2C bus, the CPU obtains the read and write results from the CPLD chip through SPI. Compared with the CPU accessing the I2C device through the I2C interface in the prior art, the CPU time occupied by accessing the I2C device can be reduced, the data access efficiency is improved, and the time for the CPU to process other services is increased.

[0132] In the embodiment of the present invention, when the CPU needs to write data to the I2C device, the access instruction is a write instruction, and the access instruction carries the data to be written. Figure 5 In the above S402, the CPLD chip performs read and write operations on the I2C device to be accessed through the I2C analog interface based on the access instruction, and stores the read and write results, which can be achieved by the following steps:

[0133] S501, sending an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, wherein the address signal includes the physical address of the I2C device to be accessed.

[0134] S502, receiving a confirmation message sent by the I2C device to be accessed to the CPLD via the I2C analog interface.

[0135] The confirmation message is sent by the I2C device to be accessed after receiving the address signal and confirming that the physical address in the address signal is the same as its own physical address. The confirmation message may be an ACK message.

[0136] S503, writing the data to be written into a register corresponding to the register address in the I2C device to be accessed through the I2C analog interface between the device and the I2C device to be accessed.

[0137] S504, receiving a write response sent by the I2C device to be accessed through the I2C analog interface between the device and the I2C device to be accessed, and storing a write result of the data to be written based on the write response.

[0138] The write result is used to indicate whether the write is successful or failed.

[0139] In an embodiment of the present invention, after the CPLD chip writes the data to be written to the I2C device, if the CPLD chip receives an ACK message fed back by the I2C device within a specified time period, it is determined that the writing is successful; or, if the CPLD chip does not receive an ACK message fed back by the I2C device within a specified time period after writing the data to be written to the I2C device, it is determined that the writing has failed. After receiving the ACK message indicating that the writing is successful, the CPLD chip stores a writing result indicating that the writing is successful. If the CPLD chip does not receive an ACK message indicating that the writing is successful within a specified time period after writing the data to be written to the I2C device, the writing result indicating that the writing has failed is stored.

[0140] When the CPU in the embodiment of the present invention needs to write data into the register of the I2C device, it can send a write instruction to the CPLD chip, and the CPLD chip completes the data writing work. During the process of the CPLD writing data, the CPU can handle other services. Since the CPU and the CPLD chip communicate via SPI, the data transmission speed of SPI is much higher than the transmission speed of I2C. Compared with the CPU directly writing data to the I2C device through the I2C interface, the embodiment of the present invention can improve the data writing speed of the CPU, and avoid the situation where the CPU cannot handle other services because of writing data to the I2C device.

[0141] In the embodiment of the present invention, when the CPU needs to read data from the I2C device, the access instruction is a read instruction. Figure 6 In the above S402, the CPLD chip performs read and write operations on the I2C device to be accessed through the I2C analog interface based on the access instruction, and stores the read and write results, which can be achieved by the following steps:

[0142] S601, sending an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, wherein the address signal includes a physical address of the I2C device to be accessed.

[0143] S602, receiving a confirmation message sent by the I2C device to be accessed to the CPLD via the I2C analog interface.

[0144] The confirmation message is sent by the I2C device to be accessed after receiving the address signal and confirming that the physical address in the address signal is the same as its own physical address. The confirmation message may be an ACK signal.

[0145] S603, reading the data to be read from the register corresponding to the register address in the I2C device to be accessed through the I2C analog interface between the device and the I2C device to be accessed.

[0146] S604, storing the data to be read so that the CPU can obtain the data to be read from the CPLD chip via SPI.

[0147] In the embodiment of the present invention, the CPU can read the data to be read from the CPLD chip once at a certain interval, thereby reducing the situation where the CPU reads the data to be read multiple times, reducing the occupation of CPU resources, and improving the management efficiency of the I2C bus, thereby improving the operating efficiency of the switch.

[0148] In a switch, if an error occurs when the CPU's I2C bus accesses data (for example, the CPU does not receive a response from the I2C device while reading data from the I2C device or writing data to the I2C device), the I2C bus will be hung. The CPU can continue to access the I2C device only after the I2C bus is restored.

[0149] The conventional method to restore the I2C bus is: the CPU sends 9 high-level signals continuously through the GPIO pin, that is, the CPU sets the GPIO pin to a high level 9 times in succession. When the special circuit on the single board where the CPU is located detects the 9 consecutive high-level signals sent by the GPIO pin, the SCL clock signal of the I2C bus is pulled down 9 times in succession to restore the I2C bus.

[0150] This method of restoring the I2C bus requires adding an additional special circuit on the single board, which not only increases the complexity of restoring the I2C bus, but also increases the hardware cost of the switch.

[0151] In the embodiment of the present invention, the method of restoring the I2C bus connected to the CPLD chip includes: if a recovery command for a specified I2C analog interface is received from the CPU via the SPI bus, the SCL clock signal of the specified I2C analog interface is pulled down 9 times in succession. The specified I2C analog interface is an I2C analog interface in which an error occurs.

[0152] The CPU obtains the read / write results from the CPLD chip. If the read / write results are used to indicate a read / write failure, the CPU sends a recovery command to the CPLD chip via SPI. After receiving the recovery command, the CPLD simulates the I2C bus through internal logic code and pulls down the SCL clock signal of the specified I2C simulation interface for 9 consecutive times to recover the I2C bus.

[0153] It can be seen that the embodiment of the present invention directly uses the CPLD chip to restore the I2C bus. Since the switch board has a built-in CPLD chip, the embodiment of the present invention does not need to add additional hardware to the switch to restore the I2C bus, thereby reducing the hardware cost of the switch.

[0154] Based on the same inventive concept, corresponding to the above method embodiment, the present invention provides a data access device, which is applied to a CPU, and the CPU is located in the above method embodiment. Figure 2 In the switch shown, Figure 7 As shown, the device includes: a writing module 701 and an acquiring module 702;

[0155] The writing module 701 is used to send an access instruction to the CPLD chip through the SPI, wherein the access instruction includes the physical address and register address of the I2C device to be accessed, so that the CPLD chip performs a read and write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction to obtain a read and write result;

[0156] The acquisition module 702 is used to acquire the reading and writing results of the CPLD chip on the I2C device to be accessed through SPI.

[0157] Optionally, the access instruction is a write instruction, and the write instruction carries data to be written; the acquisition module 702 is specifically used to:

[0158] The writing result of the data to be written is obtained from the CPLD chip through SPI, and the writing result is used to indicate the writing success or the writing failure.

[0159] Optionally, the access instruction is a read instruction; the acquisition module 702 is specifically used to:

[0160] The data to be read is obtained from the CPLD chip through SPI. The data to be read is the data read from the register corresponding to the register address of the I2C device to be accessed by the CPLD chip through the I2C analog interface.

[0161] Based on the same inventive concept, corresponding to the above method embodiment, the present invention provides a data access device, which is applied to a CPLD chip, and the CPLD chip is located in the switch of the above embodiment. Figure 8 As shown, the device includes: a receiving module 801 and an access module 802;

[0162] The receiving module 801 is used to receive an access instruction sent by the CPU through the SPI, where the access instruction includes a physical address and a register address of the I2C device to be accessed;

[0163] The access module 802 is used to perform read and write operations on the I2C device to be accessed through the I2C analog interface based on the access instruction, and store the read and write results so that the CPU can obtain the read and write results of the CPLD chip on the I2C device to be accessed through the SPI.

[0164] Optionally, the access instruction is a write instruction, and the write instruction carries data to be written; the access module 802 is specifically used to:

[0165] Sending an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, the address signal including the physical address of the I2C device to be accessed;

[0166] Receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent by the I2C device to be accessed after receiving the address signal and confirming that the physical address in the address signal is the same as its own physical address;

[0167] Writing the data to be written into the register corresponding to the register address in the I2C device to be accessed through the I2C analog interface between the device to be accessed and the I2C device to be accessed;

[0168] A write response sent by the I2C device to be accessed is received through an I2C analog interface between the I2C device to be accessed, and a write result of the data to be written is stored based on the write response, wherein the write result is used to indicate a write success or a write failure.

[0169] Optionally, the access instruction is a read instruction;

[0170] The access module 802 is specifically used for:

[0171] Sending an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, the address signal including the physical address of the I2C device to be accessed;

[0172] Receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent by the I2C device to be accessed after receiving the address signal and confirming that the physical address in the address signal is the same as its own physical address;

[0173] Reading the data to be read from the register corresponding to the register address of the I2C device to be accessed through the I2C analog interface between the I2C device to be accessed and the I2C device to be accessed;

[0174] The data to be read is stored so that the CPU can obtain the data to be read from the CPLD chip via SPI.

[0175] Optionally, the device further comprises: a pull-down module;

[0176] The pull-down module is used to pull down the SCL clock signal of the specified I2C analog interface for 9 consecutive times if a recovery command for the specified I2C analog interface is received from the CPU through the SPI bus.

[0177] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0178] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0179] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A switch, characterized in that: include: Central processing unit CPU, complex programmable logic device CPLD chip and multiple integrated circuit bus I2C devices; The CPU is connected to the CPLD chip via a serial peripheral interface SPI; the CPLD chip includes a plurality of I2C analog interfaces, each of which is implemented by two I / O pins; each of the I2C analog interfaces included in the CPLD chip is connected to a different I2C device; The CPU is used to send an access instruction to the CPLD chip through the SPI; The CPLD chip is used to perform read and write operations on the I2C device through the I2C analog interface based on the access instruction; The first I2C analog interface of the CPLD chip is connected to a plurality of I2C devices with different physical addresses; and / or, the second I2C analog interface of the CPLD chip is connected to an analog switch, the analog switch is connected to a plurality of I2C devices with the same physical address, and the analog switch is used to select to open or close the access channel of each I2C device connected to the analog switch; When there are multiple access instructions, the CPU is specifically used to send multiple access instructions to the CPLD chip through SPI; the CPLD chip is specifically used to perform read and write operations on the I2C device targeted by each access instruction through the I2C analog interface, and store the read and write results of each read and write operation.

2. The switch according to claim 1, characterized in that: The CPU includes an I2C interface, and the CPU is connected to a specified I2C device via the I2C interface; or, One of the I2C analog interfaces of the CPLD chip is connected to the designated I2C device.

3. The switch according to claim 2, characterized in that: The specified I2C devices include power supplies and fans.

4. A data access method, characterized in that: Applied to a CPU, the CPU being located in a switch according to any one of claims 1 to 3, the method comprising: The CPU sends an access instruction to the CPLD chip through the SPI, wherein the access instruction includes a physical address and a register address of the I2C device to be accessed, so that the CPLD chip performs a read and write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction to obtain a read and write result; The CPU obtains the reading and writing results of the CPLD chip on the I2C device to be accessed through the SPI.

5. The method according to claim 4, characterized in that The access instruction is a write instruction, and the write instruction carries data to be written; The CPU obtains the reading and writing results of the CPLD chip on the I2C device to be accessed through the SPI, including: The CPU obtains a writing result of the data to be written from the CPLD chip through the SPI, and the writing result is used to indicate a writing success or a writing failure.

6. The method according to claim 4, characterized in that The access instruction is a read instruction; the CPU obtains the read and write results of the CPLD chip on the I2C device to be accessed through the SPI, including: The CPU obtains the data to be read from the CPLD chip through the SPI, and the data to be read is the data read from the register corresponding to the register address in the I2C device to be accessed by the CPLD chip through the I2C analog interface.

7. A data access method, characterized in that: Applied to a CPLD chip, the CPLD chip is located in a switch according to any one of claims 1 to 3, and the method comprises: Receive an access instruction sent by the CPU through the SPI, wherein the access instruction includes a physical address and a register address of the I2C device to be accessed; Based on the access instruction, the I2C device to be accessed is read and written through the I2C analog interface, and the read and write results are stored, so that the CPU can obtain the read and write results of the CPLD chip on the I2C device to be accessed through the SPI.

8. The method according to claim 7, characterized in that The access instruction is a write instruction, and the write instruction carries data to be written; The step of performing read and write operations on the I2C device to be accessed through the I2C analog interface based on the access instruction and storing the read and write results includes: Sending an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, wherein the address signal includes a physical address of the I2C device to be accessed; Receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent by the I2C device to be accessed after receiving the address signal and confirming that the physical address in the address signal is the same as the physical address of the device itself; Writing the data to be written into a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the register address; A write response sent by the I2C device to be accessed is received through an I2C analog interface between the I2C device to be accessed, and a write result of the data to be written is stored based on the write response, wherein the write result is used to indicate a write success or a write failure.

9. The method according to claim 7, characterized in that: The access instruction is a read instruction; performing read and write operations on the I2C device to be accessed through the I2C analog interface based on the access instruction and storing the read and write results includes: Sending an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, wherein the address signal includes a physical address of the I2C device to be accessed; Receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent by the I2C device to be accessed after receiving the address signal and confirming that the physical address in the address signal is the same as the physical address of the device itself; Reading the data to be read from the register corresponding to the register address in the I2C device to be accessed through the I2C analog interface between the device and the I2C device to be accessed; The data to be read is stored so that the CPU can obtain the data to be read from the CPLD chip through the SPI.

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