Directed interrupt virtualization with blocking indicator

Abstract

The present invention relates to a method for providing an interrupt signal to a client operating system. A bus-attached device receives an interrupt signal from a bus connection module having an interrupt target ID that identifies a processor assigned to a client operating system for use as a target processor for processing the interrupt signal. The bus-attached device uses an interrupt blocking indicator provided by an interrupt table entry stored in a memory operatively connected to the bus-attached device to check whether the target processor is blocked from receiving the interrupt signal. If the target processor is not blocked, the bus-attached device forwards the interrupt signal to the target processor for processing. The target processor is directly addressed using a conversion of the interrupt target ID to the logical processor ID of the target processor.

Description

Background Art

[0001] The present invention relates generally to interrupt processing within a computer system and, more particularly, to handling interrupts generated by bus connection modules in a multiprocessor computer system.

[0002] Interrupts are used to signal a processor that an event requires the processor's attention. For example, hardware devices (e.g., hardware devices connected to a processor via a bus) use interrupts to communicate that they require attention from an operating system. In the case where a receiving processor is currently performing some activity, the receiving processor can suspend its current activity in response to receiving an interrupt signal, save its state, and handle the interrupt, for example, by executing an interrupt handler. The interruption of the processor's current activity caused by receiving an interrupt signal is only temporary. After handling the interrupt, the processor can resume its suspended activity. Therefore, interrupts can improve performance by eliminating the non-productive waiting time of the processor waiting for external events in a polling loop.

[0003] In a multi-processor computer system, interrupt routing efficiency issues may arise. The challenge is to efficiently forward interrupt signals sent by hardware devices such as bus connection modules to processors among the multiple processors assigned to the operating system. This can be particularly challenging in the case where interrupts are used to communicate with a client operating system on a virtual machine. A hypervisor or virtual machine monitor (VMM) creates and runs one or more virtual machines, or guest machines. A virtual machine provides a guest operating system running on the same platform as the virtual operating platform while hiding the physical characteristics of the underlying platform. Using multiple virtual machines allows multiple operating systems to run in parallel. Because it is executed on the virtual operating platform, the client operating system has a limited view of the processor. Figure 1 The virtual processor ID (ID) used by the guest operating system is generally different from the underlying (e.g., physical view of the processor). The guest operating system uses a virtual processor ID (identifier) ​​to identify the processor, which is generally inconsistent with the underlying logical processor ID. The hypervisor that manages the execution of the guest operating system defines the mapping between the underlying logical processor ID and the virtual processor ID used by the guest operating system. However, this mapping and the selection of the processor scheduled for use by the guest operating system is not static, but can be changed by the hypervisor while the guest operating system is running without the knowledge of the guest operating system.

[0004] This challenge is usually addressed by forwarding interrupt signals using broadcast. When broadcast is used, the interrupt signal is forwarded continuously between multiple processors until a processor suitable for handling the interrupt signal is encountered. However, in the case of multiple processors, the probability that the processor that first receives the broadcast interrupt signal is indeed suitable for handling the interrupt signal may be quite low. In addition, being suitable for handling the interrupt signal does not necessarily mean that the corresponding processor is the best choice for handling the interrupt. Summary of the invention

[0005] Various embodiments provide a method, a computer system and a computer program product for providing an interrupt signal to a client operating system executed using one or more processors of a plurality of processors of a computer system allocated for use by the client operating system as described by the subject matter of the independent claims. Advantageous embodiments are described in the dependent claims. The embodiments of the invention can be freely combined with each other insofar as they are not mutually exclusive.

[0006] On the one hand, the present invention relates to a method for providing an interrupt signal to a client operating system, wherein the client operating system is executed by one or more processors of a plurality of processors assigned to the client operating system by a computer system, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory, the bus attachment device operably connected to the memory, each of the plurality of processors being assigned a logical processor ID used by the bus attachment device to address the corresponding processor, each of the plurality of processors assigned to the client operating system being further assigned an interrupt target ID used by the client operating system and the one or more bus connection modules to address the corresponding processor, the method comprising: receiving, by the bus attachment device, a logical processor ID having a logic processor ID from one of the bus connection modules; An interrupt signal of an interrupt target ID, wherein the interrupt target ID identifies one of the processors assigned to the client operating system as the target processor for processing the interrupt signal, a bus-attached device retrieves a first copy of an interrupt table entry assigned to the received interrupt target ID from an interrupt table stored in a memory, the first copy of the interrupt table entry includes an interrupt blocking indicator indicating whether the target processor identified by the interrupt target ID is currently blocked from receiving the interrupt signal, the bus-attached device uses the interrupt blocking indicator to check whether the target processor is blocked from receiving the interrupt signal, if the target processor is not blocked, the bus-attached device converts the received interrupt target ID into a logical processor ID, and uses the logical processor ID generated by the conversion to directly address the target processor, and forwards the interrupt signal to the target processor for processing, otherwise, the bus-attached device blocks the interrupt signal from being forwarded to the target processor for processing.

[0007] On the other hand, the present invention relates to a computer system for providing an interrupt signal to a client operating system, wherein the client operating system is executed by one or more processors of a plurality of processors of the computer system assigned to the client operating system for use, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory, the bus attachment device operably connected to the memory, each of the plurality of processors being assigned a logical processor ID used by the bus attachment device to address the corresponding processor, each of the plurality of processors assigned to the client operating system for use is further assigned an interrupt target ID used by the client operating system and the one or more bus connection modules to address the corresponding processor, the computer system being configured to perform a method, the method comprising: receiving, by the bus attachment device, a logical processor ID from a bus; An interrupt signal having an interrupt target ID of one of the connection modules, the interrupt target ID identifying one of the processors assigned to the client operating system as a target processor for processing the interrupt signal, a first copy of an interrupt table entry assigned to the received interrupt target ID is retrieved by a bus-attached device from an interrupt table stored in a memory, the first copy of the interrupt table entry including an interrupt blocking indicator indicating whether the target processor identified by the interrupt target ID is currently blocked from receiving the interrupt signal, the bus-attached device using the interrupt blocking indicator to check whether the target processor is blocked from receiving the interrupt signal, if the target processor is not blocked, the bus-attached device converting the received interrupt target ID into a logical processor ID, and using the logical processor ID generated by the conversion to directly address the target processor, and forwarding the interrupt signal to the target processor for processing, otherwise, the bus-attached device blocks the interrupt signal from being forwarded to the target processor for processing.

[0008] On the other hand, the present invention relates to a computer program product for providing an interrupt signal to a client operating system, the client operating system being executed by one or more processors of a plurality of processors of a computer system assigned to the client operating system for use, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory, the bus attachment device operably connected to the memory, each of the plurality of processors being assigned a logical processor ID used by the bus attachment device to address the corresponding processor, each of the plurality of processors assigned to the client operating system for use is further assigned an interrupt target ID used by the client operating system and the one or more bus connection modules to address the corresponding processor, the computer program product comprising a computer-readable non-transitory medium readable by a processing circuit and storing instructions executed by the processing circuit to perform a method comprising: The method includes: a bus-attached device receives an interrupt signal with an interrupt target ID from one of the bus connection modules, the interrupt target ID identifies one of the processors assigned to the client operating system as a target processor for processing the interrupt signal; the bus-attached device retrieves a first copy of an interrupt table entry assigned to the received interrupt target ID from an interrupt table stored in a memory, the first copy of the interrupt table entry includes an interrupt blocking indicator indicating whether the target processor identified by the interrupt target ID is currently blocked from receiving the interrupt signal; the bus-attached device uses the interrupt blocking indicator to check whether the target processor is blocked from receiving the interrupt signal; if the target processor is not blocked, the bus-attached device converts the received interrupt target ID into a logical processor ID, and uses the logical processor ID generated by the conversion to directly address the target processor, and forwards the interrupt signal to the target processor for processing; otherwise, the bus-attached device blocks the interrupt signal from being forwarded to the target processor for processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the following, embodiments of the invention are explained in more detail, by way of example only, with reference to the accompanying drawings, in which:

[0010] Figure 1 depicts a schematic diagram of an exemplary computer system,

[0011] Figure 2 depicts a schematic diagram of an exemplary virtualization scheme,

[0012] Figure 3 depicts a schematic diagram of an exemplary virtualization scheme,

[0013] Figure 4 depicts a schematic diagram of an exemplary virtualization scheme,

[0014] Figure 5depicts a schematic diagram of an exemplary computer system,

[0015] Figure 6 depicts a schematic diagram of an exemplary computer system,

[0016] Figure 7 A schematic flow chart of an exemplary method is depicted,

[0017] FIG8 depicts a schematic flow chart of an exemplary method,

[0018] Fig. 9 A schematic flow chart of an exemplary method is depicted,

[0019] Fig.10 A schematic flow chart of an exemplary method is depicted,

[0020] Fig.11 A schematic flow chart of an exemplary method is depicted,

[0021] Fig.12 A schematic flow chart of an exemplary method is depicted,

[0022] Fig.13 A schematic diagram depicting an exemplary data structure,

[0023] Fig.14 is a schematic diagram of an exemplary vector structure,

[0024] Fig.15 is a schematic diagram of an exemplary vector structure,

[0025] FIG. 16 is a schematic diagram of an exemplary vector structure,

[0026] FIG. 17 is a schematic diagram of an exemplary vector structure,

[0027] FIG18 depicts a schematic flow chart of an exemplary method,

[0028] Fig.19 depicts a schematic diagram of an exemplary computer system,

[0029] Fig. 20 depicts a schematic diagram of an exemplary computer system,

[0030] Fig.21 depicts a schematic diagram of an exemplary computer system,

[0031] Fig. 22 depicts a schematic diagram of an exemplary computer system,

[0032] FIG23 depicts a schematic diagram of an exemplary unit, and

[0033] Fig.24 A schematic diagram of an exemplary computer system is depicted. DETAILED DESCRIPTION

[0034] The description of different embodiments of the present invention will be given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements in technology appearing in the market, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

[0035] Embodiments may have the beneficial effect of enabling a bus-attached device to directly address a target processor. Thus, an interrupt signal may be directed to a specific processor, i.e., a target processor of a multi-processor computer system, by a publishing bus connection module that selects a target processor ID. For example, a processor that has previously performed an activity related to an interrupt may be selected as the target processor for the interrupt signal. Processing an interrupt signal by the same processor as the corresponding activity may result in a performance advantage because, in the case where the same processor also processes the interrupt signal, all data in the context of the interrupt may already be available to that processor and / or stored in a local cache, enabling the corresponding processor to quickly access it without requiring a large amount of cache traffic.

[0036] Therefore, the broadcast of interrupt signals that cannot be guaranteed to ultimately handle the interrupt to the processor that is best suited for the task from a performance perspective (such as minimizing cache traffic) can be avoided. Instead of submitting the interrupt signal to all processors, each processor trying to handle the interrupt signal, and one processor winning, the interrupt signal can be directly provided to the target processor to improve the efficiency of interrupt signal processing.

[0037] The interrupt mechanism may be implemented using directed interrupts. A bus-attached device may be enabled to directly address a target processor using its logical processor ID when forwarding an interrupt signal to be processed to a target processor that issues the interrupt signal defined by a bus connection module. The conversion of the interrupt target ID to a logical processor ID by the bus-attached device may further ensure that the same processor is always addressed from the perspective of the client operating system, even though the mapping between the interrupt target ID and the logical processor ID or the selection of the processor scheduled for use by the client operating system may be controlled by the hypervisor.

[0038] According to an embodiment, a direct interruption blocking indicator is introduced in an interruption entry of an interruption table in a memory. The direct interruption blocking indicator may be implemented in the form of a single bit, ie, the diBPIA bit.

[0039] According to an embodiment, IRTE is extracted from a memory and a run indicator is checked to determine whether the target processor is scheduled. If the target processor is scheduled, a direct interrupt blocking indicator is enabled to prevent the target processor from receiving further interrupt signals while processing the current interrupt signal. Other interrupt signals may interfere with the processing of the current interrupt signal. To ensure that the target processor has not been rescheduled during this period, IRTE is re-acquired and the current run indicator is checked again to determine whether the target processor is still scheduled. In the case where the target processor is still scheduled, the logical processor ID of the target processor can be used to directly address the target processor and forward the interrupt signal to the target processor. In addition, it can be checked whether the logical processor ID of the target processor provided by IRTE for the received interrupt target ID is still the same.

[0040] According to an embodiment, the interrupt signal is received in the form of a message signaled interrupt containing an interrupt target ID of a target processor. Using message signaled interrupt (MSI) is a method in which a bus connection module (such as a peripheral component interconnect (PCI) or a peripheral component interconnect express (PCIe) function) generates a central processing unit (CPU) interrupt to notify the client operating system using the corresponding central processing unit of the occurrence of an event or the existence of a certain state. MSI provides an in-band method for signaling an interrupt using a special in-band message, thereby avoiding the need for a dedicated path separated from the main data path, such as a dedicated interrupt pin on each device, to send such control information. MSI instead relies on exchanging special messages indicating interrupts through the main data path. When the bus connection module is configured to use MSI, the corresponding module requests an interrupt by performing an MSI write operation of a specified number of bytes of data to a specific address. The combination of this specific address (i.e., MSI address) and a unique data value (i.e., MSI data) is called an MSI vector.

[0041] Modern PCIe standard adapters have the ability to submit multiple interrupts. For example, MSI-X allows the bus connection module to allocate up to 2048 interrupts. Thus, it is possible to direct individual interrupts to different processors, for example in high-speed networking applications that rely on multi-processor systems. MSI-X allows multiple interrupts to be allocated, each with a separate MSI address and MSI data value.

[0042] To transmit interrupt signals, MSI-X messages may be used. An MSI-X data table may be used to determine the required content of an MSI-X message. An MSI-X data table local to a bus connection module (i.e., a PCIe adapter / function) may be indexed by a number assigned to each interrupt signal, also known as an interrupt request (IRQ). The MSI-X data table content is controlled by the client operating system and may be set to the operating system under the guidance of hardware and / or firmware. A single PCIe adapter may include multiple PCIe functions, each of which may have an independent MSI-X data table. This may be the case, for example, for single root input / output virtualization (SR-IOV) or multifunction devices.

[0043] The interrupt target ID (such as, for example, a virtual processor ID) can be directly encoded as part of a message (such as an MSI-X message) sent by the bus connection module that includes the interrupt signal. The message (e.g., an MSI-X message) can include a requester ID, i.e., the ID of the bus connection module, the aforementioned interrupt target ID, a DIBV index, an MSI address, and MSI data. The MSI-X message can provide 64 bits for the MSI address and 32 bits for the data. The bus connection module can use the MSI to request an interrupt by performing an MSI write operation of a specific MSI data value to a specific MSI address.

[0044] The device table is a shared table that can be fully indexed by the requester ID (RID) of the interrupt requester (i.e., the bus-attached module). The bus-attached device remaps and issues interrupts, i.e., the bus-attached device translates the interrupt target ID and uses the interrupt target ID to directly address the target processor.

[0045] A client operating system may use a virtual processor ID to identify a processor in a multi-processor computer system. Thus, a client operating system's view of a processor may differ from the view of the underlying system using logical processor IDs. A bus connection module that provides resources used by a client operating system may use a virtual processor ID as a resource for communicating with the client operating system, for example, an MSI-X data table may be under the control of the client operating system. As an alternative to a virtual processor ID, any other ID may be defined for the bus connection module to address a processor.

[0046] The interrupt is delivered to the client operating system or other software executing thereon, such as other programs, etc. As used herein, the term operating system includes operating system device drivers.

[0047] As used herein, the term bus connected module may include any type of bus connected module. According to an embodiment, a module may be a hardware module, such as a storage function, a processing module, a network module, a cryptographic module, a PCI / PCIe adapter, other types of input / output modules, etc. According to other embodiments, a module may be a software module, i.e., functions such as storage functions, processing functions, network functions, cryptographic functions, PCI / PCIe functions, other types of input / output functions, etc. Therefore, in the examples given herein, unless otherwise noted, modules are used interchangeably with functions (e.g., PCI / PCIe functions) and adapters (e.g., PCI / PCIe functions).

[0048] Embodiments may have the following benefits: Provide an interrupt signal routing mechanism (e.g., MSI-X message routing mechanism) that allows it to keep bus connection modules (e.g., PCIe adapters and functions) and device drivers for operating or controlling the bus connection modules unchanged. In addition, the hypervisor may be prevented from intercepting the underlying architecture used to implement communication between the bus connection module and the client operating system, such as the PCIe MSI-X architecture. In other words, changes to the interrupt signal routing mechanism may be implemented outside the hypervisor and the bus connection module.

[0049] According to an embodiment, the method further comprises forwarding, by the bus-attached device, the interrupt signal to the remaining processors of the plurality of processors for processing using broadcasting.

[0050] According to an embodiment, the method further includes: checking by an interrupt handler of a client operating system whether there is any interrupt addressed to a target processor waiting to be processed by the target processor, and if there is no interrupt addressed to a target processor waiting to be processed by the target processor, the client operating system changes an interrupt blocking indicator in an interrupt table entry assigned to the target processor to indicate that the target processor is not blocked. The embodiment may have the beneficial effect of tracking whether the target processor is blocked. Therefore, it is possible to prevent an interrupt signal from being sent directly to a blocked target processor. According to an embodiment, the interrupt blocking indicator is implemented as a single bit. The embodiment may have the following beneficial effects, namely providing an interrupt blocking indicator in the form of minimal storage space, and the interrupt blocking indicator is quickly and efficiently processable.

[0051] According to an embodiment, the first copy of the interrupt table entry further includes a first mapping of the received interrupt target ID to a first logical processor ID of the logical processor IDs, and the bus-attached device uses the first copy of the interrupt table entry to convert the received interrupt target ID to the logical processor ID of the target processor.

[0052] Embodiments may have the beneficial effect of providing an interrupt table (IRT) comprising interrupt table entries (IRTEs), each entry providing a mapping of an interrupt target ID to a logical processor ID. Thus, the entry may define a unique assignment of each interrupt target ID to a logical processor ID. According to embodiments, the interrupt target ID may be provided in the form of a virtual processor ID. According to embodiments, the interrupt target ID may be any other ID used by a client operating system to identify the respective processor being used.

[0053] According to an embodiment, an IRT is provided in a memory for use by a bus-attached device to map an interrupt target ID to a logical processor ID. According to an embodiment, the IRT may be provided in a single location. An address indicator, such as a pointer, may be provided indicating the memory address of the IRT. The address indicator may be provided, for example, by an entry in a device table extracted from memory by the bus-attached device. An embodiment may have the beneficial effect of not having to store a large mapping table in the bus-attached device. Instead, the interrupt table used for mapping may be stored in a memory and accessed by the bus-attached device when necessary. Therefore, the bus-attached device may only need to process a working copy of one or more interrupt table entries for each interrupt signal to be forwarded. Preferably, the number of interrupt table entries may be small, such as one.

[0054] According to an embodiment, the IRT or individual IRTEs may be updated when a processor is rescheduled. According to an embodiment, the IRT may be stored in an internal section of memory (ie, the HSA).

[0055] According to an embodiment, the first copy of the interrupt table entry further includes a first copy of a run indicator, which indicates whether the target processor identified by the interrupt target ID is scheduled for use by the client operating system, wherein the method further includes using the first copy of the run indicator by the bus-attached device to check whether the target processor is scheduled for use by the client operating system, and if the target processor is scheduled, continuing to forward the interrupt signal, otherwise, using broadcasting by the bus-attached device to forward the interrupt signal to the multiple processors for processing.

[0056] Embodiments may have the effect of preventing interrupts from being directed to processors that are not running - ie processors that are not scheduled for use by a guest operating system. Embodiments may have the beneficial effect of enabling a hypervisor to reschedule a processor.

[0057] The run indicator indicates whether the target processor identified by the interrupt target ID received with the interrupt signal is scheduled for use by the client operating system. The run indicator can be implemented, for example, in the form of a run bit, i.e., a single bit, which indicates whether the processor assigned the corresponding bit is running, i.e., scheduled for use by the client operating system. Thus, an enabled run bit can tell the bus-attached device that the target processor is currently scheduled, while a disabled run bit can tell the bus-attached device that the target processor is currently not scheduled. If the target processor is not running, the bus-attached device can immediately send a backup broadcast interrupt request without trying to directly address one of the processors.

[0058] According to an embodiment, the method further includes, if the target processor is not blocked, changing, by the bus-attached device, an interrupt blocking indicator in an interrupt table entry assigned to the interrupt target ID to indicate that the first logical processor ID is blocked, the changing being performed before forwarding the interrupt signal to the target processor for processing.

[0059] According to an embodiment, the method further includes, after changing the interrupt blocking indicator, retrieving, by the bus-attached device, a second copy of the interrupt table entry assigned to the received interrupt target ID, checking, by the bus-attached device, the second copy of the interrupt table entry to exclude a predefined type of change of the second copy of the interrupt table relative to the first copy of the interrupt table entry, wherein successfully excluding the predefined type of change is required to forward the interrupt signal to the target processor for processing.

[0060] According to an embodiment, the predefined type of change is a change of a first mapping of a received interrupt target ID relative to a first mapping of the received interrupt target ID to a second logical processor ID in a logical processor ID contained by a second copy of the interrupt table entry, wherein if the second mapping includes a change relative to the first mapping, the interrupt signal is forwarded by the bus-attached device to the multiple processors for processing using a broadcast.

[0061] According to an embodiment, the predefined type of change is a change of a first copy of a run indicator relative to a second copy of the run indicator contained by an interrupt table entry, wherein, if the second copy of the run indicator includes a change relative to the first copy of the run bit, the second run indicator indicates that the target processor is not scheduled for use by the client operating system, and the bus-attached device uses broadcasting to forward the interrupt signal to the multiple processors for processing.

[0062] According to an embodiment, a double fetch of IRTE may be performed to prevent an interrupt signal from being sent to, for example, a processor that has been deactivated at the same time. According to various embodiments, after forwarding the interrupt signal to the processor identified by the logical processor ID generated by converting the interrupt target ID using the first copy of IRTE, a second copy of the same IRTE may be extracted to check whether any changes have occurred to IRTE at the same time. In the case where IRTE has been updated at the same time, there is a risk that the interrupt signal has been forwarded to the deactivated processor. Therefore, the interrupt target ID may be converted again with the second copy of IRTE, and the interrupt signal may be forwarded to the processor identified by the logical processor ID generated by the second conversion. According to an alternative embodiment, in the case where the second copy of IRTE does not match the first copy, the complete method starting from obtaining the first copy of IRTE may be repeated. For example, a third copy of IRTE may be extracted to replace the first copy of IRTE, or the first copy of IRTE may be replaced by the second copy of IRTE, and a third copy of IRTE may be extracted to implement a double fetch scheme also for partially repeating the method. This scheme may be repeated until a match is achieved. According to another alternative embodiment, in the case where the second copy of IRTE does not match the first copy, broadcasting may be used to forward the interrupt signal. According to an embodiment, the bus-attached device participates in a memory cache coherence protocol and detects changes on the IRTE through the same mechanism (eg, cache snooping) by which a CPU can detect cache line changes.

[0063] Embodiments may have the beneficial effect of avoiding cache flushes which may have inefficient scaling.Can be global or IRTE specific, ie the entire entry is double fetched or limited to specific information comprised by the corresponding entry.

[0064] According to an embodiment, the race condition caused by the time required to convert the interrupt target ID and forward the interrupt signal to the target processor until it reaches the processor can be captured by checking logic on the CPU to check whether the receiving processor is still the correct target processor until the interrupt signal reaches the processor. For inspection, the interrupt target ID and / or logical partition ID received with the interrupt request can be compared with the current interrupt target ID and / or logical partition ID assigned to the receiving processor as a reference. In the case of a match, the receiving processor directly addressed using the logical processor ID generated by the conversion of the copy of the IRTE is indeed the correct target processor. Therefore, the information provided by the copy of the IRTE is already up to date. In the case of a mismatch, the copy of the IRTE is not yet up to date, and the receiving processor is no longer the target processor. In the case of a mismatch, the interrupt signal can be forwarded to the target operating system, for example, using a broadcast.

[0065] According to an embodiment, there may be three entities operating in parallel, namely, a bus-attached device and a target processor that handles interrupt signals and a hypervisor that can change the assignment between interrupt target IDs and logical processor IDs. According to an embodiment, in a physically distributed system, there may be no central synchronization point other than a memory that provides a virtual appearance of such a system at the cost of latency. An embodiment using a double fetch scheme may have the beneficial effect of providing a method that is optimized for speed against double delivery or even loss of interrupt requests.

[0066] Regarding the interrupt signal, the following actions may be performed: A1) read a first copy of the IRTE, A2) send an interrupt request to the directly addressed processor, and A3) read a second copy of the IRTE. Meanwhile, regarding the change in the assignment between the interrupt target ID and the logical processor ID, the following sequence may occur: B1) activate an additional processor with the additional logical processor ID and deactivate the previous processor with the previous logical processor ID, and B2) update the IRTE with the additional logical processor ID, i.e., replace the previous logical processor ID with the additional logical processor ID.

[0067] In certain error situations, a processor (e.g., a target processor) may be reset to a checkpoint and lose intermediate information. To regain the lost information, the processor may scan all IRTE entries for that particular processor, i.e., assigned to its logical processor ID, and pass direct interrupt requests indicated by pending direct interrupt indicators (e.g., dPIA bits) present in memory that are not affected by processor recovery.

[0068] If an interrupt signal should be delivered, the pending direct interrupt indicator included by IRTE (e.g., the IRTE.dPIA bit) can be used as a master copy, i.e., a single point of truth. To simplify processor recovery, the pending direct interrupt indicator in the processor can be used as a shadow copy, such as the IRTE.dPIA bit, to maintain pending direct interrupts on the processor.

[0069] In the case of strict ordering of the memory, only the following order of steps A1, A2 and B1 may be possible: Alternative 1 with A1→A3→B1 and Alternative 2 with A1→B1→A3. In the case of Alternative 1, the first and second copies of IRTE may match. Therefore, the interrupt signal may be forwarded to the previous processor instead of the current target processor. The previous processor can see the mismatch of the interrupt target ID and / or logical partition ID and initiate a broadcast of the received interrupt signal. In the case of Alternative 2, the bus-attached device can see the mismatch between the first and second copies of IRTE. In response to the mismatch, the bus-attached device can broadcast the interrupt signal. Due to the broadcast, the interrupt signal can be received by additional processors that see the hit and directly handle the received interrupt request. An embodiment can have the beneficial effect of closing the timing window in an overly proactive manner.

[0070] According to an embodiment, the method further includes: retrieving, by the bus-attached device, a copy of a device table entry from a device table stored in a memory, the device table entry including a direct signaling indicator indicating whether a target processor is to be directly addressed, wherein, if the direct signaling indicator indicates direct forwarding of the interrupt signal, the target processor is directly addressed using the logical processor ID of the target processor to perform forwarding of the interrupt signal, otherwise, the bus-attached device forwards the interrupt signal to the multiple processors for processing using broadcasting.

[0071] Embodiments may have the beneficial effect of using a direct signaling indicator to control whether to use direct addressing or broadcasting to forward interrupt signals.Using the direct signaling indicator of each bus connection module, an individual predefined choice of whether to perform direct addressing or broadcasting may be provided for interrupt signals received from the bus connection module.

[0072] According to an embodiment, the device table entry further comprises an interrupt table address indicator indicating a first memory address of the interrupt table, the bus-attached device using the memory address of the interrupt table to retrieve the first copy of the interrupt table entry.

[0073] According to an embodiment, the memory further includes a directional interrupt summary vector having a directional interrupt summary indicator for each interrupt target ID, each directional interrupt summary indicator assigned to the interrupt target ID indicating whether there is an interrupt signal addressed to the corresponding interrupt target ID to be processed, and the method further includes updating, by the bus-attached device, the directional interrupt summary indicator assigned to the target processor ID addressed to the received interrupt signal using the memory address of the indicated directional interrupt summary vector, so that the updated directional interrupt summary indicator indicates that there is an interrupt signal addressed to the corresponding interrupt target ID to be processed.

[0074] According to an embodiment, the memory further includes a directional interrupt summary vector, the device table entry further includes a directional interrupt summary vector address indicator indicating the memory address of the directional interrupt summary vector, the directional interrupt summary vector includes a directional interrupt summary indicator for each interrupt target ID, each directional interrupt summary indicator assigned to the interrupt target ID indicates whether there is an interrupt signal addressed to the corresponding interrupt target ID to be processed, and the method further includes using the indicated memory address of the directional interrupt summary vector by the bus-attached device to update the interrupt summary indicator assigned to the target processor ID addressed by the received interrupt signal, so that the updated interrupt summary indicator indicates that there is an interrupt signal addressed to the corresponding interrupt target ID to be processed.

[0075] When an interrupt cannot be delivered directly, for example because the hypervisor has not scheduled a target processor, the guest operating system may benefit from using a broadcast to deliver an interrupt with the original intended affinity (i.e., information about which processor the interrupt is intended for). In this case, the bus-attached device can set a bit in the DISB that specifies the target processor after setting the DIBV and before sending the broadcast interrupt request to the guest operating system. If the guest operating system receives a broadcast interrupt request, it can identify which target processors have pending interrupt signals as indicated in the DIBV by scanning and disabling the direct interrupt summary indicators in the DISB (e.g., scanning and resetting the direct interrupt summary bits). Thus, the guest operating system can be enabled to decide whether the interrupt signal is handled by the current processor receiving the broadcast or forwarded further to the original target processor.

[0076] According to an embodiment, the memory further includes one or more interrupt signal vectors, the device table entry further includes an interrupt signal vector address indicator indicating a memory address of an interrupt signal vector of the one or more interrupt signal vectors, the interrupt signal vectors each including one or more signal indicators, each interrupt signal assigned to a bus connection module indicator and an interrupt target ID in the one or more bus connection modules indicating whether an interrupt signal addressed to the corresponding interrupt target ID has been received from the corresponding bus connection module, the method further comprising: selecting, by the bus-attached device, an interrupt signal indicator assigned to the bus connection module that issues the received interrupt signal and to the interrupt target ID addressed to the received interrupt signal using the indicated memory address of the interrupt signal vector,

[0077] According to an embodiment, the interrupt signal vectors each include an interrupt signal indicator assigned to each interrupt target ID of the corresponding interrupt target ID, each of the interrupt signal vectors is assigned to a single bus connection module, and the interrupt signal indicators of the corresponding interrupt signal vectors are further assigned to the corresponding single bus connection module.

[0078] According to an embodiment, the interrupt signal vectors each include an interrupt signal indicator assigned to each of the respective bus connection modules, each of the interrupt signal vectors is identified by a single target processor ID, and the interrupt signal indicator of the respective interrupt signal vector is further assigned to the respective target processor ID.

[0079] Therefore, the interrupt signal vector can be implemented as a directional interrupt signal vector that is sorted according to the target processor ID, i.e., optimized for tracking directional interrupts. In other words, the main order criterion is the target processor ID rather than the requester ID that identifies the bus connection module that issued the interrupt request. Depending on the number of bus connection modules, each directional interrupt signal vector may include one or more directional interrupt signal indicators.

[0080] Thus, sorting of interrupt signal indicators (e.g. in the form of interrupt signaling bits) indicating that a single interrupt signal (e.g. in the form of an MSI-X message) has been sequentially received within a contiguous region of memory (e.g., a cache line) of a single bus-connected module (e.g., a PCIe function) can be avoided. Enabling and / or disabling the interrupt signal indicator (e.g., by setting or resetting the interrupt signaling bit) requires transferring the corresponding contiguous region of memory to one of the processors to change the corresponding interrupt signal indicator accordingly.

[0081] A processor may process all indicators for which it is responsible from the perspective of the client operating system, i.e., in particular, all indicators assigned to the corresponding processor. This may achieve performance advantages because, in the case where each processor is processing all data assigned to the processor, the likelihood that the data required in this context is provided to the processor and / or stored in a local cache may be high, so that the processor's corresponding data can be quickly accessed without requiring a large amount of cache traffic.

[0082] However, each processor attempting to handle all indicators for which it is responsible may still result in higher cache traffic between processors, since each processor needs to write all cache lines for all functions, since the indicators assigned to each individual processor may be distributed over all contiguous areas, such as cache lines.

[0083] The interrupt signaling indicators can be reordered in the form of a directional interrupt signaling vector so that all interrupt signaling indicators assigned to the same interrupt target ID are combined in the same continuous area of ​​memory (e.g., cache line). Therefore, a processor that intends to process the indicator (i.e., interrupt target ID) assigned to the corresponding processor may only need to load a single continuous area of ​​memory. Therefore, a continuous area for each interrupt target ID is used instead of a continuous area for each bus connection module. Each processor may only need to scan and update a single continuous area of ​​memory, for example, a cache line of all interrupt signals targeted to a specific processor identified as the target processor by the interrupt target ID received from all available bus connection modules.

[0084] According to an embodiment, an offset may be applied by a hypervisor for a guest operating system to align bits to a different offset.

[0085] According to an embodiment, the device table entry further includes a logical partition ID identifying the logical partition to which the client operating system is assigned, wherein forwarding the interrupt signal by the bus-attached device further includes forwarding the logical partition ID along with the interrupt signal. Embodiments may have the beneficial effect of enabling a receiving processor to check which client operating system the interrupt signal is addressed to.

[0086] According to an embodiment, the method further comprises retrieving, by the bus-attached device, an interrupt subclass ID identifying the interrupt subclass to which the received interrupt signal is assigned, and forwarding, by the bus-attached device, the interrupt signal further comprises forwarding the interrupt subclass ID along with the interrupt signal.

[0087] According to an embodiment, instructions provided on a computer-readable non-transitory medium for execution by a processing circuit are configured to perform any embodiment of the method of providing an interrupt signal to a client operating system as described herein.

[0088] According to an embodiment, the computer system is further configured to perform any embodiment of the method of providing an interrupt signal to a client operating system as described herein.

[0089] Figure 1An exemplary computer system 100 for providing interrupt signals to a client operating system is depicted. The computer system 100 includes a plurality of processors 130 for executing a client operating system. The computer system 100 also includes a memory 140, also referred to as a memory storage or a main memory. The memory 140 may provide a memory space, i.e., a memory segment, allocated for use by the hardware, firmware, and software components included in the computer system 100. The memory 140 may be used by the hardware and firmware of the computer system 100 and software (e.g., a hypervisor, a host / client operating system, an application, etc.). One or more bus connection modules 120 are operably connected to the plurality of processors 130 and the memory 140 via a bus 102 and a bus attachment device 110. The bus attachment device 110 manages the communication between the bus connection module 120 and the processor 130 on the one hand, and the communication between the bus connection module 120 and the memory 140 on the other hand. The bus connection module 120 may be connected to the bus 102 directly or via one or more intermediate components such as a converter 104.

[0090] The bus connection module 120 may be provided, for example, in the form of a Peripheral Component Interconnect Express (PCIe) module (also known as a PCIe adapter or a PCIe function provided by a PCIe adapter). The PCIe function 120 may issue a request that is sent to a bus attachment device 110, such as a PCI host bridge (PHB), also known as a PCI bridge unit (PBU). The bus attachment device 110 receives the request from the bus connection module 120. These requests may, for example, include an input / output address for performing a direct memory access (DMA) to the memory 140 by the bus attachment device 110 or an input / output address indicating an interrupt signal (e.g., a message signaled interrupt (MSI)).

[0091] Figure 2 Depicted is exemplary virtual machine support provided by computer system 100. Computer system 100 may include one or more virtual machines 202 and at least one hypervisor 200. Virtual machine support may provide the ability to operate a large number of virtual machines, each capable of executing a client operating system 204, such as z / Linux. Each virtual machine 201 may be capable of acting as a separate system. Thus, each virtual machine may be independently reset, execute a client operating system, and run different programs, such as applications. An operating system or application running in a virtual machine may appear to have access to the entire and complete computer system. In reality, however, only a portion of the available resources of the computer system are available to the corresponding operating system or application.

[0092] Virtual machines may use a V=V model in which memory allocated to a virtual machine is backed by virtual memory rather than real memory. Thus, each virtual machine has a virtual linear memory space. Physical resources are owned by a hypervisor 200 (e.g., a VM hypervisor), and the hypervisor allocates shared physical resources to client operating systems as needed to meet the processing needs of the client operating systems. The V=V virtual machine model assumes that the interaction between the client operating system and the physical shared machine resources is controlled by the VM hypervisor, because a large number of guests may prevent the hypervisor from simply dividing and allocating hardware resources to configured guests.

[0093] Processor 120 may be assigned to virtual machine 202 by hypervisor 200. Virtual machine 202 may, for example, be assigned one or more logical processors. Each logical processor may represent all or part of a physical processor 120 that may be dynamically assigned to virtual machine 202 by hypervisor 200. Virtual machine 202 is managed by hypervisor 200. Hypervisor 200 may, for example, be implemented in firmware running on processor 120 or may be part of an operating system executing on computer system 100. Hypervisor 200 may, for example, be a VM hypervisor, such as provided by International Business Machines Corporation of Armonk, New York, USA.

[0094] Figure 3 Depicted is an exemplary multi-level virtual machine support provided by computer system 100. Figure 2 In addition to the first level virtualization, a second level virtualization with a second hypervisor 210 is provided, the second hypervisor 210 is executed on one of the first level guest operating systems, and the first level guest operating system acts as a host operating system for the second hypervisor 210. The second hypervisor 210 can manage one or more second level virtual machines 212, each of which can execute a second level guest operating system 212.

[0095] Figure 4An exemplary mode showing the use of different types of IDs to identify processors at different levels of the computer system 100 is depicted. The underlying firmware 220 may provide a logical processor ID, ICPU 222, to identify the processor 130 of the computer system 100. The first-level hypervisor 200 communicates with the processor 130 using the logical processor ID ICPU 222. The first-level hypervisor may provide a first virtual processor ID vCPU 224 for use by a client operating system 204 or a second-level hypervisor 210 executing on a virtual machine managed by the first-level hypervisor 200. The hypervisor 200 may group the first virtual processor ID vCPU 224 to provide a logical partition, also known as a zone, for the client operating system 204 and / or the hypervisor 210. The first-level hypervisor 200 maps the first virtual processor ID vCPU 224 to the logical processor ID lCPU 222. One or more first virtual processor ID vCPUs 224 provided by the first-level hypervisor 200 may be assigned to each client operating system 204 or hypervisor 210 executing using the first-level hypervisor 200. The second level hypervisor 210 executing on the first level hypervisor 200 can provide one or more virtual machines that execute software such as another client operating system 214. To this end, the second level hypervisor manages the second virtual processor ID vCPU 226 for use by the second level client operating system 214 executing on the virtual machine of the first level hypervisor 200. The second virtual processor ID vCPU 226 is mapped to the first virtual processor ID vCPU 224 by the second level hypervisor 200.

[0096] The bus connection module 120 used by the first / second level guest operating system 204 to address the processor 130 may use the first / second virtual processor ID vCPU 224 , 226 or a target processor ID in the form of an alternative ID derived from the first / second virtual processor ID vCPU 224 , 226 .

[0097] Figure 5A simplified schematic setup of a computer system 100 is depicted, showing the main players in a method for providing an interrupt signal to a client operating system executing on the computer system 100. For purposes of illustration, the simplified setup includes a bus connection module (BCM) 120 that sends an interrupt signal to a client operating system executing on one or more processors (CPUs) 130. The interrupt signal is sent to a bus attachment device 110 along with an interrupt target ID (IT_ID) that identifies one of the processors 130 as a target processor. The bus attachment device 110 is an intermediary device that manages communications between the bus connection module 120 and the processors 130 and memory 140 of the computer system 100. The bus attachment device 110 receives the interrupt signal and uses the interrupt target ID to identify the logical processor ID of the target processor in order to directly address the corresponding target processor. Directed forwarding to the target processor can improve the efficiency of data processing, for example, by reducing cache traffic.

[0098] Figure 6 Depicted Figure 5 The computer system 100 of claim 1. The bus-attached device 110 is configured to perform a status update on a status of the bus-attached module 120 in a module specific area (MSA) 148 of the memory 140. This status update may be performed in response to receiving a direct memory access (DMA) write from the bus-attached module specifying a status update to be written to the memory 140.

[0099] The memory further includes a device table (DT) 144 for each bus connection module 120. Upon receiving an interrupt signal (e.g., an MSI-X write message having an interrupt target ID identifying the target processor of the interrupt request and a requester ID identifying the origin of the interrupt request in the form of a bus connection module 120), the bus attachment device 110 extracts a DTE 146 assigned to the bus connection module 120 that issued the request. The DTE 146 may, for example, use a dIRQ bit to indicate whether directional addressing of the target processor is enabled for the bus connection module 120 that issued the request. The bus attachment device updates a directional interrupt signal vector (DIBV) 162 and a directional interrupt summary vector (DISB) 160 to track which processor of the processors 130 the interrupt signal was received for. The DISB 160 may include one entry for each interrupt target ID, indicating whether there is an interrupt signal from any bus connection module 120 to be processed by the processor 130. Each DIBV 162 is assigned to one of the interrupt target IDs (i.e., processors 130) and may include one or more entries. Each entry is assigned to one of the bus connection modules 120. Thus, the DIBV indicates from which bus connection modules there are pending interrupt signals for a particular processor 130. This may have the following advantages: in order to check whether there are any interrupt signals or from which bus connection modules there are pending interrupt signals for a particular processor 130, only a signal entry (e.g., a bit) or a signal vector (e.g., a bit vector) needs to be read from the memory 140. According to an alternative embodiment, an interrupt signal vector (AIBV) and an interrupt summary vector (AISB) may be used. The entries of the AIBV and the AISB are each assigned to a particular bus connection module 120.

[0100] The bus-attached device 110 uses an entry (IRTE) 152 of an interrupt table (IRT) 150 stored in memory 140 to convert the interrupt target ID (IT_ID) to a logical processor ID (ICPU) and use the logical processor ID to directly address the target processor and forward the received interrupt signal to the target processor. For the conversion, the bus-attached device 110 obtains a copy 114 of the entry (IRTE) 152. The copy may be obtained from a local cache or from memory 140 using the address (IRT@) of the interrupt table 150 provided by the copy of the DTE 146. The IRTE 152 provides a mapping of the interrupt target ID to the logical processor ID, which is used by the bus-attached device 110 to directly address the target processor in the case of directed interrupt forwarding.

[0101] IRTE 152 additionally provides a running indicator 154 indicating whether the target processor identified by the interrupt target ID is scheduled (i.e., whether it is running) and / or a blocking indicator 146 indicating whether the target processor is currently blocked from receiving interrupt signals. In the case where the target processor is not scheduled or blocked, a broadcast may be initiated to enable timely interrupt processing.

[0102] Each processor includes firmware (e.g., millicode 132) for receiving and processing direct interrupt signals. The firmware may further include, for example, microcode and / or macrocode of the processor 130. It may include hardware-level instructions and / or data structures used in the implementation of higher-level machine code. According to various embodiments, it may include proprietary code that can be delivered as a microcode including trusted software or a microcode specific to the underlying hardware and controls operating system access to system hardware. In addition, the firmware of the processor 130 may include a check logic 134 for checking whether the receiving processor is the same as the target processor based on the interrupt target ID forwarded to the receiving processor 130 by the bus-attached device 110. In the case where the receiving processor 130 is not the target processor, that is, in the case where the received interrupt target ID does not match the reference interrupt target ID of the receiving processor 130, the interrupt signal is broadcast to the logical partition to find a processor for processing the interrupt signal.

[0103] Figure 7 Flowchart of an exemplary method for performing a state update of a bus connection module 120 via a bus attachment device 110 using a DMA write request. In step 300, the bus connection module may decide to update its state and trigger an interrupt, for example, to indicate that the signal is complete. In step 310, the bus connection module initiates a direct memory access (DMA) write to a memory segment (host memory) allocated to a host running on a computer system via the bus attachment device to update the state of the bus connection module. DMA is a hardware mechanism that allows peripheral components of a computer system to transfer their I / O data directly to and from the main memory without involving the system processor. To perform DMA, the bus connection module sends a DMA write request to the bus attachment device, for example in the form of an MSI-X message. In the case of PCIe, the bus connection module may, for example, refer to a PCIe function provided on a PCIe adapter. In step 320, the bus connection module receives a DMA write request with a state update of the bus connection module and updates the memory using the received update. The update may be performed in an area of ​​the host memory reserved for the corresponding bus connection module.

[0104] Figure 8 is for use Figure 6Flowchart of an exemplary method for providing an interrupt signal to a client operating system by a computer system 100 of the present invention. In step 330, the bus-attached device receives an interrupt signal sent by a bus connection module (e.g., in the form of an MSI-X write message). The transmission of the interrupt signal can be performed according to the specification of the PCI architecture. The MSI-X write message includes an interrupt target ID that identifies the target processor of the interrupt. The interrupt target ID can be, for example, a virtual processor ID used by the client operating system to identify the processor of a multi-processor computer system. According to an embodiment, the interrupt target ID can be any other ID agreed upon by the client operating system and the bus connection module in order to be able to identify the processor. Such another ID can be, for example, the result of a mapping of the virtual processor ID. In addition, the MSI-X write message can also include an interrupt requester ID (RID) (i.e., the ID of the PCIe function that issues the interrupt request), a vector index that defines the offset of the vector entry within the vector, an MSI address (e.g., a 64-bit address), and MSI data (e.g., 32-bit data). The MSI address and the MSI data can indicate that the corresponding write message is actually an interrupt request in the form of an MSI message.

[0105] In step 340, the bus-attached device obtains a copy of an entry of a device table stored in memory. The device table entry (DTE) provides an address indicator of one or more vectors or vector entries to be updated to indicate that an interrupt signal has been received for a target processor. The address indicator of a vector entry may, for example, include the address of the vector in memory and an offset within the vector. In addition, the DTE may provide a direct signaling indicator that indicates whether the target processor will be directly addressed by the bus-attached device using an interrupt target ID provided with the interrupt signal. In addition, the DTE may provide a logical partition ID (also known as a zone ID) and an interrupt subclass ID. The corresponding copy of the device table entry may be obtained from a cache or from memory.

[0106] In step 342, the bus attached device retrieves a copy of the IRTE from memory using the interrupt target ID received with the interrupt signal and the address indicator of the memory indicating the IRT provided by the DTE. In step 350, the bus attached device updates the vector specified in the DTE.

[0107] In step 360, the bus-attached device checks the direct signaling indicator provided with the interrupt signal. In the case where the direct signaling indicator indicates indirect signaling, the bus-attached device forwards the interrupt signal by broadcasting using the region identifier and the interrupt subclass identifier in step 370 so as to provide the interrupt signal to the processor used by the client operating system. In the case where the direct signaling indicator indicates direct signaling, the bus-attached device further checks in step 362 whether the running indicator included in the copy of the IRTE indicates that the target processor identified by the interrupt target ID is running.

[0108] In the event that the target processor is not running, in step 364, the bus-attached device uses, for example, a logical partition ID and / or an interrupt subclass ID to send a broadcast interrupt as a backup to identify a processor suitable for handling the interrupt. If no suitable processor matching the logical partition ID and / or interrupt subclass ID is found, the hypervisor, i.e., the processor assigned for use by the hypervisor, can receive the interrupt request instead of the processor assigned to the client operating system. If one or more processors assigned to the client operating system are scheduled, the hypervisor can decide to broadcast the interrupt request again. On the entry for the processor assigned to the operating system, the hypervisor can check a direct interrupt pending indicator, such as a dPIA bit, to be submitted to the entering processor. According to an embodiment, the hypervisor can, for example, selectively reschedule (i.e., wake up) the target processor.

[0109] In the case where the target processor is running, in step 366, a check is made as to whether a direct interrupt blocking indicator, such as the diBPIA bit, is enabled. An enabled direct interrupt blocking indicator indicates that the client operating system interrupt handler does not currently want interrupt delivery. Therefore, if the direct interrupt blocking indicator is enabled, an interrupt signal may be broadcast in step 368. If the direct interrupt blocking indicator is disabled, indicating that the target processor is not currently blocked, in step 380, delivery of the current interrupt signal is continued by converting the received interrupt target ID so that the interrupt is forwarded directly to the target processor using the logical processor ID provided by the IRTE of the received interrupt target ID.

[0110] In step 390, the bus-attached device forwards the interrupt signal to the target processor by directly addressing the corresponding processor using the logical processor ID, that is, sending a direct message. The direct message may further include a zone ID and / or an interrupt subclass ID. In step 396, the firmware (e.g., millicode) of the target processor receives the interrupt. In response, the firmware may interrupt its activities, such as program execution, and switch to execute the interrupt handler of the client operating system. The interrupt may be submitted to the client operating system together with a direct signaling indication. In the case where the implementation check logic is implemented on the receiving processor, a check may be performed to check whether the received interrupt target ID and / or logical partition ID matches the interrupt target ID and / or logical partition currently assigned to the receiving processor and available for the check logic. In the case of a mismatch, the receiving firmware may initiate a broadcast and use the logical partition ID and / or interrupt subclass ID to identify the valid target processor for handling the interrupt, broadcasting the received interrupt request to the remaining processors.

[0111] Fig. 98 is an additional flow chart further illustrating the method of FIG. 8 . First, an interrupt message may be sent to a bus-attached device. It may be checked whether the DTE assigned to the interrupt requester (i.e., the bus connection module) is cached in a local cache operably connected to the bus-attached device. In the case where the DTE is not cached, the corresponding DTE may be retrieved from a memory by the bus-attached device. The vector address indicator provided by the DTE may be used to set a vector bit in the memory. Then, in step 410, a direct signaling indicator provided by the DTE is used to check whether the target processor is to be directly addressed by the bus-attached device using an interrupt target ID provided with the interrupt signal. If the target processor is not to be directly targeted, the method continues to broadcast the interrupt request to the processor. If the target processor is to be directly targeted, then in step 413, the method continues to obtain a copy of the IRTE assigned to the received interrupt target ID from the memory. In step 413a, it is checked whether the run indicator contained by the IRTE is enabled. In the case where the run indicator is disabled, in step 413b, the bus-attached device may use broadcasting to forward the interrupt signal. In the case where the run indicator is enabled, the bus-attached device continues to check whether the directional blocking indicator is enabled in step 413c. In the case where the directional blocking indicator is not enabled, the bus-attached device continues to use the obtained IRTE copy to convert the interrupt target ID to the logical processor ID in step 414. Otherwise, the interrupt signal can be suppressed in step 413d. In step 416, the target processor is directly addressed using the logical processor ID, and a message forwarding the interrupt signal is sent to the target processor. The message includes the interrupt target ID, the logical partition ID, and the interrupt subclass ID. In step 418, the processor receives the message. In step 419, the processor checks whether the interrupt target ID and / or the logical partition ID match the current interrupt target ID and / or the logical partition ID provided as a reference for the check. In the case of a match, the processor submits the interrupt request to the client operating system in step 420. In the case of a mismatch, the processor broadcasts the interrupt request to other processors in step 422. The processor then continues its activities until the next interrupt message is received.

[0112] Fig.10A method for performing an exemplary double fetching scheme to ensure that the IRTE used is up to date is depicted. In step 500, an interrupt signal (e.g., an MSI-X message) is sent from a bus connection module 120 (e.g., a PCIe adapter or a PCIe function on a PCIe adapter) to a bus attachment device 110 (e.g., a PCIe host bridge (PHB)). In step 502, the bus attachment device 110 requests a first copy of the IRTE for the interrupt target ID provided with the interrupt signal from the memory 140. In step 504, the memory 140 sends a copy of the IRTE in response to the request. The point in time at which the copy of the IRTE is sent marks the last point in time at which the IRTE is indeed up to date. At this point in time, a time window begins during which the IRTE may be updated and the data provided by the first copy of the IRTE may be outdated. The time window ends with the interrupt being processed by the target processor 130. From this point in time, any changes in the IRTE no longer have an impact on the processing of the received interrupt signal. In step 506, the bus connection unit 110 sends a request to the IRTE to enable a directed pending interrupt indicator, for example, by setting a bit in the directed pending interrupt array (dPIA). The enabled directed pending interrupt indicator indicates that a directed interrupt for an interrupt target ID is pending. In step 508, the setting of the directed pending interrupt indicator is confirmed by the memory 140. In step 510, the interrupt signal is forwarded to the target processor 130 in the form of a directed interrupt request using direct addressing, and the target processor 130 is identified by a logical processor ID generated by converting the interrupt target ID using the IRTE. When the target processor 130 receives the directed interrupt request, the time window is closed. In step 512, when the time window is closed, the bus attachment device 110 reads a second copy of the IRTE from the IRTE provided in the memory 140. In step 514, upon receiving the second copy of the requested IRTE, the bus-attached device 110 checks whether the second copy of the IRTE matches the first copy of the IRTE, i.e., whether the IRTE, in particular the mapping of the interrupt target ID, has changed. In case of a match, the method ends with resetting the directed pending interrupt indicator in the IRTE by the target processor 130 after submitting the interrupt request to the client operating system and processing the request. In case of a mismatch, the method may continue with step 502. Alternatively, the method may continue with the bus-attached device 110 broadcasting the received interrupt signal.

[0113] Fig.11Another method of performing a double fetch of the IRTE to ensure that the information provided by the IRTE is up to date is depicted. In step 600, an interrupt signal (e.g., an MSI-X message) is sent from a bus connection module 120 (e.g., a PCIe adapter or a PCIe function on a PCIe adapter) to a bus attachment device 110 (e.g., a PCIe host bridge (PHB)). In step 602, the bus attachment device 110 requests a copy of the IRTE assigned to the interrupt target ID provided with the interrupt signal from the memory 140. In step 604, the memory 140 sends a first copy of the IRTE in response to the request. The first copy includes: a run indicator indicating that the target processor is scheduled (e.g., a run bit R=1); a directional interrupt blocking indicator indicating that the target processor is not currently blocked from receiving the interrupt signal (e.g., a directional blocking bit dIBPIA=0); and a logical processor ID lCPU. The bus attachment device 110 directly addresses the target processor 130 using the logical processor ID lCPU. Since the run indicator indicates that the target processor 130 is running, in step 606, the bus-attached device 110 enables the directional interrupt pending indicator, such as setting dPIA=1, and blocks the target processor from receiving further interrupts, such as setting dIBPIA=1 in IRTE. In order to check that the content of IRTE has not changed during this period (for example, the target processor 130 is disabled), the critical time window is closed by requesting a re-read of IRTE in step 608. In step 610, the memory 140 sends a second current copy of IRTE in response to the request. The second copy includes a run indicator indicating that the target processor 130 is still scheduled (for example, the run bit R=1), a directional interrupt blocking indicator enabled by the bus-attached device, and the same logical processor ID lCPU as the lCPU provided by the first copy of IRTE. Since the run indicator and lCPU have not changed, the method continues in step 612, using lCPU to send an interrupt request directly addressed to the target processor 130. The target processor 130 submits the interrupt to the client operating system and handles the interrupt. When the interrupt processing is complete, the target processor 130 disables the directional interrupt pending indicator (eg, resets dPIA=0) and the directional interrupt blocked indicator (eg, resets dIBPIA=0).

[0114] Fig.12An alternative flow chart of the method of FIG. 16 is depicted, which illustrates a situation where the information contained by the IRTE changes during operation. In step 600, an interrupt signal (e.g., an MSI-X message) is sent from a bus connection module 120 (e.g., a PCIe adapter or a PCIe function on a PCIe adapter) to a bus attachment device 110 (e.g., a PCIe host bridge (PHB)). In step 602, the bus attachment device 110 requests a copy of the IRTE assigned to the interrupt target ID provided with the interrupt signal from the memory 140. In step 604, the memory 140 sends a first copy of the IRTE in response to the request. The first copy includes a run indicator (e.g., a run bit R=1) indicating that the target processor 130 is scheduled and a logical processor ID lCPU. The bus attachment device 110 directly addresses the target processor 130 using the logical processor ID lCPU. Since the run indicator indicates that the target processor 130 is running, in step 606, the bus-attached device 110 enables the directional interrupt pending indicator (e.g., sets dPIA=1) and blocks the target processor from receiving further interrupts (e.g., sets dIBPIA=1 in IRTE). In order to check that the contents of IRTE have not been changed during this period (e.g., the target processor 130 has been disabled), the critical time window is closed by requesting a re-read of IRTE in step 608. In step 610, the memory 140 sends a second current copy of IRTE in response to the request. In this example, the target processor 130 has been disabled to the client operating system during this period. Therefore, the second copy includes a run indicator (e.g., run bit R=0) indicating that the target processor 130 is no longer scheduled. The logical processor ID lCPU may be the same as the lCPU provided by the first copy of IRTE, or it may be different. The directional interrupt blocking indicator is still enabled by the bus-attached device. Since the run indicator and / or lCPU have indeed changed, the method continues in step 612 to send an interrupt request to the processor using a broadcast.

[0115] Fig.13 An exemplary DTE 146 is depicted that includes the memory address IRT@ of the IRT assigned to the interrupt target ID, the logical partition ID (region), and the offset (DIBVO) within the DIBV. The DIBVO identifies the beginning of the portion or entry of the vector assigned to a particular bus connection module. An interrupt signal (e.g., an MSI-X message) may provide a DIBV Idx that, when added to the DIBVO, identifies the particular entry of the vector assigned to the bus connection module. In addition, a number of directional interrupts (NOI) is provided that defines the maximum number of bits reserved in the DIBV for the corresponding bus connection module. Fig.16A Further details of DIBV are shown in . In the case of AIBV, Fig. 16BAs shown, DTE can provide corresponding AIBV specific parameters.

[0116] Also depicted is an exemplary IRTE 152. The IRTE 152 may include a logical partition ID (zone) assigned to the interrupt target ID of the target processor, an interrupt subclass ID (DISC), a memory address DISB@ of the DISB, an offset DISBO within the DISB, and a memory address DIBV of the DIBV.

[0117] Fig.14 A schematic structure of a DISB 160 and a plurality of DIBVs 162 is depicted. The DISB 160 may be provided in the form of a continuous memory segment, for example, in the form of a cache line, which includes an entry 161, for example, a bit, for each interrupt target ID. Each entry indicates whether there is an interrupt request (IRQ) to be processed by a corresponding processor identified by the interrupt target ID. A DIBV 162 is provided for each interrupt target ID (i.e., an entry of the DISB 160). Each DIBV 162 is assigned to a specific interrupt target ID and includes one or more entries 163 for each bus connection module MN A, MN B. Each DIBV 162 may be provided in the form of a continuous memory segment, for example, in the form of a cache line, which includes entries 163 assigned to the same interrupt target ID. The entries of different bus connection modules may be in a sequence of DIBVOs using different offset addresses for each bus connection module.

[0118] Fig.15 A schematic structure of an AISB 170 and a plurality of AIBVs 172 is depicted. The AISB 170 may be provided in the form of a continuous memory segment, for example, in the form of a cache line, which includes entries 171, for example bits, for each bus connection module MN A to MN D. Each entry indicates whether there is a pending interrupt request (IRQ) from the corresponding bus connection module. An AIBV 172 is provided for each bus connection module (i.e., an entry of the AISB 170). Each AIBV 172 is assigned to a specific bus connection module and one or more entries 173 for each interrupt target ID. The AIBVs 172 may each be provided in the form of a continuous memory segment, for example, in the form of a cache line, which includes entries 173 assigned to the same bus connection module. The entries regarding different bus connection modules may be in a sequence using different offset AIBVOs for each bus connection module.

[0119] Fig.17A and 17BAn exemplary DISB 160 and AISB 170 are shown, respectively. Entries 161, 171 may be addressed using a combination of base addresses DISB@ and AISB@ and offset addresses DISBO and AISBO, respectively. In the case of DISB 160, for example, DISBO may be the same as the interrupt target ID to which the corresponding entry 161 is assigned. The interrupt target ID may be provided, for example, in the form of a virtual processor ID (vCPU).

[0120] Fig.18A and 18B An exemplary method for providing an interrupt signal to a client operating system is shown. In step 704, a bus connection module (BCM) (e.g., a virtual function on a PCI adapter, i.e., a PCI adapter (VF)) sends an interrupt signal. The interrupt signal can be sent, for example, in the form of an MSI-X message MSI-X (VF, vCPU, DIBV Idx), including an identifier of the virtual function VF (e.g., in the form of a virtual processor ID vCPU), an interrupt target ID, and an offset (e.g., DIBV Idx) within a directional interrupt signal vector of an entry (e.g., a bit) contained in an identification vector. In step 706, a bus attachment device (BAD) (e.g., a PCI host bridge (PHB) also known as a PCI bridge unit (PBU)) receives the interrupt signal.

[0121] In step 708, the PBU reads the entry of the device table (DT) assigned to the VF. The DT entries stored in the hardware system area (HSA) of the memory are shown in the rows of the table. The entries of the DT may include the address of the interrupt table (IRT@) and the directional signaling bit indicating whether directional signaling is to be performed. The PBU uses IRT@ to obtain the IRT entry assigned to the vCPU from the HSA, which includes a run bit (R) indicating whether the vCPU is running, a directional interrupt blocking bit (dIBPIA) indicating whether the vCPU is blocked from receiving interrupts, and a directional interrupt pending bit (dPIA) indicating whether the interrupt directed to the vCPU is in a pending state. At an earlier point in time in step 700, a start interpretive execution instruction (SIE-entry) has been issued, which initiates a state change of the target processor from hypervisor mode to client mode. In step 701, the R in the IRTE assigned to the target processor and the logical processor ID (TrgtPU#) of the provided target processor is set to 1. Then, the method ends with 702. For firmware and hardware, TrgtPU# refers to the physical ID of a processing unit (1 physical PU), while for zOS and logical partitions (LPAR), TrgtPU# refers to the logical ID of a processing unit (logical PU).

[0122] In step 710, the PBU sets a bit in the DIBV assigned to the vCPU using the DIBV Idx in the MSI-X to indicate that there is an interrupt signal from the VF for the vCPU. In step 712, the PBU checks whether IRTE is blocked, i.e., whether IRTE.dIBIA == 1. If IRTE is assigned to the vCPU, and therefore the vCPU is blocked from receiving further interrupts, the method ends with step 714. If IRTE is not blocked, the method continues with step 716, in which the PBU checks whether the vCPU is running, i.e., whether R is set in IRTE.

[0123] If R is set, the method continues to step 718 to perform directed addressing. In step 718, dlBPIA and dPIA are set to 1 in IRTE, indicating that the vCPU is currently blocked from receiving interrupt signals and that the interrupt addressed to the vCPU is pending. In step 720, it is checked whether IRTE (more precisely, the state of R and / or TrgtPU# of IRTE) has changed compared to the IRTE in step 718. In this way, a double extraction scheme is implemented in which the IRTE is read twice to ensure that no relevant changes have occurred between the two reads (for example, due to the SIE-entry of another client as shown in step 722).

[0124] In step 722, the SIE-entry instruction of another client is executed on the target processor. In step 724, the other client reads the IRTE of the previous client and issues an atomic reset command of R in step 726, i.e., sets R=0 and indicates that the vCPU is no longer running. In addition, dPIA is read from IRTE. In step 728, check whether dPIA is set (IRTE.dPIA==1) - if it is set, it indicates that there are still interrupts pending for the vCPU. If no interrupt is pending, the method ends with step 730. If there is still an interrupt pending, then in step 732, reset the pending interrupt indicator PU.dPIA of the target PU and IRTE.dPIA of IRTE, and start broadcasting for the pending interrupt. Therefore, if the relevant change of IRTE is determined in step 720, the interrupt is broadcast.

[0125] If no relevant change of IRTE is determined in step 720, the method continues to step 734. In step 734, the interrupt signal (Directed PCI-Interrupt SYSOP) is directed forwarded to the target PU, also known as the directed PU. In step 736, the directed PU receives the directed PCI interrupt, and in step 738, the pending interrupt indicator PU.dPIA about the directed PU is set. In step 739, it is checked whether the directed PU is masked, that is, it is usually blocked from receiving and executing interrupts. If the directed PU is masked, the method ends with step 740. If the directed PU is unmasked (for example, due to the unmasking shown in step 742), the method continues in step 744 by executing the interrupt through the firmware (e.g., millicode) (mCode IO Irpt) of the directed PU. In step 746, PU.dPIA and IRTE.dPIA are reset to indicate that the interrupt is no longer pending.

[0126] In step 748, the operating system interrupt handler (OS IO Irpt) is called, and in step 750, the DIBV bit set in step 710 is read and reset. In step 752, a loop is performed on all DIBV bits of the DIBV assigned to the target PU (i.e., the directed PU). Thus, all interrupts for the target PU can be processed in succession. In the case that all DIBV bits have been processed, the target PU is unblocked (SIC.OC17) by resetting IRTE.dIBPIA in step 754. In addition, the DIBV is reread to determine in step 756 whether another DIBV bit is set in the meantime. If this is the case, the corresponding interrupt is processed, otherwise the method ends with step 758.

[0127] If the result of the check in step 716 is that R is not set, the method continues to step 760 to perform a broadcast as a backup. In step 760, the directional interrupt summary indicator in the directional interrupt summary vector is enabled, for example, a position is set. Each bit of the interrupt summary vector is assigned to a CPU, indicating whether there is any interrupt to be processed by the corresponding CPU. The interrupt is broadcast (SIGI.enq.IBPIA) in step 764 and received by any PU in step 766. In step 768, the blocking bit of the corresponding PU in IBPIA is set, indicating that the PU is currently blocked from receiving interrupts. In step 770, it is checked whether IBPIA has changed due to setting the blocking bit, that is, whether IBPIA 0→1. If IBPIA has not changed, that is, it has been blocked, the method ends with step 772. If IBPIA has changed, then in step 774, the pending bit set by the corresponding PU in PIA is set. In step 776, it is checked whether the PU is masked, that is, it is usually blocked from receiving and executing interrupts. If the PU is masked, the method ends with step 778. If the PU is unmasked (e.g., due to the unmasking shown in step 780), the method continues with the firmware (e.g., millicode) execution interrupt of the PU (mCode IO Irpt) in step 782. In step 784, the pending bit in the PIA is reset to indicate that the interrupt is no longer pending.

[0128] In step 786, the operating system interrupt handler (OS IO Irpt) is called, and in step 788, the DISB bit set in step 760 is read and reset. In steps 790 and 792, the corresponding directional PU is signaled that the interrupt is processed. In step 794, all DISB bits of the DISB array are looped, each bit being assigned to another PU. The DISB summarizes all interrupts to be processed by broadcast. The interrupts are sorted according to the PU they are targeted for. Therefore, all interrupts to be processed by broadcast can be processed by the PU. If all DISB bits have been processed, the PU is unblocked (SIC.OC1) by resetting IBPIA in step 796. In addition, the DISB is reread to determine in step 798 whether another DISB bit has been set in the meantime. If this is the case, the corresponding interrupt is processed, otherwise the method ends with step 799.

[0129] The client operating system may be implemented, for example, using a pageable memory mode client. For example, The pageable guest in the second interpretation layer can be interpreted and executed by the Start Interpretive Execution (SIE) instruction. For example, the logical partition (LPAR) management program executes the SIE instruction to start the logical partition in the physical, fixed memory. The operating system (e.g., ) can issue SIE instructions to execute the guest (virtual) machines in its virtual storage. Therefore, the LPAR hypervisor can use level 1 SIE, A hypervisor may use a level 2 SIE.

[0130] According to various embodiments, the computer system is provided by International Business Machines Corporation System Server. System Based on the IBM 6000 FPGA provided by International Business Machines Corporation about The details of the z / Architecture Principles of Operation are given in the paper entitled "z / Architecture Principles of Operation" ( The invention is described in the publication of WO20130119844, Publication No. SA22-7832-11, August 25, 2017, which is hereby incorporated by reference in its entirety. System and is a registered trademark of International Business Machines Corporation, Armonk, New York, U.S.A. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.

[0131] According to various embodiments, computer systems of other architectures may implement and use one or more aspects of the present invention. Servers other than servers (e.g., Power Systems servers or other servers provided by International Business Machines Corporation) or servers of other companies implement, use and / or benefit from one or more aspects of the present invention. Further, although in the examples herein, the bus connection module and the bus attachment device are considered as part of the server, in other embodiments, they do not necessarily have to be considered as part of the server, but can simply be considered as being coupled to the system memory and / or other components of the computer system. The computer system does not have to be a server. Further, although the bus connection module can be PCIe, one or more aspects of the present invention can be used with other bus connection modules. PCIe adapters and PCIe functions are only examples. Further, one or more aspects of the present invention can be applied to interrupt schemes other than PCIMSI and PCIMSI-X. Further, although examples in which bits are set are described, in other embodiments, bytes or other types of indicators can be set. In addition, DTE and other structures can include more, less or different information.

[0132] In addition, other types of computer systems may benefit from one or more aspects of the present invention. As an example, a data processing system that is suitable for storing and / or executing program code and includes at least two processors that are directly or indirectly coupled to a memory element through a system bus is available. The memory element includes, for example, a local memory, a mass storage device, and a temporary storage of at least some program codes that is provided to reduce the number of times that code must be retrieved from a mass storage device during execution.

[0133] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, DASD, tapes, CDs, DVDs, thumb drives and other storage media, etc.) may be coupled to the system either directly or through intervening I / O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems and Ethernet cards are just a few of the available types of network adapters.

[0134] Reference Fig.19, depicts representative components of a host computer system 800 for implementing one or more aspects of the present invention. The representative host computer 800 includes one or more processors (e.g., CPUs) 801 in communication with a computer memory 802, and an I / O interface connected to a storage media device 811 and a network 810 for communicating with other computers or SANs, etc. The CPU 801 conforms to an architecture having an architecture instruction set and an architecture function. The CPU 801 may have a dynamic address translation (DAT) 803 for translating program addresses, virtual addresses, into real addresses of memory. The DAT may include a translation lookaside buffer (TLB) 807 for caching translations, so that later access to blocks of the computer memory 802 does not require delays in address translation. A cache 809 may be employed between the computer memory 802 and the CPU 801. The cache 809 may be hierarchically structured, thereby providing a large high-level cache that can be used for more than one CPU and a smaller, faster, lower-level cache between the high-level cache and each CPU. In some embodiments, the lower-level cache may be divided into independent low-level caches that provide for instruction fetching and data access. According to an embodiment, the instruction may be obtained from the memory 802 by the instruction fetch unit 804 via the cache 809. The instruction may be encoded in the instruction decode unit 806 and, in some embodiments, dispatched to one or more instruction execution units 808 along with other instructions. Several execution units 808 may be employed, such as an arithmetic execution unit, a floating point execution unit, and a branch instruction execution unit. The instruction is executed by the execution unit, accessing operands from registers or memories specified by the instruction as needed. If an operand is to be accessed (e.g., loaded or stored) from the memory 802, the load / store unit 805 may handle the access under the control of the instruction being executed. The instruction may be executed in hardware circuits or in internal microcode (i.e., firmware) or by a combination of both.

[0135] A computer system may include information in local or main storage, as well as addressing, protection, and reference and change records. Some aspects of addressing include the format of addresses, the concept of address space, different types of addresses, and ways to convert one type of address to another type of address. Some of the main storage devices include permanently allocated storage locations. The main storage device provides the system with directly addressable, fast-access storage of data. Both data and programs are loaded into the main storage device, for example, from an input device, before they can be processed.

[0136] The main storage device may include one or more smaller, faster access buffer memories, sometimes called caches. The cache may be physically associated with the CPU or I / O processor. The physical construction and use of different storage media may not generally be visible to the executed program, except for the impact on performance.

[0137] Separate caches may be maintained for instructions and for data operands. Information within the cache may be maintained in contiguous bytes on intact boundaries called cache blocks or cache lines. The model may provide an EXTRACT CACHEATTRIBUTE instruction that returns the size of a cache line in bytes. The model may also provide PREFETCH DATA and PREFETCH DATA RELATIVE LONG instructions that implement prefetching of storage into a data or instruction cache or release of data from a cache.

[0138] The storage device can be viewed as a long horizontal bit string. For most operations, access to the storage device can be performed in a left-to-right order. The bit string is subdivided into units of eight bits. This eight-bit unit is called a byte, which is the basic building block of all information formats. Each byte position in the storage device can be identified by a unique non-negative integer, which is the address of the byte position, also known as the byte address. Adjacent byte positions can have consecutive addresses, starting with 0 on the left and continuing in a left-to-right order. The address is an unsigned binary integer, for example, can be 24, 31 or 64 bits.

[0139] Transfer information between memory and the CPU one byte or a group of bytes at a time. Unless otherwise specified, in e.g. In , groups of bytes in memory are addressed by the leftmost byte of the group. The number of bytes in a group is implied or explicitly specified by the operation to be performed. When used in CPU operations, a group of bytes is called a field. Within each group of bytes, for example, In , the bits are numbered from left to right. In the storage device, the leftmost bit is sometimes called the "high-order" bit and the rightmost bit is called the "low-order" bit. However, the number of bits is not the storage address. Only bytes are addressable. In order to operate on a single bit of a byte in a storage device, the entire byte can be accessed. The bits in a byte can be numbered from left to right, for example, 0 to 7 in the z / Architecture. The bits in the address can be numbered 8-31 or 40-63 for a 24-bit address, or 1-31 or 33-63 for a 31-bit address; for a 64-bit address, they are numbered 0-63. In any other fixed-length format of multiple bytes, the bits that make up the format can be numbered consecutively starting from 0. For the purpose of error detection, and preferably for correction, one or more check bits can be transmitted with each byte or a group of bytes. Such check bits are automatically generated by the machine and cannot be directly controlled by the program. The storage capacity is expressed in bytes. When the length of the storage operand field is implied by the operation code of the instruction, the field is said to have a fixed length, which can be one byte, two bytes, four bytes, eight bytes, or sixteen bytes. Larger fields may be implied for some instructions. When the length of a storage operand field is not implied but explicitly stated, the field is said to have a variable length. The length of a variable length operand may vary in increments of one byte or some instructions, in multiples of two bytes, or other multiples. When information is placed in a storage device, only the contents of those byte positions included in the specified field are replaced, even if the width of the physical path to the storage device may be greater than the length of the field being stored.

[0140] Certain units of information will be on integral boundaries in the storage device. When the storage address of information is a multiple of the unit length in bytes, the boundaries are called integral units of information. Fields of 2, 4, 8, and 16 bytes on integral boundaries have special names. A halfword is a group of two consecutive bytes on a two-byte boundary and is the basic building block of instructions. A word is a group of four consecutive bytes on a four-byte boundary. A doubleword is a group of eight consecutive bytes on an eight-byte boundary. A quadword is a group of sixteen consecutive bytes on a sixteen-byte boundary. When a storage address specifies a halfword, word, doubleword, and quadword, the binary representation of the address contains one, two, three, or four rightmost zero bits, respectively. Instructions are to be on two-byte integral boundaries. Most instructions have no boundary alignment requirements for storage operands.

[0141] On devices that implement separate caches for instructions and data operands, a program may experience significant delays if it stores into a cache line from which instructions are subsequently fetched, regardless of whether the store changes the subsequently fetched instructions.

[0142] In one embodiment, the present invention may be implemented in software, which is sometimes referred to as licensed internal code, firmware, microcode, millicode, picocode, etc., any of which would be consistent with the present invention. Fig.19 , software program code embodying the present invention may be accessed from a long-term storage media device 811 such as a CD-ROM drive, a tape drive, or a hard drive. The software program code may be embodied on any of a variety of known media for use with data processing systems, such as a disk, a hard drive, or a CD-ROM. The code may be distributed on such media, or may be distributed to users from computer memory 802 or storage devices of one computer system over a network 810 connected to other computer systems for use by users of such other systems.

[0143] The software program code may include an operating system that controls the functions and interactions of different computer components and one or more application programs. The program code may be paged from a storage medium device 811 to a relatively high-speed computer memory 802, where it may be used to be processed by a processor 801. Well-known techniques and methods for embodying the software program code in a memory, on a physical medium, and / or distributing the software code via a network may be used. When created and stored on a tangible medium (including but not limited to an electronic memory module (RAM), a flash memory, a compact disk (CD), a DVD, a magnetic tape), the program code may be referred to as a "computer program product". The computer program product medium may be readable by a processing circuit preferably located in a computer system so as to be executed by the processing circuit.

[0144] Fig. 20 A representative workstation or server hardware system is shown in which embodiments of the present invention may be implemented. Fig. 20 The system 820 includes a representative basic computer system 821, such as a personal computer, workstation or server, including optional peripheral devices. The basic computer system 821 includes one or more processors 826 and a bus for connecting and implementing communication between the processor 826 and other components of the system 821 according to known techniques. The bus connects the processor 826 to the memory 825 and the long-term storage 827, and the long-term storage 827 may include a hard drive (including, for example, any one of magnetic media, CD, DVD and flash memory) or a tape drive. The system 821 may also include a user interface adapter, which connects the microprocessor 826 to one or more interface devices via the bus, such as a keyboard 824, a mouse 823, a printer / scanner 830 and / or other interface devices, and the interface device can be any user interface device, such as a touch screen, a digitizing input board, etc. The bus also connects a display device 822 (such as an LCD screen or a monitor) to the microprocessor 826 via a display adapter.

[0145] The system 821 can communicate with other computers or computer networks through a network adapter capable of communicating 828 with a network 829. Example network adapters are communications channels, token rings, Ethernet, or modems. Alternatively, the system 821 can communicate using a wireless interface, such as a cellular digital packet data (CDPD) card. The system 821 can be associated with such other computers in a local area network (LAN) or wide area network (WAN), or the system 821 can be a client in a client / server arrangement with another computer or the like.

[0146] Fig.21 A data processing network 840 is shown in which embodiments of the present invention may be implemented. The data processing network 840 may include multiple individual networks, such as wireless networks and wired networks, each of which may include multiple individual workstations 841, 842, 843, 844. Additionally, as will be appreciated by those skilled in the art, one or more LANs may be included, wherein the LAN may include multiple intelligent workstations coupled to a host processor.

[0147] Still reference Fig.21 , the network may also include a large computer or server, such as a gateway computer (e.g., client server 846) or an application server (e.g., remote server 848), that can access the data repository and can also be directly accessed from the workstation 845. The gateway computer 846 can be used as an entry point into each individual network. When connecting one networking protocol to another, a gateway may be required. The gateway 846 can preferably be coupled to another network, such as the Internet 847, via a communication link. The gateway 846 can also be directly coupled to one or more workstations 841, 842, 843, 844 using a communication link. The IBM eServer 846 available from International Business Machines Corporation can be used. TM System The server implements the gateway computer.

[0148] Also refer to Fig. 20 and Fig.21 , software programming code that may embody the present invention may be accessed by processor 826 of system 820 from long-term storage medium 827, such as a CD-ROM drive or hard drive. The software programming code may be embodied on any of a variety of known media for use with data processing systems, such as a disk, hard drive, or CD-ROM. The code may be distributed on such media, or may be distributed to users from the computer memory 802 or storage device of one computer system over a network connected to other computer systems for use by users of such other systems.

[0149] Alternatively, the programming code may be embodied in memory 825 and accessed by processor 826 using a processor bus. Such programming code may include an operating system that controls the functionality and interaction of the various computer components and one or more application programs 832. The program code may be paged from storage medium 827 to high-speed memory 825 where it is available for processing by processor 826. Well-known techniques and methods for embodying software programming code in memory, on physical media, and / or distributing software code via a network may be used.

[0150] The most accessible cache of the processor, i.e., it can be faster and smaller than the other caches of the processor, is the lowest cache, also called L1 or first level cache. The main memory is the highest level cache, which is also called Ln level if there are n levels, for example, n=3, then it is called L3 level. The lowest level cache can be divided into instruction cache and data cache. The instruction cache is also called I cache, which stores machine-readable instructions to be executed. The data cache is also called D cache, which stores data operands.

[0151] Reference Fig. 22 , depicting an exemplary processor embodiment of a processor 826. One or more levels of cache 853 may be used to cache memory blocks in order to improve processor performance. Cache 853 is a high-speed buffer that holds cache lines of memory data that may be used. A cache line may be, for example, 64, 128, or 256 bytes of memory data. Separate caches may be used to cache instructions and cache data. Cache coherence (i.e., synchronization of copies of lines in memory and cache) may be provided by different suitable algorithms (e.g., a "snoop" algorithm). The main memory storage 825 of a processor system may be referred to as a cache. In a processor system with 4 levels of cache 853, the main memory 825 is sometimes referred to as a level 5 (L5) cache because it can be faster and only holds a portion of the non-volatile memory available to the computer system. The main memory 825 "caches" data pages that are paged in and out of the main memory 825 by the operating system.

[0152] The program counter (instruction counter) 861 keeps track of the address of the current instruction to be executed. The program counter in the processor is 64 bits and can be truncated to 31 or 24 bits to support previous addressing restrictions. The program counter can be embodied in the computer's program status word (PSW) so that it persists during context switches. Therefore, a program in progress with a program counter value may be interrupted by, for example, an operating system, resulting in a context switch from the program environment to the operating system environment. The program's PSW maintains the program counter value when the program is inactive, and uses the program counter in the operating system's PSW when the operating system is executing. The program counter can be incremented by an amount equal to the number of bytes of the current instruction. Reduced instruction set computing (RISC) instructions can be fixed length, while complex instruction set computing (CISC) instructions can be variable length. IBM The instructions are 2, 4 or 6 byte long CISC instructions. For example, the program counter 861 can be modified by a context switch operation or a branch taken operation of a branch instruction. In a context switch operation, the current program counter value is saved in the program status word along with other status information about the program being executed (e.g., condition code), and then a new program counter value pointing to the instruction of the new program module to be executed is loaded. The branch taken operation can be performed to allow the program to make decisions or loops within the program by loading the result of the branch instruction into the program counter 861.

[0153] An instruction fetch unit 855 may be employed to fetch instructions on behalf of the processor 826. The fetch unit fetches the "next sequential instruction", the target instruction of a branch taken instruction, or the first instruction of a program after a context switch. Modern instruction fetch units may employ prefetch techniques to speculatively prefetch instructions based on the likelihood that the prefetched instruction may be used. For example, the fetch unit may fetch 16 bytes of instructions containing the next sequential instruction and additional bytes of further sequential instructions.

[0154] The fetched instructions may then be executed by the processor 826. According to an embodiment, the fetched instructions may be passed from the fetch unit to the dispatch unit 856. The dispatch unit decodes the instructions and forwards information about the decoded instructions to the appropriate units 857, 858, 860. The execution unit 857 may receive information about the decoded arithmetic instructions from the instruction fetch unit 855 and may perform arithmetic operations on operands according to the opcode of the instruction. The operands may preferably be provided to the execution unit 857 from the memory 825, the architected registers 859, or from the immediate field of the instruction being executed. When the results of the execution are to be stored, they may be stored in the memory 825, the registers 859, or other machine hardware such as control registers, PSW registers, and the like.

[0155] The processor 826 may include one or more units 857, 858, 860 for executing the functions of the instructions. Fig.23A , the execution unit 857 can communicate with the architected general registers 859, the decode / dispatch unit 856, the load / store unit 860, and other 865 processor units through the interface logic 871. The execution unit 857 can use several register circuits 867, 868, 869 to hold information operated by the arithmetic logic unit (ALU) 866. The ALU performs arithmetic operations such as addition, subtraction, multiplication and division, as well as logical functions such as And, Or, XOR, rotation and shift. Preferably, the ALU can support specialized operations that depend on the design. Other circuits can provide other architected facilities 872 including, for example, conditional codes and recovery support logic. The results of the ALU operations can be stored in the output register circuit 870, which is configured to forward the results to various other processing functions. There are many ways to arrange the processor units, and this specification is only intended to provide a representative understanding of one embodiment.

[0156] An addition (ADD) instruction may be executed, for example, in an execution unit 857 having arithmetic and logic functions, while a floating point instruction will be executed, for example, in a floating point execution unit having specialized floating point capabilities. Preferably, the execution unit operates on operands by performing a function defined by an opcode on the operands identified by the instruction. For example, an addition instruction may be executed by the execution unit 857 on operands found in two registers 859 identified by the register field of the instruction.

[0157] The execution unit 857 performs arithmetic addition on the two operands and stores the result in a third operand, which may be a third register or one of the two source registers. The execution unit preferably utilizes an arithmetic logic unit (ALU) 866 that is capable of performing various logic functions such as shifts, rotations, and XORs, as well as various algebraic functions including any of addition, subtraction, multiplication, and division. Some ALUs 866 are designed for scalar operations, and some ALUs 866 are designed for floating point. Depending on the architecture, the data may be big endian (where the least significant byte is at the highest byte address) or little endian (where the least significant byte is at the lowest byte address). IBM is big endian. Signed fields can be sign and magnitude, 1's complement, or 2's complement, depending on the architecture. 2's complement can be advantageous because the ALU does not need to be designed with a subtraction function, since negative or positive values ​​in 2's complement only require addition within the ALU. Numbers can be described using shorthand where a 12-bit field defines the address of a 4,096-byte block and described as, for example, a 4K byte (kilobyte) block.

[0158] See also Fig. 23B, the branch instruction information for executing the branch instruction can be sent to the branch unit 858, and the branch unit 858 usually adopts a branch prediction algorithm (such as a branch history table 882) to predict the result of the branch before other conditional operations are completed. Before the conditional operation is completed, the target of the current branch instruction will be extracted and speculatively executed. When the conditional operation is completed, based on the condition of the conditional operation and the result of the speculation, the branch instruction that is speculatively executed is either completed or discarded. The branch instruction can test the condition code, and if the condition code meets the branch requirement of the branch instruction, the branch instruction can branch to the target address, and the target address can be calculated based on several numbers (including numbers found in the register field or immediate field of the instruction, for example). The branch unit 858 can adopt an ALU874 with multiple input register circuits 875, 876, 877 and an output register circuit 880. For example, the branch unit 858 can communicate with a general register 859, a decoding / dispatch unit 856 or other circuits 873.

[0159] The execution of a set of instructions may be interrupted for a variety of reasons, including, for example, a context switch initiated by an operating system, a program exception or error that causes a context switch, an I / O interrupt signal that causes a context switch, or multithreaded activity of multiple programs in a multithreaded environment. Preferably, the context switch action saves state information about the currently executing program and then loads state information about another program that is called. The state information may be saved, for example, in a hardware register or in a memory. The state information preferably includes a program counter value pointing to the next instruction to be executed, condition codes, memory conversion information, and architected register contents. The context switch activity may be implemented by hardware circuits, application programs, operating system programs, or firmware code, for example. Microcode, picocode, or licensed internal code (LIC), either individually or in combination.

[0160] The processor accesses operands according to the method defined by the instruction. An instruction may provide an immediate operand using the value of a portion of the instruction, or may provide one or more register fields that explicitly point to a general purpose register or a special purpose register (such as a floating point register). An instruction may use an implicit register identified by the opcode field as an operand. An instruction may use the memory location of an operand. The memory location of an operand may be provided by a register, an immediate field, or a combination of a register and an immediate field, such as The long displacement facility is exemplified in that the instruction defines a base register, an index register, and an immediate field, the displacement field, which are added together to provide the memory address of the operand. Unless otherwise indicated, locations herein may imply locations in main storage.

[0161] Reference Fig.23C , the processor uses a load / store unit 860 to access memory. The load / store unit 860 can perform a load operation by obtaining the address of the target operand in the memory 853 and loading the operand into the register 859 or another memory 853 location, or can perform a store operation by obtaining the address of the target operand in the memory 853 and storing the data obtained from the register 859 or another memory 853 location in the target operand location in the memory 853. The load / store unit 860 can be speculative and can access memory in an order that is out of order relative to the instruction sequence, however, the load / store unit 860 will keep the program from appearing to execute instructions in order. The load / store unit 860 can communicate with the general registers 859, the decode / dispatch unit 856, the cache / memory interface 853, or other elements 883, and includes various register circuits, ALU 885, and control logic 890 to calculate storage addresses and provide pipeline sequencing to maintain in-order operation. Some operations may be performed out of order, but the load / store unit provides functionality to make the out-of-order operations appear to the program to have been performed in order.

[0162] Preferably, the addresses that an application "sees" are typically referred to as virtual addresses. Virtual addresses are sometimes also referred to as "logical addresses" and "effective addresses." These virtual addresses are virtual because they are redirected to physical memory locations through one of a variety of dynamic address translation (DAT) techniques. Dynamic address translation techniques include, but are not limited to, simply prefixing the virtual address with an offset value, translating the virtual address via one or more translation tables, the translation tables preferably including at least one of a separate segment table, a separate page table, or a combination of a segment table and a page table, preferably, the segment table has an entry pointing to the page table. In A translation hierarchy is provided in which a region first table, a region second table, a region third table, a segment table, and an optional page table are included. The performance of address translation is often improved by utilizing a translation lookaside buffer (TLB) that contains entries that map virtual addresses to associated physical memory locations. When DAT uses a translation table to translate a virtual address, an entry is created. Subsequent uses of the virtual address can then utilize entries of a fast TLB rather than a slow sequential translation table access. TLB contents can be managed by various replacement algorithms including least recently used (LRU).

[0163] Each processor in a multiprocessor system is responsible for maintaining interlocks of shared resources (e.g., I / O, cache, TLB, and memory) to achieve coherency. So-called "snooping" techniques can be used to maintain cache coherency. In a snooping environment, each cache line can be marked as being in any of the shared, exclusive, changed, invalid, etc. states to facilitate sharing.

[0164] I / O unit 854 may provide the processor with a means for attaching to peripheral devices including, for example, tapes, optical disks, printers, displays, and networks. I / O units are typically presented to computer programs by software drivers. System In a host computer, channel adapters and open system adapters are I / O units of the host computer that provide communication between the operating system and peripheral devices.

[0165] Further, other types of computer systems can benefit from one or more aspects of the present invention.As an example, the computer system may include a simulator, such as software or other simulation mechanisms, wherein the simulation includes a specific architecture or a subset thereof such as instruction execution, an architected function (such as address conversion) and an architected register, such as being simulated on a native computer system with a processor and a memory.In such an environment, one or more simulation functions of the simulator can realize one or more aspects of the present invention, even if the computer executing the simulator can have a different architecture from the ability being simulated.For example, in the simulation mode, the specific instruction or operation being simulated can be decoded, and suitable simulation functions can be constructed to realize independent instructions or operations.

[0166] In a simulation environment, a host computer may, for example, include: a memory for storing instructions and data; an instruction fetch unit for fetching instructions from the memory and optionally providing a local buffer for the fetched instructions; an instruction decoding unit for receiving the fetched instructions and for determining the type of instructions that have been fetched; and an instruction execution unit for executing the instructions. Execution may include loading data from the memory into registers, storing data from registers back to the memory, and / or performing a certain type of arithmetic or logical operation as determined by the decoding unit. For example, each unit may be implemented in software. The operations performed by these units may be implemented as one or more subroutines within the simulator software.

[0167] More specifically, in a mainframe, programmers (e.g., "C" programmers) use architected machine instructions, such as through a compiler application. These instructions, stored in a storage medium, may be stored in a computer program that is compatible with the mainframe. The server executes natively, or on machines running other architectures. They can be used in existing and future Mainframe servers and Other machines (for example, Power Systems servers and System server). They can be used in AMD TM It can be executed on a variety of machines running Linux on hardware manufactured by In addition to executing on this hardware, Linux can be used and machines emulated by Hercules, UMX or FSI (Fundamental Software, Inc) can be used, which usually execute in emulation mode. In emulation mode, emulation software is executed by the native processor to emulate the architecture of the emulated processor.

[0168] The native processor can execute the simulation software including firmware or native operating system to simulate the simulation processor. The simulation software is responsible for obtaining and executing the instructions of the simulation processor architecture. The simulation software maintains the simulation program counter to track the instruction boundary. The simulation software can obtain one or more simulation machine instructions at a time, and convert the one or more simulation machine instructions into a corresponding set of native machine instructions for the native processor to execute. These converted instructions can be cached so that faster conversion can be achieved. Nevertheless, the simulation software will maintain the architecture rules of the simulation processor architecture to ensure that the operating system and application programs written for the simulation processor operate correctly. In addition, the simulation software will provide resources identified by the simulation processor architecture, including but not limited to control registers, general registers, floating point registers, dynamic address translation functions including, for example, segment tables and page tables, interrupt mechanisms, context switching mechanisms, time of day (TOD) clocks, and architectural interfaces to the I / O subsystem, so that the operating system or application programs designed to run on the simulation processor can run on the native processor with the simulation software.

[0169] Decodes the specific instruction being emulated and calls a subroutine to perform the function of the single instruction. For example, in a "C" subroutine or driver, or in some other method of providing a driver for specific hardware, the emulation software function that emulates the function of the emulated processor is implemented.

[0170] exist Fig.24, an example of an emulated host computer system 892 of a host computer system 800' emulating a host architecture is provided. In the emulated host computer system 892, a host processor (i.e., CPU) 891 is an emulated host processor or a virtual host processor and includes an emulated processor 893 having a native instruction set architecture different from the native instruction set architecture of the processor 891 of the host computer 800'. The emulated host computer system 892 has a memory 894 accessible to the emulated processor 893. In an exemplary embodiment, the memory 894 is divided into a host computer memory 896 portion and an emulated routine memory 897 portion. The host computer memory 896 is available to programs of the emulated host computer 892 in accordance with the host computer architecture. The emulation processor 893 executes native instructions of the architecture instruction set of the architecture other than the emulation processor 891, native instructions obtained from the emulation routine memory 897, and can access the host instructions for execution from the program in the host memory 896 by using one or more instructions obtained in the sequence, and access / decode the routine that can decode the accessed host instructions to determine the native instruction execution routine for simulating the function of the accessed host instructions. Other facilities defined for the architecture of the host system 800' can be emulated by the architected facility routine, including facilities such as general registers, control registers, dynamic address translation and I / O subsystem support and processor cache. The emulation routine can also utilize the functions available in the emulation processor 893 (such as dynamic translation of general registers and virtual addresses) to improve the performance of the emulation routine. Special hardware and unload engines can also be provided to assist the processor 893 in emulating the functions of the host 800'.

[0171] It is understood that one or more of the above-described embodiments of the present invention may be combined as long as the combined embodiments are not mutually exclusive. Ordinal numbers such as "first" and "second" are used herein to indicate different elements assigned the same name, but do not necessarily establish any order of the individual elements.

[0172] The present invention is described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present invention. It should be understood that each box of the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer readable program instructions.

[0173] The present invention may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium (or medium) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform various aspects of the present invention.

[0174] A computer-readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove having instructions recorded thereon, and any suitable combination of the above. As used herein, a computer-readable storage medium should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by a fiber optic cable), or an electrical signal transmitted by a wire.

[0175] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0176] The computer-readable program instructions for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as the 'C' programming language or similar programming languages. The computer-readable program instructions may be executed entirely on a computer of a "user computer system", partially on a computer of a "user computer system", as a separate software package, partially on a computer of a "user computer system" and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the computer of the user computer system via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, an electronic circuit (including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA)) may execute computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit so as to perform aspects of the present invention.

[0177] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each box of the flowchart and / or block diagram and the combination of boxes in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0178] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine that is executed by a processor of a computer or other programmable data processing device to create a device for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing device, and / or other device to function in a particular manner, such that a computer-readable storage medium having instructions stored therein includes an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0179] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing device, or other device, so that a series of operational steps are performed on the computer, other programmable data processing device, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable data processing device, or other device implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0180] The flow chart and block diagram in the accompanying drawings show the architecture, function and operation of the possible implementation of the system, method and computer program product according to different embodiments of the present invention. To this end, each box in the flow chart or block diagram can represent a part of a module, segment or instruction, which includes one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the function marked in the box may not occur in the order marked in the figure. For example, depending on the function involved, the two boxes shown in succession can actually be performed substantially at the same time, or these boxes can sometimes be performed in the opposite order. It will also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a system based on special-purpose hardware, and the system based on special-purpose hardware performs a specified function or action or performs a combination of special-purpose hardware and computer instructions.

[0181] The above features can have the following possible combinations:

[0182] 1. A method for providing an interrupt signal to a client operating system, the client operating system being executed by one or more processors of a plurality of processors of a computer system assigned to the client operating system for use, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory, the bus attachment device being operably connected to the memory,

[0183] Each processor of the plurality of processors is assigned a logical processor ID used by bus-attached devices to address the corresponding processor,

[0184] Each processor of the plurality of processors assigned to the client operating system for use is further assigned an interrupt target ID used by the client operating system and the one or more bus connection modules to address the corresponding processor,

[0185] The method comprises:

[0186] receiving, by the bus-attached device, an interrupt signal having an interrupt target ID from one of the bus-attached modules, the interrupt target ID identifying one of the processors assigned for use by the client operating system as a target processor for processing the interrupt signal,

[0187] retrieving, by the bus-attached device, from an interrupt table stored in a memory, a first copy of an interrupt table entry assigned to the received interrupt target ID, the first copy of the interrupt table entry including an interrupt blocking indicator indicating whether a target processor identified by the interrupt target ID is currently blocked from receiving interrupt signals,

[0188] The interrupt block indicator is used by the bus attached device to check whether the target processor is blocked from receiving interrupt signals,

[0189] If the target processor is not blocked, the bus-attached device converts the received interrupt target ID into a logical processor ID, and uses the converted logical processor ID to directly address the target processor, forwarding the interrupt signal to the target processor for processing.

[0190] Otherwise, the interrupt signal is blocked by the bus-attached device from being forwarded to the target processor for processing.

[0191] 2. The method of item 1, further comprising forwarding the blocked interrupt signal to the remaining processors of the plurality of processors for processing by the bus-attached device using broadcast.

[0192] 3. The method of any one of the preceding items, further comprising: checking by an interrupt handler of a client operating system whether there is any interrupt addressed to a target processor waiting to be processed by the target processor; if there is no interrupt addressed to a target processor waiting to be processed by the target processor, the client operating system changes an interrupt blocking indicator in an interrupt table entry assigned to the target processor to indicate that the target processor is not blocked.

[0193] 4. The method of any of the preceding items, wherein the interruption prevention indicator is implemented as a single bit.

[0194] 5. The method of any of the above items, wherein the interrupt signal is received in the form of a message signal interrupt, and the message signal interrupt includes an interrupt target ID of the target processor.

[0195] 6. In any of the foregoing methods, the first copy of the interrupt table entry further includes a first mapping of the received interrupt target ID to a first logical processor ID among the logical processor IDs, and the bus-attached device uses the first copy of the interrupt table entry to convert the received interrupt target ID to the logical processor ID of the target processor.

[0196] 7. The method of any of the preceding items, wherein the first copy of the interrupt table entry further comprises a first copy of an operation indicator, the operation indicator indicating whether the target processor identified by the interrupt target ID is scheduled for use by the client operating system, the method comprising:

[0197] using the first copy of the run indicator by the bus-attached device to check whether the target processor is scheduled for use by the guest operating system,

[0198] If the target processor is scheduled, continue to forward the interrupt signal.

[0199] Otherwise, the interrupt signal is forwarded by the bus-attached device to the multiple processors for processing using broadcasting.

[0200] 8. The method of any of the preceding items, further comprising, if the target processor is not blocked, changing, by the bus-attached device, an interrupt blocking indicator in an interrupt table entry assigned to the interrupt target ID, the first logical processor ID being blocked, the changing being performed before forwarding the interrupt signal to the target processor for processing.

[0201] 9. The method of item 8, further comprising

[0202] After changing the interrupt blocking indicator, retrieving, by the bus-attached device, a second copy of the interrupt table entry assigned to the received interrupt target ID,

[0203] The second copy of the interrupt table entry is checked by the bus-attached device to exclude a predefined type of change of the second copy of the interrupt table relative to the first copy of the interrupt table entry, and successful exclusion of the predefined type of change is required to forward the interrupt signal to the target processor for processing.

[0204] 10. The method of item 9, wherein the predefined type of change is a change of a first mapping of a received interrupt target ID relative to a first mapping of the received interrupt target ID to a second logical processor ID in a logical processor ID contained by a second copy of the interrupt table entry, wherein if the second mapping includes a change relative to the first mapping, the bus-attached device forwards the interrupt signal to the multiple processors for processing using broadcast.

[0205] 11. The method of item 9, wherein the predefined type of change is a change of a first copy of a run indicator relative to a second copy of the run indicator contained by an interrupt table entry, wherein if the second copy of the run indicator includes a change relative to the first copy of the run bit, the second run indicator indicates that the target processor is not scheduled for use by the client operating system, and the bus-attached device uses broadcast to forward the interrupt signal to the multiple processors for processing.

[0206] 12. The method of any of the above items, further comprising:

[0207] A copy of a device table entry is retrieved by a bus-attached device from a device table stored in a memory, the device table entry including a direct signaling indicator indicating whether a target processor is to be directly addressed, wherein

[0208] If the direct signaling indicator indicates direct forwarding of the interrupt signal, the target processor is directly addressed using the logical processor ID of the target processor to perform forwarding of the interrupt signal.

[0209] Otherwise, the interrupt signal is forwarded to the plurality of processors for processing using broadcasting by the bus-attached device.

[0210] 13. The method of item 12, the device table entry includes an interrupt table address indicator indicating a first memory address of the interrupt table, and the bus-attached device uses the memory address of the interrupt table to retrieve the first copy of the interrupt table entry.

[0211] 14. The method of any one of items 12 to 13, wherein the memory further comprises a directional interrupt summary vector having a directional interrupt summary indicator for each interrupt target ID, each directional interrupt summary indicator assigned to the interrupt target ID indicating whether there is an interrupt signal addressed to the corresponding interrupt target ID to be processed,

[0212] The method further includes updating, by the bus-attached device, a directional interrupt summary indicator assigned to a target processor ID addressed by the received interrupt signal using the memory address of the indicated directional interrupt summary vector, such that the updated directional interrupt summary indicator indicates that there is an interrupt signal addressed to the corresponding interrupt target ID to be processed.

[0213] 15. The method of any one of items 12 to 13, wherein the memory further includes a directional interrupt summary vector, the device table entry further includes a directional interrupt summary vector address indicator indicating a memory address of the directional interrupt summary vector, the directional interrupt summary vector includes a directional interrupt summary indicator for each interrupt target ID, each directional interrupt summary indicator assigned to the interrupt target ID indicates whether there is an interrupt signal addressed to the corresponding interrupt target ID to be processed,

[0214] The method further includes updating, by the bus-attached device, an interrupt summary indicator assigned to a target processor ID addressed by the received interrupt signal using the indicated memory address of the directional interrupt summary vector, such that the updated interrupt summary indicator indicates that there is an interrupt signal addressed to the corresponding interrupt target ID to be processed.

[0215] 16. The method of any one of items 12 to 13, wherein the memory further includes one or more interrupt signal vectors, the device table entry further includes an interrupt signal vector address indicator indicating a memory address of an interrupt signal vector of the one or more interrupt signal vectors, the interrupt signal vectors each including one or more signal indicators, each interrupt signal assigned to a bus connection module indicator and an interrupt target ID in the one or more bus connection modules indicating whether an interrupt signal addressed to the corresponding interrupt target ID has been received from the corresponding bus connection module,

[0216] The method further comprises:

[0217] using the indicated memory address of the interrupt signal vector to select, by the bus-attached device, an interrupt signal indicator assigned to the bus-attached module that issued the received interrupt signal and to the interrupt target ID to which the received interrupt signal was addressed,

[0218] The selected interrupt signal indicator is updated so that the selected interrupt signal indicator has an interrupt signal to be processed which is issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID.

[0219] 17. The method of item 16, wherein the interrupt signal vectors each include an interrupt signal indicator for each interrupt target ID assigned to the corresponding interrupt target ID, each of the interrupt signal vectors is assigned to a single bus connection module, and the interrupt signal indicator of the corresponding interrupt signal vector is further assigned to the corresponding single bus connection module.

[0220] 18. The method of item 16, wherein the interrupt signal vectors each include an interrupt signal indicator assigned to each bus connection module of each bus connection module, each of the interrupt signal vectors is identified by a single target processor ID, and the interrupt signal indicator of the corresponding interrupt signal vector is further assigned to the corresponding target processor ID.

[0221] 19. The method of any of the preceding items, wherein the device table entry further comprises a logical partition ID identifying the logical partition to which the client operating system is assigned, and forwarding the interrupt signal by the bus-attached device further comprises forwarding the logical partition ID along with the interrupt signal.

[0222] 20. The method of any of the preceding items, the method further comprising retrieving, by the bus-attached device, an interrupt subclass ID identifying the interrupt subclass to which the received interrupt signal is assigned, and forwarding the interrupt signal by the bus-attached device further comprising forwarding the interrupt subclass ID along with the interrupt signal.

[0223] 21. A computer system for providing an interrupt signal to a client operating system, the client operating system being executed by one or more processors of a plurality of processors of the computer system assigned for use by the client operating system, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory, the bus attachment device being operably connected to the memory,

[0224] Each processor of the plurality of processors is assigned a logical processor ID used by bus-attached devices to address the corresponding processor,

[0225] Each processor of the plurality of processors assigned to the client operating system for use is further assigned an interrupt target ID used by the client operating system and the one or more bus connection modules to address the corresponding processor,

[0226] The computer system is configured to perform a method comprising:

[0227] receiving, by the bus-attached device, an interrupt signal having an interrupt target ID from one of the bus-attached modules, the interrupt target ID identifying one of the processors assigned for use by the client operating system as a target processor for processing the interrupt signal,

[0228] retrieving, by the bus-attached device, from an interrupt table stored in a memory, a first copy of an interrupt table entry assigned to the received interrupt target ID, the first copy of the interrupt table entry including an interrupt blocking indicator indicating whether a target processor identified by the interrupt target ID is currently blocked from receiving interrupt signals,

[0229] The interrupt block indicator is used by the bus attached device to check whether the target processor is blocked from receiving interrupt signals,

[0230] If the target processor is not blocked, the bus-attached device converts the received interrupt target ID into a logical processor ID, and uses the converted logical processor ID to directly address the target processor, forwarding the interrupt signal to the target processor for processing.

[0231] Otherwise, the interrupt signal is blocked by the bus-attached device from being forwarded to the target processor for processing.

[0232] 22. A computer program product for providing an interrupt signal to a client operating system, the client operating system being executed by one or more processors of a plurality of processors of a computer system assigned for use by the client operating system, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory, the bus attachment device being operably connected to the memory,

[0233] Each processor of the plurality of processors is assigned a logical processor ID used by bus-attached devices to address the corresponding processor,

[0234] Each processor of the plurality of processors assigned to the client operating system for use is further assigned an interrupt target ID used by the client operating system and the one or more bus connection modules to address the corresponding processor,

[0235] A computer program product includes a computer-readable non-transitory medium readable by a processing circuit and storing instructions executed by the processing circuit to perform a method comprising:

[0236] receiving, by the bus-attached device, an interrupt signal having an interrupt target ID from one of the bus-attached modules, the interrupt target ID identifying one of the processors assigned for use by the client operating system as a target processor for processing the interrupt signal,

[0237] retrieving, by the bus-attached device, from an interrupt table stored in a memory, a first copy of an interrupt table entry assigned to the received interrupt target ID, the first copy of the interrupt table entry including an interrupt blocking indicator indicating whether a target processor identified by the interrupt target ID is currently blocked from receiving interrupt signals,

[0238] The interrupt block indicator is used by the bus attached device to check whether the target processor is blocked from receiving interrupt signals,

[0239] If the target processor is not blocked, the bus-attached device converts the received interrupt target ID into a logical processor ID, and uses the converted logical processor ID to directly address the target processor, forwarding the interrupt signal to the target processor for processing.

[0240] Otherwise, the interrupt signal is blocked by the bus-attached device from being forwarded to the target processor for processing.

Claims

1. A method for providing an interrupt signal to a client operating system, the client operating system being executed by one or more processors of a plurality of processors of a computer system assigned to the client operating system for use, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory, the bus attachment device being operably connected to the memory, Each processor of the plurality of processors is assigned a logical processor ID used by bus-attached devices to address the corresponding processor, Each processor of the plurality of processors assigned to the client operating system for use is further assigned an interrupt target ID used by the client operating system and the one or more bus connection modules to address the corresponding processor, The method include: receiving, by the bus-attached device, an interrupt signal having an interrupt target ID from one of the bus-attached modules, the interrupt target ID identifying one of the processors assigned for use by the client operating system as a target processor for processing the interrupt signal, retrieving, by the bus-attached device, from an interrupt table stored in a memory, a first copy of an interrupt table entry assigned to the received interrupt target ID, the first copy of the interrupt table entry including an interrupt blocking indicator indicating whether a target processor identified by the interrupt target ID is currently blocked from receiving interrupt signals, The interrupt block indicator is used by the bus attached device to check whether the target processor is blocked from receiving interrupt signals, If the target processor is not blocked, based on the target processor not being blocked and based on the run indicator indicating that the target processor is scheduled for use by the client operating system, the bus-attached device converts the received interrupt target ID into a logical processor ID, directly addresses the target processor using the logical processor ID generated by the conversion, and forwards the interrupt signal to the target processor for processing, wherein the run indicator is separate from the interrupt block indicator, Otherwise, the interrupt signal is blocked by the bus-attached device from being forwarded to the target processor for processing. 2 . The method of claim 1 , further comprising forwarding, by the bus-attached device, the blocked interrupt signal to remaining processors of the plurality of processors for processing using broadcast.

3. The method according to claim 1, further comprising: include: An interrupt handler of the guest operating system checks whether any interrupt addressed to the target processor is pending for processing by the target processor, and if no interrupt addressed to the target processor is pending for processing by the target processor, the guest operating system changes an interrupt blocking indicator in an interrupt table entry assigned to the target processor to indicate that the target processor is not blocked. The method of claim 1 , wherein the interruption prevention indicator is implemented as a single bit.

5. The method of claim 1, wherein the interrupt signal is received in the form of a message signaled interrupt, the message signaled interrupt including an interrupt target ID of a target processor.

6. The method of claim 1 , wherein the first copy of the interrupt table entry further comprises a first mapping of the received interrupt target ID to a first logical processor ID of the logical processor IDs, and the bus-attached device uses the first copy of the interrupt table entry to convert the received interrupt target ID to the logical processor ID of the target processor.

7. The method of claim 1, wherein the first copy of the interrupt table entry further comprises a first copy of an operation indicator, the operation indicator indicating whether the target processor identified by the interrupt target ID is scheduled for use by the client operating system, the method include: using the first copy of the run indicator by the bus-attached device to check whether the target processor is scheduled for use by the guest operating system, If the target processor is not scheduled, the bus-attached device forwards the interrupt signal to the multiple processors for processing using broadcasting.

8. The method of claim 1 , further comprising, if the target processor is not blocked, changing, by the bus-attached device, an interrupt blocking indicator in an interrupt table entry assigned to the interrupt target ID to indicate that the first logical processor ID is blocked, the changing being performed before forwarding the interrupt signal to the target processor for processing.

9. The method according to claim 8, further comprising After changing the interrupt blocking indicator, retrieving, by the bus-attached device, a second copy of the interrupt table entry assigned to the received interrupt target ID, The second copy of the interrupt table entry is checked by the bus-attached device to exclude a predefined type of change of the second copy of the interrupt table relative to the first copy of the interrupt table entry, and successful exclusion of the predefined type of change is required to forward the interrupt signal to the target processor for processing.

10. The method of claim 9, the predefined type of change being a change of a first mapping of a received interrupt target ID relative to a first mapping of a received interrupt target ID to a second logical processor ID in the logical processor IDs contained by the second copy of the interrupt table entry, in, If the second mapping includes changes relative to the first mapping, an interrupt signal is forwarded by the bus-attached device to the plurality of processors for processing using broadcasting.

11. The method of claim 9, wherein the change of the predefined type is a change of the first copy of the run indicator relative to the second copy of the run indicator contained by the interrupt table entry, in, If the second copy of the run indicator includes a change relative to the first copy of the run bit, the second run indicator indicates that the target processor is not scheduled for use by the client operating system, and the interrupt signal is forwarded by the bus-attached device using a broadcast to the multiple processors for processing.

12. The method according to claim 1, further comprising: include: A copy of a device table entry is retrieved by a bus-attached device from a device table stored in a memory, the device table entry including a direct signaling indicator indicating whether a target processor is to be directly addressed, wherein If the direct signaling indicator indicates direct forwarding of the interrupt signal, the target processor is directly addressed using the logical processor ID of the target processor to perform forwarding of the interrupt signal. Otherwise, the interrupt signal is forwarded to the plurality of processors for processing using broadcasting by the bus-attached device.

13. The method of claim 12, the device table entry comprising an interrupt table address indicator indicating a first memory address of the interrupt table, the bus-attached device using the memory address of the interrupt table to retrieve the first copy of the interrupt table entry.

14. The method of claim 12, wherein the memory further comprises a directional interrupt summary vector having a directional interrupt summary indicator for each interrupt target ID, each directional interrupt summary indicator assigned to the interrupt target ID indicating whether there is an interrupt signal addressed to the corresponding interrupt target ID to be processed, The method further includes updating, by the bus-attached device, a directional interrupt summary indicator assigned to a target processor ID addressed by the received interrupt signal using the memory address of the indicated directional interrupt summary vector, such that the updated directional interrupt summary indicator indicates that there is an interrupt signal addressed to the corresponding interrupt target ID to be processed.

15. The method of claim 12, wherein the memory further comprises a directional interrupt summary vector, the device table entry further comprises a directional interrupt summary vector address indicator indicating a memory address of the directional interrupt summary vector, the directional interrupt summary vector comprises a directional interrupt summary indicator for each interrupt target ID, each directional interrupt summary indicator assigned to an interrupt target ID indicates whether there is an interrupt signal addressed to the corresponding interrupt target ID to be processed, The method further includes updating, by the bus-attached device, an interrupt summary indicator assigned to a target processor ID addressed by the received interrupt signal using the indicated memory address of the directional interrupt summary vector, such that the updated interrupt summary indicator indicates that there is an interrupt signal addressed to the corresponding interrupt target ID to be processed.

16. The method of claim 12, wherein the memory further comprises one or more interrupt signal vectors, the device table entry further comprises an interrupt signal vector address indicator indicating a memory address of an interrupt signal vector of the one or more interrupt signal vectors, the interrupt signal vectors each comprising one or more signal indicators, each interrupt signal assigned to a bus connection module indicator and an interrupt target ID in the one or more bus connection modules indicating whether an interrupt signal addressed to a corresponding interrupt target ID has been received from a corresponding bus connection module, The method further include: using the indicated memory address of the interrupt signal vector to select, by the bus-attached device, an interrupt signal indicator assigned to the bus-attached module that issued the received interrupt signal and to the interrupt target ID to which the received interrupt signal was addressed, The selected interrupt signal indicator is updated so that the selected interrupt signal indicator has an interrupt signal to be processed which is issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID.

17. The method according to claim 16, wherein the interrupt signal vectors each include an interrupt signal indicator for each interrupt target ID assigned to the corresponding interrupt target ID, each of the interrupt signal vectors is assigned to a single bus connection module, and the interrupt signal indicators of the corresponding interrupt signal vectors are further assigned to the corresponding single bus connection module.

18. The method according to claim 16, wherein the interrupt signal vectors each include an interrupt signal indicator assigned to each bus connection module of each bus connection module, each of the interrupt signal vectors is identified by a single target processor ID, and the interrupt signal indicator of the corresponding interrupt signal vector is further assigned to the corresponding target processor ID.

19. The method of claim 1, the device table entry further comprising a logical partition ID identifying the logical partition to which the guest operating system is assigned, forwarding the interrupt signal by the bus-attached device further comprising forwarding the logical partition ID along with the interrupt signal.

20. The method of claim 1, further comprising retrieving, by the bus-attached device, an interrupt subclass ID identifying the interrupt subclass to which the received interrupt signal is assigned, forwarding the interrupt signal by the bus-attached device further comprising forwarding the interrupt subclass ID along with the interrupt signal.

21. A computer system for providing an interrupt signal to a client operating system, the client operating system being executed by one or more processors of a plurality of processors of the computer system assigned for use by the client operating system, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory, the bus attachment device being operably connected to the memory, Each processor of the plurality of processors is assigned a logical processor ID used by bus-attached devices to address the corresponding processor, Each processor of the plurality of processors assigned to the client operating system for use is further assigned an interrupt target ID used by the client operating system and the one or more bus connection modules to address the corresponding processor, The computer system is configured to perform the method according to any one of claims 1-20.

22. A computer program product for providing an interrupt signal to a client operating system, the client operating system being executed by one or more processors of a plurality of processors of a computer system assigned for use by the client operating system, the computer system further comprising one or more bus connection modules operably connected to the plurality of processors via a bus and a bus attachment device, the computer system further comprising a memory, the bus attachment device being operably connected to the memory, Each processor of the plurality of processors is assigned a logical processor ID used by bus-attached devices to address the corresponding processor, Each processor of the plurality of processors assigned to the client operating system for use is further assigned an interrupt target ID used by the client operating system and the one or more bus connection modules to address the corresponding processor, The computer program product comprises a computer-readable non-transitory medium readable by a processing circuit and storing instructions executed by the processing circuit to perform the method according to any one of claims 1-20.

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