Package structure

Abstract

The present application discloses a packaging structure, including a carrier, an optoelectronic component, a buffer wall, and an encapsulation colloid. A first metal pad is disposed on a substrate. The optoelectronic component is disposed on a carrier. The buffer wall is disposed on the carrier and surrounds the optoelectronic component. The encapsulation colloid covers the buffer wall and the optoelectronic component. According to the packaging structure of the embodiment of the present application, the structural strength of the packaging structure can be improved by the technical solution of "a buffer wall disposed on a carrier", and the support of the encapsulation colloid can be enhanced, thereby improving the light effect.

Description

Technical Field

[0001] The present application relates to a packaging structure, and in particular, to a packaging structure with a buffer wall. Background Art

[0002] In the prior art, the packaging structure inside the headlight is packaged with white glue. However, during the packaging process, due to the small size of the packaging structure, the thickness of the white glue is thin and the supporting force is insufficient. During the punching process, when the packaging structure is moved and fixed on the circuit board by the suction nozzle, the white glue cannot withstand the pressure of the suction nozzle during punching and is easily damaged, exposing blue light.

[0003] Therefore, how to improve the structural strength of the packaging structure and further enhance the support of the white glue through the improvement of the structural design to overcome the above-mentioned defects has become one of the important issues to be solved in this field. Summary of the invention

[0004] The technical problem to be solved by the present application is to provide a packaging structure in view of the deficiencies of the prior art, including a carrier, a photoelectric component, a buffer wall and a packaging colloid. The photoelectric component is arranged on the carrier. The buffer wall is arranged on the carrier, and the buffer wall surrounds the photoelectric component. The packaging colloid covers the buffer wall and the photoelectric component. The top of the photoelectric component is exposed to the packaging colloid. There is a height difference between the top surface of the packaging colloid and the top of the buffer wall, and the height difference is not greater than half of the height of the packaging colloid.

[0005] According to the embodiment, at least one optoelectronic component includes a light emitting diode chip and a phosphor sheet attached to the light emitting diode chip.

[0006] According to the embodiment, the buffer wall includes four L-shaped buffer parts which are not connected to each other, and the four L-shaped buffer parts are combined into an open ring structure.

[0007] According to an embodiment, the buffer wall is a closed annular structure.

[0008] According to an embodiment, the carrier includes a substrate and a first metal pad, the first metal pad is arranged on the substrate, and at least one optoelectronic component is arranged on the first metal pad, wherein the two first metal pads located on the two sides respectively have a strip groove, the strip groove is aligned with one side edge of at least one optoelectronic component, and the strip groove separates the first metal pad into a first accommodating portion and a second accommodating portion, and at least one optoelectronic component is arranged in the first accommodating portion.

[0009] According to an embodiment, the packaging structure further includes: at least one Zener diode chip, and the at least one Zener diode chip is fixed on the second accommodation portion by a die-bonding adhesive.

[0010] According to the embodiment, there is a first distance between two adjacent first metal pads, a second distance between the buffer wall and the adjacent first metal pads, and a third distance between the outer edge of the buffer wall and the edge of the carrier. The minimum third distance is 0.05 mm.

[0011] According to the embodiment, the buffer wall is made of a metal material which is electroformed and then stacked into a multi-layer structure, and the buffer wall is in a trapezoidal shape which is narrow at the top and wide at the bottom.

[0012] According to an embodiment, the height-to-width ratio of the buffer wall is less than or equal to 1.5. In order to solve the above-mentioned technical problems, another technical solution adopted in the present application is to provide a packaging structure, including a carrier, an optoelectronic component, a buffer wall, a first packaging colloid and a second packaging colloid. The optoelectronic component is arranged on the carrier. The buffer wall is arranged on the carrier, and the buffer wall surrounds the optoelectronic component. An accommodating space is formed between the buffer wall and the carrier, and the optoelectronic component is located in the accommodating space. The first packaging colloid is filled in the accommodating space. The second packaging colloid is formed on the periphery of the buffer wall. The buffer wall is a multi-layer stacked structure.

[0013] According to the embodiment, at least one optoelectronic component includes a light emitting diode chip and a phosphor sheet attached to the light emitting diode chip.

[0014] According to an embodiment, the carrier includes a substrate and a plurality of first metal pads, the substrate having a first plate surface and a second plate surface located on opposite sides, the plurality of first metal pads being arranged on the first plate surface, wherein each first metal pad has at least one L-shaped groove, and the L-shaped groove is aligned with four corners of at least one optoelectronic component.

[0015] According to the embodiment, there is a first spacing between two adjacent first metal pads, a second spacing between the buffer wall and the adjacent first metal pads, a third spacing between the outer edge of the buffer wall and the edge of the carrier, and the first spacing, the second spacing and the third spacing are all at least 0.05 mm.

[0016] According to an embodiment, it is characterized in that the buffer wall is made of a metal material that is electroformed and then stacked into a multi-layer structure, and the buffer wall is in a trapezoidal shape that is narrow at the top and wide at the bottom.

[0017] According to an embodiment, it is characterized in that the height-to-width ratio of the buffer wall is less than or equal to 1.5.

[0018] According to an embodiment, the package structure further includes: a plurality of second metal pads, the plurality of second metal pads are disposed on the second board surface, and a thickness of the second metal pads is greater than a thickness of the first metal pads.

[0019] According to an embodiment, the height ratio of the buffer wall to the second metal pad is in the range of 3 to 4. One of the beneficial effects of the present application is that the packaging structure provided by the present application can improve the structural strength of the packaging structure and enhance the support of the packaging colloid through the technical solution of "the buffer wall is arranged on the carrier", thereby improving the light effect.

[0020] To further understand the features and technical contents of the present application, please refer to the following detailed description and drawings of the present application. However, the drawings provided are only for reference and illustration and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a three-dimensional schematic diagram of the packaging structure of the first embodiment of the present application.

[0022] Figure 2 for Figure 1 Schematic cross-sectional view of section II-II.

[0023] Figure 3 It is a schematic three-dimensional exploded diagram of the packaging structure of the first embodiment of the present application.

[0024] Figure 4 It is a schematic top view of an implementation form of the buffer wall of the packaging structure of the first embodiment of the present application.

[0025] Figure 5 for Figure 4 Schematic diagram of a top view of a buffer wall structure surrounding an optoelectronic component and a Zener diode.

[0026] Figure 6 It is a top view schematically showing another implementation form of the buffer wall of the packaging structure of the first embodiment of the present application.

[0027] Figure 7 for Figure 6 Schematic diagram of a top view of a buffer wall structure surrounding an optoelectronic component and a Zener diode.

[0028] Figure 8 It is a bottom view schematic diagram of the packaging structure of the first embodiment of the present application.

[0029] Fig. 9 It is a three-dimensional schematic diagram of the packaging structure of the second embodiment of the present application.

[0030] Fig.10 for Fig. 9 Schematic cross-sectional view of section IX-IX.

[0031] Fig.11 It is a schematic three-dimensional exploded diagram of the packaging structure of the second embodiment of the present application.

[0032] Fig.12It is a schematic top view of a buffer wall of a packaging structure according to a second embodiment of the present application.

[0033] Fig.13 for Fig.11 Schematic diagram of a top view of a buffer wall surrounding an optoelectronic component and a Zener diode.

[0034] Fig.14 It is a bottom view schematic diagram of the packaging structure of the second embodiment of the present application. DETAILED DESCRIPTION

[0035] The following is an explanation of the implementation methods of the "packaging structure" disclosed in this application through specific embodiments. Those skilled in the art can understand the advantages and effects of this application from the contents disclosed in this specification. This application can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of this application. In addition, the drawings of this application are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following implementation methods will further explain the relevant technical contents of this application in detail, but the disclosed contents are not intended to limit the scope of protection of this application.

[0036] It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are mainly used to distinguish one element from another element. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0037] First embodiment

[0038] First, see Figure 1 , Figure 2 and Figure 3 As shown, the first embodiment of the present application provides a packaging structure Z, which includes: a carrier C, an optoelectronic component 3, a buffer wall 4 and an encapsulation colloid 5. The optoelectronic component 3 is disposed on the carrier C. The buffer wall 4 is disposed on the carrier C and surrounds the optoelectronic component 3.

[0039] Specifically, the carrier C includes a substrate 1 and a first metal pad 2. The material of the substrate 1 may be, for example, a ceramic material, but the present application is not limited thereto. A plurality of first metal pads 2 are disposed on the substrate 1. An optoelectronic component 3 is disposed on the first metal pad 2. In the present embodiment, the number of optoelectronic components 3 is two (double chips), but the present application is not limited thereto, and the number of optoelectronic components 3 may actually be one or more. A buffer wall 4 is disposed on the substrate 1.

[0040] Continue reading Figure 1 and Figure 2As shown. The encapsulating colloid 5 covers the buffer wall 4 and the electrical component 3. The top of the optoelectronic component 3 is exposed to the encapsulating colloid 5. The optoelectronic component 3 includes a light-emitting diode chip 31 and a phosphor sheet 32 ​​attached to the light-emitting diode chip 31. In this embodiment, the light-emitting diode chip 31 can emit a first color light, and the blue light is mixed by the phosphor sheet 32 ​​to form a predetermined color light (second color light).

[0041] See also Figure 3 and Figure 4 As shown, it should be noted that the buffer wall 4 can have two different implementation forms. The buffer wall 4 includes four unconnected buffer portions 40, and the four buffer portions 40 are all L-shaped. The four L-shaped buffer portions 40 are respectively located at the four corners of the substrate 1, and the L-shaped shape just corresponds to the four vertical corners of the substrate 1, and is further combined into an open ring structure. The mixed predetermined color light (second color light) generated by the optoelectronic component 3 can be concentrated in the light-emitting area through the buffer portion 40 to enhance the light effect of the packaging structure Z.

[0042] Next, see Figure 6 and Figure 7 As shown, another embodiment of the buffer wall 4 is a closed ring structure. Compared with the multiple buffer parts 40 in the open ring structure, which are not connected to each other and thus form an opening between two adjacent buffer parts 40, the buffer wall 4 in the closed ring structure is not cut into multiple sections, but a ring structure connected end to end. The mixed light (second color light) emitted by the optoelectronic component 3 can be concentrated in the light-emitting area through the buffer part 40 to improve the light effect of the packaging structure Z.

[0043] See also Figure 5 and Figure 7 As shown, since the optoelectronic component 3 is arranged on the first metal pad 2, the number of the first metal pads 2 is actually configured according to the number of the optoelectronic components 3. Specifically, one optoelectronic component 3 is arranged across two first metal pads 2. In this embodiment, the number of the optoelectronic components 3 is two, so the number of the first metal pads 2 is three, and the two first metal pads 2 located on the two sides each have a strip groove 20. When the optoelectronic component 3 is provided with the first metal pad 2, the strip groove 20 will be aligned with one of the side edges of the optoelectronic component 3. More specifically, when the optoelectronic component 3 on the left is arranged across the first metal pads 2 on the left and the middle, the strip groove 20 of the first metal pad 2 on the left will be aligned with the side edge of the optoelectronic component 3 on the left; when the optoelectronic component 3 on the right is arranged across the first metal pads 2 on the right and the middle, the strip groove 20 of the first metal pad 2 on the right will be aligned with the side edge of the optoelectronic component 3 on the right.

[0044] Furthermore, the strip groove 20 separates the two first metal pads 2 on the two sides into a first accommodating portion 21 and a second accommodating portion 22, and the optoelectronic component 3 is arranged in the first accommodating portion 21. In addition, the packaging structure Z further includes a Zener diode chip 6, which is an electronic technology component with a voltage stabilizing function. In this embodiment, the two Zener diode chips 6 are respectively fixed on the second accommodating portions 22 of the two first metal pads 2 on the two sides with a bonding glue 7 (for example, silver glue). The strip groove 20 is a straight groove structure, which has two functions: one is to position the optoelectronic component 3, so that the strip groove 20 will align with the side of the optoelectronic component 3; the second is that the optoelectronic component 3 and the Zener diode chip 6 are separated by the strip groove 20, which can prevent the excessive amount of the bonding glue 7 used to fix the Zener diode chip 6 from overflowing and contacting the optoelectronic component 3, thereby affecting the process.

[0045] See again Figure 2 As shown, the buffer wall 4 is formed by electroforming a metal material through multiple exposure and development processes and then stacking it into a multi-layer structure. In other words, the buffer wall 4 is actually a multi-layer stacked metal frame structure, including a lower metal layer 41 and an upper plurality of metal layers 42. The number of layers of the multi-layer metal layer 42 structure can be at least two or more, but the present application does not limit the specific number of layers.

[0046] It should also be noted that the buffer wall 4 is actually in a trapezoidal or approximately trapezoidal shape that is narrow at the top and wide at the bottom. The minimum width difference W between the bottom metal layer 41 and the multiple metal layers 42 at the top is 0.05 mm, and the height-to-width ratio of the buffer wall 4 is less than or equal to 1.5. According to the embodiment, when multiple upper and lower metal layers 41, 42 are stacked into a multi-layer structure after electroforming, if the widths of the upper and lower metal layers 41, 42 are the same, exposure alignment deviation is likely to occur, resulting in multi-layer misalignment problems. Therefore, by designing the width difference W, the width of the multiple metal layers 42 at the upper layer is smaller than the width of the lower metal layer 41, that is, the upper and lower metal layers 41, 42 are allowed to have a tolerance, thereby avoiding exposure alignment deviations that cause the structure of the buffer wall 4 to have multi-layer misalignment problems.

[0047] There is a height difference H1 between the top surface of the encapsulation colloid 5 and the top of the buffer wall 4, and the height difference H1 is not greater than one-half of the height H2 of the encapsulation colloid 5. Optionally, in this embodiment, the height difference H1 between the top surface of the encapsulation colloid 5 and the top of the buffer wall 4 is approximately one-third of the height H2 of the encapsulation colloid 5. The design of the height difference H1 between the encapsulation colloid 5 and the buffer wall 4 can increase the buffering effect, strengthen the support of the encapsulation colloid 5, and prevent the encapsulation colloid 5 from being crushed by the suction nozzle during the punching process, causing the encapsulation colloid 5 to break.

[0048] There is a first distance D1 between two adjacent first metal pads 2, and the first distance D1 is at least 0.05 mm. There is a second distance D2 between the buffer wall 4 and the adjacent first metal pad 2, and the second distance D2 is at least 0.05 mm. There is a third distance D3 between the outer edge of the buffer wall 4 and the edge of the carrier C, and the third distance is at least 0.05 mm. It should be noted that Figure 2 As shown, since the carrier C includes the substrate 1 and the first metal pad 2, the third distance D3 actually refers to the distance between the outer edge of the buffer wall 4 and the edge of the substrate 1, and the minimum distance is 0.05 mm. The design of the distance (D1-D3) is to prevent the electroplating phenomenon from occurring during the electroforming of the metal frame (i.e., the buffer wall 4), thereby preventing the metal frame from being electrically connected to the first metal pad for conducting electricity and causing the metal frame to be charged.

[0049] See also Figure 1 , Figure 2 and Figure 8 As shown, the package structure Z further includes a second metal pad 8. The second metal pad 8 is disposed on the carrier C, and the second metal pad 8 and the first metal pad 2 are respectively located on opposite sides of the carrier C. Specifically, the second metal pad 8 and the first metal pad 2 are electrically connected by punching holes in the substrate 1 and filling metal materials (not shown in the figure). During the punching process, the package structure Z is soldered to the circuit board through the second metal pad 8. The second metal pad 8 includes a conductive portion 81 and a heat dissipation portion 82. The area of ​​the heat dissipation portion 82 is larger than the area of ​​the conductive portion 81, and the conductive portion 81 and the first metal pad 2 are electrically connected by the metal material filled in the hole in the substrate 1. The second metal pad 8, like the buffer wall 4, is electroformed with a metal material and then stacked into a multi-layer structure. In this embodiment, the second metal pad 8 is a two-layer stacked structure. In addition, the height ratio of the buffer wall 4 to the second metal pad 8 is in the range of 3 to 4, which can avoid the difference in the coefficient of thermal expansion (CTE) caused by the large difference in the number of electroplating layers, which causes the substrate 1 sandwiched in the middle to produce dark cracks (assuming that the substrate 1 is made of ceramic material).

[0050] In this embodiment, the number of the conductive parts 81 is three, and they are arranged side by side with the heat dissipation part 82 on the same surface of the substrate 1. Since the area of ​​the heat dissipation part 82 is larger than the area of ​​the conductive part 81. Therefore, when the package structure Z is energized (current) with the first metal pad 2 through the conductive part 81, the large area of ​​the heat dissipation part 82 can be used to increase the heat dissipation area and reduce the thermal resistance of the structure as a whole. In addition, in this embodiment, the two first metal pads 2 on the two sides are anodes, and the first metal pad 2 in the middle is a cathode. The conductive parts 81 on both sides of the second metal pad 8 are cathodes, and the conductive part 81 sandwiched in the middle is an anode.

[0051] Second embodiment

[0052] See also Fig. 9 , Fig.10 and Fig.11 As shown, the second embodiment of the present application provides a packaging structure Z', which includes: a carrier C', an optoelectronic component 3', a buffer wall 4', a first packaging colloid 51' and a second packaging colloid 52'. The optoelectronic component 3' is disposed on the carrier C'. The buffer wall 4' is disposed on the carrier C', the buffer wall 4' surrounds the optoelectronic component 3', and a receiving space 10' is formed between the buffer wall 4' and the carrier C', and the optoelectronic component 3' is located in the receiving space 10'.

[0053] Specifically, the carrier C' includes a substrate 1' and a first metal pad 2'. The material of the substrate 1' may be, for example, a ceramic material, but the present application is not limited thereto. The substrate 1' has a first board surface 11' and a second board surface 12' located on opposite sides. A plurality of first metal pads 2' are disposed on the first board surface 11', and the optoelectronic component 3' is disposed on the first metal pad 2'. In the present embodiment, the number of the optoelectronic component 3' is one (single chip), but the present application is not limited thereto, and the number of the optoelectronic component 3' may actually be one or more.

[0054] In more detail, the buffer wall 4' is disposed on the substrate 1' and forms a receiving space 10' with the substrate 1', and the plurality of first metal pads 2' and the optoelectronic components 3' are all located in the receiving space 10'. The first encapsulation colloid 51' is filled in the receiving space 10', and the top of the optoelectronic components 3' is exposed to the first encapsulation colloid 51'. It should be noted that in the present application, the first encapsulation colloid 51' is at the same height as the buffer wall 4', that is, the top of the first encapsulation colloid 51' is flush with the top of the buffer wall 4'. However, the present application is not limited thereto, and the first encapsulation colloid 51' may actually completely cover the buffer wall 4'.

[0055] The optoelectronic component 3' includes a light-emitting diode chip 31' and a phosphor sheet 32' attached to the light-emitting diode chip 31'. In the present embodiment, the light-emitting diode chip 31' can emit a first color light, and the blue light is mixed by the phosphor sheet 32' to form a predetermined color light (second color light). The design of the buffer wall 4' can strengthen the support of the first packaging colloid 51', and has a buffering effect, thereby improving the problem that the suction nozzle can easily crush the first packaging colloid 51' during the punching process, causing rupture and leakage of blue light. In addition, the predetermined color light (second color light) generated by the optoelectronic component 3' can be concentrated in the light-emitting area through the buffer wall 4', thereby improving the light effect.

[0056] The second encapsulating colloid 52' is formed on the periphery of the buffer wall 4' and is formed by plastic injection. The first encapsulating colloid 51' is made of white glue containing epoxy resin by dispensing. In other words, the first encapsulating colloid 51' and the second encapsulating colloid 52' are different in material and manufacturing method.

[0057] See also Fig.12 and Fig.13 As shown, since the optoelectronic component 3' is disposed on the first metal pad 2', the number of the first metal pads 2' is actually configured according to the number of the optoelectronic components 3'. In this embodiment, one optoelectronic component 3' is disposed across two first metal pads 2'. Each first metal pad 2' has two L-shaped grooves 20', so the two first metal pads 2' have four L-shaped grooves 20'. Fig.12 As shown, four L-shaped grooves 20' are symmetrically arranged to indicate a die placement area. Fig.13 As shown, when the optoelectronic component 3' is placed across the two first metal pads 2', the L-shaped groove 20' is aligned with the four corners of the optoelectronic component 3'. In other words, the L-shaped groove 20' is used to position the optoelectronic component 3'.

[0058] Continue reading Fig.12 As shown, the first metal pad 2' on the left has a first identification portion 21'. More specifically, the first identification portion 21' is disposed at both ends of one side of the first metal pad 2' adjacent to the buffer wall 4'. The shape of the first identification portion 21' corresponds to the buffer wall 4'. The first identification portion 21' is used to identify polarity. The first metal pad 2' with the first identification portion 21' is a cathode, and the other first metal pad 2' without the first identification portion 21' is an anode.

[0059] Continue reading Fig.13 As shown, the package structure Z' further includes a Zener diode chip 6', which is fixed to the first metal pad 2' of the anode by a die-bonding glue 7' (such as silver glue) and connected to the first metal pad 2' of the cathode by wire bonding.

[0060] Continue reading Fig.10 As shown, there is a first distance D1 between two adjacent first metal pads 2', and the first distance D1 is at least 0.05 mm. There is a second distance D2 between the buffer wall 4' and the adjacent first metal pad 2', and the second distance D2 is at least 0.05 mm. There is a third distance D3 between the outer edge of the buffer wall 4' and the edge of the carrier C', and the third distance D3 is at least 0.05 mm. It should be noted that Fig.10 As shown, since the carrier C' includes the substrate 1' and the first metal pad 2', the third distance D3 actually refers to the distance between the outer edge of the buffer wall 4 and the edge of the substrate 1', and the minimum distance is 0.05 mm. The purpose of the design of the distance (D1-D3) of this embodiment is the same as that of the first embodiment, and will not be repeated here.

[0061] In addition, as in the first embodiment, the buffer wall 4' in this embodiment is a multi-layer stacked structure in which metal materials are electroformed and stacked into a trapezoidal or approximately trapezoidal shape that is narrow at the top and wide at the bottom through multiple exposure and development processes. In other words, the buffer wall 4' is actually a multi-layer stacked metal frame structure, including multiple metal layers 41', 42'. The minimum width difference W between the bottom metal layer 41' and the upper metal layer 42' is 0.05 mm, and the height-to-width ratio of the buffer wall 4' is less than or equal to 1.5. Similarly, the structural design purpose of the buffer wall 4' in this embodiment is the same as that of the first embodiment, and will not be repeated here.

[0062] See also Fig.10 and Fig.14 As shown, the package structure Z' further includes a plurality of second metal pads 8'. The second metal pads 8' are disposed on the carrier C', and the second metal pads 8' and the first metal pads 2' are respectively located on opposite sides of the carrier C'. Specifically, the plurality of second metal pads 8' are disposed on the second board surface 12' of the substrate 1', and the second metal pads 8' and the first metal pads 2' are electrically connected by perforating the substrate 1' and filling it with metal material (not shown). During the punching process, the package structure Z' is soldered to the circuit board through the second metal pads 8'.

[0063] In the present embodiment, the thickness of the second metal pad 8' is greater than the thickness of the first metal pad 2'. The second metal pad 8' includes a conductive portion 81' and a heat dissipation portion 82', and the area of ​​the heat dissipation portion 82' is greater than the area of ​​the conductive portion 81'. The number of the conductive portions 81' is two, and one of the conductive portions 81' has a second identification portion 813'. The second identification portion 813' is used to identify the polarity like the first identification portion 21'. The conductive portion 81' with the first identification portion 21' is a cathode, and the conductive portion 81' without the first identification portion 21' is an anode. Therefore, on the other hand, the conductive portion 81' includes an anode portion 811' and a cathode portion 812'. The heat dissipation portion 82' is located between the anode portion 811' and the cathode portion 812'. The second metal pad 8' is formed by electroforming a metal material and then stacking multiple layers. In the present embodiment, the second metal pad 8' is a two-layer stacking structure. In addition, the height ratio of the buffer wall 4' to the second metal pad 8' is in the range of 3 to 4, so as to avoid the substrate 1' sandwiched in the middle from generating dark cracks due to the difference in the coefficient of thermal expansion (CTE) caused by the large difference in the number of electroplating layers (assuming that the substrate 1 is made of ceramic material).

[0064] In addition, in this embodiment, the second metal pad 8' also has a thermal and electrical separation structural design, that is, the conductive part 81' is used for power transmission, and the large area of ​​the heat dissipation part 82' is used to increase the heat dissipation area to reduce the overall thermal resistance of the structure. Its effect is the same as that of the first embodiment and will not be repeated here.

[0065] Advantageous Effects of Embodiments

[0066] One of the beneficial effects of the present application is that the packaging structure Z, Z' provided by the present application can improve the structural strength of the packaging structure and enhance the support of the packaging colloid through the technical solution of "buffer walls 4, 4' surrounding the carrier C, C'".

[0067] Furthermore, thrust tests were performed on the packaging structures Z, Z' of the present application and the packaging structures in the prior art respectively, to compare the maximum thrust that the packaging colloid can withstand with or without a buffer wall structure. It was found from actual tests that the maximum thrust that the packaging colloid can withstand in the packaging structure without a buffer wall structure in the prior art is 586.6 grams (g); while the maximum thrust that the packaging colloid can withstand in the packaging structures Z, Z' with a buffer wall structure in the present application is 997.1 grams (g), and even the maximum thrust that the packaging colloid can withstand in the area surrounded by the buffer wall can reach 2106.6 grams (g). In other words, compared with the packaging structure in the prior art, the buffer wall design of the packaging structure of the present application can greatly enhance the support of the packaging colloid and reduce the occurrence of blue light leakage due to the rupture of the packaging colloid due to the nozzle pressure.

[0068] The contents disclosed above are only optional feasible embodiments of the present application, and are not intended to limit the protection scope of the claims of the present application. Therefore, all equivalent technical changes made using the contents of the present application specification and drawings are included in the protection scope of the claims of the present application.

Claims

1. A packaging structure, characterized in that: The packaging structure comprises: A carrier, comprising a substrate and a plurality of first metal pads, wherein the substrate has a first plate surface and a second plate surface located on opposite sides, and the plurality of first metal pads are disposed on the first plate surface; At least one optoelectronic component is disposed on the carrier, a buffer wall, disposed on the carrier and surrounding at least one of the optoelectronic components, wherein the buffer wall is a multi-layer metal stacking structure; an encapsulating colloid, covering the buffer wall and at least one of the photoelectric components, wherein the top of at least one of the photoelectric components is exposed from the encapsulating colloid, and a height difference exists between the top surface of the encapsulating colloid and the top of the buffer wall, and the height difference is no greater than one-half of the height of the encapsulating colloid; and A plurality of second metal pads are arranged on the second plate surface, and the thickness of the second metal pads is greater than the thickness of the first metal pads; The height ratio of the buffer wall to the second metal pad is in the range of 3-4.

2. The packaging structure according to claim 1, characterized in that: At least one of the optoelectronic components includes a light emitting diode chip and a phosphor sheet attached to the light emitting diode chip.

3. The packaging structure according to claim 1, characterized in that: The buffer wall comprises four L-shaped buffer parts which are not connected to each other, and the four L-shaped buffer parts are combined into an open ring structure.

4. The packaging structure according to claim 1, characterized in that: The buffer wall is a closed annular structure.

5. The packaging structure according to claim 1, characterized in that: The at least one optoelectronic component is arranged on the first metal pad, wherein the two first metal pads located on the two sides respectively have a strip groove, the strip groove is aligned with one side edge of at least one optoelectronic component, and the strip groove separates the first metal pad into a first accommodating portion and a second accommodating portion, and at least one optoelectronic component is arranged in the first accommodating portion.

6. The packaging structure according to claim 5, characterized in that: The packaging structure further includes: at least one Zener diode chip, and the at least one Zener diode chip is fixed on the second accommodation portion by a die-bonding adhesive.

7. The packaging structure according to claim 5, characterized in that: There is a first distance between two adjacent first metal pads, a second distance between the buffer wall and the adjacent first metal pads, a third distance between the outer edge of the buffer wall and the edge of the carrier, and the first distance, the second distance and the third distance are all at least 0.05 mm.

8. The packaging structure according to any one of claims 1 to 5, characterized in that: The buffer wall is made of metal material which is electroformed and then stacked into a multi-layer structure, and the buffer wall is in a trapezoidal shape which is narrow at the top and wide at the bottom.

9. The packaging structure according to any one of claims 1 to 5, characterized in that: The height-to-width ratio of the buffer wall is less than or equal to 1.

5.

10. A packaging structure, characterized in that: The packaging structure comprises: A carrier, comprising a substrate and a plurality of first metal pads, wherein the substrate has a first plate surface and a second plate surface located on opposite sides, and the plurality of first metal pads are disposed on the first plate surface; At least one optoelectronic component is disposed on the carrier; a buffer wall, disposed on the carrier, the buffer wall surrounding at least one of the optoelectronic components, forming an accommodation space between the buffer wall and the carrier, at least one of the optoelectronic components being located in the accommodation space, and the buffer wall being a multi-layer metal stacking structure; a first encapsulating colloid filling the accommodating space; a second encapsulating colloid formed on the periphery of the buffer wall; and a plurality of second metal pads disposed on the second board surface, wherein the thickness of the second metal pads is greater than that of the first metal pads; The height ratio of the buffer wall to the second metal pad is in the range of 3-4.

11. The packaging structure according to claim 10, characterized in that: At least one of the optoelectronic components includes a light emitting diode chip and a phosphor sheet attached to the light emitting diode chip.

12. The packaging structure according to claim 10, characterized in that: Each of the first metal pads has at least one L-shaped groove, and the L-shaped groove is aligned with four corners of at least one of the optoelectronic components.

13. The packaging structure according to claim 12, characterized in that: There is a first distance between two adjacent first metal pads, a second distance between the buffer wall and the adjacent first metal pads, a third distance between the outer edge of the buffer wall and the edge of the carrier, and the first distance, the second distance and the third distance are all at least 0.05 mm.

14. The packaging structure according to any one of claims 10 to 13, characterized in that: The buffer wall is made of metal material which is electroformed and then stacked into a multi-layer structure, and the buffer wall is in a trapezoidal shape which is narrow at the top and wide at the bottom.

15. The packaging structure according to any one of claims 10 to 13, characterized in that: The height-to-width ratio of the buffer wall is less than or equal to 1.5.

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