Chip packaging structure and manufacturing method thereof

Abstract

The present invention provides a chip packaging structure, which includes a circuit substrate, at least one electronic component and a chip, a two-stage thermosetting adhesive layer and a packaging colloid. The circuit substrate has a first surface and a second surface opposite to each other. The electronic component and the chip are respectively located on the first surface and are electrically connected to the circuit substrate. The electronic component is electrically connected to the circuit substrate by a conductive member. The two-stage thermosetting adhesive layer includes a first part and a second part separated from each other. The first part completely covers the electronic component and fills the gap between the electronic component and the circuit substrate. The chip is arranged on the second part and wire-bonded to the first surface or the second surface of the circuit substrate. The height of the first part is substantially the same as the height of the second part. The packaging colloid covers the two-stage thermosetting adhesive layer and the chip. A manufacturing method of a chip packaging structure is also provided.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a chip packaging structure and a manufacturing method thereof. Background Art

[0002] As the consumer market changes, consumers' demands for thinner and lighter products are also increasing, especially for electronic products, which often need to improve the integration of chip packaging within a limited volume. However, when improving the integration of semiconductor packaging, it is often impossible to simultaneously meet the design requirements of electronic components with different functions, which can easily reduce the reliability of semiconductor packaging or increase its manufacturing cost.

[0003] For example, due to the size differences of electronic components with different functions, the space between smaller electronic components and substrates is relatively small, so it is increasingly difficult to directly fill the aforementioned narrow space with epoxy molding compound (EMC). Furthermore, when epoxy molding compound with a larger filler is filled into the aforementioned narrow space, it is easy to damage the electronic components due to clogging of the filler or cause incomplete filling of the epoxy molding compound to form bubbles (void), thereby reducing the reliability of the semiconductor package. If mold underfill (MUF) with a smaller filler size but a more expensive price is used to fill the aforementioned narrow space, the manufacturing cost of the semiconductor package will increase. Summary of the invention

[0004] The present invention is directed to a chip packaging structure and a manufacturing method thereof, which can improve the reliability of the chip packaging structure while reducing the manufacturing cost.

[0005] According to an embodiment of the present invention, a chip packaging structure includes a circuit substrate, at least one electronic component and a chip, a two-stage thermosetting adhesive layer and an encapsulating colloid. The circuit substrate has a first surface and a second surface opposite to each other. At least one electronic component and the chip are respectively located on the first surface and electrically connected to the circuit substrate. At least one electronic component is electrically connected to the circuit substrate by a conductive member. The two-stage thermosetting adhesive layer includes a first part and a second part separated from each other. The first part completely covers at least one electronic component and fills the gap between at least one electronic component and the circuit substrate. The chip is arranged on the second part and wire-bonded to the first surface or the second surface of the circuit substrate. The height of the first part is substantially the same as the height of the second part. The encapsulating colloid covers the two-stage thermosetting adhesive layer and the chip.

[0006] According to an embodiment of the present invention, a method for manufacturing a chip packaging structure includes at least the following steps. A circuit substrate is provided, wherein the circuit substrate has a first surface and a second surface relative to each other. At least one electronic component is configured on the first surface, and at least one electronic component is electrically connected to the circuit substrate by a conductive member. A two-stage thermosetting adhesive layer is formed on the first surface. The two-stage thermosetting adhesive layer includes a first part and a second part separated from each other. The height of the first part is substantially the same as the height of the second part. The first part completely covers at least one electronic component and fills the gap between at least one electronic component and the circuit substrate. A chip is configured on the second part and the chip is wire bonded to the first surface or the second surface of the circuit substrate. A curing process is performed to completely cure the two-stage thermosetting adhesive layer. A packaging colloid is formed to cover the two-stage thermosetting adhesive layer and the chip.

[0007] Based on the above, the present invention uses the characteristics of the filler in the two-stage thermosetting adhesive layer being smaller in size and having better fluidity to completely cover the electronic component and fill the gap between the electronic component and the circuit substrate. Therefore, it is possible to avoid the situation where the larger filler in the encapsulation colloid flows into the gap and causes damage to the electronic component or causes the filling colloid in the gap to be incompletely filled with bubbles, thereby effectively protecting the electronic component, reducing the probability of damage to the electronic component and improving the reliability of the chip packaging structure. In addition, since the material cost of the two-stage thermosetting adhesive layer is lower than that of the molded bottom filler (MUF), it is possible to reduce the manufacturing cost while improving the reliability of the chip packaging structure. On the other hand, the height of the first part of the two-stage thermosetting adhesive layer of the present invention is substantially the same as the height of the second part, that is, a protective adhesive layer (i.e., the first part of the two-stage thermosetting adhesive layer) that completely covers the electronic component can be formed at the same time as the die bonding adhesive layer (i.e., the second part of the two-stage thermosetting adhesive layer), and the process of forming a protective layer for each electronic component can be omitted, thereby simplifying the process and further reducing the manufacturing cost.

[0008] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1A to 1D is a cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present invention;

[0010] Figure 2 It is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention.

[0011] Description of Reference Numerals

[0012] 10: Mould

[0013] 100, 100a: Chip packaging structure

[0014] 110: Circuit board

[0015] 110a: first surface

[0016] 110b: Second surface

[0017] 112: Pad

[0018] 120: Two-stage thermosetting adhesive layer

[0019] 122, 1221, 1222: Part 1

[0020] 122a: Top surface of the first section

[0021] 124: Part 2

[0022] 124a: Top surface of the second part

[0023] 130, 1301, 1302: Electronic components

[0024] 132, 1321, 1322: Conductive parts

[0025] 140: Chip

[0026] 140a: Active surface

[0027] 140b: Back

[0028] 150, 1501, 1502: Metal sheets

[0029] 160: Encapsulation colloid

[0030] G, G1, G2: Gap

[0031] H1, H2: Height

[0032] L: Wire

[0033] OP, OP1, OP2: Open

[0034] P: Through hole

[0035] R1, R2: Formation position DETAILED DESCRIPTION

[0036] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0037] The directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings shown and are not intended to imply an absolute orientation.

[0038] Unless expressly stated otherwise, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.

[0039] The present invention is more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of the layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numbers represent the same or similar components, and the following paragraphs will not be repeated one by one.

[0040] Figures 1A to 1D 1 is a cross-sectional schematic diagram of a method for manufacturing a chip package structure according to an embodiment of the present invention. In this embodiment, the method for manufacturing the chip package structure 100 may include the following steps.

[0041] Please refer to Figure 1A , providing a circuit substrate 110, wherein the circuit substrate 110 has a first surface 110a and a second surface 110b opposite to each other. The circuit substrate 110 may include a plurality of pads 112, and the pads 112 may be disposed on the first surface 110a for subsequent electrical connection.

[0042] In some embodiments, the circuit substrate 110 is, for example, a wafer, a glass substrate, a ceramic substrate, a printed circuit board, or a multilayer substrate made of other suitable materials, and the pad 112 is, for example, a copper pad. Here, the present invention does not limit the type of the circuit substrate 110, as long as the circuit substrate 110 has a suitable conductive circuit that can perform the electrical connection required in the subsequent design, it falls within the protection scope of the present invention.

[0043] Please continue to refer to Figure 1A At least one electronic component 130 is disposed on the first surface 110a, and the electronic component 130 is electrically connected to the circuit substrate 110 via a conductive member 132. Here, the present invention does not limit the number of the electronic components 130, and the number of the electronic components 130 can be one or more. Figure 1A Only two electronic components 130 are shown for example. For example, the electronic component 130 may include a first electronic component 1301 and a second electronic component 1302 . The first electronic component 1301 is electrically connected to the circuit substrate 110 via a first conductive member 1321 , and the second electronic component 1302 is electrically connected to the circuit substrate 110 via a second conductive member 1322 .

[0044] In some embodiments, the electronic component 130 may be an active component, a passive component, or a combination thereof. For example, in the present embodiment, the first electronic component 1301 may be an active component, and the second electronic component 1302 may be a passive component, but the present invention is not limited thereto. In an embodiment not shown, the first electronic component 1301 and the second electronic component 1302 may both be active components or the first electronic component 1301 and the second electronic component 1302 may both be passive components. In the case where the first electronic component 1301 is an active component and the second electronic component 1302 is a passive component, the first electronic component 1301 is, for example, configured on the circuit substrate 110 using flip chip technology, wherein the first conductive member 1321 may be a conductive ball, a conductive column, a conductive bump, or a combination thereof, and the second conductive member 1322 is, for example, a conductive paste. The material of the conductive member 1321 and the conductive member 1322 is, for example, tin, but the present invention is not limited thereto. In one embodiment, the first electronic component 1301 may be, for example, a magnetoresistive random access memory (MRAM), and the second electronic component 1302 may be a resistor, a capacitor, an inductor or the like, but the invention is not limited thereto.

[0045] In this embodiment, there is a gap G between the electronic component 130 and the circuit substrate 110. For example, Figure 1A As shown, there is a gap G1 between the first electronic component 1301 and the circuit substrate 110, and there is a gap G2 between the second electronic component 1302 and the circuit substrate 110. Further, the conductive member 132 electrically connecting the electronic component 130 and the circuit substrate 110 can maintain the gap G between the electronic component 130 and the circuit substrate 110. For example, the conductive member 1321 electrically connecting the first electronic component 1301 and the circuit substrate 110 can maintain the gap G1 between the first electronic component 1301 and the circuit substrate 110, and the conductive member 1322 electrically connecting the second electronic component 1302 and the circuit substrate 110 can maintain the gap G2 between the second electronic component 1302 and the circuit substrate 110. In some embodiments, the height of the gap G can be no greater than 75 microns. When the height of the gap G is within this range, it will increase the difficulty of filling the gap G, but the present invention is not limited thereto.

[0046] Please refer to Figure 1B, a two-stage thermosetting adhesive layer 120 is formed on the first surface 110a, and the two-stage thermosetting adhesive layer 120 includes a first portion 122 and a second portion 124 separated from each other, wherein the height H1 of the first portion 122 and the height H2 of the second portion 124 are substantially the same, and the first portion 122 completely covers the electronic component 130 and fills the gap G between the electronic component 130 and the circuit substrate 110, and the second portion 124 can be used for the subsequent chip bonding process. In other words, the top surface 122a of the first portion 122 and the top surface 124a of the second portion 124 can be substantially coplanar. For example, if Figure 1B As shown, the first part 122 may include a first part 1221 and a first part 1222, wherein the first part 1221 completely covers the first electronic component 1301 and fills the gap G1 between the first electronic component 1301 and the circuit substrate 110, and the first part 1222 completely covers the second electronic component 1302 and fills the gap G2 between the second electronic component 1302 and the circuit substrate 110.

[0047] In the present embodiment, the two-stage thermosetting adhesive layer 120 is first formed on the circuit substrate 110 in the form of A-stage liquid adhesive. The fluidity and capillary phenomenon of the A-stage liquid adhesive can reduce the difficulty of filling the gap G, so that the first portion 122 of the two-stage thermosetting adhesive layer 120 can completely cover the electronic component 130 and fill the gap G between the electronic component 130 and the circuit substrate 110. Since the size of the filler in the two-stage thermosetting adhesive layer 120 is smaller than the size of the filler in the epoxy resin molding compound and has better fluidity, the two-stage thermosetting adhesive layer 120 can smoothly and completely fill the gap G between the electronic component 130 and the circuit substrate 110, effectively protecting the electronic component 130 and avoiding the problem of ineffective filling due to the filler being too large, thereby reducing the probability of damage to the electronic component 130 and improving the reliability of the chip packaging structure 100. In addition, the material cost of the two-stage thermosetting adhesive layer 120 is lower than that of the molded underfill (MUF), and thus the manufacturing cost of the chip package structure 100 can also be reduced.

[0048] Please also refer to Figure 1A and Figure 1B The two-stage thermosetting adhesive layer 120 can be formed by the following steps. First, a mold 10 having a plurality of openings OP can be provided, and the mold 10 having a plurality of openings OP can be used to form an A-stage liquid adhesive on the first surface 110a by, for example, printing or coating, so as to subsequently form the two-stage thermosetting adhesive layer 120. In one embodiment, the mold 10 is made of, for example, a steel plate, but the present invention is not limited thereto.

[0049] In this embodiment, the plurality of openings OP may correspond to the formation positions of the first portion 122 and the second portion 124 of the subsequent two-stage thermosetting adhesive layer 120. Figure 1A As shown by the dotted frame lines, the plurality of openings OP may include a plurality of openings OP1 and openings OP2 to respectively correspond to the formation positions R1 of the first portion 122 and R2 of the second portion 124 of the subsequent two-stage thermosetting adhesive layer 120 .

[0050] It should be noted that the present invention is not limited to the aforementioned method of forming the two-stage thermosetting adhesive layer 120. As long as the two-stage thermosetting adhesive layer 120 including the first portion 122 and the second portion 124 separated from each other can be formed on the first surface 110a, the height H1 of the first portion 122 and the height H2 of the second portion 124 can be substantially the same, and the first portion 122 completely covers the electronic component 130 and fills the gap G between the electronic component 130 and the circuit substrate 110, it falls within the protection scope of the present invention.

[0051] Please continue to refer to Figure 1B After forming the A-stage liquid glue on the first surface 110a at the positions corresponding to the first portion 122 and the second portion 124 of the subsequent two-stage thermosetting glue layer 120, heating, vacuum drying or ultraviolet irradiation are performed to remove the solvent of the A-stage liquid glue, so that the A-stage liquid glue is converted into a dry and incompletely cured B-stage glue. The B-stage glue is a non-sticky dry film when the temperature is lower than its glass transition temperature (glass transition temperature, Tg), which is convenient for transportation and storage. When the B-stage glue is in an environment higher than its glass transition temperature, it becomes viscous and fluid, which can be used to wet and adhere the chip 140 or other components.

[0052] Please refer to Figure 1C , the chip 140 is configured on the second portion 124. In the present embodiment, the chip 140 is configured on the second portion 124 by lamination, and the temperature provided by the lamination step is higher than the glass transition temperature of the two-stage thermosetting adhesive layer 120 when it is in the B-stage adhesive, so that the B-stage adhesive has adhesiveness to bond the circuit substrate 110 and the chip 140. The present invention forms a protective adhesive layer (i.e., the first portion 122 of the two-stage thermosetting adhesive layer 120) that completely covers the electronic component 130 while configuring the die-bonding adhesive layer (i.e., the second portion 124 of the two-stage thermosetting adhesive layer 120), thereby omitting the process of separately forming a protective layer for the electronic component 130, thereby simplifying the process and further reducing the manufacturing cost.

[0053] In the present embodiment, the chip 140 may be wire-bonded to the first surface 110a of the circuit substrate 110. In other words, the chip 140 may be configured with its active surface 140a facing upward and the back surface 140b relative to the active surface 140a bonded to the second portion 124 of the two-stage thermosetting adhesive layer 120. For example, the electrical contacts on the chip 140 may be electrically connected to the pads 112 on the first surface 110a via wires L. The present invention does not limit the type of chip 140, which may be determined based on actual design requirements.

[0054] Please continue to refer to Figure 1C Before the subsequent curing process is performed to completely cure the two-stage thermosetting adhesive layer 120, in order to reduce the possibility that the electronic component 130 is affected by electromagnetic interference and the stability of the electronic component 130 during use or the electronic component 130 is damaged due to overheating after operation, so as to further improve the reliability of the chip packaging structure 100, the metal sheet 150 can be arranged on the first portion 122 when the two-stage thermosetting adhesive layer 120 is in the B-stage adhesive state and has viscosity. In this embodiment, the metal sheet 150 can only cover the top surface 122a of the first portion 122 to reduce the use of materials and further reduce the manufacturing cost, but the present invention is not limited to this. In an embodiment not shown, the metal sheet 150 can extend to cover the side wall of the first portion 122.

[0055] In some embodiments, based on the different functionalities of the electronic components 130, the metal sheet 150 may be an anti-magnetic metal sheet, a heat dissipation metal sheet, or a combination thereof. For example, the first electronic component 1301 completely covered by the first portion 1221 is, for example, a magnetic active component, and the metal sheet 1501 disposed thereon may be an anti-magnetic metal sheet (for example, an iron-nickel alloy), while the second electronic component 1302 completely covered by the first portion 1222 is, for example, a passive component, and the metal sheet 1502 disposed thereon may be a heat dissipation metal sheet (for example, copper, aluminum).

[0056] The present invention does not limit the order of configuring the chip 140 and the metal sheet 150. In some embodiments, the chip 140 may be configured first and then the metal sheet 150. In some embodiments, the metal sheet 150 may be configured first and then the chip 140. In some embodiments, the metal sheet 150 and the chip 140 may be configured simultaneously.

[0057] Please refer to Figure 1D, after at least configuring the chip 140, a curing process is performed to completely cure the two-stage thermosetting adhesive layer 120 in the B-stage adhesive state to the C-stage adhesive state, and to form a stable fixed adhesive layer. The curing process is, for example, baking the two-stage thermosetting adhesive layer 120 in the B-stage adhesive state. In addition, a packaging colloid 160 is formed to cover the two-stage thermosetting adhesive layer 120 and the chip 140. In this embodiment, the packaging colloid 160 is, for example, an epoxy resin molding compound. Further explanation, the curing process can be performed simultaneously in the step of forming the packaging colloid 160. In this case, the two-stage thermosetting adhesive layer 120 is still in the B-stage adhesive state and is not completely cured when the packaging colloid 160 is formed, so it can still be deformed appropriately. Under the high-pressure environment of forming the packaging colloid 160, the two-stage thermosetting adhesive layer 120 in the B-stage adhesive state is tightly compressed, so that possible gaps or bubbles are eliminated, thereby effectively increasing the die bonding area. In the process of forming the encapsulation colloid 160, a glue injection temperature higher than the curing temperature of the two-stage thermosetting glue layer 120 is provided at the same time, so that the two-stage thermosetting glue layer 120 is completely cured. Since the first part 122 of the two-stage thermosetting glue layer 120 has been filled into the gap G between the electronic component 130 and the circuit substrate 110, it is possible to prevent the larger filler in the encapsulation colloid 160 from flowing into the gap G, causing damage to the electronic component 130 or causing bubbles in the filling colloid in the gap G. In addition, there is no need to select a molded bottom filler (MUF) with a smaller filler size but a more expensive price to match the gap G, thereby improving the reliability of the chip packaging structure 100 and reducing its manufacturing cost. In this embodiment, the encapsulation colloid 160 can cover the two-stage thermosetting glue layer 120, the chip 140 and the metal sheet 150. After the above process, the chip packaging structure 100 of this embodiment can be substantially completed.

[0058] Figure 2 is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention. Figure 2 The chip package structure 100 a of this embodiment is similar to the chip package structure 100 of the above embodiment, but the difference is that the chip 140 of this embodiment can be wire-bonded to the second surface 110 b of the circuit substrate 110 .

[0059] Further, the circuit substrate 110 of the present embodiment may have a through hole P extending from the first surface 110a to the second surface 110b, and the pad 112 may also be disposed on the second surface 110b of the circuit substrate 110. The active surface 140a of the chip 140 may face the circuit substrate 110. In other words, the chip 140 may be configured in a manner that its back surface 140b faces upward and the active surface 140a is bonded to the second portion 124 of the two-stage thermosetting adhesive layer 120. In the present embodiment, the number of the second portions 124 of the two-stage thermosetting adhesive layer 120 is two, which are respectively located on both sides of the through hole P, and the chip 140 is configured on the second portion 124 in a manner that the electrical contacts on its active surface 140a are aligned with the through hole P. Therefore, the electrical contacts on the active surface 140a of the chip 140 may be electrically connected to the pad 112 on the second surface 110b through the wire L passing through the through hole P.

[0060] On the other hand, in order to protect the conductive path between the chip 140 and the second surface 110 b, the encapsulation colloid 160 can be further filled between the two second portions 124 and in the through hole P, and extended to the second surface 110 b, ensuring that the encapsulation colloid 160 completely covers the wire L, so as to effectively protect the conductive path between the chip 140 and the circuit substrate 110.

[0061] In summary, the present invention uses the characteristics of the filler in the two-stage thermosetting adhesive layer being smaller in size and having better fluidity to enable the first part of the two-stage thermosetting adhesive layer to completely cover the electronic component and fill the gap between the electronic component and the circuit substrate, thereby avoiding the situation where the larger filler in the encapsulation colloid flows into the gap and causes damage to the electronic component or causes the filling colloid in the gap to be incompletely filled and has bubbles, thereby effectively protecting the electronic component, reducing the probability of damage to the electronic component and improving the reliability of the chip packaging structure. In addition, since the material cost of the two-stage thermosetting adhesive layer is lower than that of the molded bottom filler (MUF), the manufacturing cost can be reduced while improving the reliability of the chip packaging structure. On the other hand, the height of the first part of the two-stage thermosetting adhesive layer of the present invention is substantially the same as the height of the second part, that is, a protective adhesive layer (i.e., the first part of the two-stage thermosetting adhesive layer) that completely covers the electronic component can be formed at the same time as the die bonding adhesive layer (i.e., the second part of the two-stage thermosetting adhesive layer), and the process of forming a protective layer for each electronic component can be omitted, thereby simplifying the process and further reducing the manufacturing cost. In addition, a metal sheet can be disposed on the first portion of the two-stage thermosetting adhesive layer to reduce the stability of electronic components during use due to electromagnetic interference or damage to electronic components due to overheating during operation, thereby further improving the reliability of the chip packaging structure.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a chip packaging structure, characterized in that: include: Providing a circuit substrate, wherein the circuit substrate has a first surface and a second surface opposite to each other; Disposing at least one electronic component on the first surface, and the at least one electronic component is electrically connected to the circuit substrate via a conductive member; A two-stage thermosetting adhesive layer is formed on the first surface, wherein: The two-stage thermosetting adhesive layer includes a first part and a second part separated from each other; The height of the first portion is substantially the same as the height of the second portion; and While disposing the second portion of the two-stage thermosetting adhesive layer in the A-stage adhesive state, the first portion that completely covers the at least one electronic component is formed simultaneously, wherein the first portion in the A-stage adhesive state completely covers the at least one electronic component and fills the gap between the at least one electronic component and the circuit substrate, wherein the A-stage adhesive state is in the form of liquid adhesive; After forming a two-stage thermosetting adhesive layer on the first surface, converting the two-stage thermosetting adhesive layer in an A-stage adhesive state into a dry and incompletely cured two-stage thermosetting adhesive layer in a B-stage adhesive state; Arrange a chip on the second portion in a B-stage adhesive state and wire-bond the chip to the first surface or the second surface of the circuit substrate; Performing a curing process to completely cure the two-stage thermosetting adhesive layer to a C-stage adhesive state, wherein the C-stage adhesive state is a completely cured form; and A packaging colloid is formed to cover the two-stage thermosetting adhesive layer and the chip.

2. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The method further includes printing the first part and the second part onto the first surface through a mold having a plurality of openings, wherein positions of the plurality of openings correspond to formation positions of the first part and the second part respectively.

3. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: Before performing a curing process to completely cure the two-stage thermosetting adhesive layer, a metal sheet is disposed on the first portion.

4. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The conductive member electrically connects the at least one electronic component and the circuit substrate so as to maintain the gap between the at least one electronic component and the circuit substrate.

5. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The height of the gap is no greater than 75 microns.

6. A chip packaging structure, characterized in that: The invention is manufactured by the manufacturing method according to any one of claims 1 to 5.

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