Semiconductor structure and method for forming the same

Abstract

The semiconductor structure includes: a source component; a drain component; one or more channel layers connecting the source component and the drain component; and a gate structure between the source component and the drain component. The gate structure is bonded to each of the one or more channel layers. The semiconductor structure also includes: a first source silicide component above the source component; a source contact above the first source silicide component; a second source silicide component below the source component; a through hole below the second source silicide component; and a power rail below the through hole. The first source silicide component and the second source silicide component completely surround the source component in a cross-sectional view. The power rail is a backside power rail. Embodiments of the present application also relate to a method of forming a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] Conventionally, integrated circuits (ICs) are built in a stacked fashion with transistors at the lowest level and interconnects (vias and wires) on top of the transistors to provide connectivity to the transistors. Power rails (e.g., metal lines for voltage sources and ground planes) are also located above the transistors and may be part of the interconnects. As integrated circuits continue to shrink, so do the power rails. This inevitably leads to an increase in the voltage drop across the power rails and an increase in the power consumption of the integrated circuit. Therefore, while existing methods in semiconductor manufacturing are generally adequate for their intended purposes, they are not completely satisfactory in all respects. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor structure, including: a source component; a drain component; one or more channel layers connecting the source component and the drain component; a gate structure between the source component and the drain component, the gate structure being bonded to each of the one or more channel layers; a first source silicide component above the source component; a source contact above the first source silicide component; a second source silicide component below the source component; a through hole below the second source silicide component; and a power rail below the through hole, wherein the first source silicide component and the second source silicide component completely surround the source component in a cross-sectional view.

[0004] Some other embodiments of the present application provide a semiconductor structure, comprising: a power rail on the back side of the semiconductor structure; a first interconnect structure on the front side of the semiconductor structure; a source component, a drain component, a plurality of channel layers and a gate structure between the power rail and the first interconnect structure, wherein the plurality of channel layers connect the source component and the drain component, and the gate structure wraps around each of the channel layers; a first source silicide component arranged on the back side of the source component and between the source component and the power rail, wherein the first source silicide component is also arranged on a sidewall of the source component extending from the back side of the source component toward the front side of the semiconductor structure; and a first through hole connecting the first source silicide component with the power rail.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: providing a structure having a substrate, a stack of first and second semiconductor layers alternately stacked layer by layer above the substrate, a sacrificial gate structure arranged above a channel region of the stack, and a gate spacer located on opposite side walls of the sacrificial gate structure; etching the gate spacer adjacent to the stack to form a source trench and a drain trench on both sides of the sacrificial gate structure; epitaxially growing a source component in the source trench and epitaxially growing a drain component in the drain trench; forming a first dielectric layer on a side of the source component, a side of the drain component, a side of the source trench, and a side of the drain trench; and forming a contact etch stop layer (CESL) above the first dielectric layer, the source component, and the drain component, wherein a first air gap is sealed between the CESL and the first dielectric layer in the source trench, and a second air gap is sealed between the CESL and the first dielectric layer in the drain trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A , Figure 1B and Figure 1C A flow chart illustrating a method of forming a semiconductor device having backside power rails and backside self-aligned vias according to various aspects of the present invention.

[0008] Figure 2 and Figure 3 According to some embodiments, Figures 1A to 1C A cross-sectional view of a portion of a semiconductor device during an intermediate fabrication step of an embodiment of a method.

[0009] Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A and Fig.22A A top view of a portion of a semiconductor device according to some embodiments is shown.

[0010] Figure 4B , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G , Figure 6B , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 8B , Figure 8C , Fig.8D , Fig. 8E , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 10E , Fig. 11B , Fig. 11C , Fig.11D , Fig.11E , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig. 13B , Fig. 13C , Fig.13D , Fig.13E , Fig. 14B , Fig. 14C , Fig.14D , Fig.14E , Fig. 15B , Fig. 15C , Fig.15D , Fig.15E , Fig. 16B , Fig. 16C , Fig.16D , Fig.16E , Fig. 17B , Fig. 17C , Fig.17D , Fig.17E , Fig.18B , Fig. 18C , Fig.18D , Fig.18E , Fig.19B , Fig.19C , Fig.19D , Fig.19E , Fig. 20B , Fig. 20C , Fig.20D , Fig.20E , Fig. 21B , Fig. 21C , Fig.21D , Fig.21E and Fig. 22B A cross-sectional view of a portion of a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component is in direct contact with the second component, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component is not in direct contact with the second component. In addition, the present invention may repeat reference numbers and / or characters in multiple instances. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Moreover, for ease of description, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Further, when "about," "approximately," and the like are used to describe numbers or ranges of numbers, unless otherwise stated, in view of the specific technology disclosed herein, and according to the knowledge of those skilled in the art, the term encompasses numbers within certain variations (such as + / -10% or other variations) of the described numbers. For example, the term "about 5 nm" may encompass size ranges such as 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, and the like.

[0013] The present application relates generally to semiconductor structures and manufacturing processes, and more specifically to semiconductor devices with backside power rails and backside self-aligned vias. As described above, power rails in ICs need to be further improved in order to provide the desired performance improvement and reduce power consumption. In addition to the interconnect structure (which may also include power rails) on the front side (or front side) of a structure containing transistors (such as gate-all-around (GAA) transistors and / or FinFET transistors), the purpose of the present invention also includes providing power rails (or power wiring) on ​​the back side (or back side) of the structure. This increases the number of metal tracks in the structure that can be used to directly connect to source / drain contacts and vias. It also increases the gate density compared to existing structures without backside power rails, thereby achieving greater device integration. The size of the backside power rail may be wider than the size of the first-level metal (M0) track on the front side of the structure, which advantageously reduces the resistance of the power rail. The present invention also provides structures and methods for isolating the backside power rail from nearby conductors (such as metal gates), and provides structures and methods for reducing the resistance between the backside power rail and the source / drain (S / D) components. The details of the structure and manufacturing method of the present invention are described below in conjunction with the accompanying drawings, which illustrate the process of manufacturing GAA devices according to some embodiments. GAA devices refer to devices with multi-channel transistors with vertical stacking and horizontal orientation, such as nanowire transistors and nanosheet transistors. Due to better gate control capabilities, lower leakage current, and full FinFET device layout compatibility, GAA devices are expected to push CMOS to the next stage of the roadmap. The present invention can also be used to manufacture FinFET devices with backside power rails and backside self-aligned through holes. For simplicity, the present invention takes GAA devices as an example and points out certain differences in the process between GAA embodiments and FinFET embodiments. Those of ordinary skill in the art should understand that they can easily use the present invention as a basis to design or modify other processes or structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein.

[0014] Figure 1A , Figure 1B and Figure 1C 1 is a flow chart of a method 100 for manufacturing a semiconductor device according to various aspects of the present invention. The present invention encompasses additional processing. Additional operations may be provided before, during, and after the method 100, and certain operations described may be moved, replaced, or eliminated for additional embodiments of the method 100.

[0015] Combined with the following Figures 2 to 22B Describing method 100, Figures 2 to 22BA top view and a cross-sectional view of a semiconductor device (or semiconductor structure) 200 in various manufacturing steps according to method 100 according to some embodiments are shown. In some embodiments, device 200 is part of an IC chip, a system on a chip (SoC), or a portion thereof, the portion including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations thereof. For clarity, the device 200 has been simplified. Figures 2 to 22B Additional components may be added to the device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the device 200.

[0016] At operation 102, method 100 ( Figure 1A ) A stack of first and second semiconductor layers 205 is formed over the substrate 201. According to an embodiment, Figure 2 and Figure 3 The resulting structure is shown in FIG. In particular, Figure 2 The substrate 201 in the embodiment is shown, and Figure 3 A stack 205 of semiconductor layers 210 and 215 in an embodiment is shown. In the depicted embodiment, substrate 201 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In the depicted embodiment, substrate 201 includes a semiconductor layer 204, an insulator 203, and a carrier 202. In an embodiment, semiconductor layer 204 may be silicon, silicon-germanium, germanium, or other suitable semiconductors; carrier 202 may be a portion of a silicon wafer; insulator 203 may be silicon oxide. The semiconductor-on-insulator substrate may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. In an optional embodiment, substrate 201 is a bulk silicon substrate (i.e., comprising bulk single crystal silicon). In various embodiments, the substrate 201 may include other semiconductor materials such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof.

[0017] In some embodiments, semiconductor layer 204 may include various doped regions depending on the design requirements of device 200. For example, an N-type doped region may be formed by doping with an n-type dopant such as phosphorus, arsenic, other n-type dopants, or a combination thereof; and a P-type doped region may be formed by doping with a p-type dopant such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, semiconductor layer 204 includes doped regions formed with a combination of a p-type dopant and an n-type dopant. In some embodiments, semiconductor layer 204 is undoped or unintentionally doped with a very small amount of dopant.

[0018] The semiconductor layer stack 205 is formed over the substrate 201 and includes semiconductor layers 210 and semiconductor layers 215 stacked vertically (e.g., along the z-direction) from the surface of the substrate 201 in a staggered or alternating configuration. In some embodiments, the semiconductor layers 210 and semiconductor layers 215 are epitaxially grown in the depicted staggered and alternating configuration. For example, a first semiconductor layer in the semiconductor layers 210 is epitaxially grown on the substrate, a first layer in the semiconductor layers 215 is epitaxially grown in a first layer in the semiconductor layers 215, a second layer in the semiconductor layers 210 is epitaxially grown on the first layer in the semiconductor layers 215, and so on, until the semiconductor layer stack 205 has a desired number of semiconductor layer 210 and semiconductor layer 215 positions. In such embodiments, the semiconductor layers 210 and semiconductor layers 215 may be referred to as epitaxial layers. In some embodiments, epitaxial growth of semiconductor layer 210 and semiconductor layer 215 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal organic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or a combination thereof.

[0019] The composition of semiconductor layer 210 is different from the composition of semiconductor layer 215 to achieve etching selectivity and / or different oxidation rates during subsequent processing. In some embodiments, semiconductor layer 210 has a first etching rate to an etchant and semiconductor layer 215 has a second etching rate to an etchant, wherein the second etching rate is less than the first etching rate. In some embodiments, semiconductor layer 210 has a first oxidation rate and semiconductor layer 215 has a second oxidation rate, wherein the second oxidation rate is less than the first oxidation rate. In the depicted embodiment, semiconductor layer 210 and semiconductor layer 215 include different materials, composition atomic percentages, composition weight percentages, thicknesses, and / or properties to achieve a desired etching selectivity during an etching process (such as an etching process implemented to form a suspended channel layer in a channel region of device 200). For example, where semiconductor layer 210 includes silicon germanium and semiconductor layer 215 includes silicon, the silicon etching rate of semiconductor layer 215 is less than the silicon germanium etching rate of semiconductor layer 210. In some embodiments, semiconductor layer 210 and conductor layer 215 may include the same material but have different composition atomic percentages to achieve etching selectivity and / or different oxidation rates. For example, semiconductor layer 210 and semiconductor layer 215 may include silicon germanium, wherein semiconductor layer 210 has a first silicon atomic percentage and / or a first germanium atomic percentage, and semiconductor layer 215 has a second different silicon atomic percentage and / or a second different germanium atomic percentage. The present invention contemplates semiconductor layer 210 and semiconductor layer 215 including any combination of semiconductor materials (e.g., materials that maximize current flow) that can provide a desired etch selectivity, a desired oxidation rate difference, and / or a desired performance characteristic, including any of the semiconductor materials disclosed herein.

[0020] As further described below, the semiconductor layer 215 or a portion thereof forms a channel region of the device 200. In the depicted embodiment, the semiconductor layer stack 205 includes three semiconductor layers 210 and three semiconductor layers 215, which are configured to form three semiconductor layer pairs arranged above the substrate 201, each semiconductor layer pair having a corresponding first semiconductor layer 210 and a corresponding second semiconductor layer 215. After being subjected to subsequent processing, such a configuration will result in the device 200 having three channels. However, the present invention contemplates embodiments in which the semiconductor layer stack 205 includes more or fewer semiconductor layers, for example, depending on the number of channels required for the device 200 (e.g., a GAA transistor) and / or the design requirements of the device 200. For example, the semiconductor layer stack 205 may include two to ten semiconductor layers 210 and two to ten semiconductor layers 215. In an optional embodiment in which the device 200 is a FinFET device, the stack 205 is only a layer of semiconductor material, such as a layer of Si. As will be discussed, the method 100 will process layers on both sides of the substrate 201. In the present invention, the side of the substrate 201 where the stack 205 is located is referred to as a front side, and the side opposite to the front side is referred to as a back side.

[0021] At operation 104, method 100 ( Figure 1A ) The fin 218 is formed by patterning the stack 205 and the substrate 201. Figure 4A A top view of the device 200 is shown with the fins 218 oriented along the “x” direction. Figure 4B Partly along Figure 4A The AA line in FIG. 2 shows a cross-sectional view of the device 200. Figure 4BAs shown, the fin 218 includes a patterned stack 205 (having layers 210 and 215), a patterned region 204, and one or more patterned hard mask layers 206. The fin 218 can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multiple patterning processes) can be used to pattern the fin 218. Typically, the double patterning or multiple patterning process combines photolithography with a self-aligned process, thereby allowing the creation of a pattern having, for example, a spacing smaller than that which can be obtained using a single direct photolithography method. For example, in one embodiment, a sacrificial layer is formed above the stack 205 and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used as mask elements for patterning the fin 218. For example, the mask element can be used to etch grooves into the stack 205 and the substrate 201, thereby leaving the fin 218 on the substrate 201. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, the dry etching process may be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. For example, the wet etching process may include etching in dilute hydrofluoric acid (DHF); a potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchants. Many other embodiments of the method of forming the fin 218 may be suitable.

[0022] At operation 106, method 100 ( Figure 1A ) to form various isolation structures on the substrate 201 and to isolate the fins 218, an embodiment of which FIG. 5A to FIG. 5G shown. Figure 5A A top view of the device 200 is shown, and Figures 5B to 5G The steps of operation 106 are shown along the Figure 5A A cross-sectional view of a portion of the device 200 taken along line AA in FIG.

[0023] refer to Figure 5B, an isolation component 230 is formed over and / or in the substrate 201 to isolate various regions of the device 200. For example, the isolation component 230 surrounds the bottom portion of the fin 218 to separate and isolate the fins 218 from each other. The isolation component 230 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon or other suitable isolation components) or a combination thereof. The isolation component 230 may include different structures, such as a shallow trench isolation (STI) structure and / or a deep trench isolation (DTI) structure. In an embodiment, the isolation component 230 may be formed by performing the following operations: filling the trenches between the fins 218 with an insulator material (e.g., by using a CVD process or a spin-on glass process), performing a chemical mechanical polishing (CMP) process to remove excess insulator material and / or flattening the top surface of the insulator material layer, and etching back the insulator material layer to form the isolation component 230. In some embodiments, the isolation component 230 includes a multilayer structure, such as a silicon nitride layer disposed above a thermal oxide liner layer.

[0024] refer to Figure 5C , a cladding layer 231 is deposited over the top and sidewall surfaces of the fin 218 and over the isolation feature 230. In an embodiment, the cladding layer 231 includes SiGe. The cladding layer 231 may be deposited using CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other suitable methods, or combinations thereof. After depositing the cladding layer 231, operation 106 performs an etching process to remove a portion of the cladding layer 231 from above the isolation feature 230, for example, using a plasma dry etching process.

[0025] refer to Figure 5D , a dielectric liner 232 is deposited over the cladding layer 231 and on the top surface of the isolation feature 230, and then a dielectric fill layer 233 is deposited on the dielectric liner 232 and fills the gaps between the fins 218. In an embodiment, the dielectric liner 232 includes a low-k dielectric material, such as a dielectric material including Si, O, N, and C. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, Black (Applied Materials, Santa Clara, CA), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, MI), polyimide, or a combination thereof. Low-k dielectric materials generally refer to dielectric materials having a low dielectric constant, such as a dielectric constant lower than that of silicon oxide (k≈3.9). The dielectric liner 232 may be deposited using CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. In an embodiment, the dielectric fill layer 233 includes silicon oxide, silicon nitride, silicon oxynitride, oxide formed from TEOS, PSG, BPSG, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The dielectric fill layer 233 may be deposited using a flowable CVD (FCVD) process, which includes, for example, depositing a flowable material (such as a liquid compound) over the device 200 and converting the flowable material into a solid material by appropriate techniques such as thermal annealing and / or ultraviolet radiation treatment. The dielectric fill layer 233 may be deposited using other types of methods. After depositing layers 232 and 233, operation 106 may perform a CMP process to planarize the top surface of the device 200 and expose the cladding layer 231.

[0026] refer to Figure 5E , a dielectric helmet 234 is deposited over dielectric layers 232 and 233 and between cladding layer 231 deposited on opposite sidewalls of fin 218. In an embodiment, dielectric helmet 234 comprises a high-k dielectric material such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), Si3N4, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials having a high dielectric constant, for example, greater than the dielectric constant of silicon oxide (k≈3.9). The dielectric helmet 234 is formed by any process described herein, such as ALD, CVD, PVD, an oxidation-based deposition process, other suitable processes, or combinations thereof. In an embodiment, operation 106 includes recessing dielectric layers 232 and 233 using a selective etching process that etches dielectric layers 232 and 233 and does not (or minimally) etch hard mask 206 and cladding layer 231. Operation 106 then deposits one or more dielectric materials into the recesses and performs a CMP process on the one or more dielectric materials to form dielectric helmet 234.

[0027] refer to Fig. 5F , operation 106 recesses the fins 218 (particularly removing the hard mask layer 206) and the cladding layer 231 disposed between the dielectric helmets 234. Operation 106 may selectively apply one or more etching processes to the hard mask layer 206 and the cladding layer 231, and may not etch (or etch minimally) the dielectric helmets 234. The selective etching process may be dry etching, wet drying, reactive ion etching, or other suitable etching methods.

[0028] refer to Figure 5G Operation 106 deposits a dielectric layer 235 over the surface of the fin 218 and over the dielectric helmet 234. In the present embodiment, the dielectric layer 235 is a dummy (or sacrificial) gate dielectric layer. The dummy dielectric 235 includes a dielectric material such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof, and can be deposited using any process described herein, such as ALD, CVD, PVD, other suitable processes, or a combination thereof.

[0029] At operation 108, method 100 ( Figure 1A ) A gate stack 240 is formed over the pseudo dielectric 235. According to an embodiment, FIG. 6A to FIG. 6B The resulting structure is shown in . Fig. 6A A top view of the device 200 is shown, and Figure 6B Shown along Fig. 6A. From the top view, the gate stack 240 is generally oriented in the length direction along the "y" direction perpendicular to the "x" direction. In the present embodiment, the gate stack 240 is a dummy (or sacrificial) gate stack and will be replaced by a functional gate stack 240'. The dummy gate stack 240 is formed by a deposition process, a photolithography process, an etching process, other suitable processes or a combination thereof. For example, a deposition process is performed to form a dummy gate electrode layer 245 above the dummy dielectric layer 235. In some embodiments, one or more hard mask layers 246 are deposited above the dummy gate electrode layer 245. In some embodiments, the dummy gate electrode layer 245 includes polysilicon or other suitable materials, and the one or more hard mask layers 246 include silicon oxide, silicon nitride or other suitable materials. The deposition process may include CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other suitable methods or combinations thereof. Then, a photolithography patterning and etching process is performed to pattern one or more hard mask layers 246, dummy gate electrode layer 245 and dummy gate dielectric layer 235 to form a dummy gate stack 240, such as Figure 6B As shown. The photolithography patterning process includes resist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing resist, rinsing, drying (e.g., hard baking), other suitable photolithography processes, or combinations thereof. The etching process includes dry etching process, wet etching process, other etching methods, or combinations thereof.

[0030] Operation 108 may also form gate spacers 247 (eg, Figure 7B). The gate spacer 247 is formed by any suitable process and includes a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN)). For example, a dielectric layer including silicon and nitrogen, such as a silicon nitride layer, may be deposited over the dummy gate stack 240 and then etched (e.g., anisotropically etched) to form the gate spacer 247. In some embodiments, the gate spacer 247 includes a multilayer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, are formed adjacent to the dummy gate stack 240. In such an embodiment, each set of spacers may include materials having different etching rates. For example, a first dielectric layer including silicon and oxygen (e.g., silicon oxide) may be deposited and etched to form a first set of spacers adjacent to the dummy gate stack 240, and a second dielectric layer including silicon and nitrogen (e.g., silicon nitride) may be deposited and etched to form a second set of spacers adjacent to the first set of spacers.

[0031] At operation 110, method 100 ( Figure 1A ) A source / drain (S / D) trench 250 is formed by etching the fin 218 adjacent to the gate spacer 247. According to an embodiment, in 7A to 7E The resulting structure is shown in . Fig. 7A A top view of the device 200 is shown, and Figure 7B , Figure 7C , Fig.7D and Fig. 7E Shown along Fig. 7A 2 is a cross-sectional view of the device 200 along the BB line, CC line, DD line and EE line in FIG. Specifically, the DD line is cut into the source region of the transistor and is parallel to the gate stack 240, and the EE line is cut into the drain region of the transistor and is parallel to the gate stack 240. FIG. 8A to FIG. 21A The DD line and EE line in are configured similarly.

[0032] In the depicted embodiment, the etching process completely removes the semiconductor layer stack 205 in the source / drain region of the fin 218, thereby exposing the substrate portion 204 of the fin 218 in the source / drain region. Therefore, the source / drain trench 250 has sidewalls defined by the remaining portion of the semiconductor layer stack 205 and a bottom defined by the substrate 201, which are arranged in the channel region under the gate stack 240. In some embodiments, the etching process removes some but not all of the semiconductor layer stack 205, so that the source / drain trench 250 has a bottom defined by the semiconductor layer 210 or the semiconductor layer 215 in the source / drain region. In some embodiments, the etching process further removes some but not all of the substrate portion of the fin 218, so that the source / drain source / drain trench 250 extends below the topmost surface of the substrate 201. The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or combinations thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may alternate etchants to individually and alternately remove the semiconductor layer 210 and the semiconductor layer 215. In some embodiments, the parameters of the etching process are configured to selectively etch the semiconductor layer stack and to minimally (to not) etch the gate stack 240 and / or the isolation feature 230. In some embodiments, a photolithography process, such as the photolithography process described herein, is performed to form a patterned mask layer covering the gate stack 240 and / or the isolation feature 230, and the etching process uses the patterned mask layer as an etching mask.

[0033] Operation 110 further forms an inner spacer 255 along the sidewall of the semiconductor layer 210 in the S / D trench 250 (see Figure 7B). For example, a first etching process is performed that selectively etches the semiconductor layer 210 exposed by the source / drain trenches 250 and etches the semiconductor layer 215 minimally (to no etching) so that a gap is formed between the semiconductor layers 215 and between the semiconductor layer 215 and the semiconductor layer 204 under the gate spacer 247. Therefore, a portion (edge) of the semiconductor layer 215 is suspended in the channel region under the gate spacer 247. In some embodiments, the gap partially extends below the dummy gate stack 240. The first etching process is configured to etch the semiconductor layer 210 laterally (e.g., along the "x" direction) to reduce the length of the semiconductor layer 210 along the "x" direction. The first etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. Then, a deposition process forms a spacer layer over the gate structure 240 and over the components defining the source / drain trench 250 (e.g., semiconductor layer 215, semiconductor layer 210, and semiconductor layer 204) using, for example, CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. The spacer layer partially (and in some embodiments, completely) fills the source / drain trench 250. The deposition process is configured to ensure that the spacer layer fills the gaps between the semiconductor layers 215 and between the semiconductor layers 215 and the substrate 201 under the gate spacer 247. A second etching process is then performed that selectively etches the spacer layer to form a gate structure 240 such as the gate structure 240 and the gate structure 240. Figure 7B 2 and 3. In some embodiments, the inner spacer 255 described in the present invention is removed from the sidewalls of the gate spacer 247, the sidewalls of the semiconductor layer 215, the dummy gate stack 240, and the substrate 201, and the semiconductor layer 215, the dummy gate stack 240, and the gate spacer 247 are etched minimally (to no etching). In some embodiments, the spacer layer is removed from the sidewalls of the gate spacer 247, the sidewalls of the semiconductor layer 215, the dummy gate stack 240, and the substrate 201. The spacer layer (and therefore the inner spacer 255) includes a material different from the material of the semiconductor layer 215 and the gate spacer 247 to achieve a desired etch selectivity during the second etching process. In some embodiments, the spacer layer 255 includes a dielectric material that includes silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon nitride oxide, silicon carbide, or silicon oxycarbide). In some embodiments, the inner spacer layer 255 includes a low-k dielectric material, such as the low-k dielectric materials described herein. In embodiments where the device 200 is a FinFET, the inner spacer 255 is omitted.

[0034] At operation 112, method 100 ( Figure 1A ) performs additional etching on the source region of the device 200. According to an embodiment, FIG. 8A to FIG. 8E The resulting structure is shown in . Fig. 8A A top view of the device 200 is shown, and Figure 8B , Figure 8C , Fig.8D and Fig. 8E Shown along Fig. 8A A cross-sectional view of the device 200 taken along the BB line, CC line, DD line and EE line in FIG.

[0035] In the depicted embodiment, operation 112 forms an etch mask 241 that includes a patterned hard mask 236 and a patterned resist 237. The etch mask 241 covers the device 200 except for the source region, which is exposed by an opening 238 in the etch mask 241. Operation 112 then etches the source region into the substrate 201 until only a thin layer 204 remains in the source trench 250, thereby extending the source trench 250 into the substrate 201. The etching process may include dry etching, wet etching, reactive ion etching, or other suitable etching. In this embodiment, the etching process is substantially anisotropic (i.e., substantially vertical). Moreover, the etching process is tuned selectively to the material of the semiconductor layer 204, while the gate spacer 247 and the gate hard mask layer 246 are not etched (or are minimally etched). The etching process in operation 112 may be similar to the etching process in operation 110. After the etching process is completed, operation 112 removes the patterned resist 237 , such as by a stripping process.

[0036] At operation 114, method 100 ( Figure 1A ) A semiconductor layer 239 is formed in the source trench 250. According to an embodiment, 9A to 9E The resulting structure is shown in . Fig. 9A A top view of the device 200 is shown, and Fig. 9B , Fig. 9C , Fig.9D and Fig.9E Shown along Fig. 9A A cross-sectional view of the device 200 taken along the BB line, CC line, DD line and EE line in FIG.

[0037] The semiconductor layer 239 may be deposited using an epitaxial growth process or by other suitable processes. In some embodiments, epitaxial growth of the semiconductor layer 239 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal organic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or a combination thereof. The semiconductor layer 239 includes a semiconductor material different from the semiconductor material included in the semiconductor layer 204 to achieve etching selectivity during subsequent processing. For example, the semiconductor layers 239 and 204 may include different materials, different composition atomic percentages, different composition weight percentages, and / or other components to achieve the desired etching selectivity during the etching process. In an embodiment, the semiconductor layer 204 includes silicon and the semiconductor layer 239 includes silicon germanium. In another embodiment, both the semiconductor layers 239 and 204 may include silicon germanium, but with different silicon atomic percentages. The present invention contemplates that the semiconductor layers 239 and 204 include any combination of semiconductor materials that can provide the desired etching selectivity, including any semiconductor material disclosed herein. Due to the drain region ( Fig.9E ) is covered by the patterned hard mask layer 236, so the semiconductor layer 239 is only deposited in the source region ( Fig.9D ). The semiconductor layer 239 is deposited to a thickness close to the bottom of the stack 205 ( Fig. 9B ), and the top surface of the isolation member 230 ( Fig.9D Operation 114 may include an etching process that recesses the semiconductor layer 239 to a level with the semiconductor layer 239 if the semiconductor layer 239 was initially grown higher than the semiconductor layer 239. Fig. 9B and Fig.9D After depositing the semiconductor layer 239, operation 114 removes the patterned hard mask layer 236 by one or more etching processes. As will be discussed below, in various embodiments, the additional etching in operation 112 and the growth of the semiconductor layer 239 in operation 114 may be performed only in the source region, only in the drain region, or in both the source and drain regions.

[0038] At operation 116, method 100 ( Figure 1A ) epitaxially grows a semiconductor S / D component 260 in the S / D trench 250. According to an embodiment, in FIG. 10 to FIG. Fig. 10E The resulting structure is shown in . Fig. 10A A top view of the device 200 is shown, and Fig. 10B , Fig. 10C , Fig. 10D and Fig. 10E Shown along Fig. 10A A cross-sectional view of the device 200 taken along the BB line, CC line, DD line and EE line in FIG.

[0039] like Fig. 10B , Fig. 10Dand Fig. 10E As shown, epitaxial S / D components 260 are grown from semiconductor layers 204 and 239 at the bottom of S / D trench 250 and semiconductor layer 215 at the sidewalls of S / D trench 250. The epitaxial process may use CVD deposition techniques (e.g., VPE and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the components of semiconductor layers 204, 239, and 215 (particularly semiconductor layer 215). Epitaxial S / D components 260 are doped with n-type dopants or p-type dopants for n-type transistors or p-type transistors, respectively. In some embodiments, for n-type transistors, epitaxial S / D components 260 include silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., to form Si:C epitaxial source / drain components, Si:P epitaxial source / drain components, or Si:C:P epitaxial source / drain components). In some embodiments, for p-type transistors, the epitaxial S / D component 260 includes silicon germanium or germanium, and may be doped with boron, other p-type dopants, or a combination thereof (e.g., to form a Si:Ge:B epitaxial source / drain component). In some embodiments, the epitaxial S / D component 260 includes multiple epitaxial semiconductor layers, wherein the epitaxial semiconductor layers may include the same or different materials and / or dopant concentrations. In addition, in an embodiment, the S / D component 260 (or at least a portion thereof adjacent to the semiconductor layer 239) includes a different material composition than the semiconductor layer 239 to achieve etch selectivity during the backside via formation process. For example, in an embodiment, the semiconductor layer 239 includes SiGe, and the S / D component 260' includes Si (for n-type transistors). For example, in another embodiment, the semiconductor layer 239 includes SiGe having a first Ge atomic percentage, and the S / D component 260' includes SiGe having a second Ge atomic percentage different from the first Ge atomic percentage (for p-type transistors). In some embodiments, the epitaxial S / D features 260 include materials and / or dopants that achieve desired tensile and / or compressive stresses in the corresponding channel regions. In some embodiments, the epitaxial source / drain features 260 are doped during deposition by adding impurities to the source material of the epitaxial process (i.e., in situ). In some embodiments, the epitaxial source / drain features 260 are doped by an ion implantation process after the deposition process. In some embodiments, an annealing process (e.g., rapid thermal annealing (RTA) and / or laser annealing) is performed to activate the dopants in the epitaxial source / drain features 260. In some embodiments, the epitaxial source / drain features 260 are formed in a separate processing sequence, including, for example, masking a p-type GAA transistor region when forming the epitaxial source / drain features 260 in an n-type GAA transistor region, and masking an nGAA transistor region when forming the epitaxial source / drain features 260 in a p-type GAA transistor region. In addition, as Fig. 10D and Fig. 10EAs shown, the S / D features 260 are formed in stripes and do not completely fill the S / D trenches 250, leaving some gaps 261 between the S / D features 260 and the dielectric layer 232 and the isolation features 230. In some embodiments, the gaps 261 extend along the "y" direction by a distance in the range of about 1 nm to about 10 nm. If the gaps 261 are too narrow (such as less than 1 nm), there is not enough space to deposit the dielectric layer 262 and form the air gaps 263, as will be described with reference to FIG. FIG. 11A to FIG. 11E and FIG. 12A to FIG. 12E Discussion If the gap 261 is too wide (such as greater than 10 nm), device integration will be hindered, or the S / D features 260 will be too small to achieve good device performance.

[0040] At operation 118, method 100 ( Figure 1B ) A dielectric layer 262 is formed over the S / D feature 260 and in the S / D trench 250. According to an embodiment, FIG. 11A to FIG. 11E The resulting structure is shown in . Fig.11A A top view of the device 200 is shown, and Fig. 11B , Fig. 11C , Fig.11D and Fig.11E Shown along Fig.11A A cross-sectional view of the device 200 taken along the BB line, CC line, DD line and EE line in FIG.

[0041] like Fig. 11B , Fig.11D and Fig.11E As shown, a dielectric layer 262 is deposited on the top and sidewall surfaces of the S / D features 260 and the surface of the S / D trench 250. In an embodiment, the dielectric layer 262 is deposited to have a substantially uniform thickness, such as in a range of about 0.2 nm to about 4 nm. This thickness range is designed to be thin enough to produce an air gap 263 (such as Fig.12E In the embodiment of the present invention, the dielectric layer 262 is preferably thin (larger than the dielectric layer 262) but thick enough to seal the air gap 263 to its surrounding components. In general, a larger air gap 263 is more ideal for reducing the stray capacitance associated with the S / D component 260. In the present embodiment, the dielectric layer 262 includes a material that achieves etch selectivity in the etchant relative to the S / D component 260 and the dielectric layers 232, 234 and 230. In other words, the etchant is able to etch the dielectric layer 262 and, in a later manufacturing step, etch the S / D component 260, and not etch (or minimally etch) the dielectric layer 234, the dielectric layer 232 and the isolation component 230. In various embodiments, the dielectric layer 262 may include aluminum oxide (Al2O3), other oxides, silicon nitride (Si3N4), silicon carbide (SiCN), silicon oxycarbide (SiOCN), or other dielectric materials.

[0042] At operation 120, method 100 ( Figure 1B ) to etch back the dielectric layer 262 and form a contact etch stop layer (CESL) 269 and an interlayer dielectric (ILD) layer 270. According to an embodiment, in Fig. 12A Fig.12E The resulting structure is shown in . Fig. 12A A top view of the device 200 is shown, and Fig. 12B , Fig. 12C , Fig.12D and Fig.12E Shown along Fig. 12A A cross-sectional view of the device 200 taken along the BB line, CC line, DD line and EE line in FIG.

[0043] like FIG. 12B to FIG. 12E As shown, the dielectric layer 262 is partially recessed, and the CESL 269 is deposited over the dielectric layer 262 and the S / D features 260. The air gap is sealed by the dielectric layer 262 and the CESL 269. The ILD layer 270 is deposited over the CESL 269 and fills the space between the opposing gate spacers 247. The CESL 269 includes a material different from the ILD layer 270 and different from the dielectric layer 234. The CESL 269 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable materials; and may be formed by CVD, PVD, ALD, or other suitable methods. The ILD layer 270 may include an oxide formed from tetraethyl orthosilicate (TEOS), an undoped silicate glass, or a doped silicon oxide, such as borophosphosilicate glass (BPSG), fluoride-doped silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), a low-k dielectric material, other suitable dielectric materials, or a combination thereof. The ILD 270 may be formed by PECVD (plasma enhanced CVD), FCVD (flowable CVD), or other suitable methods. After the CESL 269 and the ILD layer 270 are deposited, a CMP process and / or other planarization process may be performed until the top portion (or top surface) of the dummy gate stack 240 is reached (exposed). In some embodiments, the planarization process removes the hard mask layer 246 of the dummy gate stack 240 to expose the dummy gate electrode 245 below, such as a polysilicon gate electrode layer.

[0044] At operation 122, method 100 ( Figure 1B ) replaces the dummy gate stack 240 with a functional gate stack 240' (such as a high-k metal gate). Fig.13A , Fig. 13B and Fig. 13CThe resulting structure is shown in . Fig.13A A top view of the device 200 is shown, and Fig. 13B and Fig. 13C Shown along Fig.13A This involves a variety of processes as briefly described below.

[0045] First, operation 122 uses one or more etching processes to remove the dummy gate stack 240 (dummy gate electrode 245 and dummy gate dielectric layer 235, see Figure 6B ). This forms a gate trench. The etching process may be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may alternately use etchants to remove the various layers of the dummy gate stack 240, respectively. In some embodiments, the etching process is configured to selectively etch the dummy gate stack 240, and to etch minimally (to no etching) other components of the device 200, such as the ILD layer 270, the gate spacer 247, the isolation component 230, the cladding layer 231, the semiconductor layer 210, and the semiconductor layer 215.

[0046] Next, operation 122 removes the capping layer 231 exposed in the gate trench. The etching process can selectively etch the capping layer 231 and minimally (to no) etch the semiconductor layer 215, the gate spacer 247, and the inner spacer 255.

[0047] Next, operation 122 removes the semiconductor layer 210 exposed in the gate trench, thereby suspending the semiconductor layer 215 above the semiconductor layer 204 and connecting to the S / D features 260. This process is also referred to as a channel release process, and the semiconductor layer 215 is also referred to as a channel layer. The etching process selectively etches the semiconductor layer 210, and etches the semiconductor layer 215 minimally (to no etching), and in some embodiments, etches the gate spacer 247 and / or the inner spacer 255 minimally (to no etching). In embodiments where the device 200 is a FinFET, the channel release process is omitted because there is only the channel layer 215 and no semiconductor layer 210 in the channel region.

[0048] Next, operation 122 forms a gate dielectric layer 349 that wraps each of the semiconductor layers 215, and forms a gate electrode 350 over the gate dielectric layer 349. The functional gate stack 240' includes the gate dielectric layer 349 and the gate electrode 350. The gate dielectric layer 349 may include a high-k dielectric material such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), Si3N4, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials or combinations thereof. High-k dielectric materials generally refer to dielectric materials having a high dielectric constant, for example, greater than the dielectric constant of silicon oxide (k≈3.9). The gate dielectric layer 349 can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD) and / or other suitable methods. In some embodiments, the gate stack 240' also includes an interface layer between the gate dielectric layer 349 and the channel layer 215. The interface layer may include silicon dioxide, silicon oxynitride or other suitable materials. In some embodiments, the gate electrode layer 350 includes an n-type or p-type work function layer and a metal filling layer. For example, the n-type work function layer may include a metal with a sufficiently low effective work function, such as titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or a combination thereof. For example, the p-type work function layer may include a metal with a sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or a combination thereof. For example, the metal filling layer may include aluminum, tungsten, cobalt, copper, and / or other suitable materials. The gate electrode layer 350 may be formed by CVD, PVD, electroplating, and / or other suitable processes. Since the gate stack 240' includes a high-k dielectric layer and a metal layer, it is also referred to as a high-k metal gate.

[0049] At operation 124, method 100 ( Figure 1B ) to etch the S / D contact holes 271 to expose some of the S / D components 260. Fig.13A , Fig. 13B , Fig.13D and Fig.13E The resulting structure is shown in . Fig.13A A top view of the device 200 is shown, and Fig. 13B , Fig.13D and Fig.13E Shown along Fig.13A2. A cross-sectional view of device 200 with BB line, DD line and EE line in FIG. Operation 124 may include one or more etching processes that are selectively tuned according to the materials of ILD layer 270 and CESL 269, and do not etch (or etch minimally) dielectric layers 234 and 232. In some embodiments, S / D component 260 may be partially etched. The etching process may be dry etching, wet etching, reactive ion etching, or other etching process. In addition, operation 124 controls the etching process so that dielectric layer 262 is not exposed in contact hole 271. For example, operation 124 may use a timer to control the etching depth. In some embodiments, CESL 269 and S / D component 260 form the bottom surface of contact hole 271. In some embodiments, CESL 269, ILD layer 270 and S / D component 260 form the bottom surface of contact hole 271. Air gap 263 is still sealed by dielectric layer 262 and CESL 269.

[0050] At operation 126, method 100 ( Figure 1B ) A silicide component 273 is formed over the S / D component 260, and an S / D contact (or via) 275 is formed over the silicide component 273. According to an embodiment, Figures 14A to 14E The resulting structure is shown in . Fig.14A A top view of the device 200 is shown, and Fig. 14B , Fig. 14C , Fig.14D and Fig.14E Shown along Fig.14A 2 is a cross-sectional view of the device 200 along the BB line, CC line, DD line and EE line in FIG. Since the silicide component 273 and the S / D contact 275 are formed on the front side of the device 200, they are also referred to as the front side silicide component 273 and the front side S / D contact 275, respectively.

[0051] In an embodiment, operation 126 includes depositing one or more metals into the hole 271, performing an annealing process on the device 200 to cause a reaction between the one or more metals and the S / D features 260 to produce the silicide features 273, and removing unreacted portions of the one or more metals, thereby leaving the silicide features 273 in the hole 271. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), Er (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals), and may be deposited using CVD, PVD, ALD, or other suitable methods. The silicide feature 273 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. In an embodiment, the S / D contact 275 may include a conductive barrier layer and a metal filling layer above the conductive barrier layer. The conductive barrier layer is used to prevent the metal material of the metal filling layer from diffusing into the dielectric layer adjacent to the S / D contact 275, such as layers 232, 234, 269, and 270. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or other metals, and may be formed by CVD, PVD, ALD, electroplating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the S / D contact 275. Operation 126 may perform a CMP process to remove excess material of the S / D contact 275.

[0052] At operation 128, method 100 ( Figure 1B ) Perform middle of the line (MEOL) and back end of the line (BEOL) processes on the front side of the device 200. For example, operation 128 may form a gate aperture connected to the gate stack 240', form an S / D contact via connected to the S / D contact 275, and form one or more interconnect layers in which the wires and vias are embedded in the dielectric layer. The one or more interconnect layers connect the gates, sources, and drains of the various transistors and other circuits in the device 200 to partially or completely form an integrated circuit. Operation 128 may also form a passivation layer over the interconnect layer. Fig. 15BIn the example shown, layer 277 is used to represent the various dielectric and metal layers formed above the S / D contacts 275 at the front side of the device 200, including interconnect layers and passivation layers. Fig. 15B The middle is flipped upside down.

[0053] At operation 130, method 100 ( Figure 1B ) turns the device 200 upside down and attaches the front side of the device 200 to a carrier 370, such as Fig. 15B shown. Fig.15A A top view of the device 200 is shown, and Fig. 15B , Fig. 15C , Fig.15D and Fig.15E Shown along Fig.15A 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130 FIG. 15B to FIG. 15E In FIG. 200 (and other figures described below), the “z” direction points from the back side of device 200 to the front side of device 200 , while the “−z” direction points from the back side of device 200 to the back side of device 200 .

[0054] At operation 132, method 100 ( Figure 1C ) Thinning the device 200 from the back side of the device 200 until the semiconductor layer 204 is exposed from the back side of the device 200. According to an embodiment, Fig.16A Fig.16E The resulting structure is shown in . Fig.16A A top view of the device 200 is shown, and Fig. 16B , Fig. 16C , Fig.16D and Fig.16E Shown along Fig.16A FIG. 1 is a cross-sectional view of device 200 along line BB, line CC, line DD, and line EE in FIG. In various embodiments, operation 132 may or may not expose isolation feature 230 and semiconductor layer 239. The thinning process may include a mechanical grinding process and / or a chemical thinning process. In the mechanical grinding process, a large amount of substrate material may be first removed from substrate 201. Thereafter, the chemical thinning process may apply an etching chemical to the back side of substrate 201 to further thin substrate 201.

[0055] At operation 134, method 100 ( Figure 1C) selectively etches the semiconductor layer 204 to form a trench 272 over the back side of the gate stack 240' and the drain feature 260. According to an embodiment, FIG. 17A to FIG. 17E The resulting structure is shown in . Fig.17A A top view of the device 200 is shown, and Fig. 17B , Fig. 17C , Fig.17D and Fig.17E Shown along Fig.17A . A cross-sectional view of the device 200 along the BB line, CC line, DD line, and EE line in FIG. In the present embodiment, operation 134 applies an etching process tuned to be selective to the material of the semiconductor layer 204 (in an embodiment, such as Si), and does not etch (or minimally etches) the drain component 260, the gate stack 240' (specifically the gate dielectric layer 349 and the gate interface layer (if present)), the isolation component 230, and the semiconductor layer 239 (in an embodiment, such as SiGe). The etching process can be dry etching, wet etching, reactive ion etching, or other etching methods. Specifically, in the present embodiment, the etching of the semiconductor layer 204 is self-aligned. In other words, operation 134 does not require the preparation of an etching mask (e.g., an etching mask formed by a photolithography process) to etch the semiconductor layer 204. Instead, it relies on the etching selectivity of the materials in the semiconductor layer 204 and its surrounding layers.

[0056] At operation 136, method 100 ( Figure 1C ) to form a dielectric liner 274 and one or more dielectric layers 276 to fill the trench 272. According to an embodiment, in FIG. 18A to FIG. 18E The resulting structure is shown in . Fig.18A A top view of the device 200 is shown, and Fig.18B , Fig.18C , Fig.18D and Fig.18E Shown along Fig.18A2, BB, CC, DD, and EE lines of the device 200. In an embodiment, the dielectric liner 274 includes silicon nitride, and the dielectric layer 276 includes silicon oxide. In some embodiments, the dielectric liner 274 includes other dielectric materials, such as La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Y2O3, AlON, TaCN, ZrSi, or other suitable materials. The dielectric layer 274 may have a substantially uniform thickness along various surfaces of the trench 272 and may be formed by CVD, PVD, ALD, or other suitable methods. In some embodiments, dielectric layer 276 may include an oxide formed of tetraethyl orthosilicate (TEOS), non-doped silicate glass or doped silicon oxide such as borophosphosilicate glass (BPSG), fluoride-doped silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. Dielectric layer 276 may be formed by PECVD (plasma enhanced CVD), FCVD (flowable CVD), or other suitable methods. Operation 136 may further perform a CMP process to planarize the back side of device 200 and expose semiconductor layer 239 for further processing.

[0057] At operation 138, method 100 ( Figure 1C ) removes semiconductor layer 239 from the back side of device 200. According to an embodiment, FIG. 19A to FIG. 19E The resulting structure is shown in . Fig.19A A top view of the device 200 is shown, and Fig.19B , Fig.19C , Fig.19D and Fig.19E Shown along Fig.19A200. In the embodiment, operation 138 applies an etching process tuned to be selective to the material of semiconductor layer 239 (such as SiGe in an embodiment), and no etching (or minimal etching) is performed on dielectric liner 274, dielectric layer 276, isolation component 230, and dielectric layer 262. The etching process may partially etch source component 260. The etching process produces a trench 278 that exposes source component 260 from the back side of device 200. The etching process may be dry etching, wet etching, reactive ion etching, or other etching methods. Specifically, in the embodiment, the etching of semiconductor layer 239 is self-aligned. In other words, operation 138 does not require the preparation of an etching mask (e.g., an etching mask formed by a photolithography process) to etch semiconductor layer 239. Instead, it relies on the etching selectivity of materials in semiconductor layer 239 and its surrounding layers. This advantageously forms trench 278 to align with underlying source feature 260 without misalignment, such as that introduced by photolithographic overlay shift.Using this process will result in ideal alignment of the backside source contact (or source via) with source feature 260, as described below.

[0058] At operation 140, method 100 ( Figure 1C ) The dielectric layer 262 exposed in the trench 278 is removed from the back side of the device 200. According to an embodiment, FIG. 20A to FIG. 20E The resulting structure is shown in . Fig. 20A A top view of the device 200 is shown, and Fig. 20B , Fig. 20C , Fig.20D and Fig.20E Shown along Fig. 20A 2. A cross-sectional view of device 200 is shown in FIG. 1. In the present embodiment, operation 140 applies an etching process tuned to be selective to the material of dielectric layer 262, and does not etch (or etches minimally) dielectric liner 274, dielectric layer 276, isolation component 230, dielectric layer 232, front side silicide component 273, and source component 260. In some embodiments, the etching process may partially etch source component 260 and / or silicide component 273. As a result of the etching process, trench 278 now exposes multiple surfaces of source component 260 (particularly the side of source component 260) and silicide component 273. The etching process may be dry etching, wet etching, reactive ion etching, or other etching methods. Specifically, in the present embodiment, the etching of dielectric layer 262 is self-aligned. In other words, operation 140 does not require the preparation of an etching mask (e.g., an etching mask formed by a photolithography process) to etch dielectric layer 262. Instead, it relies on the etch selectivity of the materials in dielectric layer 262 and its surrounding layers.

[0059] At operation 142, method 100 ( Figure 1C ) to form a backside source silicide feature 280 and a backside source contact 282. According to an embodiment, FIG. 21A to FIG. 21E The resulting structure is shown in . Fig.21A A top view of the device 200 is shown, and Fig. 21B , Fig. 21C , Fig.21D and Fig.21E Shown along Fig.21A BB line, CC line, DD line and EE line of the device 200. Fig.21D As shown in FIG. 1 , the silicide component 280 wraps around three surfaces of the source component 260, including the back side surface and two side wall surfaces. The back side source silicide component 280 is connected to the front side source silicide component 273. In other words, from this cross-sectional view, the source component 260 is completely wrapped by the silicide components 273 and 280. This advantageously reduces the source resistance. In the "x" direction, as shown in FIG. Fig. 21B As shown, the source feature 260 is connected to the channel layer 215. In addition, since the above reference Fig.20D As discussed in the self-aligned etching process, the backside source contact 282 is self-aligned with the source feature 260. Therefore, it is isolated from the nearby gate stack 240' by the dielectric layers 274 and 276, as shown in FIG. Fig. 21B The self-aligned backside contact 282 minimizes the risk of shorting between the source feature 260 and the nearby gate stack 240 ′.

[0060] In some embodiments, the process of forming the backside source silicide feature 280 is similar to the process of forming the frontside source silicide feature 273, and the process of forming the backside source contact 282 is similar to the process of forming the frontside source contact 275. In an embodiment, operation 142 includes depositing one or more metals into the hole 278, performing an annealing process on the device 200 to cause a reaction between the one or more metals and the source feature 260 to produce the silicide feature 280, and removing an unreacted portion of the one or more metals, thereby leaving the silicide feature 280 in the hole 278. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), Er (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals), and may be deposited using CVD, PVD, ALD, or other suitable methods. The silicide feature 280 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. In an embodiment, the source contact 282 may include a conductive barrier layer and a metal filling layer above the conductive barrier layer. The conductive barrier layer is used to prevent the metal material of the metal filling layer from diffusing into the dielectric layer adjacent to the source contact 282, such as layers 230 and 274. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals, and may be formed by CVD, PVD, ALD, electroplating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the source contact 282. Operation 142 may perform a CMP process to remove excess material of the source contact 282. As Fig. 21C and Fig.21E As shown, in operation 142 , the gate stack 240 ′ and the drain feature 260 are protected from various deposition and etching processes.

[0061] At operation 144, method 100 ( Figure 1C ) forms a backside power rail 284 and a backside interconnect 286. According to an embodiment, FIG. 22A to FIG. 22B The resulting structure is shown in . Fig.22A A top view of the device 200 is shown, and Fig. 22B Shown along Fig.22A FIG. 2 is a cross-sectional view of a portion of the device 200 along line BB in FIG. Fig. 22B As shown, the backside source contact 282 is electrically connected to the backside power rail 284. In an embodiment, the backside power rail 284 may be formed using a damascene process, a dual damascene process, a metal patterning process, or other suitable process. The backside power rail 284 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals, and may be deposited by CVD, PVD, ALD, electroplating, or other suitable processes. Although Fig. 22B Not shown, but the backside power rail 284 is embedded in one or more dielectric layers, and the backside interconnect 286 includes wires and vias embedded in one or more dielectric layers. In some embodiments, the backside power rail 284 is considered to be part of the backside interconnect 286. Having the backside power rail 284 advantageously increases the number of metal tracks in the device 200 that can be used to directly connect to the source / drain contacts and vias. It also increases the gate density compared to other structures without backside power rails, thereby achieving greater device integration 284. The size of the backside power rail 284 can be wider than the size of the first level metal (M0) rail on the front side of the device 200, which advantageously reduces the resistance of the backside power rail.

[0062] At operation 146, method 100 ( Figure 1C ) performs further manufacturing processes on the device 200. For example, it may form a passivation layer on the back side of the device 200, remove the carrier 370, and perform other BEOL processes.

[0063] In the above embodiment, the source component 260 is formed with both the front and back silicide components and the front and back contacts, while the drain component 260 is formed with the front silicide component and the front contacts and isolated from the back power rail. In an optional embodiment, the drain component 260 may be formed with both the front and back silicide components and the front and back contacts, while the source component 260 is formed with the front silicide component and the front contacts and isolated from the back power rail. This can be achieved by switching the process specifically applied to the source region with the process specifically applied to the drain region in the above embodiment. For example, the semiconductor layer 239 may be provided in the drain region instead of in the source region. In another optional embodiment, the source component 260 and the drain component 260 may be formed with both the front and back silicide components and the front and back contacts. This can be achieved by applying the process specifically applied to the source region in the above embodiment to both the source region and the drain region. For example, the semiconductor layer 239 may be provided in both the source region and the drain region.

[0064] Although not intended to be limiting, embodiments of the present invention provide one or more of the following advantages. For example, embodiments of the present invention form a silicide component that completely encapsulates the source component, which advantageously reduces the source resistance. Moreover, embodiments of the present invention use a self-aligned process to form a backside source contact, which minimizes the risk of the source component shorting to nearby conductors (including the gate stack). Embodiments of the present invention can be easily integrated into existing semiconductor manufacturing processes.

[0065] In one example aspect, the present invention relates to a semiconductor structure, the semiconductor structure comprising: a source component; a drain component; one or more channel layers connecting the source component and the drain component; a gate structure between the source component and the drain component, the gate structure being bonded to each of the one or more channel layers; a first source silicide component above the source component; a source contact above the first source silicide component; a second source silicide component below the source component; a via below the second source silicide component; and a power rail below the via, wherein the first source silicide component and the second source silicide component completely surround the source component in a cross-sectional view.

[0066] In an embodiment, the semiconductor structure further includes: a drain silicide component above the drain component; a drain contact above the drain silicide component; a first dielectric component below the drain component and extending from the drain component to the power rail; a first dielectric layer on the sidewalls of the drain component; and an air gap exposing multiple sides of the first dielectric layer.

[0067] In some embodiments of the semiconductor structure, the second source silicide component is also arranged on the sidewall of the source component and connected to the first source silicide component. In some embodiments, the semiconductor structure further includes: a first interconnect structure above the source contact. In another embodiment, the semiconductor structure further includes: a second interconnect structure under the power rail.

[0068] In an embodiment, the semiconductor structure further comprises: a first dielectric component, the first dielectric component extending from the gate structure to the power rail. In some embodiments, the through hole comprises one of Cu, Al, Co, W, Ti, Ta, Mo and Ru. In some embodiments, the power rail comprises one of Cu, Al, Co, W, Ti, Ta, Mo and Ru.

[0069] In another example aspect, the present invention relates to a semiconductor structure, comprising: a power rail on a back side of the semiconductor structure; a first interconnect structure on a front side of the semiconductor structure; a source component, a drain component, a plurality of channel layers and a gate structure between the power rail and the first interconnect structure, wherein the plurality of channel layers connect the source component with the drain component and the gate structure wraps around each of the channel layers; a first source silicide component arranged on a back side of the source component and between the source component and the power rail, wherein the first source silicide component is also arranged on a sidewall of the source component extending from the back side of the source component toward the front side of the semiconductor structure; and a first through-hole connecting the first source silicide component with the power rail.

[0070] In an embodiment, the semiconductor structure further includes: a second source silicide feature disposed on a front side of the source feature and connected to the first source silicide feature; and a source contact disposed on the second source silicide feature and connecting the second source silicide feature to the first interconnect structure.

[0071] In another embodiment, the semiconductor structure further comprises: a first dielectric component between the drain component and the power rail and isolating the drain component from the power rail. In another embodiment, the semiconductor structure further comprises: a first dielectric layer on the sidewalls of the drain component; and an air gap exposing multiple surfaces of the first dielectric layer. In another embodiment, the semiconductor structure further comprises: a drain silicide component disposed on the front side of the drain component; and a drain contact disposed on the drain silicide component.

[0072] In some embodiments, the semiconductor structure further includes: a second interconnect structure on the back side of the semiconductor structure, wherein the power rail is connected to the second interconnect structure.

[0073] In yet another example aspect, the present invention relates to a method, the method comprising: providing a structure having a substrate, a stack of first and second semiconductor layers alternately stacked layer by layer over the substrate, a sacrificial gate structure disposed over a channel region of the stack, and a gate spacer located on opposite sidewalls of the sacrificial gate structure. The method further comprises: etching the gate spacer adjacent to the stack to form a source trench and a drain trench on both sides of the sacrificial gate structure; epitaxially growing a source feature in the source trench and epitaxially growing a drain feature in the drain trench; forming a first dielectric layer on a side of the source feature, a side of the drain feature, a side of the source trench, and a side of the drain trench; and forming a contact etch stop layer (CESL) over the first dielectric layer, the source feature, and the drain feature, wherein a first air gap is sealed between the CESL and the first dielectric layer in the source trench, and a second air gap is sealed between the CESL and the first dielectric layer in the drain trench.

[0074] In an embodiment, the method further comprises replacing the sacrificial gate structure with a high-k metal gate. In another embodiment, the method further comprises: forming a first source silicide component over the source component and the CESL; forming a drain silicide component over the drain component and the CESL; forming a source contact over the first source silicide component; and forming a drain contact over the drain silicide component. In another embodiment, the method further comprises: bonding the front side of the structure to a carrier wafer, wherein the substrate is on the back side of the structure; thinning the structure from the back side of the structure until a silicon layer of the substrate is exposed, wherein the silicon layer is disposed on the back side of the high-k metal gate and over the drain component; and replacing the silicon layer with one or more dielectric components.

[0075] In some embodiments, the thinning of the structure further exposes a silicon germanium component disposed above the source component, and the method further comprises: removing the silicon germanium component to expose the back side of the source component and the first dielectric layer on the side of the source component; removing the first dielectric layer on the side of the source component to expose the side of the source component; and forming a second source silicide component on the back side of the source component and on the side of the source component. In another embodiment, the method further comprises: forming a through hole on the second source silicide component.

[0076] The foregoing summarizes the features of several embodiments so that those of ordinary skill in the art can better understand the various aspects of the present invention. Those of ordinary skill in the art will appreciate that they can easily use the present invention as a basis to design or modify other processes or structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. Those of ordinary skill in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and changes may be made thereto without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: Source components; Drain components; one or more channel layers connecting the source component and the drain component; a gate structure, between the source feature and the drain feature, the gate structure being coupled to each of the one or more channel layers; a first source silicide feature over the source feature; a source contact over the first source silicide feature; a second source silicide feature below the source feature; a through hole below the second source silicide feature; as well as a power rail below the through hole, wherein the first source silicide feature and the second source silicide feature completely surround the source feature in a cross-sectional view; a first dielectric layer on sidewalls of the drain feature; and A contact etch stop layer, disposed on the first dielectric layer; The first dielectric layer around the drain component forms a U-shaped structure to define an air gap, and the air gap is sealed by the contact etching stop layer.

2. The semiconductor structure according to claim 1, further comprising: a drain silicide feature over the drain feature; a drain contact over the drain silicide feature; A first dielectric feature is provided below the drain feature and extends from the drain feature to the power rail.

3. The semiconductor structure according to claim 1, wherein: The second source silicide feature is also disposed on a sidewall of the source feature and connected to the first source silicide feature. 4 . The semiconductor structure of claim 1 , further comprising a first interconnect structure over the source contact.

5. The semiconductor structure of claim 4, further comprising a second interconnect structure below the power rail. 6 . The semiconductor structure of claim 1 , further comprising a first dielectric feature beneath the gate structure and extending from the gate structure to the power rail.

7. The semiconductor structure according to claim 1, wherein: The through hole includes one of Cu, Al, Co, W, Ti, Ta, Mo and Ru.

8. The semiconductor structure according to claim 1, wherein: The power rail includes one of Cu, Al, Co, W, Ti, Ta, Mo and Ru.

9. A semiconductor structure comprising: a power rail on a back side of the semiconductor structure; a first interconnect structure on a front side of the semiconductor structure; a source component, a drain component, a plurality of channel layers, and a gate structure between the power rail and the first interconnect structure, wherein the plurality of channel layers connect the source component and the drain component, and the gate structure wraps around each of the channel layers; a first source silicide feature disposed on a back side of the source feature and between the source feature and the power rail, wherein the first source silicide feature is further disposed on a sidewall of the source feature extending from the back side of the source feature toward a front side of the semiconductor structure; and a first through hole connecting the first source silicide component and the power rail; a first dielectric layer on the sidewalls of the drain feature; A contact etch stop layer, disposed on the first dielectric layer; The first dielectric layer around the drain component forms a U-shaped structure to define an air gap, and the air gap is sealed by the contact etching stop layer.

10. The semiconductor structure according to claim 9, further comprising: a second source silicide feature disposed on a front side of the source feature and connected to the first source silicide feature; as well as A source contact is disposed on the second source silicide feature and connects the second source silicide feature to the first interconnect structure.

11. The semiconductor structure of claim 9, further comprising: A first dielectric component is between the drain component and the power rail and isolates the drain component from the power rail.

12. The semiconductor structure according to claim 11, The first dielectric layer has a uniform thickness ranging from 0.2 nm to 4 nm.

13. The semiconductor structure of claim 12, further comprising: a drain silicide feature disposed on a front side of the drain feature; as well as A drain contact is disposed on the drain silicide feature.

14. The semiconductor structure of claim 9, further comprising a second interconnect structure on the back side of the semiconductor structure, wherein: The power rail is connected to the second interconnect structure.

15. A method of forming a semiconductor structure, comprising: Providing a structure having a substrate, a stack of first and second semiconductor layers alternately stacked layer by layer over the substrate, a sacrificial gate structure disposed over a channel region of the stack, and gate spacers located on opposite sidewalls of the sacrificial gate structure; etching the gate spacer adjacent to the stack to form a source trench and a drain trench on both sides of the sacrificial gate structure; epitaxially growing a source feature in the source trench and epitaxially growing a drain feature in the drain trench; forming a first dielectric layer on a side surface of the source component, a side surface of the drain component, a side surface of the source trench, and a side surface of the drain trench; as well as A contact etch stop layer is formed over the first dielectric layer, the source feature, and the drain feature, wherein a first air gap is sealed between the contact etch stop layer and the first dielectric layer in the source trench, and a second air gap is sealed between the contact etch stop layer and the first dielectric layer in the drain trench.

16. The method according to claim 15, further comprising: The sacrificial gate structure is replaced with a high-k metal gate.

17. The method according to claim 16, further comprising: forming a first source silicide feature over the source feature and the contact etch stop layer; forming a drain silicide feature over the drain feature and the contact etch stop layer; forming a source contact over the first source silicide feature; as well as A drain contact is formed over the drain silicide feature.

18. The method according to claim 17, further comprising: bonding a front side of the structure to a carrier wafer, wherein the substrate is on a back side of the structure; thinning the structure from the back side of the structure until a silicon layer of the substrate is exposed, wherein the silicon layer is disposed over the back side of the high-k metal gate and the drain feature; and The silicon layer is replaced with one or more dielectric components.

19. The method according to claim 18, wherein: The thinning of the structure further exposes a silicon germanium feature disposed above the source feature, the method further comprising: removing the silicon germanium feature to expose a back side of the source feature and the first dielectric layer on the side of the source feature; removing the first dielectric layer on the side of the source feature to expose the side of the source feature; and A second source silicide feature is formed on the back side of the source feature and on the side surfaces of the source feature.

20. The method according to claim 19, further comprising: A through hole is formed on the second source silicide feature.

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