Processor access exception processing method, device, storage medium and computing device

Abstract

The present application discloses a method, device, storage medium and computing device for processing processor access exceptions, the method comprising: including in the process of processor accessing memory, when detecting that a non-aligned access instruction causes an exception, calling the exception service function corresponding to the exception, saving the exception address and the exception pointer, wherein the exception address is the address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction; controlling the control system to enter the kernel state, exit the kernel state after creating a trap task, and return to the system state; executing the trap task, converting the non-aligned access instruction for the exception address into an aligned access instruction covering the exception address, executing the aligned access instruction, so as to simulate the non-aligned access instruction to realize access to the exception address. The present application solves the technical problem of cumbersome processing of non-aligned access in the prior art.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a method, device, storage medium and computing device for processing processor access exceptions. Background Art

[0002] The Loongson processor is based on the MIPS architecture and belongs to the RISC instruction set. It has certain requirements for access addresses. For example, when accessing a half word, the memory address must be 2-byte aligned or an integer multiple thereof. When accessing a word, the memory address must be 4-byte aligned or an integer multiple thereof.

[0003] Usually programs are designed to access data in any address space, but due to the limitations of the MIPS architecture, many programs transplanted to the Loongson platform will experience execution exceptions and irregular program crashes. This is an exception error caused by non-aligned address access. The current solution can be controlled through application writing, so that storage read and write accesses are deliberately set and aligned, including the use of byte padding or pack alignment adjustments when designing data structures. However, for some peripherals with communication functions, single-byte reading and writing are inevitable, which can easily cause non-aligned access exceptions again. Even if it is avoided through programming, it will sacrifice more time and efficiency.

[0004] With respect to the technical problem of cumbersome processing of non-aligned access in the above-mentioned prior art, no effective solution has been proposed so far. Summary of the invention

[0005] The embodiments of the present application provide a method, apparatus, storage medium and computing device for processing processor access exceptions, so as to at least solve the technical problem of cumbersome processing of non-aligned access in the prior art.

[0006] According to one aspect of an embodiment of the present application, a method for handling processor access exceptions is provided, including calling an exception service function corresponding to the exception when a non-aligned access instruction is detected to cause an exception during a process of the processor accessing memory, saving an exception address and an exception pointer, wherein the exception address is the address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction; controlling the system to enter kernel state, exiting kernel state after creating a trap task, and returning to system state; executing the trap task, converting the non-aligned access instruction for the exception address into an aligned access instruction covering the exception address, and executing the aligned access instruction to simulate the non-aligned access instruction to achieve access to the exception address.

[0007] According to another aspect of an embodiment of the present application, a device for processing processor access exceptions is provided, comprising: a detection unit, for calling an exception service function corresponding to the exception when a non-aligned access instruction is detected to cause an exception during a process of the processor accessing memory, and saving an exception address and an exception pointer, wherein the exception address is the address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction; a control unit, for controlling the system to enter kernel state, exit kernel state after creating a trap task, and return to system state; an execution unit, for executing the trap task, converting the non-aligned access instruction for the exception address into an aligned access instruction covering the exception address, and executing the aligned access instruction to simulate the non-aligned access instruction to achieve access to the exception address.

[0008] Based on any of the above embodiments, the unaligned access instruction includes: a read access instruction attempting to read information from an unaligned address, and / or a write access instruction attempting to write information to an unaligned address.

[0009] Based on any of the above embodiments, executing a trap task to convert an unaligned access instruction for an exception address into an aligned access instruction covering the exception address includes: determining an alignment boundary in the exception address to determine a first part of the exception address on the left side of the alignment boundary and a second part of the exception address on the right side of the alignment boundary; according to the alignment boundary, splitting the unaligned access instruction into a first aligned access instruction to access the first part and a second aligned access instruction to access the second part.

[0010] On the basis of any of the above embodiments, when the unaligned access instruction includes: a read access instruction that attempts to read information from an unaligned address, the first aligned access instruction includes a first aligned read access instruction, and the second aligned access instruction includes a second aligned read access instruction, wherein executing the aligned access instruction to simulate the unaligned access instruction to implement access to the abnormal address includes: executing the first aligned read access instruction to obtain a first set of data from the memory; extracting data corresponding to the first part from the first set of data and storing it in a temporary result; executing the second aligned read access instruction to obtain a second set of data from the memory; extracting data corresponding to the second part from the second set of data; shifting the temporary result according to the length of the data corresponding to the second part to merge the data corresponding to the second part into the temporary result to obtain data corresponding to the abnormal address.

[0011] Based on any of the above embodiments, the exception pointer is stored in the EPC register to store the instruction address where the exception occurs and indicate the address to be returned to after the exception is handled.

[0012] Based on any of the above embodiments, the exception address is stored in the Badvaddr invalid virtual address memory, which is used to store the address that triggers the exception.

[0013] Based on any of the above embodiments, after executing the aligned access instruction to simulate the unaligned access instruction to access the abnormal address, the method further includes: restoring the context, returning to the address pointed to by the abnormal pointer to continue execution.

[0014] According to another aspect of an embodiment of the present application, a storage medium is provided, the storage medium including a stored program, wherein when the program is running, a device where the storage medium is located is controlled to execute a method of any of the above embodiments.

[0015] According to another aspect of an embodiment of the present application, a computing device is provided, including a processor, wherein the processor is used to run a program, wherein the program executes the method of any of the above embodiments when it is run.

[0016] In an embodiment of the present application, when a non-aligned access instruction is detected to cause an exception during the process of the processor accessing the memory, the exception service function corresponding to the exception is called to save the exception address and the exception pointer, wherein the exception address is the address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction; the control system enters the kernel state, creates a trap task and then exits the kernel state and returns to the system state; the trap task is executed to convert the non-aligned access instruction for the exception address into an aligned access instruction covering the exception address, and the aligned access instruction is executed to simulate the non-aligned access instruction to achieve access to the exception address, thereby solving the technical problem of cumbersome processing of non-aligned access in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 It is a hardware structure block diagram of a computer terminal (or mobile device) for implementing a method for handling processor access exceptions according to an embodiment of the present application;

[0019] Figure 2 is a flowchart of a method for processing processor access exception according to an embodiment of the present application;

[0020] Figure 3 is a memory schematic diagram according to an embodiment of the present application;

[0021] Figure 4 is a flowchart of another method for processing processor access exception according to an embodiment of the present application; and

[0022] Figure 5 It is a structural diagram of a device for processing processor access exceptions according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0025] Example 1

[0026] According to an embodiment of the present application, an embodiment of a method for processing a processor access exception is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0027] The method embodiment provided in the first embodiment of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Figure 1 The hardware structure block diagram of a computer terminal (or mobile device) for implementing a method for handling processor access exceptions is shown. Figure 1As shown, the computer terminal 10 (or mobile device 10) may include one or more (102a, 102b, ..., 102n are used to illustrate) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 104 for storing data, and a transmission device 106 for communication functions. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the I / O interface), a network interface, a power supply and / or a camera. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above electronic device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0028] It should be noted that the one or more processors 102 and / or other data fusion circuits described above may generally be referred to herein as "data fusion circuits". The data fusion circuit may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. In addition, the data fusion circuit may be a single independent processing module, or may be fully or partially integrated into any of the other components in the computer terminal 10 (or mobile device). As involved in the embodiments of the present application, the data fusion circuit acts as a processor control (e.g., selection of a variable resistor terminal path connected to an interface).

[0029] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the product activation determination method in the embodiment of the present application. The processor 102 executes various functional applications and data fusion by running the software programs and modules stored in the memory 104, that is, the above-mentioned method for handling processor access exceptions is realized. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal 10 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0030] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the computer terminal 10. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0031] The display may be, for example, a touch screen liquid crystal display (LCD) that enables a user to interact with a user interface of the computer terminal 10 (or mobile device).

[0032] Here, it should be noted that, in some optional embodiments, the above Figure 1 The computer device (or mobile device) shown may include hardware elements (including circuits), software elements (including computer code stored on a computer-readable medium), or a combination of hardware elements and software elements. It should be noted that Figure 1 This is merely one example of a particular embodiment and is intended to illustrate the types of components that may be present in the above-described computer device (or mobile device).

[0033] This application runs in the above operating environment as follows Figure 2 A method for handling processor access exception is shown. Figure 2 is a flowchart of a method for processing processor access exceptions according to an embodiment of the present application, such as Figure 2 As shown, the method for handling processor access exceptions may include:

[0034] Step S202: During the process of the processor accessing the memory, when it is detected that an unaligned access instruction causes an exception, the exception service function corresponding to the exception is called to save the exception address and exception pointer, where the exception address is the address to be accessed by the unaligned access instruction, and the exception pointer points to the unaligned access instruction.

[0035] In the above step S202, the processor is based on, for example, the MIPS architecture. On the MIPS platform, when lh reads a half word, the address of the memory must be an integer multiple of 2; when lw reads a word, the address of the memory must be an integer multiple of 4; when sd writes a double word, the address of the memory must be an integer multiple of 8. If the target address is not aligned when accessing the memory, an exception will be caused. Typically, the system prompts "bus error" and directly kills the process. In the present application, when such an exception is detected, the exception is directly intercepted and the exception service function corresponding to the exception is called. Unaligned access instructions include: read access instructions that attempt to read information from an unaligned address, and write access instructions that attempt to write information to an unaligned address. Unaligned access instructions and their corresponding exception vector numbers and exception service functions can be specified in the system in advance. When a read access instruction that attempts to read information from an unaligned address causes an exception, for example, a load instruction used to load data from the memory into a register causes an exception, it can be determined that the exception vector number corresponding to the exception is 4, and the exception service function corresponding to the exception vector number 4 can be called. For example, when a write access instruction that attempts to write information to an unaligned address causes an exception, for example, a store instruction used to store register data into memory causes an exception, it can be determined that the exception vector number corresponding to the exception is 5, and the exception service function corresponding to the exception vector number 5 can be called.

[0036] In the above step S202, the exception pointer is stored in the EPC register, which is used to store the instruction address where the exception occurs, and indicates the address to return to after the exception is handled; the exception address is stored in the Badvaddr invalid virtual address memory, which is used to store the address that caused the exception. In addition, the exception service function will also save other related field registers.

[0037] Step S204: The control system enters the kernel state, creates the trap task and then exits the kernel state and returns to the system state.

[0038] In the above step S204, the system enters the kernel state, constructs an access exception trap program environment, creates an exception trap task, exits the kernel state, and returns to the system state.

[0039] Step S206: executing a trap task, converting the non-aligned access instruction for the abnormal address into an aligned access instruction covering the abnormal address, and executing the aligned access instruction to simulate the non-aligned access instruction to implement access to the abnormal address.

[0040] In the above step S206, the system executes the simulation program in the trap task, obtains the instruction where the exception occurs by obtaining the PC register currently being executed, obtains the address corresponding to the exception by obtaining the BadVaddr value, and then the software simulates calling two unaligned load or store instructions to perform data read and write operations on the memory address. After the execution of the simulation instruction is completed, the data result is stored as the return value, and then the context is restored and returned to the address pointed to by the EPC register to continue execution.

[0041] In summary, through the above steps S202-S206, when a non-aligned access instruction is detected to cause an exception during the process of the processor accessing the memory, the exception service function corresponding to the exception is called to save the exception address and the exception pointer, wherein the exception address is the address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction; the control system enters the kernel state, creates a trap task and then exits the kernel state and returns to the system state; the trap task is executed to convert the non-aligned access instruction for the exception address into an aligned access instruction covering the exception address, and the aligned access instruction is executed to simulate the non-aligned access instruction to achieve access to the exception address, thereby solving the cumbersome technical problem of handling non-aligned access in the prior art, and there is no need to switch the kernel state, thereby ensuring the execution efficiency of the system.

[0042] This application provides a system-level solution to the exceptions and programming problems caused by non-aligned address read and write accesses of Loongson processors, ensuring that no exception errors will be generated even if non-aligned read and write accesses are performed. This application takes over the non-aligned access exceptions through the system, and the software simulates two operations of non-aligned address access instructions to complete the loading or storage of data. Compared with other methods, this application completely solves the problem of program crashes caused by non-aligned access. For the solution of using byte padding to ensure storage address alignment when designing program data structures, a lot of memory space will be wasted, resulting in an increase in costs, and developers need to spend more time thinking, so this application improves development efficiency and reduces storage space occupancy compared to the above solution. At the same time, it is more flexible than using the compiler pack to perform special processing of structure storage.

[0043] Optionally, the unaligned access instruction includes: a read access instruction attempting to read information from an unaligned address, and / or a write access instruction attempting to write information to an unaligned address.

[0044] Optionally, in step S206: executing a trap task to convert a non-aligned access instruction for an abnormal address into an aligned access instruction covering the abnormal address includes:

[0045] Step S2062: determining an alignment boundary in the abnormal address to determine a first portion of the abnormal address on the left side of the alignment boundary and a second portion of the abnormal address on the right side of the alignment boundary;

[0046] In the above step S2062, the alignment boundary is related to the word length of the access. When 4 bytes of content are accessed at a time, the alignment boundary is a 4-byte boundary. When 2 bytes of content are accessed at a time, the alignment boundary is a 2-byte boundary. Figure 3 is a memory schematic diagram according to an embodiment of the present application; combined Figure 3 As shown, when the processor attempts to access the address 0x01 in the memory to obtain a word, an exception is caused because the access instruction accesses a non-aligned address. At this time, the exception addresses include 0x01, 0x02, 0x03, and 0x04. Subsequently, it can be determined that the alignment boundary in the exception address is aligned with 0x04, and the first part of the exception address on the left side of the alignment boundary 0x01, 0x02, 0x03 and the second part of the exception address on the right side of the alignment boundary 0x04 can be further determined.

[0047] Step S2064: splitting the unaligned access instruction into a first aligned access instruction for accessing the first part and a second aligned access instruction for accessing the second part according to the alignment boundary.

[0048] In the above step S2064, combined with Figure 3 As shown, the first alignment instruction obtains 3 bytes of the left side and stores them in the temporary result R, and the second alignment instruction obtains 1 byte of the right side.

[0049] Through the above steps S2062 and S2064, an error exception will be caused when the processor is non-aligned. Here, the kernel is used to build a storage access error execution task. In this task, software simulation is used to split the non-aligned address, perform two storage operations, and then merge them to return the correct data.

[0050] Optionally, when the unaligned access instruction includes: a read access instruction that attempts to read information from an unaligned address, the first aligned access instruction includes a first aligned read access instruction, and the second aligned access instruction includes a second aligned read access instruction, wherein executing the aligned access instruction to simulate the unaligned access instruction to implement access to the abnormal address includes:

[0051] Execute a first aligned read access instruction to obtain a first set of data from the memory;

[0052] Extract the data corresponding to the first part from the first set of data and store them in a temporary result;

[0053] Execute a second aligned read access instruction to obtain a second set of data from the memory;

[0054] Extracting data corresponding to the second part from the second set of data;

[0055] The temporary result is shifted according to the length of the data corresponding to the second part to merge the data corresponding to the first part and the data corresponding to the second part to obtain the data corresponding to the abnormal address.

[0056] Combination Figure 3 As shown, loading is divided into two steps according to the current address. The first step is to add 3 to the address, that is, address = 0x01 + 3, to 0x04. In this way, the load instruction is used to obtain 3 bytes on the left side and store them in the temporary result R. In the second step, the load instruction is used to obtain 1 byte on the right side, which is recorded as T. The shift process moves the result R obtained in the first step to the left by 3 bits, R = R << 3, so that the lower 8 bits are reserved. Finally, the merging process is entered, and the shifted result and the data obtained in the second step are bitwise ORed, that is, R = R|T, and finally the word to be loaded is merged.

[0057] Optionally, the exception pointer is stored in the EPC register, which is used to store the instruction address where the exception occurs and indicate the address to return to after the exception is handled.

[0058] Optionally, the exception address is stored in a Badvaddr invalid virtual address memory for storing the address causing the exception.

[0059] Optionally, after executing the aligned access instruction to simulate the unaligned access instruction to access the exception address, the method further includes: restoring the context, returning to the address pointed to by the exception pointer to continue execution. Specifically, after the execution of the simulated instruction is completed, the data result is stored as a return value, and then the context is restored, and the address pointed to by the EPC register is returned to continue execution.

[0060] This application will build a trap program through the unaligned access exception of the Loongson processor, and then perform unaligned address correction through the simulation program to return the correct result. The specific solution is described as follows:

[0061] 1. The system specifies an exception handling function as the vector service function for exception vector numbers 4 and 5. Vector number 4 corresponds to address errors in load and ifetch, and vector number 5 corresponds to address errors in store.

[0062] 2. When the exception number 4 and vector number 5 address non-aligned access exception occurs, it will jump to the specified exception vector entry for execution. The exception handling will save the on-site register group, among which BadVaddr and EPC are saved as important parameters and will be processed later. EPC points to the instruction that caused the exception;

[0063] 3. The system enters the kernel state, builds an access exception trap program environment, creates an exception trap task, exits the kernel state, and returns to the system state;

[0064] 4. The system executes the simulation program, obtains the currently executed PC register, obtains the instruction where the exception occurs, obtains the BadVaddr value, and obtains the address corresponding to the exception. Then the software simulates calling the load or store instruction twice to read and write data to the memory address.

[0065] 5. After the execution of the simulation instruction is completed, the data result is stored as the return value, and then the context is restored and returned to the address pointed to by the EPC register to continue execution.

[0066] Figure 4 is a flowchart of another method for processing processor access exceptions according to an embodiment of the present application; Figure 4 As shown in the figure, when the non-aligned address storage read and write occurs, the non-aligned access exception set by the system will be triggered. The exception entry function will call the general exception service function to save the register context and the address where the error occurred, as well as the current EPC value. Then the storage exception task is built and executed. When entering the storage exception task, the software simulation operation will be performed through loading, shifting, and merging according to the current erroneous instruction and the non-aligned address. If an error occurs, the task will be returned, otherwise the error handling will be executed and then returned. Among them, the specific loading process can be combined with Figure 3 As shown, when the CPU tries to access address 0x01 to get a word, it will trigger an unaligned access exception due to unaligned access. The process can be referred to Figure 1 Here we only introduce the process of loading, splitting and merging. First, this program algorithm is divided into two steps according to the current address. The first step is to add 3 to the address, that is, address = 0x01 + 3, to 0x04. In this way, the load instruction is used to obtain 3 bytes on the left side and store them in the temporary result R. In the second step, the load instruction is used to obtain 1 byte on the right side, which is recorded as T. The shift process moves the result R obtained in the first step to the left by 3 bits, R = R << 3, so that the lower 8 bits are reserved. Finally, the merging process is entered, and the shifted result and the data obtained in the second step are bitwise ORed, that is, R = R|T, and finally the word to be loaded is merged.

[0067] This application is based on the fact that unaligned access to the Loongson processor will cause an error exception. Here, the kernel is used to build a storage access error execution task. In this task, software simulation is used to split the unaligned address, perform two storage operations, and then merge them to return the correct data.

[0068] This application takes over the non-aligned access exception through the system, and the software simulates two operations of non-aligned address access instructions to complete the loading or storage of data. Compared with other methods, this application completely solves the problem of program crash caused by non-aligned access. For the solution of using byte padding to ensure storage address alignment when designing program data structure, it will cause a lot of memory space waste, resulting in cost increase, and developers need to spend more time thinking, so this application improves development efficiency and reduces storage space occupancy compared to the above solution. At the same time, it is more flexible than using compiler pack to perform special processing of structure storage.

[0069] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0070] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method for handling processor access exceptions according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of each embodiment of the present application.

[0071] Example 2

[0072] According to an embodiment of the present application, a processor access exception processing device for implementing the above-mentioned processor access exception processing method is also provided, and the device is implemented in software or hardware.

[0073] Figure 5 is a structural diagram of a device for processing processor access exceptions according to an embodiment of the present application; Figure 5 As shown, the device 500 includes: a detection unit 502, a control unit 504, and an execution unit 506, wherein:

[0074] The detection unit 502 is used to call the exception service function corresponding to the exception when detecting that the non-aligned access instruction causes an exception during the process of the processor accessing the memory, and save the exception address and the exception pointer, wherein the exception address is the address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction;

[0075] A control unit 504 is used to control the system to enter the kernel state, exit the kernel state after creating the trap task, and return to the system state;

[0076] The execution unit 506 is used to execute the trap task, convert the non-aligned access instruction for the abnormal address into the aligned access instruction covering the abnormal address, and execute the aligned access instruction to simulate the non-aligned access instruction to realize the access to the abnormal address.

[0077] It should be noted here that the above-mentioned detection unit 502, control unit 504, and execution unit 506 correspond to steps S202 to S206 in Example 1, and the examples and application scenarios implemented by the above-mentioned three modules are the same as those of the corresponding steps, but are not limited to the contents disclosed in the above-mentioned Example 1.

[0078] In summary, through the above-mentioned detection unit 502, control unit 504, and execution unit 506, when a non-aligned access instruction is detected to cause an exception during the process of the processor accessing the memory, the exception service function corresponding to the exception is called to save the exception address and the exception pointer, wherein the exception address is the address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction; the control system enters the kernel state, creates a trap task and then exits the kernel state and returns to the system state; executes the trap task, converts the non-aligned access instruction for the exception address into an aligned access instruction covering the exception address, and executes the aligned access instruction to simulate the non-aligned access instruction to achieve access to the exception address, thereby solving the technical problem of cumbersome processing of non-aligned access in the prior art.

[0079] This application provides a system-level solution to the exceptions and programming problems caused by non-aligned address read and write accesses of Loongson processors, ensuring that no exception errors will be generated even if non-aligned read and write accesses are performed. This application takes over the non-aligned access exceptions through the system, and the software simulates two operations of non-aligned address access instructions to complete the loading or storage of data. Compared with other methods, this application completely solves the problem of program crashes caused by non-aligned access. For the solution of using byte padding to ensure storage address alignment when designing program data structures, a lot of memory space will be wasted, resulting in an increase in costs, and developers need to spend more time thinking, so this application improves development efficiency and reduces storage space occupancy compared to the above solution. At the same time, it is more flexible than using the compiler pack to perform special processing of structure storage.

[0080] Optionally, the unaligned access instruction includes: a read access instruction attempting to read information from an unaligned address, and / or a write access instruction attempting to write information to an unaligned address.

[0081] Optionally, the execution unit 506 is also configured to: determine an alignment boundary in the exception address to determine a first part of the exception address on the left side of the alignment boundary, and a second part of the exception address on the right side of the alignment boundary; and according to the alignment boundary, split the unaligned access instruction into a first aligned access instruction for accessing the first part and a second aligned access instruction for accessing the second part.

[0082] Optionally, when the unaligned access instruction includes: a read access instruction that attempts to read information from an unaligned address, the first aligned access instruction includes a first aligned read access instruction, and the second aligned access instruction includes a second aligned read access instruction, wherein the execution unit 506 is further configured to: execute the first aligned read access instruction to obtain a first set of data from the memory; extract data corresponding to the first part from the first set of data and store it in a temporary result; execute the second aligned read access instruction to obtain a second set of data from the memory; extract data corresponding to the second part from the second set of data; and shift the temporary result according to the length of the data corresponding to the second part to merge the data corresponding to the first part and the data corresponding to the second part to obtain data corresponding to the abnormal address.

[0083] Optionally, the exception pointer is stored in the EPC register, which is used to store the instruction address where the exception occurs and indicate the address to return to after the exception is handled.

[0084] Optionally, the exception address is stored in a Badvaddr invalid virtual address memory for storing the address causing the exception.

[0085] Optionally, the device further includes: a recovery unit, which is used to restore the context after executing the aligned access instruction to simulate the unaligned access instruction to access the abnormal address, and return to the address pointed to by the abnormal pointer to continue execution. Specifically, after the execution of the simulated instruction is completed, the data result is stored as a return value, and then the context is restored and returned to the address pointed to by the EPC register to continue execution.

[0086] Example 3

[0087] The embodiment of the present application may provide a computing device, which may be any computer terminal device in a computer terminal group. Optionally, in this embodiment, the computing device may also be replaced by a terminal device such as a mobile terminal.

[0088] Optionally, in this embodiment, the computing device may be located in at least one network device among a plurality of network devices of a computer network.

[0089] Optionally, in this embodiment, the computing device includes one or more processors, a memory, and a transmission device. The memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the method and device for handling processor access exceptions in the embodiment of the present application. The processor executes various functional applications and data fusion by running the software programs and modules stored in the memory, that is, implementing the method for handling processor access exceptions.

[0090] Optionally, the memory may include a high-speed random access memory and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory may further include a memory remotely arranged relative to the processor, and these remote memories may be connected to the computing device 120 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0091] In this embodiment, the processor in the above-mentioned computing device can execute the following method steps when running the stored program code: during the process of the processor accessing the memory, when it is detected that an unaligned access instruction causes an exception, the exception service function corresponding to the exception is called, and the exception address and the exception pointer are saved, wherein the exception address is the address to be accessed by the unaligned access instruction, and the exception pointer points to the unaligned access instruction; the control system enters the kernel state, creates a trap task and then exits the kernel state and returns to the system state; executes the trap task, converts the unaligned access instruction for the exception address into an aligned access instruction covering the exception address, and executes the aligned access instruction to simulate the unaligned access instruction to achieve access to the exception address.

[0092] Furthermore, in this embodiment, when the processor in the computing device runs the stored program code, any method step listed in Embodiment 1 may be executed, which will not be described in detail due to space limitations.

[0093] Example 3

[0094] The embodiment of the present application further provides a storage medium. Optionally, in this embodiment, the storage medium can be used to store the program code executed by the method for handling processor access exception.

[0095] Optionally, in this embodiment, the above storage medium may be located in any computer terminal in a computer terminal group in a computer network, or in any mobile terminal in a mobile terminal group.

[0096] Optionally, in this embodiment, the storage medium is configured to store program codes for executing the following steps: during the process of the processor accessing the memory, when it is detected that an unaligned access instruction causes an exception, the exception service function corresponding to the exception is called, and the exception address and the exception pointer are saved, wherein the exception address is the address to be accessed by the unaligned access instruction, and the exception pointer points to the unaligned access instruction; the control system enters the kernel state, creates a trap task and then exits the kernel state, and returns to the system state; executes the trap task, converts the unaligned access instruction for the exception address into an aligned access instruction covering the exception address, and executes the aligned access instruction to simulate the unaligned access instruction to achieve access to the exception address.

[0097] Furthermore, in this embodiment, the storage medium is configured to store program codes for executing any one of the method steps listed in Embodiment 1, which will not be described in detail due to space limitations.

[0098] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0099] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0100] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0101] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0102] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0103] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk, etc. Various media that can store program codes.

[0104] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A method for handling processor access exceptions, characterized in that: include: When a non-aligned access instruction is detected to cause an exception during a process of the processor accessing the memory, an exception service function corresponding to the exception is called to save an exception address and an exception pointer, wherein the exception address is an address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction; The control system enters the kernel state, creates a trap task, exits the kernel state, and returns to the system state; Executing the trap task, converting the non-aligned access instruction for the abnormal address into an aligned access instruction covering the abnormal address, executing the aligned access instruction to simulate the non-aligned access instruction to access the abnormal address, Wherein, the unaligned access instruction includes: a read access instruction attempting to read information from an unaligned address, and / or a write access instruction attempting to write information to an unaligned address; The step of executing the trap task to convert the unaligned access instruction for the abnormal address into the aligned access instruction covering the abnormal address includes: determining an alignment boundary in the exception address to determine a first portion of the exception address to the left of the alignment boundary and a second portion of the exception address to the right of the alignment boundary; According to the alignment boundary, splitting the unaligned access instruction into a first aligned access instruction for accessing the first portion and a second aligned access instruction for accessing the second portion; Wherein, when the unaligned access instruction includes: a read access instruction that attempts to read information from an unaligned address, the first aligned access instruction includes a first aligned read access instruction, and the second aligned access instruction includes a second aligned read access instruction, wherein executing the aligned access instruction to simulate the unaligned access instruction to implement access to the abnormal address includes: Executing the first aligned read access instruction to obtain a first set of data from the memory; Extracting data corresponding to the first part from the first set of data, and storing the data in a temporary result; Executing the second aligned read access instruction to obtain a second set of data from the memory; Extracting data corresponding to the second part from the second set of data; The temporary result is shifted according to the length of the data corresponding to the second part to merge the data corresponding to the second part into the temporary result to obtain data corresponding to the abnormal address, wherein the merging includes performing a bitwise OR operation on the shifted result and the data obtained in the second step to merge the word to be loaded.

2. The processing method according to claim 1, characterized in that: The exception pointer is stored in the EPC register, which is used to store the instruction address where the exception occurs and indicate the address to return to after the exception is handled.

3. The processing method according to claim 1, characterized in that: The exception address is stored in a Badvaddr invalid virtual address memory for storing the address causing the exception.

4. The processing method according to claim 1, characterized in that: After executing the aligned access instruction to simulate the unaligned access instruction to implement access to the abnormal address, the method further includes: Restore the context and return to the address pointed to by the exception pointer to continue execution.

5. A device for processing processor access exceptions, characterized in that: include: A detection unit, configured to, when a non-aligned access instruction is detected to cause an exception during a process of a processor accessing a memory, call an exception service function corresponding to the exception, save an exception address and an exception pointer, wherein the exception address is an address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction; A control unit is used to control the system to enter the kernel state, exit the kernel state after creating a trap task, and return to the system state; an execution unit, configured to execute the trap task, convert the non-aligned access instruction for the abnormal address into an aligned access instruction covering the abnormal address, and execute the aligned access instruction to simulate the non-aligned access instruction to implement access to the abnormal address, Wherein, the unaligned access instruction includes: a read access instruction attempting to read information from an unaligned address, and / or a write access instruction attempting to write information to an unaligned address; Wherein, the execution unit is also used for: determining an alignment boundary in the exception address to determine a first portion of the exception address to the left of the alignment boundary and a second portion of the exception address to the right of the alignment boundary; According to the alignment boundary, splitting the unaligned access instruction into a first aligned access instruction for accessing the first portion and a second aligned access instruction for accessing the second portion; Wherein, when the unaligned access instruction includes: a read access instruction attempting to read information from an unaligned address, the first aligned access instruction includes a first aligned read access instruction, and the second aligned access instruction includes a second aligned read access instruction; the execution unit is further used to: Executing the first aligned read access instruction to obtain a first set of data from the memory; Extracting data corresponding to the first part from the first set of data, and storing the data in a temporary result; Executing the second aligned read access instruction to obtain a second set of data from the memory; Extracting data corresponding to the second part from the second set of data; The temporary result is shifted according to the length of the data corresponding to the second part to merge the data corresponding to the second part into the temporary result to obtain data corresponding to the abnormal address, wherein the merging includes performing a bitwise OR operation on the shifted result and the data obtained in the second step to merge the word to be loaded.

6. A storage medium, characterized in that: The storage medium includes a stored program, wherein when the program is running, the device where the storage medium is located is controlled to execute the method according to any one of claims 1 to 4.

7. A computing device comprising a processor, characterized in that: The processor is used to run a program, wherein the program executes the method according to any one of claims 1 to 4 when running.

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