Transistor and method of forming oxide semiconductor transistor

Abstract

A transistor including a channel layer and a method for manufacturing the same, wherein the channel layer includes an oxide semiconductor material. The transistor includes a channel layer including a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration, and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first oxide semiconductor layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first and third oxygen concentrations. Embodiments of the present invention also relate to a method for forming an oxide semiconductor transistor.

Description

Technical Field

[0001] Embodiments of the present invention relate to transistors and methods of forming oxide semiconductor transistors. Background Art

[0002] In the semiconductor industry, there is a constant desire to increase the areal density of integrated circuits. To this end, individual transistors are becoming smaller and smaller. To increase device density, smaller transistors, such as thin film transistors (TFTs), are becoming increasingly attractive. Summary of the Invention

[0003] An embodiment of the present invention provides a transistor, comprising: a gate electrode; a dielectric layer; a source electrode and a drain electrode; and a channel layer, having an upper surface, a lower surface, and a middle portion located between the upper surface and the lower surface, wherein the source electrode and the drain electrode are electrically contacted with the upper surface of the channel layer, and the channel layer has a first carrier concentration near the upper surface of the channel layer and a second carrier concentration in the middle portion of the channel layer, and the first carrier concentration is less than the second carrier concentration.

[0004] Another embodiment of the present invention provides a method for forming an oxide semiconductor transistor, comprising: depositing a gate electrode; depositing a dielectric layer; depositing a channel layer, including: depositing an In x Ga y Zn z A first oxide semiconductor layer of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, and 0<(x, y, z)<1; and a deposition layer comprising In x Ga y Zn z A second oxide semiconductor layer of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, wherein the composition of the second oxide semiconductor layer is different from the composition of the first oxide semiconductor layer; depositing an In x Ga y Zn z A third oxide semiconductor layer of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn and combinations thereof, wherein a composition of the third oxide semiconductor layer is different from a composition of the second oxide semiconductor layer; wherein a second oxygen concentration of the second oxide semiconductor layer is lower than a first oxygen concentration of the first oxide semiconductor layer; and a source electrode and a drain electrode forming contact with the channel layer.

[0005] Another embodiment of the present invention provides a method for forming an oxide semiconductor transistor, comprising: depositing a gate electrode; depositing a dielectric layer; depositing a channel layer, comprising: depositing a first oxide semiconductor layer having a first oxygen concentration using a physical vapor deposition process in an environment having a first flow ratio of O2 / (Ar+O2); depositing a second oxide semiconductor layer having a second oxygen concentration using a physical vapor deposition process in an environment having a second flow ratio of O2 / (Ar+O2); depositing a third oxide semiconductor layer having a third oxygen concentration using a physical vapor deposition process in an environment having a third flow ratio of O2 / (Ar+O2), wherein the second flow ratio of O2 / (Ar+O2) is lower than the first flow ratio and the third flow ratio of O2 / (Ar+O2), and wherein the second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration; and forming a source electrode and a drain electrode in contact with the channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a vertical cross-sectional view of an exemplary structure after forming a complementary metal oxide semiconductor (CMOS) transistor, a metal interconnect structure embedded in a dielectric material layer, and a connecting via level dielectric material layer in accordance with an embodiment of the present invention.

[0008] Figure 1B is a vertical cross-sectional view of a first exemplary structure during formation of an array of fin-type back-gate field effect transistors according to an embodiment of the present invention.

[0009] Figure 1C is a vertical cross-sectional view of the first exemplary structure after forming an upper level metal interconnect structure in accordance with an embodiment of the present invention.

[0010] Figure 2A is a plan view of an intermediate structure of a transistor after depositing a stack of alternating conductive and dielectric layers over a substrate in accordance with various embodiments of the present invention.

[0011] Figure 2B According to various embodiments of the present invention Figure 2A A vertical cross-sectional view taken along line AA'.

[0012] Figure 2C According to various embodiments of the present invention Figure 2A and Figure 2B A perspective view of the intermediate structure shown.

[0013] Figure 3 A photoresist layer is formed thereon according to various embodiments of the present invention. Figure 2C A three-dimensional diagram of the intermediate structure.

[0014] Figure 4 is a photoresist layer having a pattern according to various embodiments of the present invention Figure 3 A perspective view of an intermediate structure with a patterned photoresist layer exposing a portion of a top conductive layer of a stack of alternating conductive and dielectric layers.

[0015] Figure 5 is a first conductive layer and a first dielectric layer of a stack of alternating conductive layers and dielectric layers patterned using a photoresist layer as a mask according to various embodiments of the present invention. Figure 4 A three-dimensional diagram of the intermediate structure.

[0016] Figure 6 is a photoresist layer having a pattern according to various embodiments of the present invention Figure 5 A perspective view of an intermediate structure wherein the patterned photoresist layer exposes a second portion of the top conductive layer of the stack of alternating conductive and dielectric layers.

[0017] Figure 7 is a perspective view of an intermediate structure after several patterning and etching steps to form a stepped structure in portions of a stack of alternating conductive and dielectric layers in accordance with various embodiments of the present invention.

[0018] Figure 8 is a device having an intermetal dielectric layer (IMD) deposited over an intermediate structure according to various embodiments of the present invention. Figure 7 A three-dimensional diagram of the intermediate structure.

[0019] Figure 9 is after the planarization process according to various embodiments of the present invention Figure 8 A perspective view of an intermediate structure, wherein the planarization process exposes a top surface of a top conductive layer of a stack of alternating conductive and dielectric layers.

[0020] Figure 10A After depositing the hard mask layer and the photoresist layer according to various embodiments of the present invention Figure 9 A three-dimensional diagram of the intermediate structure.

[0021] Figure 10B is a through-hole with a hard mask layer and a photoresist layer added according to various embodiments of the present invention Figure 10A A vertical cross-section of the intermediate structure is shown in plane AA'.

[0022] Figure 11After patterning the hard mask layer and removing the photoresist layer according to various embodiments of the present invention Figure 10B A vertical cross-section of the intermediate structure.

[0023] Figure 12 After etching the stack of alternating conductive and dielectric layers using a patterned hard mask according to various embodiments of the present invention Figure 11 A vertical cross-section of the intermediate structure.

[0024] Figure 13 According to various embodiments of the present invention Figure 12 After conformally depositing a dielectric layer over the surface of the intermediate structure shown Figure 12 A vertical cross-section of the intermediate structure.

[0025] Figure 14 According to various embodiments of the present invention Figure 13 After conformal deposition of a channel layer over the intermediate structure shown Figure 13 A vertical cross-section of the intermediate structure.

[0026] Figure 15 After conformally depositing a dielectric layer over the channel layer according to various embodiments of the present invention Figure 14 A vertical cross-section of the intermediate structure.

[0027] Figure 16 After deep trench etching to separate the channel layer according to an embodiment of the present invention Figure 15 A vertical cross-section of the intermediate structure is shown.

[0028] Figure 17 is after filling the trench with dielectric material according to various embodiments of the present invention Figure 16 A vertical cross-section of the intermediate structure is shown.

[0029] Figure 18A is after performing the planarization step according to various embodiments of the present invention Figure 17 A vertical cross-section of the intermediate structure is shown.

[0030] Figure 18B According to various embodiments of the present invention Figure 18A A plan view of the intermediate structure is shown.

[0031] Figure 19 After forming the isolation trench according to an embodiment of the present invention Figure 18B A plan view of the intermediate structure is shown.

[0032] Figure 20 After forming the isolation structure in the isolation trench according to various embodiments of the present invention Figure 19A plan view of the intermediate structure is shown.

[0033] Figure 21 FIG. 1 is a diagram illustrating the formation of source line / bit line trenches according to various embodiments of the present invention. Figure 20 Floor plan.

[0034] Figure 22 FIG. 1 is a diagram showing a transistor device after forming a source line and a bit line in a source line / bit line trench according to various embodiments of the present invention. Figure 21 Floor plan.

[0035] Figure 23A According to various embodiments of the present invention Figure 22 A perspective view of the transistor device shown.

[0036] Figure 23B It passes through Figure 23A Vertical cross-sectional view of plane AA'.

[0037] Figure 23C It passes through Figure 23A A vertical cross-sectional view of line BB'.

[0038] Figure 24A is a plan view of a transistor device according to an alternative embodiment of the present invention.

[0039] Figure 24B According to an optional embodiment of the present invention, Figure 24A A vertical cross-sectional view taken along line AA'.

[0040] Figure 25A is a vertical cross-sectional view of an alternative configuration of an illustrative intermediate structure for forming a transistor device including a first channel layer formed over a dielectric layer in accordance with an embodiment of the present invention.

[0041] Figure 25B is a vertical cross-sectional view of an alternative configuration of an exemplary intermediate structure including a second channel layer conformally deposited over a first channel layer in accordance with an embodiment of the present invention.

[0042] Figure 25C is a graph showing carrier concentration across the thickness of a channel layer according to an embodiment of the present invention.

[0043] Figure 26 is a vertical cross-sectional view of another exemplary structure of a transistor device according to an embodiment of the present invention.

[0044] Figure 27 is a flowchart illustrating an embodiment method of forming an embodiment oxide semiconductor transistor.

[0045] Figure 28is a flow chart illustrating an alternative embodiment method of forming an embodiment oxide semiconductor transistor.

[0046] Figure 29 is a flow chart illustrating another alternative embodiment of forming an embodiment transistor device. DETAILED DESCRIPTION

[0047] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate a relationship between the individual embodiments and / or configurations discussed.

[0048] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or during operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless expressly stated otherwise, each element having the same reference numeral is assumed to be of the same material composition and to have a thickness within the same thickness range.

[0049] The present invention is directed to semiconductor devices, and in particular, embodiments of the present invention relate to field-effect transistors having an oxide semiconductor channel layer. Specifically, embodiments relate to field-effect transistors having a multilayer oxide semiconductor channel layer. In various embodiments, the multilayer oxide semiconductor channel layer includes a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration, and a third oxide semiconductor layer having a third oxygen concentration. In various embodiments, the second oxide semiconductor layer is located between the first oxide semiconductor layer and the third oxide semiconductor layer, and the second oxygen concentration is lower than the first oxygen concentration or the third oxygen concentration. In various embodiments, the first oxygen concentration and the third oxygen concentration may be the same.

[0050] It is known that oxide semiconductors (OS) have high carrier concentration tunability under the control of an electric field. In addition, oxide semiconductor materials can have high mobility for high-speed driving and can utilize low current for low power consumption under the control of an electric field. In view of this characteristic, metal oxide semiconductor (OS) materials can be applied to transistor devices and can be used as channel materials in transistor devices. For example, a thin film transistor (TFT) can be an example of a transistor device using an OS material such as indium gallium zinc oxide (IGZO). Such a transistor can provide a higher refresh rate and lower power consumption. However, due to the formation of physical defects in the oxide semiconductor channel layer and / or the adjacent oxide layer, carrier traps are generated at the interface between the oxide semiconductor channel layer and the adjacent oxide dielectric layer. The carrier traps formed at the interface between the oxide semiconductor channel layer and the adjacent oxide dielectric layer deteriorate the subthreshold swing (SS) and large hysteresis characteristics of the formed transistor device. Due to charge capture, the resistance and threshold voltage (the voltage required for the transistor to turn on) may increase, and the drain current in the transistor decreases. The increase in resistance and threshold voltage reduces the performance of the transistor over time until the threshold eventually collapses. Therefore, it would be advantageous to have an oxide semiconductor transistor with fewer carrier traps at the interface between an oxide semiconductor channel layer and an adjacent oxide dielectric layer.

[0051] Therefore, the various embodiments disclosed herein provide a multilayer channel layer with different oxygen levels, which reduces interface carrier traps by suppressing the interaction between the oxide semiconductor channel layer and the adjacent dielectric oxide layer. Since the interaction between the OS structure and the adjacent oxide layer is suppressed, the multilayer channel structure can have fewer carrier traps. In addition, due to the gate swing bias, the multilayer channel layer can enhance the low hysteresis characteristics of the device as a small signal RF characteristic. By changing the amount of oxygen in each layer, the carrier concentration can be similarly changed. By reducing the oxygen concentration in the layer of the multilayer channel structure, the carrier concentration can be increased. Carrier concentration control may be an important factor that contributes to the mobility and drive speed of oxide semiconductor devices. However, as the device size decreases and the overall size decreases, the channel length decreases, and the short channel effect may become more obvious. The changing oxygen concentration of the embodiment multilayer channel device can be detected and confirmed by secondary ion mass spectrometry (SIMS).

[0052] Further embodiments include an oxide semiconductor channel having a carrier concentration that increases according to a gradient distribution, the carrier concentration increasing as a function of increasing depth from the surface of the channel. Control of the carrier concentration of the oxide semiconductor channel is an important factor in the mobility and drive speed of the transistor device. However, as the channel length continues to decrease, the short channel effect becomes more pronounced. Existing oxide semiconductor transistor devices cannot fully utilize the increase in high carrier concentration to achieve ultrafast drive speeds because the generation of oxygen vacancies may result in high carrier concentrations (e.g., more than 10 18 cm -3 ), oxygen vacancies lead to the creation of an undesirable conductive path over the short channel length between the source and drain electrodes. One or more materials of the oxide semiconductor material (such as indium) can also segregate to the surface of the channel layer, which may contribute to the excessive generation of oxygen vacancies near the channel surface. This may have a negative impact on the reliability of the device. However, at lower carrier concentrations (e.g., less than 10 13 cm -3 ), there is a large positive threshold voltage shift and lower on-current, which may also have a negative impact on the performance of the transistor device.

[0053] Thus, various embodiments disclosed herein provide a channel layer having a carrier concentration that increases according to a gradient distribution as a function of increasing depth from the surface of the channel layer. In embodiments, the surface of the channel layer may be in electrical contact with corresponding source and drain electrodes (e.g., source and bit lines) of a transistor device. In various embodiments, the carrier concentration in the entire channel layer may be in the range of 1×10 11 cm -3 and 1×10 21 cm -3. In various embodiments, the channel layer may have an oxygen vacancy concentration that increases according to a gradient profile, with the carrier concentration increasing as a function of depth from the surface of the channel layer. By providing a channel layer for a transistor device with a carrier concentration that increases according to a gradient profile, with the carrier concentration increasing as a function of depth from the surface of the channel layer, the transistor device can have a small positive threshold voltage shift and a high on-current, while enabling ultra-fast driving while avoiding the formation of undesirable conductive paths through the channel due to short channel effects. In some applications, transistors can be fabricated in the back-end (BEOL) location. Fabricating transistors in the BEOL location allows functionality to be added there while freeing up valuable chip area in the front-end (FEOL) area. Furthermore, transistors using metal oxide semiconductors may be an attractive option for BEOL integration because such transistors can be processed at low temperatures, thus avoiding damage to previously fabricated devices. While fabricating transistors in the BEOL protects them from various harsh conditions, they may still be exposed to gases in the surrounding environment during the formation of other BEOL devices. For example, BEOL transistors may be exposed to plasma and air in the surrounding environment.

[0054] Figure 1A is a vertical cross-sectional view of an exemplary lower level device structure 100 after forming a complementary metal oxide semiconductor (CMOS) transistor and a metal interconnect structure formed in a dielectric layer according to an embodiment of the present invention. Figure 1A , a first exemplary structure according to an embodiment of the present invention is shown prior to forming an array of memory structures according to various embodiments of the present invention. The first exemplary lower level device structure 100 includes a substrate 8 including a semiconductor material layer 10. The substrate 8 may include a bulk semiconductor substrate, such as a silicon substrate, wherein the semiconductor material layer extends continuously from the top surface of the substrate 8 to the bottom surface of the substrate 8; or a semiconductor-on-insulator layer, including the semiconductor material layer 10 as the top semiconductor layer above a buried insulator layer (such as a silicon oxide layer). The exemplary structure may include various device regions, which may include a memory array region 50, in which at least one array of non-volatile memory cells may be subsequently formed.

[0055] For example, at least one array of nonvolatile memory cells may include a three-dimensional (3D) memory structure as described in more detail below. At least one array of nonvolatile memory cells may include resistive random access memory (RRAM or ReRAM), magnetic / magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and phase change memory (PCM) devices. The exemplary structure may also include a peripheral logic region 52, where electrical connections may be subsequently formed between each array of nonvolatile memory cells and peripheral circuitry including field effect transistors. Areas of the memory array region 50 and the logic region 52 may be used to form various elements of the peripheral circuitry.

[0056] Semiconductor devices such as field effect transistors (FETs) can be formed on and / or in the semiconductor material layer 10 during FEOL operations. For example, a shallow trench isolation structure 12 can be formed in the upper portion of the semiconductor material layer 10 by forming a shallow trench and then filling the shallow trench with a dielectric material such as silicon oxide. Other suitable dielectric materials are within the contemplation of the present invention. Various doped wells (not explicitly shown) can be formed in various regions of the upper portion of the semiconductor material layer 10 by performing a masked ion implantation process.

[0057] A gate structure 20 may be formed above the top surface of the substrate 8 by depositing and patterning a gate dielectric layer, a gate electrode layer, and a gate cap dielectric layer. Each gate structure 20 may include a vertical stack of a gate dielectric 22, a gate electrode 24, and a gate cap dielectric 28, referred to herein as a gate stack (22, 24, 28). An ion implantation process may be performed to form an extension implant region, which may include a source extension region and a drain extension region. A dielectric gate spacer 26 may be formed around the gate stack (22, 24, 28). Each component of the gate stack (22, 24, 28) and the dielectric gate spacer 26 constitutes the gate structure 20. An additional ion implantation process may be performed, which uses the gate structure 20 as a self-aligned implant mask to form a deep active region. Such a deep active region may include a deep source region and a deep drain region. The upper portion of the deep active region may overlap with a portion of the extension implant region. Each combination of an extended implant region and a deep active region can constitute an active region 14, which can be a source region or a drain region depending on the electrical bias. A semiconductor channel 15 can be formed under each gate stack (22, 24, 28) between an adjacent pair of active regions 14. A metal-semiconductor alloy region 18 can be formed on the top surface of each active region 14. Field effect transistors can be formed on the semiconductor material layer 10. Each field effect transistor can include a gate structure 20, a semiconductor channel 15, a pair of active regions 14 (one of which serves as a source region and the other as a drain region), and an optional metal-semiconductor alloy region 18. Complementary metal oxide semiconductor (CMOS) circuitry 75 can be provided on the semiconductor material layer 10. The CMOS circuitry 75 can include peripheral circuitry for an array of transistors such as subsequently formed thin film transistors.

[0058] Various interconnect hierarchical structures may then be formed, which are formed before forming an array of field effect transistors and are referred to herein as lower interconnect hierarchical structures (L0, L1, L2). In the case where a two-dimensional array of transistors is subsequently formed above two layers of interconnect hierarchical metal lines, the lower interconnect hierarchical structures (L0, L1, L2) may include a contact hierarchical structure L0, a first interconnect hierarchical structure L1, and a second interconnect hierarchical structure L2. The contact hierarchical structure L0 may include a planarization dielectric layer 31A and various contact via structures 41V, the planarization dielectric layer 31A including a planarization dielectric material such as silicon oxide, the contact via structures 41V contacting a corresponding one of the active region 14 or the gate electrode 24 and formed within the planarization dielectric layer 31A. The first interconnect hierarchical structure L1 includes a first interconnect hierarchical dielectric layer 31B and a first metal line 41L formed within the first interconnect hierarchical dielectric layer 31B. The first interconnect hierarchical dielectric layer 31B is also referred to as a first line-level dielectric layer. First metal line 41L may contact a corresponding one of contact via structures 41V. Second interconnection level structure L2 includes a second interconnection level dielectric layer 32, which may include a first via level dielectric material layer and a second line level dielectric material layer, or a stack of line and via level dielectric material layers. Second interconnection level dielectric layer 32 may have formed therein a second interconnection level metal interconnect structure (42V, 42L), which includes first metal via structure 42V and second metal line 42L. The top surface of second metal line 42L may be coplanar with the top surface of second interconnection level dielectric layer 32.

[0059] refer to Figure 1B , an array 95 of nonvolatile memory cells and selector devices can be formed in the memory array region 50 above the second interconnect hierarchy L2. Details of the structure and processing steps of the array 95 of nonvolatile memory cells and selector devices are described in detail later below. A third interconnect hierarchy dielectric layer 33 can be formed during the formation of the array 95 of nonvolatile memory cells and selector devices. The collection of all structures formed at the level of the array 95 of nonvolatile memory cells and selector devices is referred to herein as the third interconnect hierarchy L3.

[0060] refer to Figure 1C, a third interconnection level metal interconnect structure (43V, 43L) may be formed in the third interconnection level dielectric layer 33. The third interconnection level metal interconnect structure (43V, 43L) may include a second metal through-hole structure 43V and a third metal line 43L. Additional interconnection level structures may then be formed, which are referred to herein as upper interconnection level structures (L4, L5, L6, L7). For example, the upper interconnection level structures (L4, L5, L6, L7) may include a fourth interconnection level structure L4, a fifth interconnection level structure L5, a sixth interconnection level structure L6, and a seventh interconnection level structure L7. The fourth interconnection level structure L4 may include a fourth interconnection level dielectric layer 34 having a fourth interconnection level metal interconnect structure (44V, 44L) formed therein, which may include a third metal through-hole structure 44V and a fourth metal line 44L. The fifth interconnection-level structure L5 may include a fifth interconnection-level dielectric layer 35 having a fifth interconnection-level metal interconnect structure (45V, 45L) formed therein. The fifth interconnection-level metal interconnect structure may include a fourth metal via structure 45V and a fifth metal line 45L. The sixth interconnection-level structure L6 may include a sixth interconnection-level dielectric layer 36 having a sixth interconnection-level metal interconnect structure (46V, 46L) formed therein. The sixth interconnection-level metal interconnect structure may include a fifth metal via structure 46V and a sixth metal line 46L. The seventh interconnection-level structure L7 may include a seventh interconnection-level dielectric layer 37 having a sixth metal via structure 47V (being a seventh interconnection-level metal interconnect structure) and a metal bonding pad 47B formed therein. Metal bond pad 47B may be configured for solder bonding (which may employ C4 ball bonding or wire bonding), or may be configured for metal-to-metal bonding (such as copper-to-copper bonding).

[0061] Each interconnect level dielectric layer may be referred to as an interconnect level dielectric (ILD) layer 30. Each interconnect level metal interconnect structure may be referred to as a metal interconnect structure 40. Each continuous combination of a metal via structure and a metal line thereon within the same interconnect level structure (L2-L7) may be sequentially formed as two discrete structures using two single damascene processes, or may be simultaneously formed as a single structure using a dual damascene process. Each metal interconnect structure 40 may include a corresponding metal liner (such as a layer of TiN, TaN, or WN having a thickness in the range of 2 nm to 20 nm) and a corresponding metal fill material (such as W, Cu, Co, Mo, Ru, other elemental metals, or alloys thereof, or combinations thereof). Other suitable materials for use as metal liner and metal fill materials are within the contemplated scope of the present invention. Various etch stop dielectric layers and dielectric cap layers may be inserted between a pair of vertically adjacent ILD layers 30, or may be incorporated into one or more of the ILD layers 30.

[0062] Although the present invention has been described using an embodiment in which the array 95 of nonvolatile memory cells and selector devices can be formed as a component of the third interconnect hierarchy L3, embodiments are expressly contemplated herein in which the array 95 of nonvolatile memory cells and selector devices can be formed as a component of any other interconnect hierarchy (e.g., L1-L7). Furthermore, although the present invention has been described using an embodiment in which a set of eight interconnect hierarchies is formed, embodiments are expressly contemplated herein in which a different number of interconnect hierarchies is used. Additionally, embodiments are expressly contemplated herein in which two or more arrays 95 of nonvolatile memory cells and selector devices can be provided within multiple interconnect hierarchies in the memory array region 50. Although the present invention has been described using an embodiment in which the array 95 of nonvolatile memory cells and selector devices can be formed in a single interconnect hierarchy, embodiments are expressly contemplated herein in which the array 95 of nonvolatile memory cells and selector devices can be formed above two vertically adjacent interconnect hierarchies.

[0063] Figure 1A The lower level device structure 100 shown includes a substrate that can be used as a substrate on which at least one thin film transistor of the present invention can be formed. In other embodiments, a separate substrate can be used instead of the lower level device structure 100. Although the present invention is described using an embodiment in which the lower level device structure 100 includes four metal line levels for forming at least an embodiment transistor thereon, embodiments in which the substrate 100 includes a different number of metal line levels, which can be formed in additional dielectric layers, are expressly contemplated herein. Various metal lines and vias can be used to connect the embodiment transistor to devices formed in the FEOL of the lower level device structure 100.

[0064] Figure 2A is a plan view of an intermediate structure of a transistor after depositing a stack 101 of alternating conductive layers 104A-104D and dielectric layers 102A-102D over substrate 100 (or lower level device structure 100), and Figure 2B According to various embodiments of the present invention Figure 2A A vertical cross-sectional view taken along line AA'. Figure 2C is a three-dimensional diagram of the intermediate structure. Figure 2A As shown, in addition to the vertical stacking direction, a first horizontal direction hdl and a second horizontal direction hdl can be defined to help describe the following process steps. In embodiments in which the transistor stack is deposited above the substrate 100, the substrate 100 can be made of any suitable material, such as silicon, a compound semiconductor, glass, or any other suitable material. The conductive layers 104A-104D of the stack 101 may include a metallic material, such as a conductive metal nitride (such as TiN, TaN, or WN) or a combination of a conductive metal nitride and an elemental metal (such as W, Cu, Co, Mo, or Ru). The conductive layers 104A-104D can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or any other suitable method.

[0065] Dielectric layers 102A-102D may include silicon oxide, silicon oxynitride, and / or low-k dielectric materials such as organosilicate glass or any other suitable dielectric material. Dielectric layers 102A-102D may be formed by CVD, PVD, PECVD, ALD, or any other suitable method.

[0066] Figure 3 A photoresist layer is formed thereon according to various embodiments of the present invention. Figure 1C A three-dimensional diagram of the intermediate structure. Figure 3 , you can Figures 2A to 2C A photoresist layer 106 is deposited over the illustrated intermediate structure. The photoresist layer 106 can be a positive photoresist material or a negative photoresist material. A positive photoresist material is a type of photoresist material in which the portion of the photoresist layer 106 exposed to light becomes soluble in a photoresist developer. The unexposed portion of the photoresist layer 106 remains insoluble in the photoresist developer. A negative photoresist material is a type of photoresist material in which the portion of the photoresist layer 106 exposed to light becomes insoluble in a photoresist developer. In order to transfer a pattern to the photoresist layer 106, the unexposed portion of the photoresist layer 106 can be dissolved by the photoresist developer.

[0067] Figure 4 is a photoresist layer having a pattern according to various embodiments of the present invention Figure 3A perspective view of an intermediate structure with a patterned photoresist layer exposing a portion of the top conductive layer of a stack of alternating conductive and dielectric layers. Figure 4 , the photoresist layer 106 may be patterned to expose a portion 105A of the top surface of the first conductive layer 104A of the stack 101 of conductive layers 104A-104D and dielectric layers 102A-102D. Figure 4 As shown, in various embodiments, the exposed portion 105A of the top surface of the first conductive layer 104A has a stripe shape oriented in the second horizontal direction hd2.

[0068] Figure 5 is a first conductive layer and a first dielectric layer of a stack of alternating conductive layers and dielectric layers patterned using a photoresist layer as a mask according to various embodiments of the present invention. Figure 4 A three-dimensional diagram of the intermediate structure. Figure 5 , the first conductive layer 104A and the first dielectric layer 102A located below the first conductive layer 104A can be etched to form a step in the stack 101 of alternating conductive layers 104A-104D and dielectric layers 102A-102D. The etching can be performed in two steps. In the first etching step, the first conductive layer 104A can be selectively etched so that the etching stops at the top surface of the first dielectric layer 102A. Next, the first dielectric layer 102A can be selectively etched so that the etching stops at the top surface of the second conductive layer 104B in the stack 101 of alternating conductive layers 104A-104D and dielectric layers 102A-102D. Figure 5 As shown, etching of the exposed portion of the first dielectric layer 102A results in the formation of an exposed portion 105B on the top surface of the second conductive layer 104B. In this manner, steps can be formed in the stack 101 of alternating conductive layers 104A-104D and dielectric layers 102A-102D, where Figure 5 As shown, the exposed portion 105B on the top surface of the second conductive layer 104B has a stripe shape oriented in the second horizontal direction hd2.

[0069] Figure 6 is a photoresist layer having a pattern according to various embodiments of the present invention Figure 5 A perspective view of an intermediate structure wherein the patterned photoresist layer exposes a second portion of the top conductive layer of the stack of alternating conductive and dielectric layers. Figure 6 , the photoresist layer 106 may be patterned again to form an exposed portion 105A of the top surface of the first conductive layer 104A of the stack 101 in addition to the exposed portion 105B of the top surface of the conductive layer 104B of the stack 101. Figure 6 As shown, Figure 6Each of the illustrated exposed portions 105A and 105B may have a stripe shape oriented in the second horizontal direction hd2.

[0070] Figure 7 is a perspective view of an intermediate structure after several patterning and etching steps to form a stepped structure in portions of a stack of alternating conductive and dielectric layers according to various embodiments of the present invention. Figure 7 , can be repeated Figures 4 to 6 The patterning and selective etching process in FIG. 1 is continued until the exposed portion 105D of the lowermost conductive layer 104 (e.g., 104D) in the stack 101 of conductive layers 104 and dielectric layers 102 is exposed. As the photoresist layer 106 is recessed in each successive step, all exposed layers can be selectively etched simultaneously. For example, in FIG. Figure 6 After the photoresist layer 106 is recessed as shown, a subsequent selective etching step (not shown) will result in the removal of the exposed portion 105A of the top surface of the first conductive layer 104A and the exposed portion 105B of the top surface of the second conductive layer 104B, thereby exposing the top surface of the third dielectric layer 102C below. The process can then be repeated as many times as needed. In this way, a stepped structure 103 can be formed in the stack 101 of conductive layers 104 and dielectric layers 102. Each step includes an exposed portion 105A-105D of the top surface of the conductive layers 104A-104D and an underlying dielectric layer 102A-102D that electrically isolates adjacent conductive layers 104A-104D from each other. As shown in FIG. Figure 7 As shown, the stack 101 of alternating conductive layers 104A-104D and dielectric layers 102A-102D includes four conductive layers 104A-104D and four dielectric layers 102A-102D. However, this is for illustration only. The stack 101 of alternating conductive layers 104A-104D and dielectric layers 102A-102D may have fewer layers or more layers, such as 2-64 conductive layers 104A-104D and 2-64 dielectric layers 102A-102D, or 4-32 conductive layers 104A-104D and 4-32 dielectric layers 102A-102D.

[0071] Figure 8 is a device having an intermetal dielectric layer (IMD) deposited over an intermediate structure according to various embodiments of the present invention. Figure 7 A three-dimensional diagram of the intermediate structure. Figure 8Once the lowest conductive layer 104 (e.g., 104D) in the stack 101 of conductive layers 104 and dielectric layers 102 is exposed, the remaining photoresist layer 106 can be removed. Removal of the photoresist layer 106 can be achieved by ashing or dissolving the photoresist layer 106 with a solvent. After removing the photoresist layer 106, the top conductive layer 104A of the stack 101 of conductive layers 104 and dielectric layers 102 includes a remaining portion 105R, wherein, as discussed in more detail below, the vertical pillars of the transistor can be fabricated. Next, the intermediate structure can be covered with an intermetallic dielectric (IMD) layer 107. The IMD can be made of silicon oxide, silicon oxynitride, and / or a low-k dielectric material (such as organosilicate glass or any other suitable dielectric material). The IMD layer 107 can be deposited by CVD, PVD, PECVD, ALD, or any other suitable process.

[0072] Figure 9 is after the planarization process according to various embodiments of the present invention Figure 8 A perspective view of an intermediate structure, with the planarization process exposing the top surface of the top conductive layer of the stack of alternating conductive and dielectric layers. Figure 9 , can be flattened Figure 8 The intermediate structure shown allows the IMD layer 107 to be removed from the remaining portion 105R of the surface of the top conductive layer 104. Figure 9 As shown, a portion of the IMD layer 107 remains above the stepped structure 103 of the stack 101 of conductive layers 104 and dielectric layers 102. Planarization can be achieved by chemical mechanical polishing. The top surface of the IMD layer 107 can be coplanar with the top surface 105A of the topmost conductive layer 104 (e.g., 104A) in the stack 101.

[0073] Figure 10A After depositing the hard mask layer and the photoresist layer according to various embodiments of the present invention Figure 9 A three-dimensional diagram of the intermediate structure. Figure 10B is a through-hole with a hard mask layer and a photoresist layer added according to various embodiments of the present invention Figure 10A A vertical cross-section of the intermediate structure shown along plane AA'. Figure 10A and Figure 10B , you can Figure 9 A hard mask layer 108 is deposited over the surface of the intermediate structure shown. Next, a photoresist layer 106 can be deposited over the hard mask layer 108. The hard mask layer 108 can include amorphous carbon, an organosiloxane-based material, SiN, SiON, or a combination thereof. The hard mask layer 108 can be deposited by CVD, PECVD, ALD, or any other suitable method. Next, a photoresist layer 106 can be deposited over the hard mask layer 108.

[0074] Figure 11 After patterning the hard mask layer and removing the photoresist layer according to various embodiments of the present invention Figure 10B A vertical cross-section of the intermediate structure. Figure 11 , the photoresist layer 106 may be patterned and used to pattern the hard mask layer 108. After patterning the hard mask layer 108, the photoresist layer 106 may be removed. Figure 11 As shown, patterning of the hard mask layer 108 results in exposed portions 108T of the remaining portion 105A of the surface of the top conductive layer 104. The exposed portions 108T may be generally stripe-shaped oriented in a first horizontal direction hd1.

[0075] Figure 12 After etching the stack of alternating conductive and dielectric layers using a patterned hard mask according to various embodiments of the present invention Figure 11 A vertical cross-section of the intermediate structure. Figure 12 , the stack 101 of alternating conductive layers 104 and dielectric layers 102 can be etched until the top surface of the substrate 100 is exposed. The etching can be performed in a single anisotropic etching step or in a series of anisotropic etching steps. In this way, a track 101R of alternating conductive layers 104 and dielectric layers 102 separated by trenches 109 can be formed. As discussed above, the alternating conductive layers 104 and dielectric layers 102 can be etched in a series of selective etching steps.

[0076] Figure 13 According to various embodiments of the present invention Figure 12 After conformally depositing a dielectric layer over the surface of the intermediate structure shown Figure 12 A vertical cross-section of the intermediate structure. Figure 13 , the hard mask layer 108 may be removed after forming the track 101R of alternating conductive layer 104 and dielectric layer 102. The hard mask layer 108 may be removed by wet etching or dry etching. Next, Figure 12A dielectric layer 110 is conformally deposited over the surface of the illustrated intermediate structure. That is, dielectric layer 110 may be deposited over the exposed top surface of conductive layer 104 in each track 101R of alternating conductive layer 104 (104A, 104B, 104C...) and dielectric layer 102 (102A, 102B, 102C...), over the exposed sidewall surfaces of conductive layer 104 and dielectric layer 102 in the tracks 101R of alternating conductive layer 104 and dielectric layer 102, and over the exposed top surface of substrate 100. Dielectric layer 110 may include a dielectric material. In various embodiments, dielectric layer 110 may include a high-k dielectric material having a higher dielectric constant than silicon oxide (SiO2), which has a dielectric constant k of 3.9. Exemplary high-k dielectric materials include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium dioxide-aluminum oxide (HfO2-Al2O3), and tantalum oxide (Ta2O5). In some embodiments, the dielectric layer 110 may include silicon oxide, such as SiO x / SiN y / SiO x (ONO). In some embodiments, dielectric layer 110 may include a ferroelectric material. Other suitable materials are within the contemplation of the present invention. Dielectric layer 110 may be made of a single layer of dielectric material or a multilayer dielectric material, wherein different layers may have different compositions. Dielectric layer 110 may be manufactured by CVD, PECVD, ALD, PVD, or any other suitable method.

[0077] Figure 14 According to various embodiments of the present invention Figure 13 After conformal deposition of a channel layer over the intermediate structure shown Figure 13 A vertical cross-section of the intermediate structure. Figure 14 , the channel layer 112 may be conformally deposited on the dielectric layer 110. Figure 14 As shown, in various embodiments, the channel layer 112 may include a first oxide semiconductor layer 112A, a second oxide semiconductor layer 112B, and a third oxide semiconductor layer 112C. In various embodiments, the first oxide semiconductor layer 112A may have a first oxygen concentration, the second oxide semiconductor layer 112B may have a second oxygen concentration, and the third oxide semiconductor layer 112C may have a third oxygen concentration. In various embodiments, the second oxygen concentration may be lower than the first oxygen concentration or the third oxygen concentration. In various embodiments, the first oxygen concentration and the third oxygen concentration may be the same.

[0078] In various embodiments, each of the first oxide semiconductor layer 112A, the second oxide semiconductor layer 112B, and the third oxide semiconductor layer 112C may include In x Ga y Zn z M w O. M may be a metal selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof. In various embodiments, 0<(x, y, z)<1. In various embodiments, the ratio In:Ga:Zn:M may be the same in all three oxide semiconductor layers 112A, 112B, 112C. Therefore, in some embodiments, the respective layers of the oxide semiconductors 112A, 112B, 112C may be formed of the same material. In an optional embodiment, the first oxide semiconductor layer 112A, the second oxide semiconductor layer 112B, and the third oxide semiconductor layer 112C may have different ratios of In:Ga:Zn:M from each other. Further, as Figure 14 As shown, the dielectric layer may be adjacent to the first oxide semiconductor layer 112A and opposite the second oxide semiconductor layer 112B. In some embodiments, although the first oxide semiconductor layer 112A may have a different material composition than the second oxide semiconductor layer 112B, the first oxide semiconductor layer 112A may have the same composition as the third oxide semiconductor layer 112C. By varying the composition of the oxide semiconductor layers 112A, 112B, and 112C, the oxygen concentration of each oxide semiconductor layer may be varied relative to one another.

[0079] In an embodiment, the oxide semiconductor layers 112A, 112B, and 112C may be formed using PVD or ALD. During the PVD process, oxygen (O2) and argon (Ar) may be introduced into the deposition chamber. By controlling the amount of O2 gas in the atmosphere, the carrier concentration of the oxide semiconductor layer may be controlled. For example, the first oxide semiconductor layer 112A may be deposited using a high O2 flow rate to the total flow rate of Ar and O2 ratio (i.e., O2 / Ar+O2) during oxide semiconductor film deposition. A higher oxygen to argon ratio ensures a desired oxygen percentage in the environment during the deposition process to form an oxide semiconductor with a lower carrier concentration. To form the first oxide semiconductor layer 112A, a flow rate ratio "X" of O2 / (Ar+O2) (where 0.05<X<1) provides a desired O2 percentage during the deposition process. Thus, for example, when the flow rate of O2 is 1 sccm and the flow rate of Ar is 19 sccm, the ratio may be 1 / (19+1) or 0.05. In other embodiments, the atmosphere may contain primarily or entirely O2, and the ratio may be 1 / (0+1) or 1.

[0080] The second oxide semiconductor layer 112B can be formed to have a higher carrier concentration than the first oxide semiconductor layer 112A. The oxygen content of the second oxide semiconductor layer 112B can be lower than the oxygen content of the first oxide semiconductor layer 112A. The lower ratio of the O2 flow rate to the total flow rate of Ar and O2 (i.e., O2:Ar+O2) ensures the desired oxygen percentage in the environment during the deposition process to form an oxide semiconductor with a higher carrier concentration. In order to form the second oxide semiconductor layer 112B, the ratio of the flow ratio "Y" of O2 / (Ar+O2) (where 0<Y<0.05) provides the desired O2 percentage during the deposition process. Thus, for example, when no O2 flows into the deposition chamber, the flow ratio can be 0 (i.e., 0 / Ar+0=0). In other embodiments, the flow rate of O2 can be as high as 1 sccm and the flow rate of Ar is 19 sccm, and the ratio can be 1 / (19+1) or 0.05. In this manner, the oxygen content of the second oxide semiconductor layer 112B can be lower than the oxygen content of the first oxide semiconductor layer 112A.

[0081] The third oxide semiconductor layer 112C can be formed in a similar manner to the first oxide semiconductor layer 112A (i.e., using a flow rate ratio similar to the flow rate ratio used to form the first oxide semiconductor layer 112A). Therefore, to form the third oxide semiconductor layer 112C, a high flow rate ratio "X" of O2 / (Ar+O2) (where 0.05<X<1) provides a desired O2 percentage during the deposition process. In this manner, the first oxide semiconductor layer 112A and the third oxide semiconductor layer 112C can have a higher oxygen content than the second oxide semiconductor layer 112B.

[0082] Furthermore, in some embodiments, the first oxide semiconductor layer 112A, the second oxide semiconductor layer 112B, and the third oxide semiconductor layer 112C may have In x Ga y Zn z M w The composition of O, wherein the ratio In:Ga:Zn:M may be the same in all three oxide semiconductor layers 112A, 112B, 112C.

[0083] In various embodiments, the thickness (t b ) may be larger than the first oxide semiconductor layer 112A (t a ) and the third oxide semiconductor layer 112C (t c ) of the combined thickness (e.g., t b ≥t a +t c For example, the first oxide semiconductor layer 112A (ie, t a) and the third oxide semiconductor layer 112C (ie, t c The thickness of the second oxide semiconductor layer 112B (t b ) may be in the range of 10-100 nm, but a thicker or thinner second oxide semiconductor layer 112B may be used. b ) and the first oxide semiconductor layer (t a ) or the third oxide semiconductor layer (t c )'s thickness ratio can be in the range of 1:10 to 1:100.

[0084] In various embodiments, the carrier concentration in the second oxide semiconductor layer 112B may be greater than the carrier concentration in the first oxide semiconductor layer 112A or the third oxide semiconductor layer 112C. In various embodiments, the carrier concentration in the second oxide semiconductor layer 112B may be greater than the combined carrier concentration of the first oxide semiconductor layer 112A and the third oxide semiconductor layer 112C. In various embodiments, the carrier concentration in the first oxide semiconductor layer 112A and the third oxide semiconductor layer 112C may be greater than 1×10 11 to 1×10 14 In various embodiments, the carrier concentration in the second oxide semiconductor layer 112B may be within the range of 1×10 14 to 1×10 20 Therefore, the ratio of the carrier concentration in the second oxide semiconductor layer 112B to the carrier concentration in the first oxide semiconductor layer and / or the third oxide semiconductor layer may be in the range of 1:1 to 1:10. 9 within the range.

[0085] In various embodiments, the first oxide semiconductor layer 112A, the second oxide semiconductor layer 112B, and the third oxide semiconductor layer 112C may be formed by PVD or ALD or any other suitable method. In various embodiments, the channel layer 112 may be formed so that the first oxide semiconductor layer 112A and the third oxide semiconductor layer 112C may be formed using a higher O2 / Ar+O2 ratio than the second oxide semiconductor layer 112B. In various embodiments, the channel layer 112 may be formed by annealing. Figure 14 The intermediate structure shown. The annealing may be performed at any suitable temperature for any suitable time, such as in the range of 800-1200° C. for a time in the range of 0.5-4 hours.

[0086] Figure 15After conformally depositing a dielectric layer over the channel layer according to various embodiments of the present invention Figure 14 A vertical cross-section of the intermediate structure. Figure 15 , a dielectric layer 114 may be conformally deposited over the channel layer 112. The dielectric layer 114 may be made of or include silicon oxide, silicon oxynitride, and / or a low-k dielectric material (such as organosilicate glass or any other suitable dielectric material). The dielectric layer 114 may be formed by CVD, PECVD, PVD, ALD, or any other suitable method. As discussed above, the metal oxide semiconductor materials utilized in the transistor may suffer from carrier traps generated at the interface between the oxide semiconductor channel layer 112 and the adjacent oxide dielectric layer 110. Due to physical defects in the oxide semiconductor channel layer 112 and / or the adjacent oxide layers (110, 114), carrier traps may be generated at the interface between the oxide semiconductor channel layer 112 and the adjacent oxide dielectric layers (i.e., the high-k dielectric layer 110 and the dielectric layer 114). Due to carrier capture, the resistance and threshold voltage in the channel (the voltage required for the transistor to turn on) may increase, and the drain current in the transistor decreases. The increase in resistance and threshold voltage will degrade chip performance over time until the channel threshold eventually collapses. In addition, carrier traps can interfere with the more useful doping type by compensating for the main charge carrier type, eliminating free electrons or electron holes (depending on which is more prevalent). In addition, deep-level traps can shorten the non-radiative lifetime of charge carriers and promote the recombination of minority carriers through the Shockley-Reed Hall (SRH) process. Shortening the non-radiative lifetime of charge carriers and promoting the recombination of minority carriers may also have an adverse effect on semiconductor device performance.

[0087] Various embodiments of the present invention provide a channel layer 112 formed with multiple sublayers, wherein the second oxide semiconductor layer 112B has an oxygen concentration lower than that of the first oxide semiconductor layer 112A. The second oxide semiconductor layer 112B may also have an oxygen concentration lower than that of the third oxide semiconductor layer 112C. The varying oxygen concentrations of the various sublayers provide for suppression of interactions between the first oxide semiconductor layer 112A and the third oxide semiconductor layer 112C and the adjacent oxide layers (i.e., the high-k dielectric layer 110 and the dielectric layer 114). In this way, charge traps may be formed at the interfaces between the channel layer 112 and the high-k dielectric layer 110 and the dielectric layer 114, resulting in lower recombination and improved device performance.

[0088] Figure 16 After deep trench etching to separate the channel layer according to an embodiment of the present invention Figure 15 A vertical cross-section of the intermediate structure is shown. Figure 16, the dielectric layer 114 and the channel layer 112 can be selectively etched so that portions of the dielectric layer 114 and the channel layer 112 in the bottom of the trench 109 are etched. The selective etching can be performed by dry etching, such as by reactive ion etching. In this way, the channel layer 112 can be separated into individual channel layers 112 so that each track 101R of alternating conductive layer 104 and dielectric layer 102 has its own channel layer 112 that is separated from the channel layer 112 of the adjacent track 101R. In this way, vertical pillars of transistors can be manufactured as discussed in more detail below.

[0089] Figure 17 is after filling the trench with dielectric material according to various embodiments of the present invention Figure 16 A vertical cross-section of the intermediate structure is shown. Figure 17 , the remaining space in the trench 109 , including the etched portions of the dielectric layer 114 and the channel layer 112 , may be filled with material of the additional dielectric layer 114 .

[0090] Figure 18A is after performing the planarization step according to various embodiments of the present invention Figure 17 A vertical cross-section of the intermediate structure is shown. Figure 18B According to various embodiments of the present invention Figure 18A Planar view of the intermediate structure shown. Planarization can be performed by chemical mechanical polishing. Figure 18A and Figure 18B As shown, planarization can be performed until the top surfaces of the conductive layer 104, dielectric layer 110, and channel layer 112 are exposed and are all coplanar with the top surface of the dielectric layer 114. The conductive layer 104 of the track 101R forms the word lines of the individual transistors, as discussed in more detail below. The device track 113R is located between adjacent tracks 101R of the alternating conductive layers 104A-104D and dielectric layers 102A-102D, where vertical pillars of transistors can be formed, as discussed in more detail below.

[0091] Figure 19 yes Figure 18B An enlarged plan view of the intermediate device structure is shown. Figure 19 , can be in the adjacent device vertical column 117 (see Figure 23B 、 Figure 23C ) is formed between the isolation trench 115. The isolation trench 115 can be formed by covering the isolation trench 115 with a photoresist layer (not shown). Figure 18A and Figure 18BThe surface of the intermediate structure shown is etched and a photoresist layer is patterned to expose surface portions of the channel layer 112 and the dielectric layer 114 to form isolation trenches 115. Next, the exposed portions of the channel layer 112 and the dielectric layer 114 can be anisotropically etched down to the surface of the substrate 100. The isolation trenches 115 extend between adjacent dielectric layers 110. As discussed in more detail below, the isolation trenches 115, which result in the formation of vertical pillars of channel material, can be used to form device vertical pillars 117 of transistors.

[0092] Figure 20 After forming the isolation structure in the isolation trench according to various embodiments of the present invention Figure 19 A plan view of the intermediate structure is shown. Figure 20 , the isolation trench 115 may be filled with a dielectric material to form an isolation structure 116. The isolation structure 116 may be made of any suitable dielectric material, such as, but not limited to, silicon oxide, silicon oxynitride, and / or a low-k dielectric material (such as organosilicate glass) or a high-k material (such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, or hafnium dioxide-aluminum oxide (HfO2-Al2O3). The isolation structure may be formed by any suitable method, such as CVD, PECVD, or ALD.

[0093] Figure 21 FIG. 1 is a diagram illustrating the formation of source line / bit line trenches according to various embodiments of the present invention. Figure 20 Floor plan. Reference Figure 21 , source line / bit line trenches 118 may be formed on alternate sides of the isolation structure 116. The source line / bit line trenches 118 extend between adjacent dielectric layers 110 and perpendicular to the surface of the substrate 100. Figure 20 A photoresist layer (not shown) is deposited and patterned over the illustrated intermediate structure to form source line / bit line trenches 118. The patterned photoresist layer can then be used as a mask for an etching step. The etching can be performed by wet etching or dry etching.

[0094] Figure 22 FIG. 1 is a diagram showing a transistor device after forming a source line and a bit line in a source line / bit line trench according to various embodiments of the present invention. Figure 21 Floor plan. Reference Figure 22, a conductive material can be deposited in the source line / bit line trench 118 to form a source / drain region 120. The source / drain region 120 can be made of a metal material, such as a conductive metal nitride (such as TiN, TaN or WN) or a combination of a conductive metal nitride and an elemental metal (such as W, Cu, Co, Mo or Ru). The source line / bit line 120 can be made by CVD, PECVD, PVD, ALD or any other suitable method. In this way, a plurality of transistors 122 can be manufactured. Each transistor can include a word line 104 serving as a gate electrode, a dielectric layer 110, a channel 112 and a source / drain region 120. Each channel 112 can include multiple sublayers, for example, a first oxide semiconductor layer 112A, a second oxide semiconductor layer 112B and a third oxide semiconductor layer 112C. Each track 101R may include transistors 122 formed on opposite sides of the track 101R, wherein each adjacent transistor 122 may be spaced apart from one another in a first horizontal direction hd1 and isolated from one another by isolation structures 116. Furthermore, each track 101R may include additional transistors 122 spaced apart from one another in a vertical direction, wherein each transistor 122 may be isolated from one another by each dielectric layer 102 formed between conductive wordline layers 104. Thus, each layer of conductive layer 104 may include multiple transistors 122 formed on the track 101R.

[0095] Figure 23A yes Figure 22 The integrated semiconductor device 200 is shown in a perspective view, wherein the IMD layer 107 ( Figure 10A ) to show the following details. Figure 23B It passes through Figure 23A A vertical cross-sectional view along line AA'. Figure 23C It passes through Figure 23A A vertical cross-sectional view of the line B-B'. Figure 23A As can be seen in FIG, the track 101R of alternating conductive layers 104 and dielectric layers 102 can have a staircase structure 103. This configuration allows easy access to individual word lines through contact via structures (not shown) coupled to each level of the word lines in the conductive layers 104A-104D. That is, separate contact via structures can be subsequently formed to connect to individual word lines (steps) in the staircase. As described with respect to FIG. Figure 23B and Figure 23C As discussed in more detail, between the tracks 101R of the alternating conductive layer 104 and dielectric layer 102 may be tracks 113R that include vertical pillars 117 of oxide semiconductor transistors 122 .

[0096] refer to Figure 23B and Figure 23C, transistors 122A-122D may be located in vertical device levels separated by dielectric layers 102A-102D, thereby forming vertical columns of oxide semiconductor transistors 122A-122D. Figure 23B As shown, the channel layer 112 extends vertically through each device level 102A-102D and can be separated from the word lines (i.e., conductive layers 104A-104D) by a high-k dielectric layer 114. Thus, the channel layer 112 can serve as a common channel for all transistors 122 in a vertical column of oxide semiconductor transistors 122A-122D. As discussed above, adjacent word lines (i.e., conductive layers 104A-104D) can be separated from each other by the intervening dielectric layer 102A-102D.

[0097] like Figure 23C As shown, the source / drain regions 120 can extend vertically through each device level. Thus, each transistor 122A-122D in a vertical column 117 of transistors 122A-122D can share a common drain line 120 and a common source line 120. Adjacent vertical columns 117 of transistors 122A-122D can be separated from each other by isolation structures 116.

[0098] Figure 24A and Figure 24B An alternative integrated semiconductor device 300 according to various embodiments is shown. Figure 24A is a plan view of an optional integrated semiconductor device 300, and Figure 24B It passes through Figure 24A A-A' vertical cross section. Figure 24B As shown, the alternative integrated semiconductor device 300 has two stepped structures 103A and 103B. The vertical pillar of the oxide semiconductor transistor 122 is located between the two stepped structures 103. This configuration allows additional contact via structures (not shown) to contact the word lines 104A-104D.

[0099] Figure 25A is a vertical cross-sectional view of an alternative configuration of an exemplary intermediate structure for forming a transistor device according to an embodiment of the present invention. Figure 25A , according to various embodiments of the present invention, it is possible to Figure 13 An optional configuration of the exemplary intermediate structure is obtained by conformally depositing the first channel layer 111A on the dielectric layer 110 in the intermediate structure shown. In various embodiments, the first channel layer 111A can be made of a semiconductor oxide material. In an embodiment, the first channel layer 111A can be made of a semiconductor oxide material having the formula In x Ga y Zn zThe first channel layer 111A may be made of a semiconductor oxide material of MO, wherein M is a metal selected from the group consisting of Ti, Al, Ag, W, Ce and Sn and combinations thereof. In various embodiments, 0≤x≤1, 0≤y≤1 and 0≤z≤1. Other semiconductor oxide materials are within the intended scope of the present invention. The first channel layer 111A may be deposited using a suitable deposition process, including physical vapor deposition (PVD), pulsed laser deposition (PLD), chemical vapor deposition (CVD) and atomic layer deposition (ALD). The first channel layer 111A may have a thickness between 0.1 nm and 50 nm, such as a thickness between 5 nm and 35 nm.

[0100] Reference again Figure 25A After the first channel layer 111A is deposited, the exemplary intermediate structure including the first channel layer 111A may be subjected to a heat treatment at an elevated temperature. In various embodiments, the heat treatment may be performed in a vacuum or low-pressure environment. As used herein, "vacuum or low-pressure environment" means that the total pressure within the vessel or other container containing the exemplary intermediate structure during the heat treatment process is controlled to be less than the ambient pressure outside the vessel or container. In various embodiments, the pressure during the heat treatment may be 10 -17 Torr to 760 Torr, such as 10 -9 In various embodiments, the pressure during the heat treatment may be between 10 -3 The temperature during the thermal treatment may be between 100 torr and 760 torr. In an embodiment, the temperature during the thermal treatment may be greater than room temperature (e.g., >25°C, such as ≥30°C) and may be as high as about 450°C. In an embodiment, the thermal treatment may be performed as a soaking anneal or a plasma treatment. The thermal treatment in a vacuum or low-pressure environment may promote carrier generation in the first channel layer 111A.

[0101] In various embodiments, the exemplary intermediate structure including the first channel layer 111A can be subjected to a heat treatment at an elevated temperature in the presence of a process gas including CO, H2, CH4, HBr, and combinations thereof. Other gas species are also within the contemplated scope of the present invention. The process gas can include a reducing gas, such as CO, to promote oxygen desorption from the first channel layer 111A. In particular, in embodiments where CO is included in the process gas, CO can be reduced according to the formula MO+CO→MO 1-x +CO 1+x +V O +e - reacts with the semiconductor oxide material of the first channel layer 111A, where MO is metal-oxygen, V Oare oxygen vacancies. Therefore, this reaction can promote the desorption of oxygen from the first channel layer 111A, as well as the increase of oxygen vacancies and carrier concentration in the first channel layer 111A. Alternatively or additionally, the process gas can include a hydrogen-based gas such as H2, CH4, HBr, etc. The heat treatment in the presence of the hydrogen-based gas can promote hydrogen doping of the semiconductor oxide material and increase free carriers in the first channel layer 111A.

[0102] During the thermal treatment process, process gases may be introduced into a vessel or other container containing the exemplary intermediate structure. In various embodiments, the thermal treatment of the exemplary intermediate structure including the first channel layer 111A may be performed in an environment that is substantially or substantially free of oxygen (O2).

[0103] Figure 25B is a vertical cross-sectional view of an alternative configuration of an exemplary intermediate structure according to an embodiment of the present invention, the exemplary intermediate structure including a second channel layer 111B conformally deposited over a first channel layer 111A. Figure 25B , the second channel layer 111B may be made of a semiconductor oxide material. In an embodiment, the second channel layer 111B may be made of a material having the formula In x Ga y Zn z The semiconductor oxide material of MO is made, where M is a metal selected from the group consisting of Ti, Al, Ag, W, Ce and Sn and combinations thereof. In various embodiments, 0≤x≤1, 0≤y≤1 and 0≤z≤1. Other semiconductor oxide materials are within the intended scope of the present invention. In various embodiments, the ratio In:Ga:Zn:M in the first channel layer 111A and the second channel layer 111B may be the same. Therefore, in some embodiments, the first channel layer 111A and the second channel layer 111B may be formed of the same material. In an optional embodiment, the second channel layer 111B may be formed of a material different from that of the first channel layer 111A. In various embodiments, the second channel layer 111B may be composed of InxGayZn z The MO material has a ratio of In:Ga:Zn:M that is different from the ratio of these elements in the first channel layer 111A.

[0104] The second channel layer 111B may be deposited using a suitable deposition process, including physical vapor deposition (PVD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). In some embodiments, the amount of O2 gas in the atmosphere may be controlled so that the flow rate ratio of O2 during the deposition of the second channel layer 111B is higher than the flow rate ratio of O2 used during the deposition of the first channel layer 111A. The second channel layer 111B may have a thickness between 0.1 nm and 50 nm, such as a thickness between 5 nm and 35 nm. The thickness of the second channel layer 111B may be equal to or greater than the thickness of the first channel layer 111A. In various embodiments, the combined thickness of the first channel layer 111A and the second channel layer 111B may be 50 nm or less.

[0105] In various embodiments, the Figure 25B The exemplary intermediate structure of the second channel layer 111B shown is subjected to a heat treatment at an elevated temperature in the presence of a process gas containing oxygen. In various embodiments, the pressure during the heat treatment may be between 10 and 20°C. -3 The thermal treatment may be performed at a temperature between 100 torr and 760 torr. In an embodiment, the temperature during the thermal treatment may be greater than room temperature (e.g., >25°C, such as ≥30°C) and may be as high as about 450°C. In an embodiment, the thermal treatment may be performed as a soaking anneal or a plasma treatment. The thermal treatment in an oxygen-containing gas environment may promote a reduction in the carrier concentration of the second channel layer 111B.

[0106] The exemplary intermediate structure including the second channel layer 111B can be subjected to a heat treatment in the presence of an oxidizing process gas, which can include, for example, gases based on CO2, O2, O3, N2O, and combinations thereof. Other oxidizing gases are within the contemplation of the present invention. In particular, the oxidizing gas can be prepared according to formula MO y-1 +V O +e - +O→MO y reacts with the semiconductor oxide material of the second channel layer 111B, wherein MO is metal-oxygen, O is an oxygen atom from the oxidizing process gas, and V O Therefore, this reaction can promote the reduction of oxygen vacancies in the second channel layer 111B and the reduction of carrier concentration in the second channel layer 111B.

[0107] In various embodiments, annealing may also include Figure 25BAn exemplary intermediate structure of the second channel layer 111B is shown. The annealing may be performed at any suitable temperature for any suitable time, such as within the range of 800-1200° C. for a time within the range of 0.5-4 hours. In various embodiments, the annealing may be performed in the presence of an oxygen-containing gas. This may promote further oxidation of the semiconductor oxide material of the second channel layer 111B and reduction of oxygen vacancies in the second channel layer 111B.

[0108] Reference again Figure 25B , Figure 25B The enlarged portion of FIG. 1 shows a second channel layer 111B on and above the first channel layer 111A, which can be combined to form the channel layer 111. The channel layer 111 can include a first surface 119 facing the dielectric layer 110 and a second surface 121 opposite the first surface 119. The second surface 121 of the channel layer 111 can be in electrical contact with the source and drain electrodes (e.g., source and bit lines 120) in the fully assembled transistor device. The source and drain electrodes can then be electrically connected as described above with reference to FIG. Figures 22 to 24A The channel layer may have a total thickness t between the first surface 119 and the second surface 121. tot . Portions of the channel layer 111 that are closer to the first surface 119 than the second surface 121 may be relatively oxygen-deficient relative to portions of the channel layer 111 that are closer to the second surface 121 than the first surface 119. This may be a result of the process conditions used to form the first channel layer 111A and the second channel layer 111B, which may promote oxygen desorption from the material of the first channel layer 111A and oxygen diffusion into the material of the second channel layer 111B. This may also increase the concentration of oxygen vacancies in the first channel layer 111A relative to the concentration of oxygen vacancies in the second channel layer 111B. By controlling the process conditions used to form the first channel layer 111A and the second channel layer 111B, the overall thickness t of the channel layer 111 may be controllably varied. tot The oxygen content and carrier concentration in .

[0109] Figure 25C is a graph showing the carrier concentration throughout the thickness of the channel layer 111 according to an embodiment of the present invention. Figure 25C ,against Figure 25B The three different thicknesses t1, t2 and t n The carrier concentration per cubic centimeter is plotted. The dashed lines represent the charge carrier concentration at thicknesses t1, t2, and t n Extrapolation of the carrier concentration in the channel layer 111 between . Figure 25CAs shown, the carrier concentration has a gradient distribution, wherein the highest carrier concentration is closest to the first surface 119 of the channel layer 111, and the carrier concentration gradually decreases throughout the thickness of the channel layer 111 between the first surface 119 and the second surface 121 of the channel layer 111. In other words, the carrier concentration of the channel layer 111 can increase according to the gradient distribution as a function of increasing depth from the second surface 121 of the channel layer 111. In an embodiment, the second surface 121 of the channel layer 111 can be in electrical contact with the corresponding source and drain electrodes (e.g., source lines and bit lines) of the transistor device. In various embodiments, the carrier concentration of the entire channel layer 111 can be in the range of 1×10 11 cm -3 and 1×10 21 cm -3 In an embodiment, the carrier concentration of the channel layer 111 at the second surface 121 may be less than 1×10 18 cm -3 , such as in 1×10 11 cm -3 and 1×10 15 cm -3 Between, including 1×10 11 cm -3 and 1×10 13 cm -3 between.

[0110] In addition, X-ray photoelectron spectroscopy (XPS) depth profile analysis of the embodiment channel layer 111 confirmed that the peak ratio of oxygen vacancies in the channel layer 111 gradually decreases throughout the thickness of the channel layer 111 between the first surface 119 and the second surface 121 of the channel layer 111. Therefore, the oxygen vacancy concentration of the channel layer 111 can increase according to a gradient profile, which is a function of increasing depth from the second surface 121 of the channel layer 111.

[0111] Various embodiments of the present invention provide a channel layer 111 having a carrier concentration that increases according to a gradient profile as a function of increasing depth from a surface 121 of the channel layer 111. In embodiments, the surface 121 of the channel layer 111 may be in electrical contact with corresponding source and drain electrodes (e.g., source and bit lines) of a transistor device. In various embodiments, the carrier concentration of the entire channel layer 111 may be between 1×10 11 cm -3 and 1×10 21 cm -3In various embodiments, the channel layer 111 may have an oxygen vacancy concentration that increases according to a gradient profile as a function of increasing depth from a surface 121 of the channel layer 111. By providing a channel layer 111 for a transistor device having a carrier concentration that increases according to a gradient profile as a function of increasing depth from the surface 121 of the channel layer 111, the transistor device may have a small positive threshold voltage shift and a high on-current, and may achieve ultrafast driving while avoiding the formation of an undesirable conductive path through the channel due to a short channel effect.

[0112] After forming the channel layer 111, the Figures 15 to 23C The process steps include forming a dielectric layer 114 over the channel layer 111, selectively etching the dielectric layer 114 and the channel layer 111 to separate the channel layer 111 so that each track 101R of the alternating conductive layer 104 and dielectric layer 102 has its own channel layer 111 separated from the channel layer 111 of the adjacent track 101R, filling the trench with the dielectric material 114 and planarizing the dielectric material 114 to form a dielectric layer 114 between the adjacent tracks 101R of the alternating conductive layer 104 and dielectric layer 102. Device rails 113R are formed, portions of the channel layer 111 and the dielectric material 114 are selectively etched to form isolation trenches 115 between adjacent device vertical pillars 117, the isolation trenches are filled with dielectric material to form isolation structures 116, source line and bit line trenches 118 are formed on alternating sides of the isolation structure 116, and conductive material is deposited within the source line and bit line trenches 118 to form source lines 120 and bit lines 120 in electrical contact with the second surface 121 of the channel layer 111 to form transistor devices 122.

[0113] Each transistor device 122 may include a word line 104 serving as a gate electrode, a dielectric layer 110, a channel layer 111, and source / drain electrodes in contact with a surface 121 of the channel layer 111. Each channel layer 111 may have a carrier concentration that increases according to a gradient profile as a function of increasing depth from the surface 121 of the channel layer 111.

[0114] Each track 101R can include a plurality of transistor devices 122 formed on opposite sides of the track 101R, wherein each adjacent transistor device 122 can be spaced apart from each other in a first horizontal direction hd1 and isolated from each other by an isolation structure 116. In addition, each transistor device 122 can be spaced apart from each other and isolated in a vertical direction by a dielectric layer 102 formed between each conductive word line layer 104. One or more stepped structures 103, 103A, 103B can be provided in alternating conductive layers 104 and dielectric layers 102 to facilitate formation of electrical contact with each conductive word line layer 104.

[0115] In some embodiments, the channel of the transistor device 122 may include a channel layer 112 formed with a plurality of sub-layers (as described above with reference to FIG. Figure 14 ) and the channel layer 111 having a gradient carrier concentration distribution (as described above with reference to Figures 25A to 25C In one exemplary embodiment, for example, a high flow ratio of O2 to the total flow of Ar and O2 (i.e., O2 / Ar+O2) can be used to deposit the first oxide semiconductor layer 112A during the oxide semiconductor film deposition. The higher oxygen to argon ratio ensures a desired oxygen percentage in the environment during the deposition process to form an oxide semiconductor with a lower carrier concentration. To form the first oxide semiconductor layer 112A, a flow ratio "X" of O2 / (Ar+O2) (where 0.05<X<1) provides a desired O2 percentage during the deposition process. Thus, for example, when the flow rate of O2 is 1 sccm and the flow rate of Ar is 19 sccm, the ratio can be 1 / (19+1) or 0.05. In other embodiments, the atmosphere can contain primarily or entirely O2, and the ratio can be 1 / (0+1) or 1.

[0116] The second oxide semiconductor layer 112B may be formed over the first oxide semiconductor layer 112A. The second oxide semiconductor layer may have a higher carrier concentration than the first oxide semiconductor layer 112A. The oxygen content of the second oxide semiconductor layer 112B may be lower than the oxygen content of the first oxide semiconductor layer 112A. In an embodiment, a lower flow ratio of O2 to the total flow of Ar and O2 (i.e., O2:Ar+O2) ensures a desired oxygen percentage in the environment during the deposition process to form an oxide semiconductor with a higher carrier concentration. To form the second oxide semiconductor layer 112B, a higher flow ratio "Y" of O2 / (Ar+O2) (where 0<Y<0.05) may be used to provide a desired O2 percentage during the deposition process. Thus, for example, when no O2 flows into the deposition chamber, the flow ratio may be 0 (i.e., 0 / Ar+0=0). In other embodiments, the O2 flow rate may be as high as 1 sccm and the Ar flow rate is 19 sccm, and the ratio may be 1 / (19+1) or 0.05. In this manner, the oxygen content of the second oxide semiconductor layer 112B can be lower than the oxygen content of the first oxide semiconductor layer 112A.

[0117] Then, the second oxide semiconductor layer 112B may be subjected to heat treatment at an elevated temperature to promote desorption of oxygen from the second oxide semiconductor layer 112B, such as described above with reference to FIG. Figure 25AIn various embodiments, the heat treatment may be performed in a vacuum or low-pressure environment and may optionally be performed in the presence of a process gas such as CO, H2, CH4, HBr, and combinations thereof to further promote the desorption of oxygen from the second oxide semiconductor layer 112B and the generation of oxygen vacancies in the second oxide semiconductor layer 112B. The heat treatment may be performed in an environment that is substantially free of or essentially free of oxygen (O2).

[0118] The third oxide semiconductor layer 112C may be formed over the second oxide semiconductor layer 112B. In some embodiments, the amount of O2 gas in the atmosphere may be controlled to have a higher O2 flow rate during deposition of the third oxide semiconductor layer 112C than that used during deposition of the second oxide semiconductor layer 112B. In an embodiment, the third oxide semiconductor layer 112C may be formed in a manner similar to the first oxide semiconductor layer 112A (i.e., using a flow rate similar to the flow rate used to form the first oxide semiconductor layer 112A). Alternatively, the third oxide semiconductor layer 112C may be formed using a flow rate similar to the flow rate used to form the second oxide semiconductor layer 112B. In some embodiments, the flow rate used to form the third oxide semiconductor layer 112C may be different from the flow rate used to form the first oxide semiconductor layer 112A and the second oxide semiconductor layer 112B.

[0119] After depositing the third oxide semiconductor layer 112C, the intermediate structure may be annealed, optionally in the presence of an oxygen-containing gas, which may further oxidize the third oxide semiconductor layer 112C. The process conditions used to form the second oxide semiconductor layer 112B and the third oxide semiconductor layer 112C may promote desorption of oxygen from the second oxide semiconductor layer 112B and diffusion of oxygen into the third oxide semiconductor layer 112C (and optionally the first oxide semiconductor layer 112A), and may also increase the concentration of oxygen vacancies in the second oxide semiconductor layer 112B relative to the concentration of oxygen vacancies in the first oxide semiconductor layer 112A and the third oxide semiconductor layer 112C.

[0120] The channel layer 112 formed of the plurality of sublayers 112A, 112B, and 112C as described above can have a carrier concentration that initially increases according to a gradient profile as a function of increasing depth from a first surface of the channel layer 112 (corresponding to the upper surface of the third oxide semiconductor layer 112C), and then decreases near a second surface of the channel layer 112 (corresponding to the lower surface of the first oxide semiconductor layer 112A). Similarly, the oxygen vacancy concentration of the channel layer 112 can increase according to a gradient profile as a function of increasing depth from the first surface, and then decrease near the second surface. Thus, the channel layer 112 can prevent the formation of an undesirable conductive path between the source and drain electrodes due to a short channel effect, while also forming fewer charge traps at the interface between the channel layer 112 and the high-k dielectric layer 110, resulting in lower recombination and improved device performance.

[0121] Figure 26 FIG. 2 is a vertical cross-sectional view of another exemplary structure of a transistor device 222 according to an embodiment of the present invention. The transistor device 222 may be formed over a support structure, which may be a support structure such as Figures 1A to 1C The substrate or lower level device structure 100 is shown. Figure 26 The transistor device 222 may include a word line 204 made of a conductive material, such as a metal (e.g., W, Cu, Co, Mo, Ru, etc.), a conductive metal nitride (e.g., TiN, TaN, or WN), or various combinations of conductive materials. The word line 204 may serve as a gate electrode for the transistor device 222.

[0122] A dielectric layer 210 may be disposed over the word lines 204. The dielectric layer 210 may include, for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), titanium oxide (TiO2), hafnium lanthanum oxide (HfLaO), aluminum oxide (Al2O3), hafnium dioxide-aluminum oxide (HfO2-Al2O3), tantalum oxide (Ta2O5), or combinations thereof. In some embodiments, the dielectric layer 210 may include SiO x / SiN y / SiO x (ONO), ferroelectric or another memory layer.

[0123] Reference again Figure 26 , a channel layer 212 may be provided over the dielectric layer 210. The channel layer 212 may include an oxide semiconductor material, such as In x Ga y Zn zMO, where M is a metal selected from the group consisting of Ti, Al, Ag, W, Ce, and Sn and combinations thereof. In various embodiments, 0 < x < 1, 0 ≤ y ≤ 1, and 0 ≤ z ≤ 1.

[0124] The channel layer 212 may include a channel layer formed with multiple sub-layers, such as the channel layer 112 described above with reference to Figure 14 Description of the channel layer 112. In particular, the channel layer 212 may include a first oxide semiconductor layer 112A having a first oxygen concentration above the high-k layer 210, a second oxide semiconductor layer 112B having a second oxygen concentration above the first oxide semiconductor layer 112A, and a third oxide semiconductor layer 112C having a third oxygen concentration above the second oxide semiconductor layer 112B, where the oxygen concentration of the second oxide semiconductor layer 112B is lower than the oxygen concentrations of the first oxide semiconductor layer 112A and the third oxide semiconductor layer 112C. The second oxide semiconductor layer 112B may have a higher carrier concentration than the first oxide semiconductor layer 112A and the third oxide semiconductor layer 112C. Thus, in various embodiments, compared to the carrier concentration in the middle portion 228 of the channel layer 212 between the lower surface 224 and the upper surface 226, the channel layer 212 may have a lower carrier concentration near the lower surface 224 of the channel layer 212 (i.e., at the interface between the channel layer 212 and the dielectric layer 210) and a lower carrier concentration near the upper surface 226 of the channel layer 212 (i.e., at the interface between the channel layer 212, the cap layer 207, and the source electrode 220 and the drain electrode 221).

[0125] Optionally or additionally, the channel layer 212 may include a channel layer having a gradient carrier concentration profile, such as the channel layer 111 described above with reference to Figures 25A to 25C Description of the channel layer 111. In particular, the channel layer 212 may have a carrier concentration that increases according to a gradient distribution as a function of increasing depth from the upper surface 226 of the channel layer 212. The channel layer 112 may also have an oxygen vacancy concentration that decreases according to a gradient distribution as a function of increasing depth from the upper surface 226 of the channel layer 212. Thus, in various embodiments, compared to the carrier concentration in the middle portion 228 of the channel layer 212, the channel layer 212 may have a lower carrier concentration near the upper surface 226 of the channel layer 212 (i.e., at the interface between the channel layer 212, the cap layer 207, and the source electrode 220 and the drain electrode 221).

[0126] Referring again to <关于图14的描述> (这里推测你原文中 Figure 26 对应的中文是“关于图14的描述”,你可根据实际情况修改) 请注意,由于你提供的原文中 Figure 26 对应的中文部分缺失完整信息,我按照推测进行了补充翻译,你可根据实际内容进行调整。如果还有其他疑问,请随时告诉我。A cap layer 207 may be disposed above the upper surface 226 of the channel layer 212. The cap layer 207 may include a suitable dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), or a high-k material, such as aluminum oxide (Al2O3). Other suitable dielectric materials are within the contemplated scope of the present invention.

[0127] The transistor device 222 may further include a source line 220 and a bit line 221, which extend through an opening in the cap layer 207 and contact an upper surface 226 of the channel layer 212. The source line 220 and the bit line 221 may be made of a conductive material, such as a metal (e.g., W, Cu, Co, Mo, Ru, etc.), a conductive metal nitride (e.g., TiN, TaN, or WN), or various combinations of conductive materials. The source line 220 may serve as a source electrode for the transistor device 222, and the bit line 221 may serve as a drain electrode for the transistor device 222. The source line 220 and the bit line 221 may be laterally spaced apart from each other, and the cap layer 207 may extend above the upper surface 226 of the channel layer 212 between the source line 220 and the bit line 221. The distance between the source line 220 and the bit line 221 defines the effective channel length L of the transistor device 222. In various embodiments, the effective channel length L of the transistor device 222 can be in the range of 5 nm to 500 nm. In embodiments, the relatively low carrier concentration of the channel layer 212 near the upper surface 226 of the channel layer 212 can prevent the formation of a conductive path through the channel layer 212 between the source line 220 and the bit line 221 due to a short channel effect, and can also limit the formation of charge traps at the interface between the channel layer 112 and the cap layer 207.

[0128] A dielectric material 214 may be disposed over the surface of the cap layer 207, over the lateral sides of the cap layer 207 and the channel layer 212, and over the exposed upper surface of the dielectric layer 210. The dielectric material 214 may be an interlayer dielectric (ILD) material such as silicon oxide, silicon oxynitride, and / or a low-k dielectric material such as organosilicate glass, or any other suitable dielectric material. The dielectric material 214 may laterally surround portions of the source line 220 and the bit line 221.

[0129] In various embodiments, the dielectric layer 210 may be fabricated by depositing a continuous channel layer and a continuous cap layer over the dielectric layer 210, forming a patterned mask over at least a region of the continuous cap layer using a photolithography process, and etching the remaining unmasked portions of the continuous cap layer and the continuous channel layer to provide a patterned channel layer 212 and a patterned cap layer 207 over the dielectric layer 210. Figure 262. A transistor device 222 is shown. A dielectric material 214 may then be deposited over the top surface of the patterned cap layer 207, over the lateral sides of the patterned cap layer 207 and the patterned channel layer 212, and over the exposed upper surface of the dielectric layer 210 using a suitable deposition method (such as by CVD, PVD, PECVD, ALD, etc.). A patterned mask may be formed over the dielectric material 214 using a photolithography process, and unmasked portions of the dielectric material 214 may be etched to form openings through the dielectric material 214 and the cap layer 207, wherein a portion of the upper surface 226 of the channel layer 212 may be exposed in the bottom surface of the opening. A conductive material may then be deposited within the opening and, optionally, planarized to form a source line 220 and a bit line 221, respectively, that are in electrical contact with the upper surface 226 of the channel layer 212.

[0130] Although Figure 26 The transistor device 222 shown is a bottom gate or back gate transistor in which the gate electrode (i.e., word line 204) is disposed below the lower surface 224 of the channel layer 212, but in an optional embodiment, the transistor device 222 can be a top gate transistor in which a patterned dielectric layer 210 and a patterned gate electrode (i.e., word line 205) can be disposed above the upper surface 226 of the channel layer 212 between the source line 220 and the bit line 221.

[0131] Figure 27 An embodiment method 400 for forming an embodiment oxide semiconductor transistor (122, 222) is shown. Figure 27 , method 400 includes step 402 of depositing a gate electrode (104, 204). Referring to step 404, the method includes depositing a dielectric layer (110, 210) in contact with the gate electrode (104, 204). Referring to step 406, the method includes depositing a channel layer (112, 212) in contact with the dielectric layer 110, wherein depositing the channel layer (112, 212) includes depositing a dielectric layer including In x Ga y Zn z The step of depositing the first oxide semiconductor layer 112A of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn and combinations thereof; and 0<(x, y, z)<1. Referring to step 408, the step of depositing the channel layer (112, 212) further includes depositing an In x Ga y Zn zThe second oxide semiconductor layer 112B of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn and combinations thereof, wherein the composition of the second oxide semiconductor layer 112B is different from the composition of the first oxide semiconductor layer 112A. Referring to step 410, the step of depositing the channel layer (112, 212) further includes depositing an In x Ga y Zn z A third oxide semiconductor layer 112C of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, wherein the composition of the third oxide semiconductor layer 112C is different from the composition of the second oxide semiconductor layer 112B. Referring to step 412, the method further includes the step of forming a source / drain line (120, 220, 221) in contact with the channel layer (112, 212). In the embodiment method 400, the composition of the first oxide semiconductor layer 112A and the second oxide semiconductor layer 112B results in a second oxygen concentration in the second oxide semiconductor layer being lower than the first oxygen concentration in the first oxide semiconductor layer.

[0132] Figure 28 An alternative embodiment method 500 for forming an embodiment oxide semiconductor transistor (122, 222) is shown. Figure 28 , the method includes step 502 of depositing a gate electrode (104, 204). Referring to step 504, the method includes depositing a dielectric layer (110, 210) in contact with the gate electrode (104, 204). Referring to step 506, the method includes depositing a channel layer (112, 212) in contact with the dielectric layer (110, 210), wherein depositing the channel layer (112, 212) includes the step of depositing a first oxide semiconductor layer 112A in an environment with a high flow ratio of O2 to Ar+O2. Referring to step 508, the step of depositing the channel layer (112, 212) also includes depositing a second oxide semiconductor layer 112B in an environment with a low ratio of O2 to Ar+O2. Referring to step 510, the step of depositing the channel layer (112, 212) also includes depositing a third oxide semiconductor layer 112C in an environment with a high ratio of O2 to Ar+O2. Referring to step 512, the method further includes forming source / drain lines (120, 220, 221) in contact with the channel layer (112, 212). In the embodiment method 500, the resulting first oxygen concentration of the first oxide semiconductor layer 112A is higher than the second oxygen concentration of the second oxide semiconductor layer 112B.

[0133] Figure 29 An alternative embodiment method 600 for forming an embodiment oxide semiconductor transistor (122, 222) is shown. Figure 29, the method includes step 602 of depositing a gate electrode (104, 204). Referring to step 604, the method includes depositing a dielectric layer (110, 210) in contact with the gate electrode (104, 204). Referring to step 606, the method includes depositing a first layer 111A of an oxide semiconductor material. Referring to step 608, the method also includes performing a thermal treatment of the first layer 111A of the oxide semiconductor material in a vacuum or low-pressure environment. Referring to step 610, the method also includes depositing a second layer 111B of an oxide semiconductor material over the first layer 111A to provide a channel layer (111, 212) having a carrier concentration that increases according to a gradient profile, the carrier concentration increasing as a function of depth from a surface (121, 226) of the channel layer (111, 212). Referring to step 612, the method further includes the step of forming source / drain lines (120, 220, 221) above the surface (121, 226) of the channel layer (111, 212).

[0134] In some applications, various embodiments disclosed herein provide multilayer channel layers with varying oxygen levels that reduce interface carrier traps by suppressing interactions between the oxide semiconductor channel layer and the adjacent dielectric oxide layer. Furthermore, due to gate swing bias, the multilayer channel layer can enhance the low hysteresis characteristics of the device as a small-signal RF characteristic. Another advantage of multilayer channel layers with varying oxygen levels is that the oxygen concentration can be detected and confirmed by secondary ion mass spectroscopy (SIMS).

[0135] In some applications, various embodiments disclosed herein provide a channel layer having a carrier concentration that increases according to a gradient profile as a function of increasing depth from the surface of the channel layer. In embodiments, the surface of the channel layer may be in electrical contact with corresponding source and drain electrodes (e.g., source and bit lines) of a transistor device. In various embodiments, the carrier concentration in the entire channel layer may be in the range of 1×10 11 cm -3 and 1×10 21 cm -3 In various embodiments, the channel layer may have an oxygen vacancy concentration that increases according to a gradient profile as a function of increasing depth from the surface of the channel layer. By providing a channel layer for a transistor device, the carrier concentration of the channel layer increases according to a gradient profile as a function of increasing depth from the surface of the channel layer, the transistor device can provide high performance while avoiding the formation of an undesirable conductive path through the channel due to a short channel effect.

[0136] With reference to all drawings and in accordance with various embodiments of the present invention, there is provided a transistor (122, 222), wherein the transistor (122, 222) comprises a gate electrode (104, 204), a dielectric layer (110, 210), a source electrode and a drain electrode (120, 220, 221), and a channel layer (112, 111, 226), wherein the channel layer (112, 111, 226) has an upper surface (121, 226), a lower surface (119, 224) and a dielectric layer (119, 226) disposed between the upper surface (121, 226) and the lower surface (119, 224). 24), wherein the source electrode and the drain electrode (120, 220, 221) are in electrical contact with the upper surface (121, 226) of the channel layer (112, 111, 226), and the channel layer (112, 111, 226) has a first carrier concentration near the upper surface of the channel layer (112, 111, 226) and a second carrier concentration in the middle portion (112B, 228) of the channel layer (112, 111, 226), and the first carrier concentration is less than the second carrier concentration.

[0137] In an embodiment, the channel layer (112, 226) has a third carrier concentration near a lower surface (119, 224) of the channel layer (112, 111, 226), and the third carrier concentration is less than the second carrier concentration.

[0138] In another embodiment, the channel layer (112, 226) includes a first oxide semiconductor layer 112A having a first oxygen concentration, a second oxide semiconductor layer 112B having a second oxygen concentration, and a third oxide semiconductor layer 112C having a third oxygen concentration. In the embodiment transistor, the second oxide semiconductor layer 112B is located between the first oxide semiconductor layer 112A and the third oxide semiconductor layer 112C. In addition, the second oxygen concentration is lower than the first oxygen concentration or the third oxygen concentration.

[0139] In another embodiment, the first oxygen concentration and the third oxygen concentration are equal. In another embodiment, the dielectric layer (110, 210) is adjacent to the first oxide semiconductor layer 112A and opposite to the second oxide semiconductor layer 112B. In another embodiment, the gate electrode (104, 204) is adjacent to the dielectric layer (110, 210) and opposite to the first oxide semiconductor layer 112A. In another embodiment, the dielectric layer (110, 210) can be selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium dioxide-aluminum oxide (HfO2-Al2O3), tantalum oxide (Ta2O5), SiO x / SiNy / SiO x In another embodiment, the first oxide semiconductor layer 112A, the second oxide semiconductor layer 112B, and the third oxide semiconductor layer 112C include In x Ga y Zn z MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof; and 0<(x, y, z)<1. In another embodiment, the first oxide semiconductor layer 112A, the second oxide semiconductor layer 112B, and the third oxide semiconductor layer 112C include In x Ga y Zn z M w In another embodiment, the thickness of the second oxide semiconductor layer 112B is greater than the combined thickness of the first oxide semiconductor layer 112A and the third oxide semiconductor layer 112C. In another embodiment, the ratio of the carrier concentration in the second oxide semiconductor layer 112B to the carrier concentration in the first oxide semiconductor layer 112A is in the range of 1:1 to 1:10. 9 within the range.

[0140] Additional embodiments relate to a method of forming an oxide semiconductor transistor (122, 222), the method comprising depositing a gate electrode (104, 204), depositing a dielectric layer (110, 210), and depositing a channel layer (112, 212), wherein depositing the channel layer comprises depositing a dielectric layer comprising In x Ga y Zn z The first oxide semiconductor layer 112A of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn and combinations thereof; and 0<(x, y, z)<1, is deposited including In x Ga y Zn z A second oxide semiconductor layer 112B of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, and wherein the composition of the second oxide semiconductor layer 112B is different from that of the first oxide semiconductor layer 112A, and an In x Ga y Zn zA third oxide semiconductor layer 112C of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, and wherein a composition of the third oxide semiconductor layer 112C is different from a composition of the second oxide semiconductor layer 112B, and wherein a second oxygen concentration of the second oxide semiconductor layer 112B is lower than a first oxygen concentration of the first oxide semiconductor layer 112A. The method further includes forming a source electrode (120, 220) and a drain electrode (120, 221) in contact with the channel layer (112, 212).

[0141] In another embodiment, the channel layer (112, 212) is deposited by at least one of atomic layer deposition and physical vapor deposition. In another embodiment, the composition of the first oxide semiconductor layer 112A and the composition of the third oxide semiconductor layer 112C are the same. In another embodiment, the second oxygen concentration of the second oxide semiconductor layer 112B is lower than the third oxygen concentration of the third oxide semiconductor layer 112C.

[0142] Additional embodiments relate to a method of forming an oxide semiconductor transistor (122, 222), the method comprising depositing a gate electrode (104, 204), depositing a dielectric layer (110, 210), and depositing a channel layer (112, 212), wherein depositing the channel layer comprises depositing a first oxide semiconductor layer 112A having a first oxygen concentration using a physical vapor deposition process in an environment having a first flow ratio of O2 / (Ar+O2), depositing a second oxide semiconductor layer 112B having a second oxygen concentration using a physical vapor deposition process in an environment having a second flow ratio of O2 / (Ar+O2), and depositing a third oxide semiconductor layer 112C having a third oxygen concentration using a physical vapor deposition process in an environment having a third flow ratio of O2 / (Ar+O2), wherein the second flow ratio of O2 / (Ar+O2) is lower than the first and third flow ratios of O2 / (Ar+O2), and wherein the second oxygen concentration is lower than the first and third oxygen concentrations. The method also includes forming a source electrode (120, 220) and a drain electrode (120, 221) in contact with the channel layer (112, 212).

[0143] In another embodiment, depositing the channel layer (112, 212) is performed by physical vapor deposition. In another embodiment, the method includes annealing the channel layer (112, 212). In another embodiment, the first flow ratio and the third flow ratio of O2 / (Ar+O2) are greater than 0.05 and less than 1. In another embodiment, the second flow ratio of O2 / (Ar+O2) is greater than or equal to 0 and less than or equal to 0.05. In another embodiment, the first oxide semiconductor layer 112A, the second oxide semiconductor layer 112B, and the third oxide semiconductor layer 112C include Inx Ga y Zn z The composition of MO, where M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, and the ratio of In:Ga:Zn:M is the same in each of the first oxide semiconductor layer 112A, the second oxide semiconductor layer 112B, and the third oxide semiconductor layer 112C.

[0144] Some embodiments of the present application provide a transistor, comprising: a gate electrode; a dielectric layer; a source electrode and a drain electrode; and a channel layer, having an upper surface, a lower surface, and a middle portion located between the upper surface and the lower surface, wherein the source electrode and the drain electrode are electrically contacted with the upper surface of the channel layer, and the channel layer has a first carrier concentration near the upper surface of the channel layer and a second carrier concentration in the middle portion of the channel layer, and the first carrier concentration is less than the second carrier concentration.

[0145] In some embodiments, the channel layer has a third carrier concentration near the lower surface of the channel layer, and the third carrier concentration is less than the second carrier concentration. In some embodiments, the channel layer includes: a first oxide semiconductor layer having a first oxygen concentration; a second oxide semiconductor layer having a second oxygen concentration; and a third oxide semiconductor layer having a third oxygen concentration, wherein the second oxide semiconductor layer is located between the first oxide semiconductor layer and the third oxide semiconductor layer; and wherein the second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration. In some embodiments, the first oxygen concentration and the third oxygen concentration are equal. In some embodiments, the dielectric layer is adjacent to the first oxide semiconductor layer and opposite to the second oxide semiconductor layer, and the gate electrode is adjacent to the dielectric layer and opposite to the first oxide semiconductor layer. In some embodiments, the dielectric layer comprises a material selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium dioxide-aluminum oxide (HfO2-Al2O3), tantalum oxide (Ta2O5), SiO x / SiN y / SiO x In some embodiments, the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer include In x Ga y Zn zMO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, and 0<(x, y, z)<1; and the source electrode and the drain electrode comprise a conductive metal material. In some embodiments, the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprise In x Ga y Zn z M w In some embodiments, the thickness of the second oxide semiconductor layer is greater than the combined thickness of the first oxide semiconductor layer and the third oxide semiconductor layer. In some embodiments, the ratio of the carrier concentration in the second oxide semiconductor layer to the carrier concentration in the first oxide semiconductor layer is between 1:1 and 1:10. 9 within the range.

[0146] Some other embodiments of the present application provide a method for forming an oxide semiconductor transistor, comprising: depositing a gate electrode; depositing a dielectric layer; depositing a channel layer, including: depositing an In x Ga y Zn z A first oxide semiconductor layer of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, and 0<(x, y, z)<1; and a deposition layer comprising In x Ga y Zn z A second oxide semiconductor layer of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, wherein the composition of the second oxide semiconductor layer is different from the composition of the first oxide semiconductor layer; depositing an In x Ga y Zn z A third oxide semiconductor layer of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn and combinations thereof, wherein a composition of the third oxide semiconductor layer is different from a composition of the second oxide semiconductor layer; wherein a second oxygen concentration of the second oxide semiconductor layer is lower than a first oxygen concentration of the first oxide semiconductor layer; and a source electrode and a drain electrode forming contact with the channel layer.

[0147] In some embodiments, the channel layer is deposited by at least one of atomic layer deposition and physical vapor deposition. In some embodiments, the composition of the first oxide semiconductor layer and the composition of the third oxide semiconductor layer are the same. In some embodiments, the second oxygen concentration of the second oxide semiconductor layer is lower than the third oxygen concentration of the third oxide semiconductor layer.

[0148] Still other embodiments of the present application provide a method for forming an oxide semiconductor transistor, comprising: depositing a gate electrode; depositing a dielectric layer; depositing a channel layer, comprising: depositing a first oxide semiconductor layer having a first oxygen concentration using a physical vapor deposition process in an environment having a first flow ratio of O2 / (Ar+O2); depositing a second oxide semiconductor layer having a second oxygen concentration using a physical vapor deposition process in an environment having a second flow ratio of O2 / (Ar+O2); depositing a third oxide semiconductor layer having a third oxygen concentration using a physical vapor deposition process in an environment having a third flow ratio of O2 / (Ar+O2), wherein the second flow ratio of O2 / (Ar+O2) is lower than the first flow ratio and the third flow ratio of O2 / (Ar+O2), and wherein the second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration; and forming a source electrode and a drain electrode in contact with the channel layer.

[0149] In some embodiments, the channel layer is deposited by physical vapor deposition. In some embodiments, the method further comprises annealing the channel layer. In some embodiments, the first flow ratio and the third flow ratio of O2 / (Ar+O2) are greater than 0.05 and less than 1. In some embodiments, the second flow ratio of O2 / (Ar+O2) is greater than or equal to 0 and less than or equal to 0.05. In some embodiments, the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer include In x Ga y Zn z A composition of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, and a ratio of In:Ga:Zn:M is the same in each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer.

[0150] The features of several embodiments have been summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a substrate to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent configurations do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A transistor comprising: stacked gate electrodes stacked on top of each other and separated by a first dielectric layer; a second dielectric layer disposed along a sidewall of each of the gate electrodes; source electrode and drain electrode; as well as a channel layer having a first surface facing the second dielectric layer, a second surface opposite the first surface, and a middle portion located between the first surface and the second surface, wherein the source electrode and the drain electrode are in electrical contact with the second surface of the channel layer, a portion of the second dielectric layer is disposed between the channel layer and the sidewall of each of the gate electrodes, and the channel layer has a first carrier concentration near the second surface of the channel layer and a second carrier concentration in the middle portion of the channel layer, and the first carrier concentration is less than the second carrier concentration; Wherein, the channel layer includes: a first oxide semiconductor layer having a first oxygen concentration; a second oxide semiconductor layer having a second oxygen concentration; and a third oxide semiconductor layer having a third oxygen concentration; Wherein, the second oxide semiconductor layer is located between the first oxide semiconductor layer and the third oxide semiconductor layer; The thickness of the second oxide semiconductor layer is greater than the combined thickness of the first oxide semiconductor layer and the third oxide semiconductor layer.

2. The transistor according to claim 1, wherein The channel layer has a third carrier concentration close to the first surface of the channel layer, and the third carrier concentration is less than the second carrier concentration.

3. The transistor according to claim 2, wherein The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.

4. The transistor according to claim 3, wherein The first oxygen concentration and the third oxygen concentration are equal.

5. The transistor according to claim 3, wherein The second dielectric layer is adjacent to the first oxide semiconductor layer and is opposite to the second oxide semiconductor layer, and the gate electrode is adjacent to the second dielectric layer and is opposite to the first oxide semiconductor layer. The transistor according to claim 5 , wherein: The second dielectric layer includes a material selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium dioxide-aluminum oxide (HfO2-Al2O3), tantalum oxide (Ta2O5), SiO x / SiN y / SiO x or a group consisting of ferroelectrics.

7. The transistor according to claim 3, wherein: The first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer include In x Ga y Zn z MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, and 0<(x, y, z)<1; and The source electrode and the drain electrode include a conductive metal material.

8. The transistor according to claim 7, wherein The first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer include In x Ga y Zn z Different components of MO.

9. The transistor according to claim 1, wherein A ratio of a thickness of the second oxide semiconductor layer to a thickness of the first oxide semiconductor layer is in a range of 10:1 to 100:1, and a ratio of a thickness of the second oxide semiconductor layer to a thickness of the third oxide semiconductor layer is in a range of 10:1 to 100:

1.

10. The transistor according to claim 3, wherein The ratio of the carrier concentration in the second oxide semiconductor layer to the carrier concentration in the first oxide semiconductor layer is 1:1 to 1:

10. 9 within the range.

11. A method of forming an oxide semiconductor transistor, comprising: depositing a gate electrode; depositing a dielectric layer; Depositing the channel layer, including: Depositing a material comprising In using a physical vapor deposition process in an environment having a first flow ratio of O2 / (Ar+O2) x Ga y Zn z A first oxide semiconductor layer of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, and 0<(x, y, z)<1; Depositing the Indium using a physical vapor deposition process in an environment having a second flow ratio of O2 / (Ar+O2) x Ga y Zn z a second oxide semiconductor layer of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, wherein a composition of the second oxide semiconductor layer is different from a composition of the first oxide semiconductor layer; In an environment having a third flow ratio of O2 / (Ar+O2), a physical vapor deposition process is used to deposit a x Ga y Zn z a third oxide semiconductor layer of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, wherein a composition of the third oxide semiconductor layer is different from a composition of the second oxide semiconductor layer; wherein the second flow rate ratio of O2 / (Ar+O2) is lower than the first flow rate ratio and the third flow rate ratio of O2 / (Ar+O2), and the second oxygen concentration of the second oxide semiconductor layer is lower than the first oxygen concentration of the first oxide semiconductor layer; wherein the thickness of the second oxide semiconductor layer is greater than the combined thickness of the first oxide semiconductor layer and the third oxide semiconductor layer; and A source electrode and a drain electrode are formed in contact with the channel layer. The method of claim 11 , further comprising annealing the channel layer.

13. The method according to claim 11, wherein: The composition of the first oxide semiconductor layer and the composition of the third oxide semiconductor layer are the same.

14. The method according to claim 11, wherein The second oxygen concentration of the second oxide semiconductor layer is lower than a third oxygen concentration of the third oxide semiconductor layer.

15. A method of forming an oxide semiconductor transistor, comprising: depositing a gate electrode; depositing a dielectric layer; Depositing the channel layer, including: depositing a first oxide semiconductor layer having a first oxygen concentration using a physical vapor deposition process in an environment having a first flow ratio of O 2 / (Ar+O 2 ); depositing a second oxide semiconductor layer having a second oxygen concentration using a physical vapor deposition process in an environment having a second flow ratio of O 2 / (Ar+O 2 ); depositing a third oxide semiconductor layer having a third oxygen concentration using a physical vapor deposition process in an environment having a third flow ratio of O2 / (Ar+O2), wherein the second flow ratio of O2 / (Ar+O2) is lower than the first flow ratio and the third flow ratio of O2 / (Ar+O2), and wherein the second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration; and A source electrode and a drain electrode are formed in contact with the channel layer.

16. The method according to claim 15, wherein Depositing the channel layer is performed by physical vapor deposition. The method of claim 16 , further comprising annealing the channel layer.

18. The method according to claim 15, wherein The first flow rate ratio and the third flow rate ratio of O 2 / (Ar+O 2 ) are greater than 0.05 and less than 1.

19. The method according to claim 15, wherein The second flow rate ratio of O 2 / (Ar+O 2 ) is greater than 0 and less than or equal to 0.

05.

20. The method according to claim 15, wherein The first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer include In x Ga y Zn z A composition of MO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn, and combinations thereof, and a ratio of In:Ga:Zn:M is the same in each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer.

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