Wafer process failure prediction method, device, electronic equipment and storage medium

Abstract

The embodiment of the present invention discloses a method, device, electronic device and storage medium for predicting process failure of a wafer. The method includes determining a detection parameter matrix according to the detection parameters fed back by the process control monitoring unit; inputting the detection parameter matrix into the process failure prediction model; obtaining the prediction result matrix output by the process failure prediction model; the wafer includes a device placement area, the center of the device placement area, the vertex of the inscribed N-gon of the device placement area, and the midpoint of the line connecting the vertex and the center are reference points, and the wafer also includes multiple mask areas, and the mask area where the reference point is located is provided with a process control monitoring unit; the prediction result matrix includes multiple first elements, and the preparation process of the wafer includes multiple process steps, and different first elements are used to characterize the probability of failure in different process steps. The technical solution provided by the embodiment of the present invention can reduce the time of wafer detection and realize process failure prediction for each process step in the wafer preparation process.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular to a method, device, electronic device and storage medium for predicting process failures of a wafer. Background Art

[0002] Silicon photonic integration technology is a photonic integration technology that integrates optical waveguides, modulators, detectors, wavelength division multiplexing and other devices on a silicon substrate to achieve a deep fusion of electrical signal processing and optical signal processing. It has great innovations in chip structure and optoelectronic hybrid packaging. Silicon photonic integration technology uses indirect modulation to solve the performance bottlenecks such as power consumption and temperature drift caused by multi-channel traditional solutions. In addition, since silicon photonic integration technology integrates many optical devices, the number of optical devices that need to be assembled is greatly reduced compared to traditional optical solutions, which reduces production line links and reduces packaging and supply chain management costs. Compared with other photonic integration technologies such as indium phosphide, the most unique advantage of silicon photonic integration technology is that its processing technology is compatible with the complementary metal oxide semiconductor (CMOS) manufacturing process used in industry, which gives silicon photonic devices the hardware foundation for large-scale production and expansion.

[0003] There are nearly 100 processes in silicon photonics wafer manufacturing, and the process parameters of each process have a direct or indirect impact on the processing quality of the wafer; on the other hand, since photonic devices are more sensitive to the process than electronic devices, it is generally more difficult to manufacture silicon photonic chips that meet the requirements than traditional electronic chips. In order to control the quality of silicon photonics wafer manufacturing so that the performance of silicon photonics chips can meet certain expectations, the wafer manufacturing plant will test the manufactured silicon photonics wafers before leaving the factory and evaluate the performance of the silicon photonics wafers. If the evaluation performance of the silicon photonics wafer is very poor, it is possible that a certain process step has failed. The silicon photonics wafer manufacturing plant will troubleshoot the process steps one by one. The silicon photonics wafer detection unit, namely the process control monitor (PCM) device, is generally evenly distributed at different positions of the silicon photonics wafer. A large number of PCMs are generally required on a silicon photonics wafer. Testing and analyzing each PCM will lead to a cumbersome process troubleshooting process and generate large time and labor costs. On the other hand, there is a certain correlation between the wafer fab's process and the test results. Using algorithms to mine this relationship can improve the efficiency of wafer inspection and save time and labor costs. Summary of the invention

[0004] The present invention provides a wafer process failure prediction method, device, electronic equipment and storage medium to reduce wafer detection time and realize process failure prediction for each process step in the wafer preparation process.

[0005] In a first aspect, an embodiment of the present invention provides a method for predicting process failures of a wafer, the method comprising:

[0006] Determine a detection parameter matrix according to the detection parameters fed back by the process control monitoring unit;

[0007] Inputting the detection parameter matrix into a process failure prediction model;

[0008] Obtaining a prediction result matrix output by the process failure prediction model;

[0009] The wafer includes a device placement area, the center of the device placement area, the vertex of the inscribed N-polygon of the device placement area, and the midpoint of the line connecting the vertex and the center are reference points, the wafer also includes a plurality of mask areas, the mask area where the reference point is located is provided with the process control monitoring unit, and N is an integer greater than 3;

[0010] The prediction result matrix includes multiple first elements, the wafer preparation process includes multiple process steps, and different first elements are used to characterize the probability of failure occurring in different process steps.

[0011] In a second aspect, an embodiment of the present invention further provides a device for predicting process failures of a wafer, the device comprising:

[0012] A detection parameter matrix determination module, used to determine the detection parameter matrix according to the detection parameters fed back by the process control monitoring unit;

[0013] An input module, used for inputting the detection parameter matrix into a process fault prediction model;

[0014] A prediction result matrix acquisition module, used to acquire the prediction result matrix output by the process fault prediction model;

[0015] The wafer includes a device placement area, the center of the device placement area, the vertex of the inscribed N-polygon of the device placement area, and the midpoint of the line connecting the vertex and the center are reference points, the wafer also includes a plurality of mask areas, the mask area where the reference point is located is provided with the process control monitoring unit, and N is an integer greater than 3;

[0016] The prediction result matrix includes multiple first elements, the wafer preparation process includes multiple process steps, and different first elements are used to characterize the probability of failure occurring in different process steps.

[0017] In a third aspect, an embodiment of the present invention further provides an electronic device, the electronic device comprising:

[0018] one or more processors;

[0019] A memory for storing one or more programs;

[0020] When the one or more programs are executed by the one or more processors, the one or more processors implement the wafer process failure prediction method as described in the first aspect.

[0021] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which, when executed by a processor, implements the wafer process failure prediction method as described in the first aspect.

[0022] The process failure prediction method of the wafer provided by the embodiment of the present invention can obtain the prediction result matrix by inputting the detection parameter matrix into the process failure prediction model. Since the process control monitoring unit is set at some specific positions of the wafer instead of being evenly and densely distributed on the wafer, the area occupied by the process control monitoring unit and the corresponding detection time are reduced. In addition, since the process failure prediction model establishes a mapping relationship between the detection parameters tested by the process control monitoring unit and the process steps with problems in the wafer preparation process through deep learning technology, the process failure prediction model can be used to improve the efficiency of troubleshooting, thereby improving the efficiency of wafer manufacturing. The problem of cumbersome and high cost of wafer process failure troubleshooting in the prior art is solved, and the effect of quickly predicting the faulty process steps of the wafer is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a flow chart of a method for predicting process failure of a wafer provided by an embodiment of the present invention;

[0024] Figure 2 is a schematic structural diagram of a wafer provided by an embodiment of the present invention;

[0025] Figure 3 It is a structural schematic diagram of a photomask area in which a process control monitoring unit is set;

[0026] Figure 4 is a structural schematic diagram of a waveguide alignment test structure provided by an embodiment of the present invention;

[0027] Figure 5 is a structural schematic diagram of a waveguide width test structure provided by an embodiment of the present invention;

[0028] Figure 6 is a structural schematic diagram of a ring diameter test structure provided by an embodiment of the present invention;

[0029] Figure 7 is a structural schematic diagram of a heating resistor test structure provided by an embodiment of the present invention;

[0030] Figure 8 is a schematic diagram of the structure of the terminal resistance test structure provided by an embodiment of the present invention;

[0031] Fig. 9 is a structural schematic diagram of a modulator structure provided by an embodiment of the present invention;

[0032] Fig.10 is a schematic structural diagram of a detector structure provided by an embodiment of the present invention;

[0033] Fig.11 is a structural schematic diagram of a spiral waveguide structure provided by an embodiment of the present invention;

[0034] Fig.12 is a flow chart of another wafer process failure prediction method provided by an embodiment of the present invention;

[0035] Fig.13 It is a structural schematic diagram of a wafer process failure prediction device provided by an embodiment of the present invention;

[0036] Fig.14 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0038] Figure 1 This is a flowchart of a wafer process failure prediction method provided by an embodiment of the present invention. The method can be applied to the case where process failure prediction is performed in each process step in the wafer preparation process. Typically, the embodiment of the present application is applicable to the case where process failure prediction is performed in each process step in the silicon photonic wafer preparation process. The method can be specifically performed by a process failure prediction device, which can be implemented by software and / or hardware, and the device can be integrated in an electronic device that can implement the process failure prediction method. See Figure 1 , the wafer process failure prediction method specifically includes the following steps:

[0039] S110 . Determine a detection parameter matrix according to the detection parameters fed back by the process control monitoring unit.

[0040] Among them, the wafer includes a device placement area, the center of the device placement area, the vertex of the inscribed N-gon of the device placement area, and the midpoint of the line connecting the vertex and the center are reference points, and the wafer also includes multiple mask areas, and the mask area where the reference point is located is provided with a process control monitoring unit, and N is an integer greater than 3.

[0041] For example, Figure 2 It is a structural schematic diagram of a wafer provided by an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of the mask area where the process control and monitoring unit is set up. Figure 2 Normally, considering the poor quality of edge glue coating on the wafer and other factors, an edge exclusion area BA is usually left on the edge of the wafer. The edge exclusion area BA surrounds the device placement area QA, where devices are placed, but no devices are placed. That is, devices are placed inside the wafer, and no devices are placed within a certain distance from the edge. The wafer also includes a mask area 101, which is the area on the wafer where exposure is performed. There are two types of mask areas 101: a complete mask area that does not intersect with the edge exclusion area BA, and a partial mask area that overlaps with the edge exclusion area BA. In the device placement area QA ( Figure 3 The example shows a positive N ( Figure 3 In the figure, an N=6)-gon is exemplarily shown as the calibration shape. The intersection of the regular N-gon and the edge of the inner arc, the center of the inner arc, and the midpoint of the line connecting the center and the intersection are used as reference points 102. The mask area 101 whose center is closest to the reference point 102 is used as the area for setting the process control monitoring unit. Optionally, if the area of ​​the mask area 101 where the reference point 102 is located is smaller than the area of ​​the process control monitoring unit, a process control monitoring unit is set in a mask area 101 adjacent to the mask area 101 where the reference point 102 is located and whose area is larger than the area of ​​the process control monitoring unit; and / or; if the reference point 102 is located on the boundary of two adjacent mask areas 101, a process control monitoring unit is set in one of the two adjacent mask areas 101. In other words, if there is more than one mask area 101 closest to the reference point 102, then select the mask area 101 that is large enough to place the process control monitoring unit. If all conditions are met, then select any mask area 101 to place the process control monitoring unit. If none of the conditions are met, then select the mask area 101 that is the next closest to the reference point 102. Figure 3 The mask area 101 usually contains many bare chips and an area for placing process control and monitoring units. Figure 3 In the figure, the areas numbered 1 to 12 are the areas where the bare chips are placed, and the area numbered 13 is the area where the process control monitoring unit is placed. Figure 2 In order to clearly distinguish between the mask area 101 where the process monitoring control unit is placed and the mask area 101 where the process monitoring control unit is not placed, a grid filling pattern is used to fill the mask area 101 where the process monitoring control unit is not set, and a dot filling pattern is used to fill the mask area 101 where the process monitoring control unit is set.

[0042] It is understandable that in the prior art, a large number of process control monitoring units are usually evenly distributed on the wafer. For example, a process control monitoring unit is set in each mask area, resulting in a large demand for process control monitoring units, and the detection and analysis of each process control monitoring unit will incur a large time and labor cost. However, in this application, considering the rotational symmetry of the wafer and the characteristics of the radial distribution, placing the process control monitoring device in the above manner can better reflect the overall characteristics of the manufacturing process. The minimum number of sides N of the regular N-gon is limited by the closed figure characteristics, and the minimum value is 3. The maximum value can be set by those skilled in the art according to actual conditions, and is not limited here. For example, the maximum value can be the total number of mask areas 101 that overlap with the edge of the device placement area 11.

[0043] Specifically, the process control monitoring unit may include a variety of process control monitoring devices, which are used to test the performance of the wafer to obtain detection parameters. The detection parameters detected by each process control monitoring unit in the wafer are pre-processed and sorted into a matrix to obtain a detection parameter matrix. The number of process control monitoring devices contained in the process control monitoring unit and the specific detection content can be set by those skilled in the art according to actual conditions, and are not limited here. Exemplarily, the process control monitoring unit may include at least one of a size control structure, an electrical performance test structure, an optical performance test structure, and a photoelectric performance test structure. The specific process control monitoring device structure and its test items included in the four types of process control monitoring items are shown in Table 1 below. For example, the wafer device process monitoring unit test items may include the following nine items: waveguide alignment deviation, waveguide width, ring diameter, waveguide loss, heating film resistance, modulator terminal resistance, modulator leakage current, modulator half-wave voltage, detector dark current, and detector responsivity.

[0044] Table 1

[0045]

[0046]

[0047] For example, Figure 4 is a schematic diagram of a waveguide alignment test structure provided by an embodiment of the present invention. Figure 4 The test method of the alignment deviation is as follows: place two single-mode waveguides with a width of 0.5um and a spacing of 200um between the two single-mode waveguides, align the two single-mode waveguides to the left, and test the alignment deviation at the edges of the two single-mode waveguides. Figure 5 is a schematic diagram of a waveguide width test structure provided by an embodiment of the present invention. Figure 5 , divide a waveguide with a length of 500um and a width of 0.5um into eight equal parts, measure the width of the waveguide at the seven middle points and calculate the average value. Figure 6 Schematic diagram of a ring diameter test structure provided by an embodiment of the present invention. Figure 6 , place multiple ring waveguide arrays side by side, the waveguide width of the ring waveguide array is 0.5um, the inner diameter of the ring waveguide array is 50um, measure the inner diameter of the ring waveguide array, and calculate its average value. Figure 7 It is a structural schematic diagram of a heating resistor test structure provided in an embodiment of the present invention. Figure 8 It is a structural schematic diagram of a terminal resistance test structure provided in an embodiment of the present invention. Fig. 9 It is a structural schematic diagram of a modulator structure provided by an embodiment of the present invention. Fig.10 is a schematic diagram of the structure of the detector provided by an embodiment of the present invention. Figure 7-Figure 10 , insert the test probe TZ into the corresponding electrode plate to test its electrical properties, such as the terminal resistance of the modulator, leakage current, dark current of the detector, etc. Fig.11 is a schematic diagram of the structure of the spiral waveguide structure provided by an embodiment of the present invention. Fig.10 The spiral waveguide structure consists of two grating light ports and a spiral waveguide. The length of the spiral waveguide is set to 100um and 1mm. Two spiral waveguides with different lengths are tested. The loss of the spiral waveguide can be calculated based on the test results. Finally, the grating and modulator detector are combined into a combined structure to test the half-wave voltage of the modulator and the responsivity of the detector.

[0048] S120, inputting the detection parameter matrix into the process failure prediction model.

[0049] S130, obtaining a prediction result matrix output by the process failure prediction model.

[0050] The prediction result matrix includes multiple first elements, the wafer preparation process includes multiple process steps, and different first elements are used to characterize the probability of failure in different process steps.

[0051] Specifically, the process failure prediction model can be an artificial neural network model trained with a training set, which establishes a mapping relationship between the detection parameters tested by the process control monitoring unit and the process steps that have problems in the wafer preparation process. Therefore, by inputting the detection parameter matrix into the process failure prediction model, the prediction result matrix output by the process failure prediction model can be obtained, and the prediction result matrix contains the probability of failure of at least one process step in the wafer preparation process. It should be noted that the number of first elements and the probability of failure of each process step specifically represented by each first element can be set according to actual conditions. Optionally, the number of first elements is greater than 0 and less than or equal to the total number of process steps included in the wafer preparation process. Optionally, the prediction result matrix includes eight first elements, and the eight first elements respectively represent the probability of failure of the following process steps: etching of silicon waveguide, modulator ion implantation, germanium detector silicon material ion implantation, detector germanium epitaxial growth, detector germanium material ion implantation, heating film growth, through hole setting, and metal layer formation.

[0052] It is understandable that the application of the process failure prediction model to the process failure test of new wafers can quickly predict the probability of failure in each process step of the wafer. Compared with the method of evenly placing various process control monitoring devices on the wafer and testing them, and checking and troubleshooting the process steps one by one in the related art, the artificial neural network model using the mapping relationship can greatly shorten the detection time. And the use of the artificial neural network model is of great significance in understanding the processing status of the same batch of wafers and the maintenance and improvement of process parameters.

[0053] The process failure prediction method of the wafer provided by the embodiment of the present invention can obtain the prediction result matrix by inputting the detection parameter matrix into the process failure prediction model. Since the process control monitoring unit is set at some specific positions of the wafer instead of being evenly and densely distributed on the wafer, the area occupied by the process control monitoring unit and the corresponding detection time are reduced. In addition, since the process failure prediction model establishes a mapping relationship between the detection parameters tested by the process control monitoring unit and the process steps with problems in the wafer preparation process through deep learning technology, the process failure prediction model can be used to improve the efficiency of troubleshooting, thereby improving the efficiency of wafer manufacturing. The problem of cumbersome and high cost of wafer process failure troubleshooting in the prior art is solved, and the effect of quickly predicting the faulty process steps of the wafer is achieved.

[0054] Based on the above technical solution, optionally, the prediction result matrix also includes a second element, which is used to characterize the manufacturing quality of the wafer; and / or; the prediction result matrix also includes a third element, which is used to characterize whether a fault occurs during the preparation process of the wafer.

[0055] Specifically, the specific value of the second element can be between 0 and 1, and the larger the value, the better the manufacturing quality of the wafer. The third element indicates whether there is a fault in any process step during the entire wafer preparation process. Optionally, if the third element is less than or equal to 0.5, the third element is set to 0; if the third element is greater than 0.5, the third element is set to 1, where 1 indicates a fault and 0 indicates no fault.

[0056] It can be understood that by setting the prediction result matrix to also include the second element and the third element, it is also possible to quickly predict the manufacturing quality of the devices processed by the wafer and whether there are any faults in the entire preparation process of the wafer, thereby enriching the prediction information about wafer processing and enabling a more comprehensive prediction of the performance of the processed wafer.

[0057] Fig.12 1 is a flow chart of another wafer process failure prediction method provided by an embodiment of the present invention. The present embodiment is a further optimization of the above embodiment. For details not described in detail in the present embodiment, please refer to the above embodiment. Fig.12 The wafer process failure prediction method may specifically include the following steps:

[0058] S210, obtaining a detection parameter matrix and a detection result matrix corresponding to a plurality of sample wafers as training samples.

[0059] The detection result matrix includes multiple fourth elements, and different fourth elements are used to characterize failures occurring in different process steps.

[0060] Optionally, S210 specifically includes: S121, acquiring detection parameters fed back by a process control monitoring unit on each sample wafer.

[0061] S122 . Determine an intermediate detection parameter matrix for each sample wafer according to the detection parameters.

[0062] Specifically, for each sample wafer, the detection parameters fed back by each process control monitoring device on it are obtained; all detection parameters corresponding to the same sample wafer are sorted in a two-dimensional matrix to determine the intermediate detection parameter matrix. Specifically, (2N+1) process control monitoring units are set on each sample wafer, and each process control monitoring unit includes M process control monitoring devices, so the intermediate detection parameter matrix is ​​an M×(2N+1) two-dimensional matrix.

[0063] For example, Figure 2 As shown, 13 process control monitoring units are arranged on the sample wafer, each process control monitoring unit includes 9 process monitoring control devices, and the intermediate detection parameter matrix is ​​a 9×13 two-dimensional matrix.

[0064] S123. Normalize the multiple intermediate detection parameter matrices to obtain multiple detection parameter matrices.

[0065] Specifically, S123 specifically includes: calculating the average value P of all elements in all intermediate detection parameter matrices in the training set; subtracting the average value P from each element in each intermediate detection parameter matrix, calculating the variance of all elements in all intermediate detection parameter matrices, and taking the square root of the variance to obtain S; dividing each element in all intermediate detection parameter matrices by S to obtain multiple detection parameter matrices.

[0066] It can be understood that normalizing the intermediate detection parameter matrix to obtain the detection parameter matrix can prevent the artificial neural network algorithm from falling into a local solution and is conducive to the convergence of the network training, so as to improve the training efficiency of the process fault prediction model.

[0067] S124 . Determine a test result matrix of each sample wafer according to the test results of each sample wafer.

[0068] Specifically, for each sample wafer, at least one process step in its preparation process is detected to see if there is a fault, and a detection result is obtained. All detection results corresponding to the same sample wafer are organized in a one-dimensional matrix to determine a detection result matrix.

[0069] Specifically, the detection result matrix includes multiple fourth elements, and different fourth elements are used to characterize the occurrence of failures in different process steps. If a process step is detected to have a failure, the fourth element corresponding to the process step is set to 1; if a process step is detected to have no failure, the fourth element corresponding to the process step is set to 0. Optionally, the detection result matrix also includes a fifth element, which is used to characterize the manufacturing quality of the wafer; and / or; the detection result matrix also includes a sixth element, which is used to characterize whether a failure occurs during the preparation process of the wafer.

[0070] Exemplarily, after the wafer production is completed, the eight process steps of silicon waveguide etching, modulator ion implantation, germanium detector silicon material ion implantation, detector germanium epitaxial growth, detector germanium material ion implantation, heating film growth, through hole setting, and metal layer formation are detected for failures. In addition, the manufacturing quality of the wafer and whether any failures occur in the wafer preparation process are detected, and a one-dimensional matrix of 1×10 detection results can be obtained.

[0071] S125. Use multiple detection parameter matrices and multiple detection result matrices as training samples.

[0072] Specifically, testing a sample wafer can obtain a two-dimensional matrix of M×(2N+1) (for example, 9×13) and a corresponding one-dimensional matrix of 1×C (for example, 1×10). The correspondence between these two matrices represents the mapping relationship between the detection parameters tested by the process control monitoring unit and whether certain process steps in the sample wafer preparation process have failed. If the data of Z sample wafers are collected, there are Z two-dimensional matrices of M×(2N+1) and Z corresponding one-dimensional matrices of 1×C. These Z wafer samples are used as training samples.

[0073] It should be noted that the number of sample wafers can be set by those skilled in the art according to actual conditions, and is not limited here. It should also be noted that, for the sample wafer, the setting mode of the monitoring control unit, the number M of process control monitoring devices and the specific detection content are the same as the setting mode when predicting wafer process failures, and will not be repeated here. In addition, the detection result matrix corresponds to the prediction result matrix, that is, the multiple fourth elements in the detection result matrix represent the situation where certain process steps on the sample wafer fail, and the corresponding multiple first elements in the prediction result matrix represent the probability of failure of these process steps on the newly produced wafer.

[0074] S220 , inputting the detection parameter matrix into the process fault prediction model to be trained.

[0075] Specifically, the specific architecture of the artificial neural network included in the process fault prediction model can be set by those skilled in the art according to actual conditions, which is not limited here. In addition, the network parameters of the process fault prediction model can be randomly initialized, which is also not limited here.

[0076] S230, obtaining a prediction result matrix output by the process fault prediction model to be trained.

[0077] S240: Determine whether the matching degree between the prediction result matrix and the detection result matrix reaches a preset degree.

[0078] Specifically, the specific implementation of S240 can be set by those skilled in the art according to actual conditions, and is not limited here. Optionally, S240 specifically includes:

[0079] S241. Normalize the first element in the prediction result matrix.

[0080] Specifically, the specific process of normalizing the first element in the prediction result matrix is ​​as follows: Among them, Z j is the jth first element in the i-th prediction result matrix; d is the number of first elements in the prediction result matrix. In this way, the specific value of the first element can be between 0 and 1.

[0081] Optionally, the prediction result matrix also includes a third element, and the third element is used to characterize whether a fault occurs during the preparation of the wafer; after obtaining the prediction result matrix output by the process fault prediction model to be trained, it also includes: if the third element is less than or equal to 0.5, then the value of the third element is set to 0; if the third element is greater than 0.5, then the value of the third element is set to 1. It can be understood that in the actual production process, there are two results for whether a fault occurs during the preparation of the wafer, a fault occurs and no fault occurs. Therefore, if the third element is less than or equal to 0.5, then the value of the third element is set to 0, and if the third element is greater than 0.5, then the value of the third element is set to 1, which is conducive to accurately judging the degree of approximation of the prediction result matrix and the detection result matrix in the process of training the process fault prediction model, and improving the training efficiency of the process fault prediction model.

[0082] Exemplarily, if the intermediate detection parameter matrix is ​​a 9×13 two-dimensional matrix, then the detection parameter matrix is ​​also a 9×13 two-dimensional matrix. After the detection parameter matrix is ​​input into the process fault prediction model to be trained, a 1×10 one-dimensional prediction result matrix can be obtained. After the prediction result matrix directly output by the process fault prediction model is normalized, and the second element and the third element are processed as above, the first element to the eighth element in the prediction result matrix respectively represent the probability of failure of the eight process steps of silicon waveguide etching, modulator ion implantation, germanium detector silicon material ion implantation, detector germanium epitaxial growth, detector germanium material ion implantation, heating film growth, through hole setting, and metal layer formation, and the value is between 0 and 1. The ninth element (i.e., the second element) in the prediction result matrix represents the manufacturing quality of the wafer, and the value is between 0 and 1. The larger the value, the better the quality of wafer manufacturing. The tenth element (i.e., the third element) in the prediction result matrix indicates whether there is a process step failure in the wafer preparation process, and the value is 1 or 0, 1 indicates a failure, and 0 indicates no failure. If the third element in the prediction result matrix is ​​less than or equal to 0.5, the value of the third element is set to 0; if the third element is greater than 0.5, the value of the third element is set to 1.

[0083] S242, calculating the objective function value according to the objective function;

[0084] S243: Determine whether the objective function value is less than a preset threshold.

[0085] S244: If yes, the matching degree between the prediction result matrix and the detection result matrix reaches a preset degree;

[0086] Among them, the objective function is:

[0087] m is the number of training samples, C is the number of elements in the prediction result matrix, Y ij is the jth element in the prediction result matrix of the i-th training sample, X ij is the jth element in the detection result matrix of the i-th training sample.

[0088] It can be understood that the above method is used to determine whether the matching degree between the prediction result matrix and the detection result matrix reaches a preset degree, which is simple and fast and is conducive to the efficient training of the process fault prediction model.

[0089] S250: If yes, the process fault prediction model training is completed.

[0090] Specifically, for the sample wafer, the detection result matrix is ​​obtained by actually testing the sample wafer, and the prediction result matrix is ​​the output of the process failure prediction model, which contains the prediction results of the process steps that have problems in the preparation of the sample wafer. When the matching degree between the prediction result matrix and the detection result matrix reaches a preset degree, it indicates that the prediction is very close to the actual detection situation and the prediction accuracy is high. At this point, the process failure prediction model training is completed and can be used to predict process failures for newly produced wafers.

[0091] Optionally, if the degree of matching between the prediction result matrix and the detection result matrix does not reach a preset value, the network parameters of the process fault prediction model to be trained are updated, and the process returns to input the normalized detection parameter matrix into the process fault prediction model to be trained until the degree of matching between the prediction result matrix and the detection result matrix reaches a preset value.

[0092] Exemplarily, after calculating the objective function Q, it is compared with the set threshold: if Q is less than the set threshold, the process fault prediction model is trained; if Q is greater than the set threshold, the gradient of the objective function Q is calculated and the network parameters of the process fault prediction model are updated using the gradient descent algorithm, and the objective function Q is recalculated. When the objective function Q is less than the threshold or the number of training times reaches the set number of iterations, the training of the process fault prediction model is terminated. If the number of training times of the process fault prediction model reaches the set number of iterations, then the training of the process fault prediction model is likely to be "insufficient", and it is necessary to define a new artificial neural network of the process fault prediction model by changing the network architecture of the process fault prediction model, the number of network layers, introducing a regularization algorithm, etc., and train the new process fault prediction model until the objective function Q of the new process fault prediction model is less than the set threshold.

[0093] S260 . Determine a detection parameter matrix according to the detection parameters fed back by the process control monitoring unit.

[0094] Optionally, S260 specifically includes: S261, obtaining the detection parameters fed back by each process control monitoring device; S262, determining the intermediate detection parameter matrix according to the detection parameters; S263, normalizing the detection parameter matrix to obtain the detection parameter matrix. The process control monitoring unit includes M process control monitoring devices, and the intermediate detection parameter matrix and the detection parameter matrix are two-dimensional matrices of M×(2N+1).

[0095] Specifically, the process control monitoring unit includes M process control monitoring devices. Since (2N+1) process control monitoring units are arranged in the wafer, the process control monitoring device on a wafer can feedback M×(2N+1) detection parameters. By directly writing them into a two-dimensional matrix of M×(2N+1), an intermediate detection parameter matrix can be obtained. The intermediate detection parameter matrix is ​​normalized as follows: the average value P is subtracted from each element in the intermediate detection parameter matrix; and then each element is divided by S to obtain the detection parameter matrix; wherein the average values ​​P and S are the average values ​​P and S calculated in S213.

[0096] S280, inputting the detection parameter matrix into the process failure prediction model.

[0097] S290. Obtain a prediction result matrix output by the process failure prediction model.

[0098] The wafer process failure prediction method provided by the embodiment of the present invention first trains the process failure prediction model before predicting the process failure of a new wafer, so that the prediction result matrix output by the process failure prediction model can accurately predict the probability of failure in each process step. In addition, the detection parameter matrix is ​​first normalized before being input into the process failure prediction model to be trained, which can avoid the artificial neural network algorithm from falling into a local solution and is conducive to the convergence of the network training, thereby improving the training efficiency of the process failure prediction model.

[0099] Fig.13 The present invention provides a schematic diagram of a wafer process failure prediction device. The device can be used to predict process failures in various process steps during wafer preparation. Typically, the present invention is used to predict process failures in various process steps during silicon photonic wafer preparation. The device can be implemented in software and / or hardware, and can be integrated in electronic devices. Fig.13 , the device specifically comprises:

[0100] A detection parameter matrix determination module 110, used to determine a detection parameter matrix according to the detection parameters fed back by the process control monitoring unit;

[0101] A first input module 120, for inputting the detection parameter matrix into the process fault prediction model;

[0102] A first prediction result matrix acquisition module 130, used to acquire a prediction result matrix output by a process fault prediction model;

[0103] The wafer includes a device placement area, the center of the device placement area, the vertex of the inscribed N-polygon of the device placement area, and the midpoint of the line connecting the vertex and the center are reference points, the wafer also includes multiple mask areas, and the mask area where the reference point is located is provided with a process control monitoring unit, and N is an integer greater than 3;

[0104] The prediction result matrix includes multiple first elements, the wafer preparation process includes multiple process steps, and different first elements are used to characterize the probability of failure in different process steps.

[0105] Based on the above technical solution, optionally, the prediction result matrix further includes a second element, and the second element is used to characterize the manufacturing quality of the wafer; and / or;

[0106] The prediction result matrix also includes a third element, and the third element is used to characterize whether a failure occurs during the preparation process of the wafer.

[0107] Optionally, the device further includes: a training sample acquisition module, which is used to acquire detection parameter matrices and detection result matrices corresponding to a plurality of sample wafers as training samples before inputting the detection parameter matrix into the process fault prediction model;

[0108] A second input module, used for inputting the detection parameter matrix into the process fault prediction model to be trained;

[0109] A second prediction result matrix acquisition module, used to acquire the prediction result matrix output by the process fault prediction model to be trained;

[0110] A judgment module is used to judge whether the matching degree between the prediction result matrix and the detection result matrix reaches a preset degree;

[0111] The training completion determination module is used to determine that the training of the process fault prediction model is completed when the matching degree between the prediction result matrix and the detection result matrix reaches a preset degree; wherein the detection result matrix includes multiple fourth elements, and different fourth elements are used to characterize the situations in which faults occur in different process steps.

[0112] Optionally, the training sample acquisition module includes: a detection parameter acquisition unit, used to obtain the detection parameters fed back by the process control monitoring unit on each sample wafer;

[0113] An intermediate detection parameter matrix determination unit, used to determine the intermediate detection parameter matrix of each sample wafer according to the detection parameters;

[0114] A first normalization processing unit, used for normalizing a plurality of intermediate detection parameter matrices to obtain a plurality of detection parameter matrices;

[0115] A detection result matrix determination unit, used to determine the detection result matrix of each sample wafer according to the detection result of each sample wafer;

[0116] The training sample acquisition unit is used to use multiple detection parameter matrices and multiple detection result matrices as training samples.

[0117] Optionally, the prediction result matrix also includes a third element, which is used to characterize whether a fault occurs in the wafer preparation process; the device also includes: a third element redetermination module, which is used to, after obtaining the prediction result matrix output by the process fault prediction model to be trained, set the value of the third element to 0 when the third element is less than or equal to 0.5; and set the value of the third element to 1 when the third element is greater than 0.5.

[0118] Optionally, the judgment module is specifically used to normalize the first element in the prediction result matrix; calculate the objective function value according to the objective function; and judge whether the objective function value is less than a preset threshold; if so, the matching degree between the prediction result matrix and the detection result matrix reaches a preset degree; wherein the objective function is:

[0119] Among them, m is the number of training samples, C is the number of elements in the prediction result matrix, and Y ij is the jth element in the prediction result matrix of the i-th training sample, X ij is the jth element in the detection result matrix of the i-th training sample.

[0120] Optionally, if the area of ​​the mask region where the reference point is located is smaller than the area of ​​the process control monitoring unit, a process control monitoring unit is provided in a mask region adjacent to the mask region where the reference point is located and having an area larger than the area of ​​the process control monitoring unit; and / or;

[0121] If the reference point is located on the boundary between two adjacent mask areas, a process control monitoring unit is disposed in one of the two adjacent mask areas.

[0122] The process fault prediction device provided in the embodiment of the present invention can execute the process fault prediction method provided in any embodiment of the present application, and has the corresponding functional modules and beneficial effects of the execution method. It will not be described here in detail, and can be understood by referring to the above text.

[0123] Fig.14 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Fig.14 A block diagram of an exemplary electronic device 212 suitable for implementing embodiments of the present application is shown. Fig.14The electronic device 212 shown is merely an example and should not limit the functionality and scope of use of the embodiments of the present application.

[0124] like Fig.14 As shown, the electronic device 212 may include: one or more processors 216; a memory 228, which is used to store one or more programs. When the one or more programs are executed by the one or more processors 216, the one or more processors 216 implement the process fault prediction method provided in the embodiment of the present application, including:

[0125] Determine a detection parameter matrix according to the detection parameters fed back by the process control monitoring unit;

[0126] Inputting the detection parameter matrix into a process failure prediction model;

[0127] Obtaining a prediction result matrix output by the process failure prediction model;

[0128] The wafer includes a device placement area, the center of the device placement area, the vertex of the inscribed N-polygon of the device placement area, and the midpoint of the line connecting the vertex and the center are reference points, the wafer also includes a plurality of mask areas, the mask area where the reference point is located is provided with the process control monitoring unit, and N is an integer greater than 3;

[0129] The prediction result matrix includes multiple first elements, the wafer preparation process includes multiple process steps, and different first elements are used to characterize the probability of failure occurring in different process steps.

[0130] Components of the electronic device 212 may include, but are not limited to, one or more processors 216 , a memory 228 , and a bus 218 that connects the various device components (including the memory 228 and the processor 216 ).

[0131] Bus 218 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor or a local bus using any of a variety of bus architectures. For example, these architectures include but are not limited to Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Processor ISA bus, Video Electronics Standards Association (VESA) local bus and Peripheral Component Interconnect (PCI) bus.

[0132] The electronic device 212 typically includes a variety of computer device readable storage media. These storage media can be any available storage media that can be accessed by the electronic device 212, including volatile and non-volatile storage media, removable and non-removable storage media.

[0133] The memory 228 may include computer device readable storage media in the form of volatile memory, such as random access memory (RAM) 230 and / or cache memory 232. The electronic device 212 may further include other removable / non-removable, volatile / non-volatile computer device storage media. By way of example only, the storage system 234 may be used to read and write non-removable, non-volatile magnetic storage media ( Fig.14 not shown, usually called a "hard drive"). Although Fig.14 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical storage medium) may be provided. In these cases, each drive may be connected to bus 218 via one or more data storage medium interfaces. Memory 228 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present application.

[0134] A program / utility 240 having a set (at least one) of program modules 242 may be stored, for example, in the memory 228, such program modules 242 including, but not limited to, operating devices, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 242 generally perform the functions and / or methods of the embodiments described herein.

[0135] The electronic device 212 may also communicate with one or more external devices 214 and / or a display 224, and may also communicate with one or more devices that enable a user to interact with the electronic device 212, and / or communicate with any device that enables the electronic device 212 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). Such communication may be performed via an input / output (I / O) interface 222. Furthermore, the electronic device 212 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 228. Fig.14 As shown, the network adapter 228 communicates with other modules of the electronic device 212 via the bus 218. It should be understood that although Fig.14Not shown, other hardware and / or software modules may be used in conjunction with the electronic device 212, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID devices, tape drives, and data backup storage devices. The processor 216 executes at least one of the other programs in the plurality of programs stored in the memory 228 to perform various functional applications and data processing, such as implementing a process failure prediction method provided in an embodiment of the present application.

[0136] An embodiment of the present invention provides a storage medium containing computer executable instructions, wherein the computer executable instructions are used to perform a process fault prediction and analysis method when executed by a computer processor, including:

[0137] Determine a detection parameter matrix according to the detection parameters fed back by the process control monitoring unit;

[0138] Inputting the detection parameter matrix into a process failure prediction model;

[0139] Obtaining a prediction result matrix output by the process failure prediction model;

[0140] The wafer includes a device placement area, the center of the device placement area, the vertex of the inscribed N-polygon of the device placement area, and the midpoint of the line connecting the vertex and the center are reference points, the wafer also includes a plurality of mask areas, the mask area where the reference point is located is provided with the process control monitoring unit, and N is an integer greater than 3;

[0141] The prediction result matrix includes multiple first elements, the wafer preparation process includes multiple process steps, and different first elements are used to characterize the probability of failure occurring in different process steps.

[0142] The computer storage medium of the embodiment of the present invention may adopt any combination of one or more computer-readable storage media. The computer-readable storage medium may be a computer-readable signal storage medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor device, apparatus or device, or any combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In an embodiment of the present application, a computer-readable storage medium may be any tangible storage medium containing or storing a program, which may be used by or in combination with an instruction execution device, apparatus or device.

[0143] A computer-readable signal storage medium may include a data signal propagated in baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal storage medium may also be any computer-readable storage medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution device, apparatus, or device.

[0144] The program code contained on the computer-readable storage medium may be transmitted using any appropriate storage medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0145] Computer program code for performing the operation of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or device. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., using an Internet service provider to connect through the Internet).

[0146] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for predicting process failure of a wafer, characterized in that: include: Determine a detection parameter matrix according to the detection parameters fed back by the process control monitoring unit; Inputting the detection parameter matrix into a process failure prediction model; Obtaining a prediction result matrix output by the process failure prediction model; The wafer includes a device placement area, the center of the device placement area, the vertex of the inscribed N-polygon of the device placement area, and the midpoint of the line connecting the vertex and the center are reference points, the wafer also includes a plurality of mask areas, the mask area where the reference point is located is provided with the process control monitoring unit, and N is an integer greater than 3; The prediction result matrix includes multiple first elements, the wafer preparation process includes multiple process steps, and different first elements are used to characterize the probability of failure occurring in different process steps.

2. The wafer process failure prediction method according to claim 1, characterized in that: The prediction result matrix further includes a second element, and the second element is used to characterize the manufacturing quality of the wafer; and / or; The prediction result matrix also includes a third element, and the third element is used to characterize whether a failure occurs during the preparation process of the wafer.

3. The wafer process failure prediction method according to claim 1, characterized in that: Before inputting the detection parameter matrix into the process failure prediction model, the following step is also included: Obtaining the detection parameter matrix and the detection result matrix corresponding to a plurality of sample wafers as training samples; Inputting the detection parameter matrix into the process fault prediction model to be trained; Obtaining the prediction result matrix output by the process fault prediction model to be trained; Determining whether the matching degree between the prediction result matrix and the detection result matrix reaches a preset degree; If yes, the process fault prediction model training is completed; The detection result matrix includes multiple fourth elements, and different fourth elements are used to characterize failures occurring in different process steps.

4. The wafer process failure prediction method according to claim 3, characterized in that: The obtaining of the detection parameter matrix and the detection result matrix corresponding to the plurality of sample wafers as training samples includes: Acquiring the detection parameters fed back by the process control monitoring unit on each of the sample wafers; Determine an intermediate detection parameter matrix of each of the sample wafers according to the detection parameters; Normalizing the plurality of intermediate detection parameter matrices to obtain a plurality of detection parameter matrices; Determine a test result matrix of each of the sample wafers according to the test results of each of the sample wafers; A plurality of the detection parameter matrices and a plurality of the detection result matrices are used as training samples.

5. The wafer process failure prediction method according to claim 3, characterized in that: The prediction result matrix also includes a third element, and the third element is used to characterize whether a fault occurs during the preparation process of the wafer; After obtaining the prediction result matrix output by the process fault prediction model to be trained, the method further includes: If the third element is less than or equal to 0.5, then the value of the third element is set to 0; If the third element is greater than 0.5, the value of the third element is set equal to 1.

6. The wafer process failure prediction method according to claim 5, characterized in that: The determining whether the matching degree between the prediction result matrix and the detection result matrix reaches a preset value includes: Normalizing the first element in the prediction result matrix; Calculate the objective function value according to the objective function; Determine whether the objective function value is less than a preset threshold; If so, the matching degree between the prediction result matrix and the detection result matrix reaches a preset degree; Wherein, the objective function is: m is the number of training samples, C is the number of elements in the prediction result matrix, Y ij is the jth element in the prediction result matrix of the i-th training sample, X ij is the jth element in the detection result matrix of the i-th training sample.

7. The wafer process failure prediction method according to claim 1, characterized in that: If the area of ​​the mask area where the reference point is located is smaller than the area of ​​the process control monitoring unit, the process control monitoring unit is set in the mask area adjacent to the mask area where the reference point is located and whose area is larger than the area of ​​the process control monitoring unit; and / or; If the reference point is located on a boundary between two adjacent mask areas, the process control monitoring unit is disposed in one of the two adjacent mask areas.

8. A wafer process failure prediction device, characterized in that: include: A detection parameter matrix determination module, used to determine the detection parameter matrix according to the detection parameters fed back by the process control monitoring unit; An input module, used for inputting the detection parameter matrix into a process fault prediction model; A prediction result matrix acquisition module, used to acquire the prediction result matrix output by the process fault prediction model; The wafer includes a device placement area, the center of the device placement area, the vertex of the inscribed N-polygon of the device placement area, and the midpoint of the line connecting the vertex and the center are reference points, the wafer also includes a plurality of mask areas, the mask area where the reference point is located is provided with the process control monitoring unit, and N is an integer greater than 3; The prediction result matrix includes multiple first elements, the wafer preparation process includes multiple process steps, and different first elements are used to characterize the probability of failure occurring in different process steps.

9. An electronic device, characterized in that: The electronic device comprises: one or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the process failure prediction method for a wafer as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the process failure prediction method for a wafer as described in any one of claims 1 to 7 is implemented.

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