Static random access memory device and manufacturing method thereof

Abstract

The present invention discloses a static random access memory element and a manufacturing method thereof, wherein the static random access memory element includes a substrate, a first transistor, a second transistor, a metal interconnect structure and a capacitor. The metal interconnect structure is formed on the first and second transistors, and the capacitor is arranged in the metal interconnect structure and coupled between the first transistor and the second transistor. The capacitor includes a lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer and an upper metal layer from bottom to top. The lower metal layer couples the source node of the first transistor and the source node of the second transistor. The lower metal layer and the metal layer of the nth layer in the metal interconnect structure are formed by the same layer of material, where n≥1; the upper metal layer and the metal layer of the mth layer in the metal interconnect structure are formed by the same layer of material, where m≥n+1.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory, and in particular to a static random access memory element and a manufacturing method thereof. Background Art

[0002] Static random access memory (SRAM) is a volatile semiconductor memory device. Currently, a memory element is developed that is coupled with two transistors and a capacitor. In this memory element, a capacitor is used as a storage component. Therefore, how to increase the capacitance of the capacitor to improve the electrical performance of the memory element is a goal that the industry continues to work hard on. Summary of the invention

[0003] The invention provides a static random access memory element, which can greatly increase the capacitance of a capacitor.

[0004] The invention also provides a method for manufacturing a static random access memory element, which can manufacture a static random access memory element with high capacitance without adding additional photomasks and manufacturing processes.

[0005] A static random access memory element of the present invention comprises a substrate, a first transistor, a second transistor, a metal interconnect structure and a capacitor. The first transistor is formed on the substrate, and the first transistor comprises a first gate, a first source node and a first drain node. The second transistor is also formed on the substrate, and the second transistor comprises a second gate, a second source node and a second drain node. The metal interconnect structure is formed on the first and second transistors, wherein the metal interconnect structure comprises multiple metal layers, multiple interlayer dielectric (ILD) layers and multiple vias connecting different metal layers. The capacitor is arranged in the metal interconnect structure and coupled between the first transistor and the second transistor. The capacitor comprises a lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer and an upper metal layer. The lower metal layer couples the first source node and the second source node, and the lower metal layer and the metal layer of the nth layer in the metal interconnect structure are formed of the same layer of material, wherein n≥1. The upper metal layer is arranged on the lower metal layer, and the upper metal layer and the metal layer of the mth layer in the metal interconnect structure are formed of the same layer of material, wherein m≥n+1. The first electrode layer is arranged between the lower metal layer and the upper metal layer, the second electrode layer is arranged between the upper metal layer and the first electrode layer, and the dielectric layer is arranged between the first electrode layer and the second electrode layer.

[0006] In an embodiment of the present invention, the static random access memory device may further include a plurality of word lines (WL) respectively coupled to the first gate and the second gate, wherein the word lines and the lower metal layer are formed of the same material.

[0007] In an embodiment of the present invention, an extension direction of the word line is the same as an extension direction of the first gate, and an extension direction of the word line is the same as an extension direction of the second gate.

[0008] In one embodiment of the present invention, the metal interconnect structure has an opening, and the capacitor is formed in the opening.

[0009] In one embodiment of the present invention, the first electrode layer is formed on the surface of the opening, the dielectric layer is formed on the surface of the first electrode layer, and the second electrode layer fills the opening and covers the dielectric layer.

[0010] In one embodiment of the present invention, the capacitor further has an extension portion extending beyond the opening.

[0011] In one embodiment of the present invention, the thickness of the upper metal layer is thinner than the thickness of the m-th metal layer.

[0012] In an embodiment of the present invention, the first transistor and the second transistor are respectively one and the other of an N-type metal oxide semiconductor transistor and a P-type metal oxide semiconductor transistor.

[0013] A method for manufacturing a static random access memory element of the present invention includes providing a substrate, and then forming a first transistor and a second transistor, wherein the first transistor includes a first gate, a first source node, and a first drain node, and the second transistor includes a second gate, a second source node, and a second drain node. An inner dielectric layer covering the first and second transistors is formed, and a plurality of contact windows coupling the first source node and the second source node are formed in the inner dielectric layer. A metal interconnect structure is formed on the inner dielectric layer, wherein the metal interconnect structure includes multiple metal layers, multiple interlayer dielectric (ILD) layers, and multiple vias connecting different metal layers, and a portion of the metal layer of the nth layer is a lower metal layer, wherein n≥1. An opening is formed in the metal interconnect structure, and the bottom of the opening exposes the lower metal layer. Then, a capacitor is formed in the opening, wherein the capacitor includes a lower metal layer, a first electrode layer formed on the surface of the opening, a dielectric layer formed on the surface of the first electrode layer, a second electrode layer filling the opening and covering the dielectric layer, and an upper metal layer formed on the surface of the second electrode layer, wherein the upper metal layer is a part of the mth metal layer, where m≥n+1.

[0014] In another embodiment of the present invention, the step of forming the above-mentioned opening includes forming a multi-layer mask layer above the metal interconnect structure, forming a patterned photoresist layer on the multi-layer mask layer, wherein the patterned photoresist layer has a pattern aligned with the lower metal layer. Then, using the patterned photoresist layer as a mask, the pattern is transferred to the multi-layer mask layer, and then using the multi-layer mask layer as a mask, the pattern is transferred to the metal interconnect structure. Thereafter, the patterned photoresist layer and the multi-layer mask layer are removed.

[0015] In another embodiment of the present invention, the method of forming the first electrode layer comprises metal organic vapor deposition (MOCVD).

[0016] In another embodiment of the present invention, a method of forming the second electrode layer includes supercritical fluid deposition (SFD), physical vapor deposition (PVD) or a combination thereof.

[0017] In another embodiment of the present invention, the step of forming the above-mentioned capacitor includes sequentially depositing the first electrode layer, the dielectric layer and the second electrode layer on the metal interconnect structure and the lower metal layer, patterning the above-mentioned layers, and then forming the upper metal layer on the second electrode layer.

[0018] In another embodiment of the present invention, the step of patterning the second electrode layer, the dielectric layer and the first electrode layer includes retaining a portion of the second electrode layer, a portion of the dielectric layer and a portion of the first electrode layer outside the opening to form an extension portion of the capacitor.

[0019] In various embodiments of the present invention, the material of the dielectric layer includes a high dielectric constant material.

[0020] Based on the above, the capacitor of the present invention is formed in the metal interconnect structure, so its height is the same as the total thickness of at least one metal layer and at least one dielectric window in the metal interconnect structure, so it has a much larger surface area than the conventional capacitor formed on the substrate with a thickness close to the inner dielectric layer, thereby increasing the capacitance. In addition, since the coupling between the capacitor and the transistor is through the lower metal layer, the manufacturing process conditions of the present invention are more relaxed compared to the conventional capacitor manufacturing process that directly contacts the source node, and can be integrated into the existing 2-transistor-static random-access memory (2T-SRAM) manufacturing process. In addition, because the position of the capacitor is moved to the metal interconnect structure, there is space to set the metal word line connected to the gate, thereby reducing the impedance and avoiding the problem of shifting the gate power supply capacity.

[0021] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a cross-sectional schematic diagram of a static random access memory element according to a first embodiment of the present invention;

[0023] Figure 2A and Figure 2B They are cross-sectional schematic diagrams of two examples of the static random access memory device of the first embodiment;

[0024] Figures 3A to 3G It is a schematic diagram of a manufacturing process of a static random access memory element according to the second embodiment of the present invention.

[0025] Explanation of symbols

[0026] 100, 300: base

[0027] 102, 302: first transistor

[0028] 104, 304: second transistor

[0029] 106, 324: Metal interconnect structure

[0030] 106a, 344: Opening

[0031] 108, 354: Capacitor

[0032] 108a, 354a: extension

[0033] 110, 306a: first gate

[0034] 112, 308a: first drain node

[0035] 114, 308b: first source node

[0036] 116, 130, 316a, 316b: LDD area

[0037] 118, 312: gate dielectric layer

[0038] 120, 314: gap wall

[0039] 122, 318: Component isolation structure

[0040] 124, 306b: second gate

[0041] 126, 310a: second source node

[0042] 128, 310b: second drain node

[0043] 132 1～4 , 132 N ,326 1～3 ,326 N :Metal layer

[0044] 134 1～4 , 134 N ,328 1～3 ,328 N :ILD layer

[0045] 136 1～3 , 136 N ,330 1～2 ,330 N :Interlayer Window

[0046] 140 1～4 ,334 1～3 :Middle layer

[0047] 142, 320: Inner dielectric layer

[0048] 144, 322: Contact window

[0049] 146, 200, 332: Lower metal layer

[0050] 148, 346: first electrode layer

[0051] 150, 348: Dielectric layer

[0052] 152, 350: second electrode layer

[0053] 154, 202, 352: upper metal layer

[0054] 156, 336: Character line

[0055] 338:Multi-layer mask layer

[0056] 340a:SiCN layer

[0057] 340b: SiCO layer

[0058] 340c: Amorphous carbon layer

[0059] 340d: MLR SiON layer

[0060] 342: Patterned photoresist layer

[0061] t1, t2: thickness

[0062] w1, w2: width DETAILED DESCRIPTION

[0063] Some embodiments are listed below and described in detail with the accompanying drawings, but the embodiments provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn according to the original size. For example, the thickness of each layer is not drawn according to the actual scale. For ease of understanding, the same elements in the following description will be illustrated with the same symbols. In addition, the terms "including", "including", "having", etc. used in the text are all open terms; that is, they mean including but not limited to. Moreover, the directional terms mentioned in the text, such as "upper", "lower", etc., are only used to refer to the direction of the drawings. Therefore, the directional terms used are used for illustration, not to limit the present invention.

[0064] Figure 1 is a cross-sectional schematic diagram of a static random access memory device according to a first embodiment of the present invention.

[0065] Please refer to Figure 1 , the static random access memory element of the first embodiment includes a substrate 100, a first transistor 102, a second transistor 104, a metal interconnect structure 106 and a capacitor 108. The first transistor 102 is formed on the substrate 100, and the first transistor 102 includes a first gate 110, a first drain node 112 and a first source node 114. In addition, the first transistor 102 may also have a LDD (lightly doped drain) region 116, a gate dielectric layer 118 and a spacer 120, but the present invention is not limited thereto. In one embodiment, a silicide metal layer (not shown) may be provided on the surface of the first drain node 112 and the surface of the first source node 114 to reduce the resistance of subsequent circuits; the spacer 120 may be a single-layer or multi-layer structure. The second transistor 104 is also formed on the substrate 100, and may be separated from the first transistor 102 by an element isolation structure 122 (such as STI). In this embodiment, the first transistor 102 and the second transistor 104 are N-type metal oxide semiconductors (NMOS ) transistor and a P-type metal oxide semiconductor (PMOS) transistor. The second transistor 104 includes a second gate 124, a second source node 126 and a second drain node 128. In addition, the second transistor 104 may also have structures such as an LDD region 130, a gate dielectric layer 118 and a spacer 120, but the present invention is not limited thereto. In one embodiment, a silicide metal layer (not shown) may be further provided on the surface of the second source node 126 and the second drain node 128. In this embodiment, the first gate 110 and the second gate 124 are combined into a transmission gate. The metal interconnect structure 106 is formed on the first transistor 102 and the second transistor 104, wherein the metal interconnect structure 106 includes a plurality of metal layers 132 N, multi-layer inter-layer dielectric (ILD) layer 134 N Connecting different metal layers 132 N Multiple vias 136 N , N is an integer greater than 1. Figure 1 For example, the metal interconnect structure 106 includes four metal layers 132 1～4 , four ILD layers 134 1～4 Connecting different metal layers 132 1～3 Multiple vias 136 1～3 , and in the ILD layer 134 1～4 Other intermediate layers 140 of different materials may be provided between 1～4 , in order to facilitate the control of the manufacturing process; for example, the ILD layer 134 1～4 The material is SiCO, the intermediate layer is 140 1～4 The material of is SiCN, but the present invention is not limited thereto. In addition, there is usually an interlayer dielectric layer 142 and a contact window 144 between the first and second transistors 102, 104 and the metal interconnect structure 106 to connect the two.

[0066] Please continue to refer to Figure 1 , the capacitor 108 is disposed in the metal interconnect structure 106 and coupled between the first transistor 102 and the second transistor 104. For example, the metal interconnect structure 106 has an opening 106a, and the capacitor 108 is formed in the opening 106a. The capacitor 108 includes a lower metal layer 146, a first electrode layer 148, a dielectric layer 150, a second electrode layer 152 and an upper metal layer 154, and is a metal-insulator-metal (MIM) capacitor. The lower metal layer 146 can be coupled to the first source node 114 and the second source node 126 via the contact window 144, and the lower metal layer 146 can be connected to the metal layer 132 of the nth layer in the metal interconnect structure 106. n The upper metal layer 154 is disposed on the lower metal layer 146 and can be connected to the metal layer 132 of the mth layer in the metal interconnect structure 106. m The first electrode layer 148 is disposed between the lower metal layer 146 and the upper metal layer 154, the second electrode layer 152 is disposed between the upper metal layer 154 and the first electrode layer 148, and the dielectric layer 150 is disposed between the first electrode layer 148 and the second electrode layer 152. Figure 1For example, the lower metal layer 146 and the first metal layer 1321 are formed of the same material, and thus can be integrated into the back-end of line (BEOL) process of the existing 2-transistor-static random-access memory (2T-SRAM) process without the need for additional photomasks and processes; the upper metal layer 154 and the fourth metal layer 1324 are formed of the same material, and due to the manufacturing process, the thickness t1 of the upper metal layer 154 is thinner than the thickness t2 of the fourth metal layer 1324, but the present invention is not limited thereto. Figure 1 It can be seen that the height of the storage capacitance of the capacitor 108 is equal to the height of the two metal layers 132 in the metal interconnect structure 106. 2～3 With three-layer via 136 1～3 The total thickness of the capacitor is the same as that of the conventional capacitor formed on the substrate 100 and having a thickness close to that of the inter-layer dielectric layer 142, so its capacitance can be increased.

[0067] In the present embodiment, the first electrode layer 148 is formed on the surface of the opening 106a, the dielectric layer 150 is formed on the surface of the first electrode layer 148, and the second electrode layer 152 fills the opening 106a and covers the dielectric layer 150, wherein the material of the first electrode layer 148 is, for example, Ti, TiN, Ta, TaN, Al, In, Nb, Hf, Sn, Zn, Zr, Cu, Y or a combination thereof. The material of the dielectric layer 150 is, for example, a high-k material, silicon oxide, silicon nitride, silicon oxide / silicon nitride / silicon oxide (ONO) or a combination thereof; the high-k material is, for example, tantalum oxide (Ta2O5), aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), zirconium oxide (ZrO2) or a combination thereof. The material of the second electrode layer 152 is, for example, Ti, TiN, Ta, TaN, Al, In, Nb, Hf, Sn, Zn, Zr, Cu, Y or a combination thereof. In this embodiment, the capacitor 108 further has an extension portion 108 a extending beyond the opening 106 a , which can further increase the capacitance of the capacitor 108 .

[0068] exist Figure 1 In the embodiment, a plurality of word lines (WL) 156 are provided to couple the first gate 110 and the second gate 124 respectively, and the word lines 156, the lower metal layer 146 and the first metal layer 1321 are all formed of the same material. Figure 1The cross section of the device is shown, so even though it cannot be seen, the direction in which the word line 156 extends can actually be the same as the direction in which the first gate 110 / second gate 124 extends. This is because the capacitor 108 is moved to the metal interconnect structure 106, so there is room to set the metal word line 156 connecting the gate (110 / 124), reducing the impedance of the lower electrode of the conventional capacitor directly contacting the first source node 114 and the second source node 126, thereby avoiding the problem of gate power supply capacity shift and capacitor leakage.

[0069] Figure 2A and Figure 2B They are cross-sectional schematic diagrams of two examples of the static random access memory element of the first embodiment, wherein the same element symbols as those in the previous embodiment are used to represent the same or similar components, and the same or similar components can also refer to the previous embodiment and will not be described in detail.

[0070] exist Figure 2A In the embodiment, the lower metal layer 200 of the capacitor 108 and the second metal layer 1322 of the metal interconnect structure 106 are formed of the same material, and the remaining components are Figure 1 Therefore, the lower metal layer 200 of the capacitor 108 is coupled to the first source node 114 and the second source node 126 via the contact window 144, the metal layer 1321 and the via window 1361. Figure 2A It can be obtained that the height of the storage capacitance of the capacitor 108 is related to the height of the metal layer 1323 and the two layers of the vias 136 in the metal interconnect structure 106. 2～3 The total thickness of the capacitor 108 is the same as that of the inner dielectric layer 142, so the surface area of ​​the capacitor 108 is still larger than that of a conventional capacitor formed on the substrate 100 with a thickness close to that of the inner dielectric layer 142, thereby increasing its capacitance. For example, if the thickness of the inner dielectric layer 142 is 0.28 μm, the metal layer 1323 above it and the two vias 136 2～3 The total thickness is about 0.49μm or more, so the capacitance is increased by at least 64%.

[0071] exist Figure 2B In the embodiment, the upper metal layer 202 of the capacitor 108 and the third metal layer 1323 of the metal interconnect structure 106 are formed of the same material, and the remaining components are Figure 1 Same. From Figure 2B It can be seen that the height of the storage capacitance of the capacitor 108 is related to the height of the metal layer 1322 and the two layers of the vias 136 in the metal interconnect structure 106. 1～2 The total thickness is the same, so the surface area of ​​capacitor 108 is still larger than the surface area of ​​a conventional capacitor with a thickness close to that of the inner dielectric layer 142, thereby increasing its capacitance.

[0072] Figures 3A to 3G It is a schematic diagram of a manufacturing process of a static random access memory device according to a second embodiment of the present invention.

[0073] Please refer to Figure 3A , including providing a substrate 300, and then forming a first transistor 302 and a second transistor 304, wherein the first transistor 302 includes a first gate 306a, a first drain node 308a and a first source node 308b, and the second transistor 304 includes a second gate 306b, a second source node 310a and a second drain node 310b. The manufacturing process of the first transistor 302 and the second transistor 304 can refer to the existing technology, so the first transistor 302 and the second transistor 304 can also be formed with components such as a gate dielectric layer 312, a spacer 314 and LDD regions 316a, 316b. For example, a gate dielectric layer 312 and a conductive layer (not shown) may be sequentially formed on the surface of a substrate 300 having an element isolation structure 318 (such as STI), and then the gate dielectric layer 312 and the aforementioned first gate 306a and second gate 306b may be defined, and LDD regions 316a and 316b may be formed in the substrate 300 using an ion implantation process, and then a spacer 314 may be formed on the sidewalls of the first gate 306a and second gate 306b. Since the first transistor 302 and the second transistor 304 are respectively one of an N-type metal oxide semiconductor transistor and the other of a P-type metal oxide semiconductor transistor, an ion implantation process may be used to form a first drain node 308a and a first source node 308b of different conductivity types, as well as a second source node 310a and a second drain node 310b. In addition, a silicide metal layer (not shown) may be formed on the surfaces of the first drain node 308a and the first source node 308b and the second source node 310a and the second drain node 310b to facilitate subsequent electrical coupling. The above manufacturing process is only one example that can be implemented, and can be changed accordingly according to the components included in the transistor, and is not limited to the above steps and processes.

[0074] Then, please refer to Figure 3B , forming an inner dielectric layer 320 covering the first and second transistors 302 and 304, and forming a contact window 322 coupling the first source node 308b and the second source node 310a in the inner dielectric layer 320. The material of the inner dielectric layer 320 is, for example, silicon oxide formed by chemical vapor deposition using tetraethoxysilane (TEOS) as a reaction gas, or selected from borophosphosilicate glass (BPSG), phosphorus-doped silicate glass (PSG), low dielectric constant (low k) materials, etc. In the present embodiment, the formed contact window 322 can also be used as a contact window for individually connecting the first gate 306a, the second gate 306b, the first drain node 308a, and the second drain node 310b.

[0075] Afterwards, please refer to Figure 3C , forming a metal interconnect structure 324 on the inner dielectric layer 320, which includes a plurality of metal layers 326 N , multi-layer inter-layer dielectric (ILD) layer 328 N Connecting different metal layers 326 N Multiple vias 330 N , N is an integer greater than 1. In the process of manufacturing the metal interconnect structure 324, the lower metal layer 332 of the capacitor can be completed first, which can be connected to the metal layer 326 of the nth layer. N Make together (where n ≥ 1), such as Figure 3C The lower metal layer 332 in the embodiment is manufactured together with the metal layer 3261 of the first layer, so the lower metal layer 332 is a part of the metal layer 3261 of the first layer. In another embodiment, the lower metal layer 332 can also be manufactured together with the metal layer 3262 of the second layer, so as to obtain Figure 2A In addition, the capacitor of ILD layer 328 1～3 Other intermediate layers 334 of different materials may be provided between 1～3 , in order to facilitate the control of the manufacturing process, and its materials can refer to the above embodiment, so it will not be repeated. In addition, when the metal layer 3261 is manufactured, a word line (WL) 336 can also be manufactured at the same time, which is coupled to the first gate 306a and the second gate 306b respectively. Since the word line 336 connecting the first gate 306a and the second gate 306b is metal, the impedance can be reduced to avoid the problem of gate power supply capacity transfer.

[0076] Then, please refer to Figure 3D In order to form an opening that can accommodate the capacitor, a multi-layer mask layer 338 may be formed on the metal interconnect structure 324, which may include film layers of different materials to facilitate subsequent etching of the opening. In one embodiment, the multi-layer mask layer 338 includes a SiCN layer 340a, a SiCO layer 340b, an amorphous carbon (aC) layer 340c, and a multi-layer photoresist (MLR) SiON layer 340d. However, the present invention is not limited to this. Subsequently, a patterned photoresist layer 342 is formed on the multi-layer mask layer 338, wherein the patterned photoresist layer 342 has a pattern aligned with the lower metal layer 332.

[0077] Next, please refer to Figure 3E, using the patterned photoresist layer 342 as a mask, the pattern is transferred to the multi-layer mask layer 338, and then using the multi-layer mask layer 338 as a mask, the pattern is transferred to the metal interconnect structure 324 to form an opening 344, and the bottom of the opening 334 exposes the lower metal layer 332. In this embodiment, the width w1 of the opening 344 is slightly larger than the width w2 of the lower metal layer 332, but the present invention is not limited to this. In another embodiment, the width w1 of the opening 344 can be equal to or smaller than the width w2 of the lower metal layer 332.

[0078] Afterwards, please refer to Figure 3F , remove the patterned photoresist layer ( Figure 3E 342) and multi-layer mask layer ( Figure 3E 338 in the opening 344), or some materials such as SiCN layer 340a and SiCO layer 340b may be retained. Then, in order to form a capacitor in the opening 344, a first electrode layer 346 is first deposited on the metal interconnect structure 324 and the lower metal layer 322. The method for forming the first electrode layer 346 is, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD) or a combination thereof, such as metal organic vapor deposition (MOCVD); and then a dielectric layer 348 and a second electrode layer 350 are deposited. The method for forming the second electrode layer 350 is, for example, supercritical fluid deposition (SFD), physical vapor deposition (PVD) or a combination thereof. Moreover, since the depth-to-width ratio of the opening 344 is relatively large, it is preferred to first perform SFD to deposit part of the second electrode layer, and then use PVD to deposit the remaining second electrode layer. As for the optional materials for the first electrode layer 346, the dielectric layer 348 and the second electrode layer 350, please refer to the above embodiments, so they will not be repeated.

[0079] Afterwards, please refer to Figure 3G , patterning the second electrode layer 350, the dielectric layer 348 and the first electrode layer 346, and then forming an upper metal layer 352 on the second electrode layer 350, thus completing the fabrication of the capacitor 354. The upper metal layer 352 can be connected to the metal layer 326 of the mth layer. N Make together (where m≥n+1), such as Figure 3G The upper metal layer 352 is formed together with the fourth metal layer 3264, so the upper metal layer 352 is a part of the fourth metal layer 3264. That is, the ILD layer 3284 can be covered on the second electrode layer 350 first, and the via window 3303 and the metal layer 3264 can be formed therein, and the upper metal layer 352 can be formed simultaneously during the formation of the metal layer 3264. In addition, in the patterning step, part of the second electrode layer 350, part of the dielectric layer 348 and part of the first electrode layer 346 outside the opening 344 can be retained to form the extension part 354a of the capacitor 354 to further increase the capacitance.

[0080] In summary, the present invention integrates the original 2T-SRAM manufacturing process and forms the capacitor in the metal interconnect structure, so its height is much larger than the surface area of ​​the conventional capacitor formed on the substrate with a thickness close to the inner dielectric layer, thereby increasing the capacitance. Moreover, since the coupling between the capacitor and the two transistors is through the lower metal layer, the manufacturing process conditions of the present invention are looser than those of the conventional capacitor manufacturing process that directly contacts the source node. At the same time, because the position of the capacitor is moved up to the metal interconnect structure, there is space to set the metal word line connected to the gate, thereby reducing the impedance of the conventional polysilicon as the word line, which can reduce the probability of the gate power supply capacity being transferred.

[0081] Although the present invention is disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the attached claims.

Claims

1. A static random access memory device, characterized in that: include: substrate; A first transistor formed on the substrate, the first transistor comprising a first gate, a first source node and a first drain node; A second transistor formed on the substrate, the second transistor comprising a second gate, a second source node, and a second drain node; A metal interconnect structure formed on the first transistor and the second transistor, wherein the metal interconnect structure comprises a plurality of metal layers, a plurality of inter-layer dielectric (ILD) layers, and a plurality of vias connecting the metal layers of different layers; as well as A capacitor is disposed in the metal interconnect structure and coupled between the first transistor and the second transistor, wherein the capacitor comprises: A lower metal layer, coupled to the first source node and the second source node, wherein the lower metal layer and the metal layer of the nth layer are formed of the same layer of material, wherein n≥1; An upper metal layer, disposed on the lower metal layer, wherein the upper metal layer and the metal layer of the mth layer are formed of the same layer of material, wherein m≥n+1; A first electrode layer, disposed between the lower metal layer and the upper metal layer; a second electrode layer, disposed between the upper metal layer and the first electrode layer; and a dielectric layer, disposed between the first electrode layer and the second electrode layer, The capacitor is electrically connected to the first source node and the second source node through the lower metal layer, and the lower metal layer is electrically connected to the first electrode layer.

2. The static random access memory device as claimed in claim 1, further comprising a plurality of word lines respectively coupled to the first gate and the second gate, wherein the word lines and the lower metal layer are formed of the same layer of material.

3. The SRAM device as claimed in claim 2, wherein an extension direction of the plurality of word lines is the same as an extension direction of the first gate, and an extension direction of the plurality of word lines is the same as an extension direction of the second gate.

4. The SRAM device as claimed in claim 1, wherein the metal interconnect structure has an opening, and the capacitor is formed in the opening. 5 . The SRAM device as claimed in claim 4 , wherein the first electrode layer is formed on a surface of the opening, the dielectric layer is formed on a surface of the first electrode layer, and the second electrode layer fills the opening and covers the dielectric layer. 6 . The SRAM device as claimed in claim 5 , wherein a material of the dielectric layer comprises a high dielectric constant material.

7. The SRAM device as claimed in claim 4, wherein the capacitor has an extension extending beyond the opening. 8 . The SRAM device according to claim 1 , wherein the thickness of the upper metal layer is thinner than the thickness of the m-th metal layer. 9 . The SRAM device as claimed in claim 1 , wherein the first transistor and the second transistor are respectively one and the other of an N-type metal oxide semiconductor transistor and a P-type metal oxide semiconductor transistor.

10. A method for manufacturing a static random access memory element, comprising: providing a substrate; forming a first transistor and a second transistor, wherein the first transistor includes a first gate, a first source node, and a first drain node, and the second transistor includes a second gate, a second source node, and a second drain node; forming an interlayer dielectric layer covering the first transistor and the second transistor; forming a plurality of contact windows coupling the first source node and the second source node in the inner dielectric layer; forming a metal interconnect structure on the ILD layer, wherein the metal interconnect structure comprises a plurality of metal layers, a plurality of inter-layer dielectric (ILD) layers, and a plurality of vias connecting the metal layers of different layers, and a portion of the metal layer of the nth layer is a lower metal layer, wherein n≥1, and the lower metal layer couples the first source node and the second source node; forming an opening in the metal interconnect structure, wherein the bottom of the opening exposes the lower metal layer; as well as A capacitor is formed in the opening, wherein the capacitor comprises the lower metal layer, a first electrode layer formed on a surface of the opening, a dielectric layer formed on a surface of the first electrode layer, a second electrode layer filling the opening and covering the dielectric layer, and an upper metal layer formed on a surface of the second electrode layer, wherein the upper metal layer is a part of the metal layer of the mth layer, wherein m≥n+1, The capacitor is electrically connected to the first source node and the second source node through the lower metal layer, and the lower metal layer is electrically connected to the first electrode layer.

11. The method for manufacturing a static random access memory device as claimed in claim 10, wherein the step of forming the opening comprises: forming a plurality of mask layers above the metal interconnect structure; forming a patterned photoresist layer on the multi-layer mask layer, the patterned photoresist layer having a pattern aligned with the lower metal layer; Using the patterned photoresist layer as a mask, transferring the pattern to the multi-layer mask layer; Using the multi-layer mask layer as a mask, transferring the pattern to the metal interconnect structure; as well as The patterned photoresist layer and the multi-layer mask layer are removed.

12. The method for manufacturing a static random access memory device according to claim 10, wherein a method of forming the first electrode layer comprises metal organic vapor deposition (MOCVD). 13 . The method for manufacturing a static random access memory device as claimed in claim 10 , wherein a material of the dielectric layer comprises a high dielectric constant material. 14 . The method for manufacturing a static random access memory device as claimed in claim 10 , wherein a method of forming the second electrode layer comprises supercritical fluid deposition (SFD), physical vapor deposition (PVD) or a combination thereof.

15. The method for manufacturing a static random access memory device as claimed in claim 10, wherein the step of forming the capacitor comprises: Depositing the first electrode layer, the dielectric layer and the second electrode layer in sequence on the metal interconnect structure and the lower metal layer; patterning the second electrode layer, the dielectric layer and the first electrode layer; as well as The upper metal layer is formed on the second electrode layer.

16. The method for manufacturing a static random access memory device as claimed in claim 15, wherein the step of patterning the second electrode layer, the dielectric layer and the first electrode layer comprises retaining portions of the second electrode layer, the dielectric layer and the first electrode layer outside the opening to form an extension portion of the capacitor.

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