Timing recovery device, jitter mitigation circuit and receiver device

Abstract

This invention relates to a timing recovery device, a jitter reduction circuit, and a receiver device. More specifically, a particular embodiment of the invention provides a timing recovery device with two stages. The first stage generates a clock signal to sample a received waveform, and the second stage provides timing jitter reduction. The second stage includes a jitter reduction circuit having coefficients of an instantaneous jitter estimation function; it also includes a jitter estimation tracking loop consisting of an error generator, a timing error detector, and a loop filter for compensating for timing jitter associated with the clock signal. Other embodiments also exist.

Description

Technical Field

[0001] The present invention relates to circuits and communications. Background Art

[0002] The use of communication networks has exploded over the past few decades. In the early days of the Internet, popular applications were limited to email, bulletin boards, and mostly information and text-based web surfing, and the amount of data transferred was relatively small. Today, as more and more people use the Internet for media consumption, Internet and mobile applications require large amounts of bandwidth to transfer photos, videos, music, and other multimedia files. Data centers often need to transfer and process hundreds of terabits of data every hour. With such high requirements for data storage and data transmission, existing data communication systems need to be improved to meet these needs.

[0003] Timing recovery is an important component of a receiver. Timing recovery involves extracting a clock frequency from received data; the rate at which the receiver processes received data is based on the extracted clock frequency. The performance of a receiver depends, among other things, on the performance of the receiver's timing recovery mechanism. In the past, there have been many conventional timing recovery designs, but they are all inadequate. New and improved timing recovery methods and systems are desired. Summary of the invention

[0004] The present invention relates to circuits and communications. More specifically, a particular embodiment of the present invention provides a timing recovery apparatus having two stages. The first stage adjusts the clock signal, and the second stage provides further jitter mitigation. The second stage includes a jitter mitigation circuit and a jitter estimation circuit to reduce jitter associated with the clock signal. Other embodiments also exist.

[0005] According to one embodiment, the present invention provides a timing recovery device, which includes a first stage circuit, the first stage circuit including an analog-to-digital converter (ADC) and an equalizer. The ADC is configured to digitize a data stream using a recovered clock signal. The recovered clock signal is impaired by timing jitter, which causes jitter-related inter-symbol interference (ISI) in the digitized data. The equalizer is configured to provide equalized data based on the output of the ADC. The device also includes a second stage circuit. The second stage circuit includes a jitter mitigation circuit coupled to the equalizer and configured to output a signal with reduced jitter-related ISI. The second stage circuit also includes a jitter estimation circuit. The jitter estimation circuit includes an error generator, which is configured to generate an error signal based on the output signal and a data detector signal.

[0006] According to another embodiment, the present invention provides a jitter mitigation circuit for timing recovery. The circuit includes a jitter mitigation circuit coupled to an equalizer and configured to generate an output signal with reduced jitter-related ISI. The jitter mitigation circuit has a finite response filter configured with a plurality of tap values, the tap values ​​depending on an estimate of instantaneous jitter. The circuit also includes a jitter estimation circuit having an error generator configured to generate an error signal based on the output signal and a data detector signal. The circuit also includes a timing error detector (TED) configured to generate a timing error signal. The circuit also includes a loop filter configured to generate an estimate of instantaneous timing jitter based on the timing error signal.

[0007] According to another embodiment, the present invention provides a receiver device, which includes an interface for receiving a data stream. The device also includes a timing recovery module, the timing recovery module including a first stage circuit and a second stage circuit. The first stage circuit includes an analog-to-digital converter (ADC), the analog-to-digital converter is configured to digitize the data stream using a recovered clock signal. The recovered clock signal is damaged due to timing jitter. The first stage circuit also includes an equalizer, the equalizer is configured to provide equalized data based on the output of the ADC. The second stage circuit includes a jitter mitigation circuit coupled to the equalizer and configured to generate an output signal with reduced ISI caused by timing jitter.

[0008] It should be appreciated that embodiments of the present invention provide numerous advantages over conventional techniques. A timing recovery mechanism according to the present invention can effectively compensate for jitter on a recovered clock. In various embodiments, a timing recovery mechanism according to the present invention extends the timing recovery bandwidth (e.g., beyond 15 MHz) without increasing the design requirements of other components in a receiver (e.g., delays of existing receiver components). When implemented in conjunction with a first-stage timing recovery circuit, the second-stage timing recovery circuit detects and reduces residual jitter after the first-stage timing recovery. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a simplified diagram illustrating a communication system according to an embodiment of the present invention.

[0010] Figure 2 is a simplified block diagram illustrating a timing recovery apparatus 200 according to an embodiment of the present invention.

[0011] Figure 3 is a simplified block diagram illustrating a jitter mitigation mechanism 300 for timing recovery according to an embodiment of the present invention.

[0012] Figure 4A and Figure 4BA graph is provided showing genie-aided performance of jitter mitigation according to an embodiment of the present invention.

[0013] Figure 5A and Figure 5B A graph illustrating simulated performance of jitter mitigation (utilizing FFE and DFE) according to an embodiment of the present invention is provided.

[0014] Fig. 6A and Figure 6B Graphs showing simulated performance of jitter mitigation (using FFE) according to embodiments of the present invention are provided.

[0015] Figure 7 is a simplified block diagram illustrating a two-stage timing recovery apparatus according to an embodiment of the present invention.

[0016] Figure 8 is a simplified block diagram illustrating a two-stage timing recovery apparatus according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The present invention relates to circuits and communications. More specifically, a particular embodiment of the present invention provides a timing recovery apparatus having two stages. The first stage adjusts the clock signal and the second stage provides further jitter mitigation by increasing the overall timing recovery tracking bandwidth. The second stage includes a jitter mitigation circuit, an error generator, a timing error detector, and a tracking loop filter to reduce jitter associated with the clock signal. Other embodiments also exist.

[0018] Figure 1 is a simplified diagram illustrating a communication system according to an embodiment of the present invention. Figure 1This is only an example and should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, substitutions and modifications. The communication system 100 includes a transmitter 110, a receiver 120 and a link 130. The transmitter 110 sends data to the receiver 120 via the communication link 130. The receiver 120 includes a sampler 121, an analog-to-digital converter (ADC) 122, a digital signal processor (123) and a timing recovery module 124. It should be understood that the receiver 120 shown in the figure only provides an example, and it includes additional components (e.g., a receiver interface, an equalizer, a variable gain amplifier, a reference clock, etc.) and can have different configurations. The sampler 121 samples the analog data received via the communication link 130. As shown, the sampler 121 is also connected to the timing recovery module 124. The ADC 122 converts the sampled analog data into a digital format. The DSP 123 further processes the received data, which is now in a digital format after being converted by the ADC 122. For example, DSP 123 can be configured to perform equalization, detection, error correction and other processing. The output of DSP 123 is provided to timing recovery module 124, which extracts timing information (e.g., clock signal). As an example, timing recovery module 124 is implemented according to an embodiment of the present invention, and timing recovery module 124 includes two stages that allow high performance levels. Timing recovery module 124 includes a first stage circuit and a second stage circuit. The first stage circuit is configured to adjust the clock frequency. The second stage circuit is configured to compensate for jitter in the clock.

[0019] The timing information extracted by the timing recovery module 124 is important for data processing because the receiver 120 relies on the timing information to sample the received data. Whether the link 130 is wired, wireless or optical, timing recovery is necessary, and the performance of the timing recovery mechanism directly affects the performance and reliability of data communications and data processing systems. For example, serializers / deserializers (SerDes), transceivers, data management systems, and other devices are implemented with various types of timing recovery mechanisms. In some embodiments, the timing recovery mechanism according to the present invention is used in a communication system using pulse amplitude modulation (PAM) signaling.

[0020] There are many considerations for digital timing recovery design. The performance of the digital timing recovery mechanism depends primarily on (or is limited by) the loop delay and the signal-to-noise ratio (SNR) of the timing error detector. It should be understood that embodiments of the present invention relate to these mechanisms and also take into account other considerations. In some cases, the timing recovery process enables reliable communication with an incompatible transmitter. For example, an incompatible transmitter may have jitter that exceeds the achievable bandwidth of a conventional timing recovery loop, and in order to address this problem, it is necessary to improve the jitter tracking performance. In addition, in digital timing recovery schemes that turn off the timing at the analog sampling circuit, reducing the loop delay increases power consumption and / or reduces the timing SNR. It should therefore be understood that in various embodiments, the present invention improves various aspects of the timing recovery mechanism that can be used in many applications.

[0021] Figure 2 2 is a simplified block diagram of a timing recovery device 200 according to an embodiment of the present invention. This diagram is only an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. As an example, the timing recovery device 200 may be implemented as Figure 1 The timing recovery device 200 includes a first stage circuit 210 and a second stage circuit 220. The first stage circuit 210 generates a recovered clock signal based on received samples and adjusts the sampling clock frequency. The second stage circuit 220 detects and mitigates timing jitter.

[0022] In the timing recovery process, untracked jitter causes inter-symbol interference (ISI) associated with the timing phase error. Although ISI can be compensated by a finite impulse response (FIR) filter, the tap amplitude of the jitter mitigation circuit needs to reflect the instantaneous residual jitter, which means that the jitter needs to be tracked. The second stage circuit 220 of the timing recovery device 200 compensates for residual jitter with an amplitude less than 1 unit interval (UI) peak to peak, and the jitter compensation efficiency decreases as the timing phase error increases.

[0023] The timing recovery process begins with sampled data being received and processed by ADC 201. For example, the sampled data is received by a sampler (e.g., Figure 1 Sampler 121 in Figure 2 ADC 201 digitizes the sampled data by performing an analog-to-digital conversion process at a clock frequency (typically, the received baud rate), which is regulated by a timing correction signal received by a digitally controlled oscillator (DCO) 206. Feedforward equalizer (FFE) 202 equalizes the channel. Other types of equalization may also be performed depending on the implementation.

[0024] The equalized data provided by FFE 202 is processed by detector (DET) 203, which can be implemented using different types of mechanisms. For example, DET 203 can be implemented using a slicer, a decision feedback equalizer (DFE), a maximum likelihood sequence detector (MLSD), and / or other types of mechanisms. In a particular embodiment, DET 203 is implemented by a DFE that implements a first post-cursor tap and includes a slicer. MLSD-based DET can also be implemented by a slicer, etc.

[0025] As shown, the error generator (ErrGen) 204 uses the outputs of both the FFE 202 and the DET 203. For an ISI detector (e.g., DFE, MLSE), the error generator 204 uses the slicer decision from the DET 203 to remove the (decision-dependent) vernier and ISI terms from the FFE output. When the DET 203 is implemented with only a slicer, the error generator 204 removes the decision-dependent vernier contribution from the FFE output.

[0026] Block 205 includes a timing error detector (TED) and a loop filter (LF). The TED uses the output of the error generator 204 and the DET 203 to generate an indication of whether the sampling process is early or late. The LF filters the TED output to generate a signal that controls the frequency of the clock generated by the DCO 206.

[0027] The performance of the first stage circuit 210 is limited by, among other things, the loop delay of the first stage circuit 210. To provide an improvement in jitter tracking bandwidth, the delay of the second stage circuit 220 is implemented to be much smaller than the delay of the first stage circuit 210. For example, the delay of the first stage circuit 210 can be described as the total delay of its components (e.g., ADC, FFE, DET, ErrGen, TED, LF, and DCO), which is greater than the total delay of the components in the second stage circuit 220. Due to the delay limitation of the first stage circuit 210, the first stage circuit 210 may not provide sufficient jitter tracking bandwidth for some applications. It should be appreciated that the second stage circuit 220, which is optimized for both delay and accuracy, is effective in removing residual timing jitter from the first stage circuit 210.

[0028] In some embodiments, interference and / or reflection cancellation functions (not shown) are integrated into a single impairment mitigation block with the jitter mitigation circuit 211. To avoid increasing loop delay, these additional functions (e.g., interference and reflection cancellation) may be performed before (or in parallel with) the jitter mitigation circuit.

[0029] like Figure 2As shown, the connection between the first stage circuit 210 and the second stage circuit 220 is realized by the connection between the FFE202 and the jitter mitigation circuit 211. More specifically, the jitter mitigation circuit 211 performs jitter mitigation processing using the FFE 202 output (i.e., the equalized sampled data). In a specific embodiment, the jitter mitigation circuit 211 is a lookup table indexed by the equalizer output. The second stage circuit 220 includes the jitter mitigation circuit 211, the DET 212, the error generator 213, and the block 214. In a specific embodiment, the block 214 is omitted, and the output of the block 205 is used as the input of the jitter mitigation circuit 211. It should be understood that the blocks 212-214 can be similar to the corresponding blocks of the first stage 210, but they are specifically implemented for the second stage circuit 220 and are configured for jitter mitigation functions. The output of the second stage circuit 220 is provided by the DET 212. DET 212 provides improved error correction performance, but when included in the jitter tracking control loop, DET 212 introduces additional latency. In some embodiments, selector 215 is configured to select values ​​from DET 203 that translate into increased tracking bandwidth and stability at the relatively small cost of reduced accuracy. In some applications, second stage circuitry 220 may be bypassed entirely (e.g., to save power, reduce latency, etc.). For example, control module ( Figure 2 (not shown) can turn on and off the second stage circuit 220 as needed. In various embodiments, the conditions for turning off or bypassing the second stage circuit 220 include power consumption, jitter level below a predetermined threshold, etc.

[0030] exist Figure 2 2, error generator 213 receives input from jitter mitigation circuit 211 in addition to input from DET 203 or DET 212. When error generator 213 is configured to receive input from DET 203, jitter tracking loop delay is minimized, which increases the achievable jitter tracking bandwidth of second stage 220. The specific functionality and configuration of error generator 213 will be described in further detail below.

[0031] Figure 3 1 is a simplified block diagram illustrating a jitter mitigation mechanism 300 for timing recovery according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. As an example, the jitter mitigation mechanism 300 is implemented as the second stage circuit 220 of the timing recovery device 200.

[0032] The jitter reduction mechanism 300 includes a jitter estimation circuit 311 and a jitter reduction circuit 309. Figure 2Expanded to provide an exemplary implementation. The jitter mitigation circuit 309 includes a 7-tap linearized implementation of a FIR filter, with the tap amplitudes depending on an estimate of the instantaneous jitter. The three post-vernier taps and the three pre-vernier taps have fixed coefficient multipliers (i.e., α -3 to α3), and their summed output is scaled by the estimate of the instantaneous jitter θ[l] at node 305, so that the effective non-vernier FIR tap weight is α i ·θ[1]. To account for the contribution of the non-zero first post-wiper in the equalization response, node 306 multiplies the DFE tap amplitude β by the delayed summing node output. The wiper tap is unity gain, and the wiper input is combined with the output of node 305 to generate a jitter-mitigated output. The input to the wiper tap is the FFE output. The input to the non-wiper tap is either the FFE output or the first stage detector output, depending on the application. The number of taps in filter 309 can vary, depending on the implementation. The number of taps affects power consumption and performance, among other things. In this exemplary implementation, the jitter tracking loop only needs to be closed at node 305 (which is multiplied by θ), thereby facilitating low loop delay.

[0033] In some embodiments, as the insertion loss of the channel decreases, fewer taps are used (e.g., three or five taps). At startup, a coefficient set can be selected based on the FFE and DFE coefficients. As shown, error generator 301 receives a value calculated at node 308. Node 308 provides an output r[l] of jitter mitigation circuit 309, which is the difference between the value provided at line 310 and the value at node 305. In addition, error generator 301 also uses the output of a DET block as its input, which DET block can be a second stage DET (e.g., Figure 2 212 in the example) or a first-level DET (e.g., Figure 2 For example, when operating in FFE-only mode (i.e., DET is a PAM limiter; β=0), the output e[l] of the error generator is:

[0034] e[l]=r[l]-d[l]

[0035] Where r[l] is the output of the jitter mitigation FIR, and d[l] is the PAM level corresponding to the DET output. Otherwise, when β≠0, the output e[l] of the error generator 301 is:

[0036] e[l]=r[l]-(d[l]+β·d[l-1])

[0037] As shown, the output e[l] of the error generator 301 is processed at block 302, which includes TED and LF. Block 302 is coupled to a selector 303, which selects between the value at node 304 and the DET signal d[l]. Depending on the implementation, the TED used in the second stage (e.g., Figure 2 214 in the first stage) does not need to be the same as the TED used in the first stage (e.g., Figure 2 The TED in block 302 can be implemented in various ways, such as zero-forcing (ZF) TED and minimum mean square error (MMSE) TED. The output T[l] of the zero-forcing TED can be described as:

[0038] T[l]=e[l]·(d[l+1]-d[l-1])

[0039] where d[l] is the PAM level corresponding to DET.

[0040] The output of the MMSE TED, T[l]—where e[l] is the output of the error generator and w[l] is the output from the non-vernier tap of the jitter mitigation FIR filter (just before multiplication by θ)—is:

[0041] T[l]=e[l]·w[l]

[0042] A loop filter (LF) is implemented together with the TED as part of block 302. In various embodiments, the loop filter output θ is the integral of some function q(·) of the TED output:

[0043] θ[l]=θ[l-1]+μ·q(T(l))

[0044] For example, LF is implemented using a proportional controller, and the LF output is:

[0045] θ[l]=θ[l-1]+k P ·T(l)

[0046] As another example, LF is implemented using a proportional-integral controller, and the output of LF is:

[0047] θ[l]=θ[l-1]+μ·(T(l)+U[l])

[0048] Where U[l]=U[l-1]+μ I ·T(l)

[0049] There are two main factors that affect the overall jitter mitigation performance. The first is the jitter tracking control loop, that is, the ability of θ[l] to track the residual timing jitter. The second is the jitter compensation data path equalizer, which determines the ability of the jitter mitigation FIR filter to compensate for the residual ISI caused by timing jitter.

[0050] Figure 4A and Figure 4B A graph illustrating the performance of a Genie-assisted jitter mitigation according to an embodiment of the present invention is provided. This graph is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art will recognize many variations, substitutions, and modifications. The Genie-assisted performance assumes that the residual timing jitter is static but fully known (e.g., Genie-assisted jitter tracking control loop). As insertion loss (IL) increases, the penalty in the absence of jitter compensation increases, but the penalty with compensation decreases. Figure 4A The performance of a PAM4 configuration with FFE and DFE is shown. Figure 4B The performance of a PAM4 configuration with FFE is shown.

[0051] Figure 5A and Figure 5B A graph is provided showing simulated performance of jitter mitigation (utilizing FFE and DFE) according to an embodiment of the present invention. This graph is an example only and should not unduly limit the scope of the claims. One of ordinary skill in the art will recognize many variations, substitutions, and modifications. The simulation corresponds to conditions of 3dB jitter suppression at 18MHz and less than 2.6dB peak (zero peak before 27MHz). For SJ=0.2UI peak-to-peak (p2p) at 8MHz, the degradation relative to the baseline SNR is less than 0.75dB. Figure 5A The jitter error transfer function is shown. Figure 5B The PAM4 SNR based on SER is shown. For comparison Figure 5B , graph 501 corresponds to SJ=0 UI p2p, and Kp=0; graph 502 corresponds to SJ=0.2 UI p2p, Kp=0; and graph 503 corresponds to SJ=0.2 UI p2p with a 7-tap dither FIR.

[0052] Fig. 6A and Figure 6BA graph is provided showing simulated performance of jitter mitigation (with FFE) according to an embodiment of the present invention. This graph is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art will recognize many variations, substitutions, and modifications. The simulation corresponds to 3dB jitter suppression at 16.5MHz, with a peak value of less than 1.9dB (zero peak before 27MHz). For SJ=0.2UI p2p@8MHz, the degradation relative to the baseline signal-to-noise ratio is less than 0.6dB. Fig. 6A The jitter error transfer function measured in dB is shown. Figure 6B The PAM4 SNR (in dB) based on SER is shown. Figure 6B , graph 601 corresponds to SJ=0UI p2p, and Kp=0; graph 602 corresponds to SJ=0.2UI p2p, Kp=0; and graph 603 corresponds to SJ=0.2UI p2p with a 3-tap dither FIR.

[0053] In addition to performance advantages, as shown in the graph, the timing recovery mechanism according to the present invention also provides implementation advantages. For example, the jitter mitigation circuit and the second stage of the timing recovery device can be configured as a modular implementation, allowing them to be incorporated into various systems and devices. In various implementations, the timing recovery mechanism according to the present invention extends the timing recovery bandwidth to more than 15MHz without increasing the design requirements of other components in the receiver (e.g., delays of existing receiver components). When implemented in conjunction with the first stage timing recovery, the second stage timing recovery detects residual jitter after the first stage timing recovery. In order to obtain the best overall performance, the peak value and bandwidth of the first stage are optimized relative to the peak value and bandwidth of the second stage.

[0054] Figure 77 is a simplified block diagram illustrating a two-stage timing recovery device according to an embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the claims. One of ordinary skill in the art will recognize many variations, substitutions, and modifications. The timing recovery device 700 includes an ADC 701 that digitizes a received data signal at a recovery clock frequency provided by a timing recovery circuit 706. The digitized data is equalized by an equalizer 702. The timing recovery circuit 702 determines the recovery clock frequency by processing the equalized data provided by the equalizer. The timing recovery circuit 706 is capable of adjusting the clock frequency and providing limited jitter reduction, but the bandwidth of the timing recovery circuit 706 is limited by the delay of the timing recovery circuit 706, etc. As an example, the timing recovery circuit 706 includes components such as a DCO, a TED, a LF, an error generator, and / or a detector. The jitter mitigation circuit 703 uses the error estimate provided by the jitter estimation circuit 705 to process the equalized digital data provided by the equalizer 702 and reduce jitter. For example, the jitter estimation circuit 705 can be implemented with a detector, an error generator, a TED, a LF, and / or other components. One or more components of the jitter estimation circuit 705 may be shared with the timing recovery circuit 706. In some embodiments, the jitter estimation circuit 705 does not have its own detector or TED, but uses the output of the detector or TED of the timing recovery circuit. For example, the jitter mitigation circuit 703 may be implemented using a FIR filter. In some embodiments, the jitter mitigation circuit 703 includes a lookup table indexed by the output of the equalizer 702. The output of the jitter mitigation circuit 703 is equalized by the equalizer 704, which provides a receiver output (RX output).

[0055] Figure 88 is a simplified block diagram showing a two-stage timing recovery device according to an embodiment of the present invention. This figure is only an example and should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize many variations, substitutions and modifications. This figure is only an example and should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize many variations, substitutions and modifications. The timing recovery device 800 includes an ADC 801, which digitizes a received data signal at a recovery clock frequency provided by a timing recovery circuit 806. The digitized data is equalized by an equalizer 803. For example, the equalizer 803 is implemented with an FFE. The timing recovery circuit 802 determines the recovered clock frequency by processing the equalized data provided by the equalizer. The timing recovery circuit 802 is capable of adjusting the clock frequency and providing limited jitter reduction, but the bandwidth of the timing recovery circuit 802 is limited by the delay of the timing recovery circuit 802, etc. As an example, the timing recovery circuit 802 includes components such as a DCO, a TED, a LF, an error generator and / or a detector. For example, the detector 804 can be implemented as part of the timing recovery circuit 802. Jitter mitigation circuit 805 processes the equalized digital data provided by equalizer 803 and reduces jitter. Error generator 807 selects between detector 804 and detector 806 as its input to generate an error signal, which is used by block 808 to generate a timing error signal. Block 808 includes TED and LF. For example, jitter mitigation circuit 805 can be implemented using a FIR filter. In some embodiments, jitter mitigation circuit 805 includes a lookup table indexed by the output of equalizer 803. As shown, the output (RX output) of timing recovery device 800 is coupled to the output of detector 806.

Claims

1. A receiver, comprising: a feedforward equalizer configured to equalize digitized samples of a received signal and output equalized samples; a first detector configured to detect symbols in the equalized samples; a jitter estimation circuit configured to estimate jitter in the equalized samples; as well as Jitter suppression circuit, including: a linearized FIR filter configured to receive an input comprising the equalized samples or the detected symbols and to compensate for the intersymbol interference in the equalized samples based on the estimated jitter and an estimate of intersymbol interference due to the jitter; an error generator configured to generate an error signal based on the detected symbol and an output of the jitter suppression circuit; and A second detector is configured to generate an estimated jitter based on the error signal and one of (i) the detected symbol and (ii) the estimate of the inter-symbol interference.

2. A receiver, comprising: a feedforward equalizer configured to equalize digitized samples of a received signal and output equalized samples; a first detector configured to detect symbols in the equalized samples; a jitter estimation circuit configured to estimate jitter in the equalized samples; as well as Jitter suppression circuit, including: a linearized FIR filter configured to receive an input comprising the equalized samples or the detected symbols and to compensate for the intersymbol interference in the equalized samples based on the estimated jitter and an estimate of intersymbol interference due to the jitter; a multiplier configured to multiply an output of the linearized FIR filter by the estimated jitter to generate the estimate of the intersymbol interference; and A subtractor is configured to subtract the estimate of the intersymbol interference from the equalized samples to generate an output signal with reduced intersymbol interference.

3. The receiver of claim 2, wherein: The output signal is fed back to the jitter estimation circuit, and wherein the jitter suppression circuit reduces latency of the jitter estimation circuit by estimating the intersymbol interference and subtracting the estimate of the intersymbol interference from equalized samples external to the jitter estimation circuit.

4. A receiver, comprising: a feedforward equalizer configured to equalize digitized samples of a received signal and output equalized samples; a first detector configured to detect symbols in the equalized samples; a jitter estimation circuit configured to estimate jitter in the equalized samples; as well as a jitter suppression circuit comprising a linearized FIR filter configured to receive an input comprising the equalized samples or the detected symbols and to compensate for the intersymbol interference in the equalized samples based on the estimated jitter and an estimate of the intersymbol interference due to the jitter, wherein the linearized FIR filter comprises a plurality of delay lines connected in series to each other, and wherein outputs of respective ones of the delay lines are multiplied by respective coefficients and summed to generate outputs scaled by the estimated jitter to generate the estimate of the intersymbol interference.

5. The receiver of claim 4, further comprising a subtractor configured to subtract the estimate of the intersymbol interference from the equalized samples to generate an output signal with reduced intersymbol interference.

6. A method for a receiver, comprising: generating equalized samples by equalizing digitized samples of a received signal; detecting a symbol in the equalized sample; estimating jitter in the equalized samples; Processing an input including the equalized samples or detected symbols using a linearized FIR filter; Based on the processing, compensating for the intersymbol interference in the equalized samples due to the jitter according to the estimated jitter and an estimate of the intersymbol interference; generating an error signal based on the detected symbols and an output of the linearized FIR filter; and The estimated jitter is generated based on the error signal and one of (i) the detected symbol and (ii) the estimate of the inter-symbol interference.

7. A method for a receiver, comprising: generating equalized samples by equalizing digitized samples of a received signal; detecting a symbol in the equalized sample; estimating jitter in the equalized samples; Processing an input including the equalized samples or detected symbols using a linearized FIR filter; Based on the processing, compensating for the intersymbol interference in the equalized samples due to the jitter according to the estimated jitter and an estimate of the intersymbol interference; generating the estimate of the intersymbol interference by multiplying an output of the linearized FIR filter by the estimated jitter; and An output signal having reduced intersymbol interference is generated by subtracting the estimate of the intersymbol interference from the equalized samples.

8. The method according to claim 7, further comprising: estimating the jitter based on the output signal; and The delay of the circuit that estimates the jitter is reduced by estimating the intersymbol interference and subtracting the estimate of the intersymbol interference from the equalized samples external to the circuit.

9. A method for a receiver, comprising: generating equalized samples by equalizing digitized samples of a received signal; detecting a symbol in the equalized sample; estimating jitter in the equalized samples; Processing an input including the equalized samples or detected symbols using a linearized FIR filter; Based on the processing, compensating for the intersymbol interference in the equalized samples due to the jitter according to the estimated jitter and an estimate of the intersymbol interference; Wherein the linearized FIR filter comprises a plurality of delay lines connected in series with each other, the method further comprises: multiplying the output of the corresponding delay line by a corresponding coefficient; generating an output by combining the multiplied outputs; and The estimate of the intersymbol interference is generated by scaling the output by the estimated jitter.

10. The method according to claim 9, further comprising: An output signal having reduced intersymbol interference is generated by subtracting the estimate of the intersymbol interference from the equalized samples.

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