EFUSE switch circuit and control method

Abstract

Disclosed are an efuse switch circuit and a control method. The efuse switch circuit includes an efuse switch, a closed-loop control circuit, and an open-loop pull-down circuit. The closed-loop control circuit amplifies the error between a sampling signal representing a current flowing through the efuse switch and a reference signal to generate an error signal. The open-loop pull-down circuit is coupled between a control terminal and an output terminal of the efuse switch. When the error signal is greater than a pull-down threshold, the open-loop pull-down circuit clamps the voltage between the control terminal of the efuse switch and the output terminal of the efuse switch to a preset voltage value. The efuse switch circuit can timely and effectively limit the current flowing through the efuse switch to prevent the efuse switch from being damaged.

Description

Technical Field

[0001] The present invention relates to electronic circuits, and in particular to an electronic fuse (efuse) switch circuit and a control method. Background Art

[0002] In efuse applications, when overcurrent or overvoltage occurs, the control circuit will lower the gate-source voltage of the efuse switch to increase the on-resistance of the efuse, thereby reducing the current flowing through the efuse switch or the output voltage at the output end of the efuse switch. Figure 1 FIG. 1 shows a circuit diagram of an efuse switch in the prior art. Figure 1 As shown, the efuse switch is coupled at both ends of the system, and the control circuit receives a current sampling signal CS representing the current signal Ie flowing through the efuse switch. The control circuit generates a control signal C according to the current sampling signal CS. GATE Control the control end of the efuse switch. When the current flowing through the efuse switch is normal, the efuse switch is fully turned on; when the current flowing through the efuse switch is overcurrent, the control signal C GATE The on-resistance of the efuse switch will be increased to reduce the current flowing through the efuse switch. In some applications, when the current continues to over-current, the system does not want the efuse switch to be turned off immediately due to over-current. However, due to the bandwidth limitation of the control loop, the current flowing through the efuse switch cannot be adjusted to the expected value in time, resulting in the risk of the efuse switch being burned by the large current.

[0003] Therefore, we hope to propose a solution that can quickly reduce the current flowing through the efuse switch when the current continues to over-current. Summary of the invention

[0004] The purpose of the present invention is to solve the above problems in the prior art and to provide an efuse switch circuit and a control method.

[0005] On the one hand, the present invention provides an efuse switch circuit, including: an efuse switch having an input terminal, an output terminal and a control terminal; a closed-loop control circuit, receiving a sampling signal representing a current signal flowing through the efuse switch, and comparing the sampling signal with a reference signal to generate an error signal, wherein the error signal represents the difference between the sampling signal and the reference signal; and an open-loop pull-down circuit, having a first terminal, a second terminal and a third terminal, the first terminal of the open-loop pull-down circuit receiving the error signal, the second terminal of the open-loop pull-down circuit coupled to the control terminal of the efuse switch, and the third terminal of the open-loop pull-down circuit coupled to the output terminal of the efuse switch, wherein when the error signal is greater than a pull-down threshold, the open-loop pull-down circuit clamps the voltage between the control terminal of the efuse switch and the output terminal of the efuse switch to a preset voltage value.

[0006] On the other hand, the present invention provides a control method for an efuse switch circuit, comprising: sampling a current signal flowing through the efuse switch and generating a sampling signal representing the current signal flowing through the efuse switch; comparing the sampling signal with a reference signal to generate an error signal, wherein the error signal represents the difference between the sampling signal and the reference signal; judging the magnitude of the error signal and a pull-down threshold; and when the error signal is greater than the pull-down threshold, clamping the voltage value between the control end and the output end of the efuse switch to a preset voltage value. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other objects, features and advantages of the embodiments of the present invention will become readily understood by reading the following detailed description with reference to the accompanying drawings, in which several possible embodiments of the present invention are shown in an exemplary and non-limiting manner.

[0008] Figure 1 The figure shows a circuit structure diagram of a cfuse switch in the prior art.

[0009] Figure 2 FIG. 1 is a schematic diagram showing a principle of an efuse switch circuit 100 according to an embodiment of the present invention.

[0010] Figure 3 FIG. 5 is a schematic structural diagram of an open-loop pull-down circuit 50 according to an embodiment of the present invention.

[0011] Figure 4 FIG. 2 is a specific circuit schematic diagram of an efuse switch circuit 200 according to an embodiment of the present invention.

[0012] Figure 5 FIG. 2 is a schematic diagram showing a principle of an efuse switch circuit 300 according to another embodiment of the present invention.

[0013] Figure 6FIG. 4 is a flow chart of an efuse switch circuit control method 400 according to an embodiment of the present invention.

[0014] In the drawings, the same or corresponding reference numerals are used to designate the same or corresponding elements. DETAILED DESCRIPTION

[0015] The specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it is obvious to those of ordinary skill in the art that these specific details do not have to be used to implement the present invention. In other examples, in order to avoid confusing the present invention, known circuits, materials or methods are not specifically described.

[0016] Figure 2 FIG. 1 shows a functional block diagram of an efuse switch circuit 100 according to an embodiment of the present invention. Figure 2 As shown, the efuse switch circuit 100 includes an efuse switch 10 , a sampling circuit 20 , a closed-loop control circuit 30 , a driving circuit 40 and an open-loop pull-down circuit 50 .

[0017] exist Figure 2 In the illustrated embodiment, the efuse switch 10 may be coupled between the system input terminal IN and the system output terminal OUT. The current signal Ie flows from the system input terminal IN through the efuse switch 10 to the output terminal OUT. In one embodiment, the input terminal IN includes an output terminal of a power supply that can provide a power supply voltage signal, and the output terminal OUT includes an input terminal of a switching converter that can receive the power supply voltage signal provided by the power supply. In another embodiment, the input terminal IN includes an output terminal of a switching converter that can provide an output voltage signal, and the output terminal OUT includes an input terminal of a load that can receive the output voltage signal. It can be understood by a person skilled in the art that the input terminal IN and the output terminal OUT may include any terminals of an element, circuit or system that may need protection. The efuse switch 10 includes an input terminal, an output terminal and a control terminal. Among them, the input terminal of the efuse switch 10 is coupled to the system input terminal IN, and the output terminal is coupled to the system output terminal OUT. In Figure 2In the illustrated embodiment, the efuse switch 10 is schematically illustrated as an N-type metal oxide semiconductor field effect transistor (MOSFET) having a source S, a drain D, and a gate G. The input end of the efuse switch 10 is the source S of the N-type MOSFET, the output end is the drain D of the N-type MOSFET, and the control end is the gate G of the N-type MOSFET. It can be understood by those skilled in the art that the efuse switch 10 can be any suitable controllable semiconductor switch device, such as a P-type MOSFET, an insulated gate bipolar transistor (IGBT), a junction field effect transistor (JFET), and the like.

[0018] exist Figure 2 In the illustrated embodiment, the sampling circuit 20 is used to sample the current signal or voltage signal of the efuse switch 10 to generate a sampling signal Sense. In one embodiment, the sampling circuit 20 is a current sampling circuit that samples the current signal Ie flowing through the efuse switch 10. In this case, the sampling signal Sense represents the current signal Ie flowing through the efuse switch 10. In another embodiment, the sampling circuit 20 is a voltage sampling circuit that samples the input voltage signal V received at the input end of the efuse switch 10. IN At this time, the sampling signal Sense represents the input voltage signal V received by the input end of the efuse switch 10. IN .

[0019] exist Figure 2 In the illustrated embodiment, the closed-loop control circuit 30 is coupled to the sampling circuit 20 to receive the sampling signal Sense, and generates an error signal EA according to the sampling signal Sense. In one embodiment, the closed-loop control circuit 30 compares the sampling signal Sense with a reference signal, and amplifies the difference between the sampling signal Sense and the reference signal to generate the error signal EA. The error signal EA represents the difference between the sampling signal Sense and the reference signal. In one embodiment, the error signal EA represents the difference between the current signal flowing through the efuse switch 10 and the current signal expected to flow. In another embodiment, the error signal EA represents the input voltage signal V received at the input end of the efuse switch 10. IN The difference between the input voltage signal and the expected input voltage signal. In one embodiment, the error signal EA is a voltage signal. In other embodiments, the error signal EA may also be a current signal.

[0020] The driving circuit 40 receives the error signal EA and generates a driving signal DRV according to the error signal EA for driving the control terminal of the efuse switch 10. In one embodiment, the driving signal DRV is a voltage signal whose value changes according to the change of the error signal EA. The driving circuit 40 adjusts the gate-source voltage V between the gate G and the source S by changing the value of the driving signal DRV. GS value, thereby turning on the efuse switch 10 or adjusting the on-resistance value of the efuse switch 10.

[0021] The open-loop pull-down circuit 50 has a first end, a second end, and a third end. The first end of the open-loop pull-down circuit 50 is coupled to the closed-loop control circuit 30 to receive the error signal EA; the second end of the open-loop pull-down circuit 50 is coupled to the control end of the efuse switch 10; and the third end of the open-loop pull-down circuit 50 is coupled to the output end of the efuse switch 10. In one embodiment, the open-loop pull-down circuit 50 compares the error signal EA with a pull-down threshold. When the error signal EA is greater than the pull-down threshold, the open-loop pull-down circuit 50 electrically connects the control end of the efuse switch 10 and the output end of the efuse switch 10, and controls the current between the control end and the output end of the efuse switch 10 through the error signal, thereby increasing the gate-source voltage V GS The value of is clamped to a preset voltage value. In one embodiment, the preset voltage value is greater than the on-threshold VGS(TH) of the efuse switch 10. In one embodiment, the preset voltage value is an adaptive voltage value related to the device parameters of the efuse switch 10. In one embodiment, the adaptive voltage value is related to the maximum current value Imax allowed to flow through the efuse switch 10. In one embodiment, the preset voltage value is the gate-source voltage V when the current flowing through the efuse switch 10 is Imax. GS That is to say, when the error signal EA is greater than the pull-down threshold, the gate-source voltage V GS The gate-source voltage V will be clamped when the current flowing through the efuse switch 10 is Imax. GS to ensure that the current flowing through the efuse switch 10 does not exceed Imax. In one embodiment, the preset voltage value is 1.4V.

[0022] Figure 3 FIG. 5 is a schematic diagram of the structure of an open-loop pull-down circuit 50 according to an embodiment of the present invention. Figure 3 As shown, the open-loop pull-down circuit 50 includes a determination circuit 51 and an adaptive clamp circuit 52. The determination circuit 51 receives the error signal EA and compares the error signal EA with the pull-down threshold OC. TH In one embodiment, when the error signal EA is greater than the pull-down threshold OC, THWhen the error signal EA is less than the pull-down threshold OC, the pull-down indication signal OC is in a valid state; when the error signal EA is less than the pull-down threshold OC TH When the pull-down indication signal OC is in an invalid state. In one embodiment, the pull-down indication signal OC is a logic signal with a logic high and low level. In one embodiment, the logic high level of the pull-down indication signal OC is a valid state, and the logic low level of the pull-down indication signal OC is an invalid state.

[0023] The adaptive clamp circuit 52 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the adaptive clamp circuit 52 receives the pull-down indication signal OC; the second terminal of the adaptive clamp circuit 52 receives the error signal EA; the third terminal of the adaptive clamp circuit 52 is coupled to the control terminal (e.g., gate G) of the efuse switch 10; and the fourth terminal of the adaptive clamp circuit 52 is coupled to the output terminal (e.g., source S) of the efuse switch 10. When the pull-down indication signal OC is in the valid state, the adaptive clamp circuit 52 increases the voltage between its third terminal and the fourth terminal (i.e., gate-source voltage V GS ) is clamped to a preset voltage value. In one embodiment, the adaptive clamping circuit 52 controls the current flowing between the third terminal and the fourth terminal to remain unchanged through the error signal EA, thereby clamping the voltage value between the third terminal and the fourth terminal to a preset voltage value. In one embodiment, the adaptive clamping circuit 52 will provide a current discharge channel from its third terminal to the logic ground, and the current flowing through the current discharge channel is controlled by the error signal EA. In one embodiment, the larger the error signal EA, the larger the current flowing through the current discharge channel.

[0024] Figure 4 FIG. 1 is a specific circuit diagram of an efuse switch circuit 100 according to an embodiment of the present invention. Figure 4 In the illustrated embodiment, the sampling circuit 20 is illustrated as a current sampling circuit. A person skilled in the art will appreciate that in other embodiments, the sampling circuit may be other suitable voltage sampling circuits for sampling the input voltage signal V of the efuse switch 10. IN .exist Figure 4 In the embodiment, the sampling circuit 20 includes a sampling resistor 201 and an operational amplifier 202. The sampling resistor 201 is connected in series between the output terminal of the efuse switch 10 and the system output terminal OUT. The operational amplifier 202 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal and the second input terminal of the operational amplifier 202 are respectively coupled to the two ends of the sampling resistor 201, and outputs a sampling signal Sense at the output terminal, wherein the sampling signal Sense represents the current Ie flowing through the efuse switch 10. In other embodiments, the sampling resistor 201 can also be replaced by a transistor connected in parallel with the efuse switch 10.

[0025] exist Figure 4 In the illustrated embodiment, the closed-loop control circuit 30 is illustrated as an error amplifier 301. The error amplifier 301 has a first input terminal, a second input terminal, and an output terminal. The first terminal of the error amplifier 301 receives a sampling signal Sense; the second terminal of the error amplifier 301 receives a reference signal REF; the error amplifier 301 compares the sampling signal Sense with the reference signal REF, and amplifies the error between the two to generate an error signal EA.

[0026] exist Figure 4 In the illustrated embodiment, the determination circuit 51 is illustrated as a comparator 511. The comparator 511 has a first input terminal, a second input terminal and an output terminal. The first terminal of the comparator 511 receives the error signal EA; the second terminal of the comparator 511 receives the pull-down threshold OC TH The comparator 511 compares the error signal EA with the pull-down threshold OC TH Compare and generate a pull-down indication signal OC. Figure 4 In the embodiment shown, when the error signal EA is greater than the pull-down threshold OC TH , the pull-down indication signal OC is at a logic high level.

[0027] exist Figure 4 In the illustrated embodiment, the adaptive clamping circuit 52 includes a preset voltage generating module 521 , a clamping switch 522 , a first current mirror circuit 523 , a second current mirror circuit 524 , and a controllable current source 525 .

[0028] The preset voltage generating module 521 has a first end, a second end and a third end, wherein the first end is coupled to the control end of the efuse switch 10 , the second end is coupled to the output end of the efuse switch 10 , and the third end is coupled to the first end of the clamp switch 522 .

[0029] The first current mirror circuit 523 has a first end, a second end and a third end, wherein the first end is coupled to the control end of the efuse switch 10, the second end is coupled to the logic ground through the controllable current source 525, and the third end is coupled to the first end of the clamp switch 522. The magnitude of the controllable current source 525 is controlled by the error signal EA. In one embodiment, when the current Ie flowing through the efuse switch 10 is larger, the error signal EA is larger, and the first pull-down current signal Idrop1 generated by the controllable current source 525 is larger.

[0030] The second end of the second current mirror 524 has a first end, a second end and a third end, wherein the first end is coupled to the logic ground, the second end is coupled to the second end of the clamp switch 522 , and the third end is coupled to the control end of the efuse switch 10 .

[0031] The control end of the clamp switch 522 receives the pull-down indication signal OC. In one embodiment, when the pull-down indication signal OC is in a valid state, the clamp switch 522 is turned on, and at this time, the preset voltage generating module 521 electrically connects the control end of the efuse switch 10 and the output end of the efuse switch 10. The controllable current source 525 generates a first pull-down current signal Idrop1 at the second end of the first current mirror circuit 523. The first current mirror circuit 523 generates a second pull-down current signal Idrop2 at its first end after mirroring and amplifying the first pull-down current signal Idrop1 at the second end. The second current mirror circuit 524 mirrors and amplifies the sum of the second pull-down current signal Idrop2 received at its first end and the current signal outputted from the third end of the preset voltage generating module 521, and generates a third pull-down current signal Idrop3 at the second end of the second current mirror circuit 524. In one embodiment, when the current value of the current signal Ie flowing through the efuse switch 10 exceeds the expected current value, the greater the third pull-down current signal Idrop3 is, so that the voltage between the first end and the second end of the preset voltage generating module 521 is maintained at the preset voltage value. In another embodiment, when the input voltage V IN The greater the voltage value exceeds the expected input voltage value, the greater the third pull-down current signal Idrop3 is, so that the voltage between the first end and the second end of the preset voltage generating module 521 is maintained at the preset voltage value.

[0032] exist Figure 4 In the illustrated embodiment, the preset voltage generating module 521 includes a first transistor 5211 and a second transistor 5212. The first transistor 5211 and the second transistor 5212 have a gate, a source and a drain, respectively. In one embodiment, the first transistor 5211 is an N-type MOS transistor, and the second transistor 5212 is a P-type MOS transistor. At this time, the gate and the drain of the first transistor 5211 are coupled together, and the source of the first transistor 5211 is coupled to the source of the second transistor 5212. The gate of the second transistor 5212 is coupled to the output end of the efuse switch 10, and the drain of the second transistor 5212 is coupled to the first end of the clamp switch 522. Figure 4 In the illustrated embodiment, the N-type MOS tube 5211 is equivalent to a resistor with a resistance value of 1 / gm, wherein gm is the transconductance value of the N-type MOS tube 5211 when operating in the saturation region; the P-type MOS tube 5212 is a source follower, such that the source potential of the P-type MOS tube 5212 changes with the gate.

[0033] Figure 5 FIG. 4 shows a functional block diagram of an efuse switch circuit 300 according to another embodiment of the present invention. Figure 2 Compared with the efuse switch circuit 200 shown, Figure 5The efuse switch circuit 300 shown further includes a temperature determination circuit 60. The temperature determination circuit 60 detects the temperature of the efuse switch circuit 300 and determines whether the temperature of the efuse switch 10 is higher than a preset temperature value, thereby generating a temperature indication signal TC. Figure 5 In the illustrated embodiment, the driving circuit 40 generates the driving signal DRV based on the temperature indication signal TC and the error signal EA. In one embodiment, when the temperature indication signal TC indicates that the temperature of the efuse switch circuit 300 is higher than a preset temperature value, the driving signal DRV will turn off the efuse switch 10.

[0034] Figure 6 FIG. 4 is a flow chart of an efuse switch circuit control method 400 according to an embodiment of the present invention. Figure 6 The efuse switch circuit control method shown can be used to Figure 2 and Figure 4-5 The efuse switch circuit shown, and other efuse switch circuits within the protection scope of the present invention. Figure 6 In the illustrated embodiment, the efuse switch circuit control method 400 includes steps 410 - 450 .

[0035] Step 410, sampling the current or voltage parameter of the efuse switch and generating a sampling signal representing the current or voltage parameter of the efuse switch 10. In one embodiment, step 410 includes sampling the current flowing through the efuse switch 10 and generating a current sampling signal representing the current flowing through the efuse switch 10. In another embodiment, step 410 includes sampling the input voltage signal V at the input end of the efuse switch 10. IN , and generates an input voltage signal V representing the input terminal of the efuse switch 10 IN The voltage sampling signal.

[0036] Step 420, compare the sampled signal with the reference signal to generate an error signal. The error signal represents the difference between the sampled signal and the reference signal. The error signal is used to turn on the efuse switch 10 or adjust the magnitude of the on-resistance when the efuse switch 10 is turned on.

[0037] Step 430, determine the magnitude of the error signal and the pull-down threshold. If the error signal is greater than the pull-down threshold, go to step 440; otherwise, continue to execute step 430.

[0038] Step 440: clamp the voltage between the control terminal and the output terminal of the efuse switch 10 to a preset voltage value. In one embodiment, the preset voltage value is greater than the conduction threshold V GS(TH)In one embodiment, the preset voltage value is an adaptive voltage value, and the adaptive voltage value is related to the maximum current value Imax allowed to flow through the efuse switch 10. In one embodiment, the preset voltage value is the gate-source voltage V when the current flowing through the efuse switch 10 is Imax. GS That is to say, when the error signal EA is greater than the pull-down threshold, the gate-source voltage V GS The gate-source voltage V will be clamped when the current flowing through the efuse switch 10 is Imax. GS to ensure that the current flowing through the efuse switch 10 does not exceed Imax. In one embodiment, the preset voltage value is 1.4V.

[0039] Throughout the specification, reference to "one embodiment", "an embodiment", "an example" or "an example" means that a particular feature, structure or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment", "in an embodiment", "an example" or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, specific features, structures or characteristics can be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes, and the drawings are not necessarily drawn to scale. It should be understood that when an "element" is said to be "connected to" or "coupled" to another element, it can be directly connected or coupled to another element or there can be an intermediate element. On the contrary, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The same reference numerals indicate the same element. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0040] Although the present invention has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present invention can be embodied in a variety of forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. An electronic fuse efuse switching circuit, comprising: An efuse switch has an input terminal, an output terminal and a control terminal; a closed-loop control circuit, receiving a sampling signal representing a current signal flowing through the efuse switch, and comparing the sampling signal with a reference signal to generate an error signal, wherein the error signal represents a difference between the sampling signal and the reference signal; and An open-loop pull-down circuit has a first end, a second end and a third end, the first end of the open-loop pull-down circuit receives an error signal, the second end of the open-loop pull-down circuit is coupled to the control end of the efuse switch, and the third end of the open-loop pull-down circuit is coupled to the output end of the efuse switch, wherein when the error signal is greater than a pull-down threshold, the open-loop pull-down circuit clamps the voltage between the control end of the efuse switch and the output end of the efuse switch to a preset voltage value to limit the current flowing through the efuse switch.

2. The efuse switch circuit according to claim 1, wherein: When the error signal is greater than the pull-down threshold, the open-loop pull-down circuit controls the current between the control end of the efuse switch and the output end of the efuse switch through the error signal, thereby clamping the voltage between the control end of the efuse switch and the output end of the efuse switch to a preset voltage value.

3. The efuse switch circuit according to claim 1, wherein: The preset voltage value is greater than the conduction threshold of the efuse switch.

4. The efuse switch circuit according to claim 1, wherein: The preset voltage value is an adaptive voltage value, which is related to the maximum current value allowed to flow through the efuse switch.

5. The efuse switch circuit as claimed in claim 4, wherein: The preset voltage value is equal to the voltage value between the efuse switch control terminal and the efuse switch output terminal when the current flowing through the efuse switch is equal to the maximum current value allowed to flow.

6. The efuse switch circuit as claimed in claim 1, wherein: The open-loop pull-down circuit includes: A determination circuit receives the error signal, compares the error signal with a pull-down threshold, and generates a pull-down indication signal; and An adaptive clamping circuit has a first end, a second end, a third end and a fourth end. The first end of the adaptive clamping circuit receives a pull-down indication signal, the second end of the adaptive clamping circuit receives an error signal, the third end of the adaptive clamping circuit is coupled to the control end of the efuse switch, and the fourth end of the adaptive clamping circuit is coupled to the output end of the efuse switch. When the pull-down indication signal is in a valid state, the adaptive clamping circuit controls the current flowing between the third end and the fourth end through the error signal to remain unchanged.

7. The efuse switch circuit as claimed in claim 6, wherein: The adaptive clamping circuit includes: A preset voltage generating module, having a first end, a second end and a third end, the first end of the preset voltage generating module serving as the third end of the adaptive clamping circuit, and the second end of the preset voltage generating module serving as the fourth end of the adaptive clamping circuit; A clamp switch having a first end, a second end and a control end, wherein the first end of the clamp switch is coupled to the third end of the preset voltage generating module, and the control end of the clamp switch serves as a first end of the adaptive clamp circuit to receive a pull-down indication signal; A controllable current source has a first terminal, a second terminal and a control terminal, the first terminal of the controllable current source is electrically connected to a logic ground, and the control terminal of the controllable current source serves as a second terminal of the adaptive clamping circuit to receive an error signal; a first current mirror circuit, having a first end, a second end and a third end, the first end of the first current mirror circuit being coupled to the first end of the preset voltage generating module, the second end of the first current mirror circuit being coupled to the second end of the controllable current source, and the third end of the first current mirror circuit being coupled to the first end of the clamp switch; and The second current mirror circuit has a first end, a second end and a third end. The first end of the second current mirror circuit is coupled to the logic ground, the second end of the second current mirror circuit is coupled to the second end of the clamp switch, and the third end of the second current mirror circuit is coupled to the first end of the preset voltage generating module.

8. The efuse switch circuit as claimed in claim 7, wherein: The preset voltage generation module includes: A first transistor having a first end, a second end and a control end, wherein the first end and the control end of the first transistor are coupled together as a first end of a preset voltage generating module; and The second transistor has a first end, a second end and a control end. The first end of the second transistor serves as the third end of the preset voltage generating module. The second end of the second transistor is coupled to the second end of the first transistor. The control end of the second transistor serves as the second end of the preset voltage generating module.

9. The efuse switch circuit according to claim 1, wherein: The closed-loop control circuit no longer receives a sampling signal representing a current signal flowing through the efuse switch, but instead receives a sampling signal representing an input voltage signal received at the input end of the efuse switch.

10. The efuse switch circuit as claimed in claim 1, further comprising a temperature determination circuit, wherein: The temperature judgment circuit detects the temperature of the efuse switch. When the temperature of the efuse switch is higher than a preset temperature value, the efuse switch is turned off.

11. A control method for an efuse switch circuit, comprising: sampling a current signal flowing through the efuse switch and generating a sampling signal representing the current signal flowing through the efuse switch; Comparing the sampled signal with a reference signal to generate an error signal, wherein the error signal represents a difference between the sampled signal and the reference signal; Determining the magnitude of the error signal and the pull-down threshold; and When the error signal is greater than the pull-down threshold, the voltage value between the control terminal and the output terminal of the efuse switch is clamped to a preset voltage value to limit the current flowing through the efuse switch.

12. The control method according to claim 11, wherein: The step of sampling the current signal flowing through the efuse switch and generating a sampling signal representing the current signal flowing through the efuse switch can be replaced by sampling the input voltage signal received at the input end of the efuse switch and generating a sampling signal representing the input voltage signal received at the input end of the efuse switch.

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