Multi-gate transistor

Abstract

A multi-gate transistor is disclosed, comprising a source, a drain separated from the source, a semiconductor region disposed between the source and the drain, and an insulating region disposed above the semiconductor region. The multi-gate transistor also includes: a current control gate for controlling the magnitude of a current flowing between the source and the drain through the semiconductor region according to a first electric field applied to the current control gate, the current control gate being separated from the source by the semiconductor region and the insulating region; and a switch gate for allowing a current to flow between the source and the drain through the semiconductor region according to a second electric field applied to the switch gate. The conduction state (i.e., on / off) of the transistor can be controlled by changing the second electric field applied to the switch gate, and the magnitude of the current passing through the multi-gate transistor can be set by changing the first electric field applied to the current control gate.

Description

Technical Field

[0001] The present invention relates to semiconductor transistor technology. More specifically, the present invention relates to a transistor including a source, a drain and a plurality of gates. Background Art

[0002] Printing electronic devices on flexible substrates has gained increasing attention, especially for large-area electronics such as display technology, sensors, wearable devices, and other applications where roll-to-roll manufacturing would allow for rapid, cost-effective manufacturing. However, several limitations have been encountered, most notably poor device performance under electrical stress, which typically limits circuit speeds to hundreds of kilohertz (kHz).

[0003] Transistors have been developed in which the source contact contains a barrier, such as a Schottky contact, the gate overlaps the source, and the semiconductor is thin enough to allow the voltage applied to the drain contact to completely deplete the free carriers at the source edge of the semiconductor. Such transistors are often called source-gated transistors (SGTs). SGTs offer several advantages over conventional field-effect thin-film transistors (FETs), including lower operating voltages, reduced power consumption, and high gain due to low output conductance.

[0004] These advantages make SGTs particularly suitable for use in large-area flexible electronic devices where current uniformity is required. However, a significant disadvantage of the SGT design is its speed. Due to its lower drain current compared to FETs or other types of TFTs, the transconductance is reduced, which in turn affects the operating frequency and limits the SGT to a switching speed that is much lower than the switching speed of a TFT of the same geometry. Therefore, SGTs are not suitable for radio frequency (RF) and other high-speed applications. Therefore, there is a need in the art for a transistor that provides the advantages of SGTs with faster switching speeds. Summary of the invention

[0005] According to a first aspect of the present invention, a multi-gate transistor is provided, which includes: a source; a drain, which is separated from the source; a semiconductor region, which is arranged between the source and the drain; an insulating region, which is arranged above the semiconductor region; a current control gate, which is used to control the magnitude of the current flowing between the source and the drain through the semiconductor region according to a first electric field applied to the current control gate, and the current control gate is separated from the source by the semiconductor region and the insulating region; and a switch gate, which is used to allow the current to flow between the source and the drain through the semiconductor region according to a second electric field applied to the switch gate.

[0006] In some embodiments according to the first aspect, the drain is laterally spaced apart from the source, the semiconductor region is disposed above the source and the drain, and the current control gate and the switch gate are disposed on a side of the semiconductor region opposite the source and the drain.

[0007] In some embodiments according to the first aspect, the current control gate and the switch gate are disposed at the same height above the source and the drain, wherein the current control gate or the switch gate further comprises a portion extending above a gap separating the current control gate from the switch gate.

[0008] In some embodiments according to the first aspect, the portion of the current control gate or the switch gate extends at least to the same lateral position as an adjacent edge of the other of the current control gate and the switch gate, and the portion of the current control gate or the switch gate is longitudinally separated from the edge of the other of the current control gate and the switch gate.

[0009] In some embodiments according to the first aspect, the current control gate is longitudinally offset from the switch gate.

[0010] In some embodiments according to the first aspect, the current control gate extends at least to an edge of the switch gate in a lateral direction, and the current control gate is longitudinally separated from the switch gate by an electrical insulation region.

[0011] In some embodiments according to the first aspect, the switch gate is configured to cause a conductive layer to be generated in a portion of the semiconductor region between the source and the drain when a second electric field is applied to the switch gate.

[0012] In some embodiments according to the first aspect, the multi-gate transistor also includes a gate terminal disposed above at least a portion of the current control gate and at least a portion of the switch gate, wherein a third electric field sufficient to generate the first and second electric fields is applied to the gate terminal, and wherein the current control gate and the switch gate act as floating gates.

[0013] In some embodiments according to the first aspect, the gate terminal extends across the length of the current control gate and the switch gate.

[0014] In some embodiments according to the first aspect, the multi-gate transistor includes a plurality of switch gates including the switch gate, wherein each of the plurality of switch gates is electrically isolated from other switch gates of the plurality of switch gates, so that current is allowed to flow between the source and the drain through the semiconductor region only when a voltage applied to each of the plurality of switch gates is equal to or greater than a corresponding switching threshold voltage of the switch gate of the plurality of switch gates.

[0015] In some embodiments according to the first aspect, the multi-gate transistor further comprises: a plurality of inputs, each input being connected to a corresponding switch gate among the plurality of switch gates; and an output connected to the drain, such that the multi-gate transistor is configured to perform an AND function by allowing current to flow at the output only when the voltage at all of the plurality of inputs is equal to or greater than a switch threshold voltage.

[0016] In some embodiments according to the first aspect, the multi-gate transistor includes a plurality of current control gates including the current control gate, wherein the plurality of current control gates are spaced apart from each other in a direction parallel to an edge of the source adjacent to a channel between the source and the drain, and each is configured to receive a corresponding input voltage among a plurality of input voltages, so that a magnitude of a current flowing between the source and the drain depends on the plurality of input voltages.

[0017] In some embodiments according to the first aspect, each current control gate of the plurality of current control gates is configured to receive a corresponding digit of an input digital codeword comprising a plurality of digits, such that the multi-gate transistor is configured to convert the input digital codeword into an analog output current at the drain.

[0018] In some embodiments according to the first aspect, the multiple digits of the input digital codeword include n bits, and the multi-gate transistor includes n current control gates, each current control gate has a different overlap area with the source, and wherein the overlap area of ​​the current control gates increases from the first current control gate to the nth current control gate in a geometric series following a common ratio r=2.

[0019] In some embodiments according to the first aspect, the semiconductor region includes: a first doped region between the source and the first gate; and a second doped region disposed in the channel between the source and the drain.

[0020] In some embodiments according to the first aspect, the first doped region is configured to operate in a normally-on mode and the second doped region is configured to operate in a normally-off mode, or the first doped region is configured to operate in a normally-off mode and the second doped region is configured to operate in a normally-on mode.

[0021] In some embodiments according to the first aspect, the multi-gate transistor includes an auxiliary gate disposed on a side of the semiconductor region opposite to the switch gate, wherein a threshold voltage of the switch gate allowing current to flow between the source and the drain depends on a voltage applied to the auxiliary gate.

[0022] In some embodiments according to the first aspect, the multi-gate transistor comprises a field mitigation element configured to extend beyond an edge of the source closest to the drain in a direction towards the drain so as to at least partially shield the source from an electric field in the channel between the source and the drain.

[0023] In some embodiments according to the first aspect, the first electric field and / or the second electric field is an applied voltage, or an electric field generated by incident electromagnetic radiation via the photovoltaic effect, or an electric field generated by chemical adsorption.

[0024] According to a second aspect of the present invention, there is provided a method for operating a multi-gate transistor, the multi-gate transistor comprising: a source; a drain separated from the source; a semiconductor region arranged between the source and the drain; an insulating region arranged above the semiconductor region; a current control gate for controlling the magnitude of a current flowing between the source and the drain through the semiconductor region according to a first electric field applied to the current control gate, the current control gate being separated from the source by the semiconductor region and the insulating region; and a switch gate for allowing a current to flow between the source and the drain through the semiconductor region according to a second electric field applied to the switch gate, the method comprising: applying a second electric field to the switch gate to allow a current to flow in the semiconductor region between the source and the drain; and using the current control gate to control the magnitude of the current flowing in the semiconductor region between the source and the drain.

[0025] In some embodiments according to the second aspect, the applied second electric field is greater than or equal to the threshold switching field.

[0026] In some embodiments according to the second aspect, controlling the magnitude of the current using the current control gate comprises: applying a first electric field to the current control gate, and subsequently turning on the multi-gate transistor by increasing a second electric field applied to the switch gate to at least a threshold switch field.

[0027] In some embodiments according to the second aspect, the multi-gate transistor includes a plurality of switch gates including the switch gate, each of the plurality of switch gates being electrically isolated from other switch gates of the plurality of switch gates, so that current is allowed to flow between the source and the drain through the semiconductor region only when a corresponding second electric field applied to each of the plurality of switch gates is equal to or greater than a corresponding switching electric field of the switch gate of the plurality of switch gates, and the method further includes: applying a corresponding second electric field greater than or equal to a corresponding threshold switching electric field to each of the plurality of switch gates.

[0028] In some embodiments according to the second aspect, each of the plurality of inputs is connected to a corresponding switch gate of the plurality of switch gates and the output is connected to the drain, so that the multi-gate transistor is configured to perform an AND function by allowing current to flow at the output only when the corresponding second electric field at all the plurality of inputs is equal to or greater than the corresponding switch electric field. In addition, the magnitude of the output current can be controlled by changing the first electric field applied to the current control gate.

[0029] In some embodiments according to the second aspect, the first electric field and / or the second electric field is an applied voltage, or an electric field generated by incident electromagnetic radiation via the photovoltaic effect, or an electric field generated by chemical adsorption. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0031] Figure 1 A multi-gate transistor including a current control gate and a switch gate according to an embodiment of the present invention is shown;

[0032] Figure 2 shows examples of Mode I and Mode II currents of a multi-gate transistor operating in a mode similar to a source-gated transistor (SGT) according to an embodiment of the present invention;

[0033] Figure 3 A multi-gate transistor including a current control gate longitudinally offset from a switch gate according to an embodiment of the present invention is shown;

[0034] Figure 4 shows a timing diagram according to an embodiment of the present invention, which shows the voltage ramp on the current control gate of the multi-gate transistor before abruptly switching the transistor by increasing the voltage on the switch gate;

[0035] Figure 5 is a graph comparing the transient response of a multi-gate transistor according to an embodiment of the present invention with the transient response of an SGT and a field effect transistor (FET) having similar device geometry;

[0036] Figure 6 A multi-floating-gate transistor including two floating gates according to an embodiment of the present invention is shown;

[0037] Figure 7 An example of a floating gate (FG) SGT is shown;

[0038] Figure 8 is a diagram showing an example of output characteristics of an SGT and an FG SGT according to an embodiment of the present invention;

[0039] Fig. 9is a diagram comparing output characteristics of a floating gate multi-gate transistor (FG MGT) with examples of an SGT and an FG SGT according to an embodiment of the present invention;

[0040] Fig.10 A multi-gate transistor including a plurality of switch gates according to an embodiment of the present invention is shown;

[0041] Fig.11 A multi-gate transistor including a plurality of switch gates according to an embodiment of the present invention is shown;

[0042] Fig.12 A multi-gate transistor including a plurality of switch gates disposed at different heights above a source-drain gap according to an embodiment of the present invention is shown;

[0043] Fig.13 A multi-gate transistor according to an embodiment of the present invention is shown, comprising a first doped region and a second doped region extending across the entire thickness of a semiconductor region;

[0044] Fig.14 A multi-gate transistor according to an embodiment of the present invention is shown, comprising a first doped region and a second doped region extending partially across a semiconductor region;

[0045] Fig.15 A multi-gate transistor according to an embodiment of the present invention is shown, comprising a doped region extending across the source and the channel and extending across the entire thickness of the semiconductor region;

[0046] Fig.16 A multi-gate transistor according to an embodiment of the present invention is shown, comprising a doped region extending across a source and a channel and extending partially across a semiconductor region;

[0047] Fig.17 A multi-gate transistor according to an embodiment of the present invention is shown, which includes an auxiliary gate electrode disposed on a side of the channel opposite to the switch gate;

[0048] Fig.18 A multi-gate transistor including field mitigation structures in the source and drain is shown according to an embodiment of the present invention;

[0049] Fig.19 shows a multi-gate transistor including a field mitigation electrode according to an embodiment of the present invention;

[0050] Fig. 20 A multi-gate transistor according to an embodiment of the present invention is shown, comprising a tunnel layer disposed between a source and a semiconductor region;

[0051] Fig.21A multi-gate transistor according to an embodiment of the present invention is shown, which includes a barrier formed by doping a semiconductor region above a source;

[0052] Fig. 22 A multi-gate transistor according to an embodiment of the present invention is shown, which includes a heterostructure barrier formed by a second semiconductor material disposed between a source and a semiconductor region;

[0053] Fig.23 A multi-gate transistor including a switch gate electrode and a floating current control gate according to an embodiment of the present invention is shown;

[0054] Fig.24 A multi-gate transistor according to an embodiment of the present invention is shown, comprising a plurality of input terminals disposed above a floating current control gate;

[0055] Fig.25 A multi-gate transistor including a plurality of current control gates according to an embodiment of the present invention is shown, wherein the plurality of current control gates have different overlapping areas with a source;

[0056] Fig.26 A multi-gate transistor according to an embodiment of the present invention is shown, wherein the drain is arranged on a side of the semiconductor region opposite to the source;

[0057] Fig. 27 A multi-gate transistor according to an example is shown, wherein a current control gate and a switch gate are disposed on the same side of a semiconductor region as a source and a drain; and

[0058] Fig.28 A multi-gate transistor according to an example is shown, which includes a semiconductor region in the form of a nanowire. DETAILED DESCRIPTION

[0059] In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described by way of illustration only. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways, all without departing from the scope of the present invention. Therefore, the accompanying drawings and descriptions are to be considered illustrative rather than restrictive in nature. Throughout the specification, similar reference numerals designate similar elements.

[0060] For convenience, in the following description, various device geometries according to embodiments of the present invention are described with respect to the device in the orientation shown in the accompanying drawings. Where terms such as "above", "above", "lateral", "vertical" and the like are used in the description, these should not be interpreted as meaning that such embodiments are limited to the specific orientation shown in the accompanying drawings. It should be readily understood that the devices described herein will be able to operate correctly regardless of the physical orientation of the device or the physical orientation of the apparatus in which the device is included, and therefore the following description should be interpreted accordingly. In addition, transistors according to embodiments of the present invention include a semiconductor region, which may include a semiconductor, a semimetal or a degenerately doped semiconductor, or a combination thereof. Therefore, references to "semiconductor region" herein should be interpreted accordingly.

[0061] Reference now Figure 1 , according to an embodiment of the present invention, a multi-gate transistor including a current control gate and a switch gate is shown. The multi-gate transistor 100 includes a source 101, a drain 102, a first gate 103 and a second gate 104. The source 101 and the drain 102 are spaced apart from each other and separated by a semiconductor region 105. In other words, the source 101 and the drain 102 are separated by the semiconductor region 105. The contact between the source 101 and the semiconductor 105 includes a potential barrier. For example, the potential barrier between the source 101 and the semiconductor region 105 can be provided by selecting suitable materials for the source 101 and the semiconductor region 105, by doping the materials of the source 101 and / or the semiconductor region 105, or by forming a heterojunction contact between two or more semiconductor materials.

[0062] The source 101, the drain 102, the first gate 103, the second gate 104, and the semiconductor region 105 may each be formed of any suitable material or combination of materials. Examples of materials that can be used for the source 101, the drain 102, the first gate 103, and / or the second gate 104 include, but are not limited to: metals; conductive or semiconductive metal oxides; conductive or semiconductive polymers; doped semiconductors; graphene; and two-dimensional (2D) semiconductors. Examples of materials that can be used for the semiconductor region 105 include, but are not limited to: crystalline or amorphous silicon; semiconductive metal oxides; transition metal chalcogenides; graphene; carbon nanotubes; semiconductive nanowires; organic semiconductors; and 2D semiconductors.

[0063] The first gate 103 is disposed over at least a portion of the source 101 and is separated from the source 101 by a semiconductor region 105 and by an electrical insulator 106 disposed over the semiconductor region 105. The electrical insulator 106 may generally be referred to as an "insulating region" and may include the same material throughout the device or may include different insulating materials in different portions of the device. The region of the semiconductor material 105 above the source 101 may be referred to as the "source region" of the semiconductor 105. When a potential difference greater than a certain threshold is applied to the first gate 103, an accumulation layer is formed in the source region at the interface between the semiconductor 105 and the insulator 106. Similarly, the second gate 104 is disposed over the gap 107 between the source 101 and the drain 102 and is separated from the source 101 and the drain 102 by the semiconductor region 105 and by the electrical insulator 106. Depending on the embodiment, the second gate 104 may or may not overlap vertically with the drain 102. When a potential difference greater than a certain threshold is applied to the second gate 104 , an accumulation layer is formed in the gap 107 between the source 101 and the drain 102 (also called “source-drain gap” or “channel” 107 ) at the interface between the semiconductor 105 and the insulator 106 .

[0064] In this embodiment, the applied electric field on the second gate 104 is an applied voltage. However, in another embodiment, the applied electric field on the second gate 104 can be an electric field generated by incident electromagnetic radiation via the photovoltaic effect. In this way, the transistor can operate as a phototransistor. Similarly, the electric field applied to the first gate 103 can either be an applied voltage or an electric field generated by incident electromagnetic radiation via the photovoltaic effect.

[0065] As another alternative, in some embodiments, the electric field applied to the first gate 103 and / or the second gate 104 may be generated via a chemical reaction, such as adsorption of molecules on the surface of the first gate 103 or the second gate 104. Such an embodiment may be used in sensor applications because the absence / presence of an output current or its magnitude may indicate the presence or absence of a particular chemical species that is capable of being adsorbed onto the surface of the first gate 103 or the second gate 104. When chemical adsorption is used to generate the electric field in a floating gate embodiment, such as the following reference Figure 6 and Fig.23 Those described, adsorption may occur at the control gate above the floating first gate and / or second gate, thereby causing an electric field to be generated across the floating first gate and / or second gate.

[0066] In some embodiments, the multi-gate transistor 100 may include an interfacial layer between the source 101 and the semiconductor region 105 for controlling the characteristics of the barrier. For example, the interfacial layer may be formed by depositing a different material on the source 101 before depositing the semiconductor region 105, or by doping the surface region of the source 101. As another example, in some embodiments, the interfacial layer may be formed by treating the source material before depositing the semiconductor region 105 (e.g., by oxidizing the surface of the source 101 before depositing the semiconductor region 105, or applying a suitable chemical treatment to change the surface chemistry of the source material).

[0067] In some embodiments, source 101 may not directly overlap first gate 103, but a region of semiconductor 105 on one side of source 101 may be doped to provide a region overlapping first gate 103. As another alternative, in some embodiments, a different material (e.g., another metal) may be deposited to one side of source metallization 101 in the direction of drain 102, and first gate 103 may be formed over and overlapping this region of the other material adjacent to source 101.

[0068] In the present embodiment, the source 101 and the drain 102 are arranged so that when a potential difference greater than a certain threshold is applied across the source 101 and the drain 102, a depletion layer is formed in the semiconductor region 105 adjacent to the source 101 across the entire cross-section of the semiconductor layer 105 at the edge of the source 101 closest to the drain 102. In the present embodiment, the source 101 includes a single continuous layer, but in other embodiments, the source 101 may include a plurality of separate portions electrically connected in parallel to the semiconductor region 105. In some embodiments, a depletion layer may not be formed across the entire cross-section of the semiconductor layer 105, although device performance may be impaired due to an increase in saturation voltage and a reduction in intrinsic gain. Compared to the embodiments of the present invention (which function in a manner similar to SGT by forming a depletion region at the edge of the source 101, which allows source pinch-off), the field effect transistor uses a field effect to modulate current and may form a depletion region at the drain edge so that pinch-off occurs at the drain. Generally speaking, a transistor according to an embodiment of the present invention may be configured to allow source pinch-off by forming a depletion region at an edge of the source 101 closest to the drain 102 .

[0069] The first gate 103 and the second gate 104 are configured together so that a continuous conductive layer is generated at the interface between the semiconductor region 105 and the insulator 106. In the present embodiment, the conductive layer is an accumulation layer, but in other embodiments, an inversion layer may be formed as the conductive layer. In this context, "continuous" means that the conductive layer extends from the drain 102, extends across the gap 107 between the source 101 and the drain 102, and extends over at least a portion of the source 101. The conductive layer thus provides a path for current to flow between the source 101 and the drain 102 in the semiconductor region 105. In this way, when the correct voltage is applied to both the first gate 103 and the second gate 104, the multi-gate transistor 100 functions in a manner similar to a conventional SGT.

[0070] You can refer to Figure 2 The Mode I current and Mode II current are shown to understand Figure 1 Operation of the multi-gate transistor 100 . Figure 2 The figure in shows an example of a multi-gate transistor 100 according to an embodiment of the present invention when operating in a mode similar to SGT. This operating mode of the multi-gate transistor 100 can be called a "quasi-SGT" mode. In the SGT-like operating mode, there are two different current modes due to the source pinch-off effect. The mode I current I1 is determined by the electric field in the depletion region 205a at the tip of the source 101. This can be called a high field mode. The mode I current has a high temperature coefficient and a high electric field dependence.

[0071] The mode II current I2 is injected along the remaining length of the source 101 (i.e., away from the source-drain gap) and encounters resistance in the horizontal accumulation layer 205b as it travels along the length of the source 101 through the semiconductor 105. It should be understood that, in effect, charge is injected along the source 101, and the movement of these charges is referred to as the mode II current I2. Therefore, references to the "injection" of current should be interpreted accordingly. When the mode II current is injected from the source contact 101 and passes through the semiconductor 105, it also encounters resistance vertically, so the mode II current is measured in ohms in nature. Therefore, subject to proper device design in terms of selection of materials and layer thicknesses, the mode II current is linearly proportional to the voltage applied to the first gate 103. The total current I flowing into the drain 102 D Equal to the sum of the mode I current and the mode II current, that is, I D =(I1+I2).

[0072] As described above, in this embodiment, when the correct voltage is applied to both the first gate 103 and the second gate 104, the multi-gate transistor 100 functions in a similar manner to a conventional SGT. However, unlike a conventional SGT, the multi-gate transistor 100 of this embodiment includes multiple gates 103, 104. The magnitude of the mode I and mode II currents can be controlled by changing the electric field applied to the first gate 103 (e.g., by changing the voltage applied to the first gate 103). By providing Figure 1 and Figure 2 The first gate 103 and the second gate 104 are shown, the first gate 103 can be used to control the injection from the source electrode 101, and the second gate 104 can be used to control the conductive channel between the source 101 and the drain 102. Therefore, the first gate 103 is hereinafter referred to as a "current control gate", and the second gate 104 is hereinafter referred to as a "switch gate".

[0073] In addition, by appropriately designing the current control gate 103 to make the source 101 avoid the electric field generated by the switch gate 104, the coupling of the switch gate 104 with the source 101 can be reduced. For example, in the present embodiment, the current control gate 103 includes an extension portion 103a, which is suspended above the gap between the current control gate 103 and the switch gate 104. The extension portion 103a is used to make the source 101 avoid the influence of the switch gate 104. Since the current control gate 103 is separated from the switch gate 104 by the insulator 106, different voltages can be applied to the current control gate 103 and the switch gate 104, and the current control gate 103 can electrically shield the source 101 from the potential difference applied to the switch gate 104. In this way, since the drain 102 voltage and the switch gate 104 voltage will not affect the amount of injected current, the device operation can be improved. When a voltage is applied to the switch gate 104, current is allowed to flow within the semiconductor region 105 in the gap 107 between the source 101 and the drain 102. This can be considered as switching the transistor from "off" to "on", so the second gate 104 can be called a "switch gate". At the same time, the magnitude of the current flowing between the source 101 and the drain 102 is determined by the potential applied to the current control gate 103.

[0074] Since the current flowing between the source 101 and the drain 102 is linearly proportional to the current control gate 103 voltage, the multi-gate transistor 100 can be considered to behave as a linear variable resistor or a linear voltage-controlled current source with an integrated switch in a single device. If the switch gate 104 is "on", meaning that the voltage applied to the switch gate 104 is above a certain threshold, and the voltage on the current control gate 103 is also below the corresponding threshold of the current control gate 103, the device remains "off" and no current will flow between the source 101 and the drain 102. Therefore, the switch gate 104 controls the on / off behavior, and the current control gate 103 controls the device as a linear current source when the transistor 100 is in the "on" state.

[0075] Therefore, by providing a separate current control gate 103 and switch gate 104, the conduction state (on / off) of the device can be controlled in a portion of the device (i.e., by changing the voltage applied to the switch gate 104), and the magnitude of the current passing through the multi-gate transistor 100 can be set in a separate portion of the device (i.e., by changing the voltage applied to the current control gate 103).

[0076] In some embodiments, transistor 100 may operate in a "subthreshold" state, where the voltage applied to switch gate 104 is less than the threshold voltage. Although transistor 100 may not be considered "fully on" in this state, some current may still flow between source 101 and drain 102 at voltages close to the threshold voltage. In this region of the IV curve of transistor 100, drain current I D Variance varies exponentially with the voltage applied to the switch gate 104 .

[0077] exist Figure 1 In the illustrated embodiment, the drain 102 is laterally spaced apart from the source 101, the semiconductor region 105 is disposed above the source 101 and the drain 102, and the current control gate 103 and the switch gate 104 are disposed on a side of the semiconductor region 105 opposite the source 101 and the drain 102. However, in other embodiments, different device geometries are possible. For example, in some embodiments, the drain may be disposed above the source, and the control gate and the switch gate may be disposed on one side of the source and the drain.

[0078] In the present embodiment, the current control gate 103 and the switch gate 104 are disposed at the same height above the source 101 and the drain 102. To keep the two gates separated, the current control gate 103 and the switch gate 104 are spaced apart from each other and separated by an electrical insulator 106. In addition, to achieve a continuous electric field across the source 101 and the source-drain gap 107, the current control gate 103 includes a portion 103a extending over the gap separating the current control gate 103 from the switch gate 104. In other embodiments, a similar extension portion may be formed by the switch gate 104 instead of the current control gate 103. However, it may be advantageous to form the extension portion 103a as part of the current control gate 103 (rather than the switch gate 104) because the extension portion 103a formed by the current control gate 103 may help keep the source 101 away from the switch gate 104, as described above.

[0079] like Figure 1 As shown, a portion of the current control gate 103 or the switch gate 104 may extend to at least the same lateral position as an adjacent edge of the other of the current control gate 103 and the switch gate 104, so that a continuous electric field can be maintained over the source 101 and the source-drain gap 107. In some embodiments, the extension portion 103a may overlap the switch gate 104, which means that a portion of the extension portion 103a is directly above a portion of the switch gate 104. In addition, the extension portion 103a is longitudinally separated from an edge of the other of the current control gate 103 and the switch gate 104 to ensure that the current control gate 103 and the switch gate 104 are electrically isolated from each other within the device.

[0080] In another embodiment, Figure 3 As shown, the current control gate and the switch gate may be longitudinally offset from each other. Figure 3 The multi-gate transistor 300 shown is similar to Figure 1 The multi-gate transistor 100 of the present embodiment includes a source 301, a drain 302, a current control gate 303, a switch gate 304, a semiconductor region 305 and an insulator 306. Figure 1The multi-gate transistor 100 of FIG. 1 is different in that the current control gate 303 is longitudinally offset from the switch gate 304. In other words, if the source 301 and the drain 302 are disposed at the same height within the layer structure of the multi-gate transistor 300, the vertical distance d1 between the source 301 and the current control gate 303 may be different from the vertical distance d2 between the source-drain gap 307 and the switch gate 304. In addition, the upper edge of the switch gate 304 is spaced apart from the lower edge of the current control gate 303 by a distance d3, such that the current control gate 303 and the switch gate 304 do not contact each other. It will be readily appreciated that the opposite arrangement may be used in other embodiments, that is, the current control gate 303 may be disposed at a lower height than the switch gate 304.

[0081] By positioning the current control gate 303 and the switch gate 304 at different heights, the current control gate 303 can extend in the lateral direction at least to the edge of the switch gate 304 without contacting the switch gate 304. This arrangement can therefore also provide a continuous electric field across the source 301 and the source-drain gap 307 while keeping the current control gate 303 and the switch gate 304 separated. Figure 1 This arrangement may also enable a simplified manufacturing process compared to the device geometry shown, as the current control gate 303 and the switch gate 304 may each be formed as a single planar layer within the multi-gate transistor 300 .

[0082] However, in some embodiments, the current control gate 103, 103a, 303 and the switch gate 104, 304 may not together completely cover the entire length of the gap 107, 307 between the source 101, 301 and the drain 102, 302. Figures 1 to 3 In the device orientation shown, the rightmost edge of the current control gate 103, 303 and any extension 103a can be laterally spaced from the leftmost edge of the switch gate 104, 304, so that a portion of the source-drain gap 107, 307 is neither covered by the current control gate 103, 103a, 303 nor by the switch gate 104, 304. For example, the rightmost edge of the current control gate 103, 303 and any extension 103a can be laterally spaced from the leftmost edge of the switch gate 104, 304 by a relatively small gap on the order of one micron or less. It will be understood that such a gap may naturally occur due to manufacturing tolerances, depending on the manufacturing process used. In general, such gaps should be minimized or avoided because as the size of the gap between the current control gate 103, 103a, 303 and the switch gate 104, 304 increases, device linearity and energy efficiency may be negatively affected.

[0083] exist Figure 1 and Figure 3 In the embodiment of the present invention, the source 101, 301 and the current control gate 103, 303 are arranged on opposite sides of the semiconductor region 105, 305. However, in some embodiments, the current control gate metallization 103, 303 can in principle be on the same side as the source 101, 301, and the doping or semiconductor heterostructure is used to create an effective barrier in the source region, which is effectively located on the side of the semiconductor region 105, 305 opposite to the current control gate 103, 303.

[0084] Reference now Figure 4 , according to an embodiment of the present invention, it is shown Figure 1 The timing diagram of the multi-gate transistor is similar to that of the multi-gate transistor shown in FIG. Figure 4 In the figure shown, a graph of voltage versus time is shown when a multi-gate transistor is placed in a common-source amplifier configuration. Figure 4 a shows a quasi-DC response and shows the voltage drop (V R ): When the current controls the voltage on the gate (V CCG ) is ramped from 0V to 10V, and a 10V voltage (V DD =10V), and then pass the switch gate V SG After applying 10V voltage which has switched the transistor to the "on" state.

[0085] Figure 4 b shows the voltage V on the switch gate during a 1 nanosecond (1 ns) period. SG The voltage V on the gate increases from 0V to 10V before the transistor is suddenly switched on by causing the current to be controlled CCG The transient response of the multi-gate transistor in this case (its Figure 5 ) demonstrates that multi-gate transistors can operate faster than SGTs and also provide improvements over the performance of conventional thin-film transistors (TFTs). Figure 5 The graph in compares the corresponding recovery times of multi-gate transistors (MGTs) versus conventional SGTs and FETs, expressed as a percentage of the final drain voltage. Figure 5 As shown, the multi-gate transistor recovers to the final drain voltage faster than a conventional SGT or FET.

[0086] Without wishing to be bound by any particular theory, it is assumed that the increase in operating speed of the multi-gate transistor according to embodiments of the present invention relative to conventional SGTs and FETs occurs due to the decoupling of current injection and device on-off switching mechanisms (which are controlled by the current control gate and the switch gate, respectively). Unlike conventional SGTs, even if the voltage V on the current control gate isCCG After ramping up to the steady-state value, the multi-gate transistor remains in the “off” state until sufficient switching voltage is applied to the switch gate V SG until.

[0087] Reference now Figure 6 , according to an embodiment of the present invention, a multi-floating-gate transistor including two floating gates is shown. Like the multi-gate transistor of the previous embodiment, the multi-floating-gate transistor includes a source 601, a drain 602, a current control gate 603, a switch gate 604, a semiconductor region 605 and an insulator 606.

[0088] However, in this embodiment, voltage is not applied directly to the current control gate 603 or the switch gate 604. Instead, the transistor also includes a gate terminal 608 disposed above at least a portion of the current control gate 603 and at least a portion of the switch gate 604. In this embodiment, an applied voltage for allowing current to flow between the source 601 and the drain 602 through the semiconductor region 605 is applied to the gate terminal 608, and the current control gate 603 and the switch gate 604 act as floating gates. The control gate 608 above the source-drain gap 607 thus provides the necessary electric field in order to operate the transistor. For comparison purposes, in Figure 7 , an example of an SGT including a floating gate (hereinafter referred to as “FG SGT”) is shown, which includes a source 701, a drain 702, a floating gate 703, a semiconductor region 705, an insulator 706, and a control gate 708.

[0089] Figure 8 It shows SGT and Figure 7 The output characteristics of the FG SGT shown in the figure are similar to those of the FG SGT. Figure 8 The data plotted in are obtained from a series of experiments in which voltages of 2.5V, 5V, 7.5V and 10V were applied to the gate of the SGT, and voltages of 4V, 8V, 12V and 16V were applied to the gate of the FG SGT 708. Higher voltages were used for the FGSGT to obtain similar current levels to enable a direct comparison.

[0090] like Figure 8 As shown, incorporating FG into the SGT has a negative impact on the device performance and causes the SGT to lose its flat output characteristic, which in a normal (ie, non-FG) SGT is responsible for the high gain of the device. Figure 8It is shown that the inclusion of FG results in two saturation points. At the first saturation point 801, the FG SGT is initially saturated due to pinch-off at the source, and at the second saturation point 802, the FG SGT is finally saturated due to pinch-off at the drain, similar to a conventional TFT. Similar behavior is also observed in standard SGTs, whose sources are poorly protected from the effects of varying drain voltages. Between the two saturation points 801, 802, there is a large gain loss (slope>0), which occurs due to capacitive coupling with the channel potential and drain potential of FG 703, thereby increasing the FG 703 potential, which in turn produces more mode I and mode II currents. Due to this dual saturation behavior, the FG SGT does not provide the high gain advantage of a normal SGT.

[0091] Reference now Fig. 9 , according to an embodiment of the present invention, a diagram comparing the output characteristics of a multi-floating gate transistor with an example of an SGT and an FG SGT is shown. Compared with the FG SGT, the floating gate 703 is divided into Figure 6 The same multiple floating gates 603, 604 as in the floating gate multi-gate transistor (FG-MGT) shown cause the switch gate 704 to couple to the channel potential and effectively keep the current control gate 703 away from capacitive coupling. Therefore, the multi-floating gate transistor according to the embodiment of the present invention can achieve performance similar to that of the SGT in terms of gain. In addition, in the case of Figure 6 In the illustrated multiple floating gate transistor, the Mode II current is linearly proportional to the voltage applied to the gate terminal 608 as long as the voltage on the drain 602 is of sufficient magnitude (compared to a conventional FET where the relationship is quadratic).

[0092] exist Figure 6 In the illustrated embodiment, the gate terminal 608 extends across at least the full length of each of the current control gate 603 and the switch gate 604, such that the gate terminal 608 completely overlaps each of the current control gate 603 and the switch gate 604. However, in other embodiments, the gate terminal 608 may only partially overlap one or both of the current control gate 603 and the switch gate 604.

[0093] Additionally, in some embodiments, the multi-floating gate transistor may include a plurality of switch gates 604 disposed over a gap 607 between a source 601 and a drain 602. In such embodiments, a gate terminal 608 may extend across, i.e., overlap, all of the plurality of switch gates 604, such that each of the plurality of switch gates 604 behaves as a floating gate.

[0094] Alternatively, in some embodiments, gate terminal 608 may only extend across, i.e., overlap, one or more of switch gates 604, and may not overlap one or more other of switch gates 604. In such embodiments, one or more switch gates 604 overlapping gate terminal 608 may behave as floating gates, while one or more switch gates 604 not overlapping gate terminal 608 may behave similarly to the above referenced embodiments. Figure 1 and Figure 3 The switch gates 104, 304 described in the embodiments of the present invention may also behave as floating gates when voltage is not directly applied to each switch gate. The device can then be turned "on" by directly applying a threshold switching voltage to each of the one or more switch gates 604 that do not overlap with the gate terminal 608.

[0095] Reference now Fig.10 , according to an embodiment of the present invention, a multi-gate transistor including a plurality of switch gates is shown. The multi-gate transistor includes a source 1001, a drain 1002, a current control gate 1003, a semiconductor region 1005, and an insulator 1006. In addition, in this embodiment, the multi-gate transistor includes a plurality of switch gates 1004a, 1004b, 1004c, 1004d disposed above a source-drain gap 1007. Each of the multiple switch gates 1004a, 1004b, 1004c, 1004d is electrically isolated from other switch gates in the multiple switch gates 1004a, 1004b, 1004c, 1004d, so that current is allowed to flow between the source 1001 and the drain 1002 through the semiconductor region 1005 only when the voltage applied to each of the multiple switch gates 1004a, 1004b, 1004c, 1004d is equal to or greater than the corresponding switching threshold voltage of the switch gate in the multiple switch gates.

[0096] In some embodiments, one or more of the plurality of switch gates may include Figure 1 A similar extension of the current control gate 103 in the illustrated embodiment. Fig.11 An example of such an embodiment is shown in FIG. 1 , where four switch gates 1104a, 1104b, 1104c, 1104d are disposed at the same height with respect to the source-drain gap 1107. Three of the switch gates 1104a, 1104b, 1104c include a portion that extends vertically from an edge of the switch gate and then extends horizontally across the gap between the switch gate and an adjacent one of the switch gates. As another alternative, in some embodiments, as Fig.12As shown, adjacent switch gates among the plurality of switch gates 1204 a , 1204 b , 1204 c , and 1204 d may be disposed at different heights above the source-drain gap 1207 .

[0097] By connecting each of the plurality of switch gates 1004a, 1004b, 1004c, 1004d to a corresponding input and using the drain as the output of an AND gate, such as in Fig.10 , 11 Transistors such as those shown in FIG. 10 and 12 can be used as multi-input analog AND gates. The multi-gate transistor can then operate as an AND gate by allowing current to flow at the output only when the voltage at all multiple inputs is equal to or greater than the switching threshold voltage. The switching threshold voltage can be the same for all switch gates 1004a, 1004b, 1004c, 1004d, or can be different for different gates 1004a, 1004b, 1004c, 1004d, depending on various factors including but not limited to the following: the materials used, the distance from each gate 1004a, 1004b, 1004c, 1004d to the semiconductor region 1005, and the local characteristics of the semiconductor region 1005 in the gap 1007 between the source 1001 and the drain 1002.

[0098] When all of the switch gates 1004a, 1004b, 1004c, 1004d are applied with a corresponding threshold voltage, a continuous electric field is provided along the channel and current is allowed to flow between the source 1001 and the drain 1002. Using the transistor in this manner, the "AND" function provided by the switch gates 1004a, 1004b, 1004c, 1004d is combined with the ability to pass a current whose magnitude is controlled by the potential on 1003. This may be advantageous for space applications or other harsh environments where the device is exposed to radiation, because the decoupling between the magnitude of the signal (i.e., the signal applied to the current control gate 1003) and the switching behavior can create a robust electronic platform. In addition, by enabling the "AND" function to be implemented in the analog domain, a digital control system may no longer be required.

[0099] exist Fig.10 , 11 In the embodiments of 1 and 12, the multi-gate transistor includes a plurality of switch gates. In other embodiments, the Fig.10 , 11 In a similar manner to the embodiment of 12 where the switch gate is divided into a plurality of switch gates, the current control gate in the multi-gate transistor can be divided into a plurality of current control gates, which are separated from each other by an insulator. In addition to including a plurality of current control gates, the multi-gate transistor can include one switch gate or a plurality of switch gates, depending on the embodiment.

[0100] Reference now Fig.13 and 14 According to an embodiment of the present invention, a multi-gate transistor including a first doping region and a second doping region in a semiconductor region will now be described. Figure 1 As in the described embodiment, Fig.13 and 14 The multi-gate transistors 1300 and 1400 shown include sources 1301 and 1401, drains 1302 and 1402, current control gates 1303 and 1403, and switch gates 1304 and 1404. For the sake of brevity, the description of the current control gates 1303 and 1403 will not be repeated here. Figure 1 , 13 Detailed description of features common to the embodiments of 14. It will be understood that references such as those made herein Fig.13 and 14 Those first doped regions and second doped regions described above may also be used in any other embodiments described herein and thus may be used in conjunction with those not described herein. Figure 1 , 13 Combined with the features of other embodiments shown in 14.

[0101] exist Fig.13 In the illustrated embodiment, the multi-gate transistor 1300 includes a first doped region 1305a and a second doped region 1305b, the first doped region 1305a and the second doped region 1305b extending across the entire thickness of the semiconductor region. In other words, the first doped region 1305a and the second doped region 1305b each extend from a side of the semiconductor region where the source 1301 and the drain 1302 are disposed to a side where the insulator 1306 is disposed. In other embodiments, one or both of the first doped region 1305a and the second doped region 1305b may extend only partially across the thickness of the semiconductor region. For example, in Fig.14 In the illustrated embodiment, the first doped region 1405a and the second doped region 1405b each extend only partially across the thickness of the semiconductor region.

[0102] exist Fig.13 and 14 In the two embodiments shown, the first doped regions 1305a, 1405a and the second doped regions 1305a, 1405a are separated by undoped semiconductor regions 1305c, 1405c. However, in other embodiments, the first doped regions 1305a, 1405a and the second doped regions 1305a, 1405a may be immediately adjacent, that is, may contact each other. In some embodiments, the first doped regions 1305a, 1405a and the second doped regions 1305a, 1405a may overlap each other.

[0103] exist Fig.13 and 14 In the two embodiments shown, the first doped region 1305a, 1405a is disposed between the source 1301, 1401 and the current control gate 1303, 1403. The behavior of the transistor 1300, 1400 in response to the voltage applied to the current control gate 1303, 1403 can be controlled by selecting appropriate dopant species and concentrations in the first doped region 1305a, 1405a. For example, by selecting appropriate dopants, the first doped region 1305a, 1405a can be operated in an enhancement mode or a depletion mode. The enhancement mode can also be referred to as a "normally off" mode, and the depletion mode can be referred to as a "normally on" mode. In this way, the doping type used in the first doped region 1305a, 1405a can determine whether the magnitude of the current flowing between the source 1301, 1401 and the drain 1302, 1402 increases as the voltage applied to the current control gate 1303, 1403 increases or decreases as the voltage applied to the current control gate 1303, 1403 increases.

[0104] In addition, Fig.13 and 14 In the two embodiments shown, the second doped regions 1305b, 1405b are disposed in the channels 1307, 1407. The behavior of the transistors 1300, 1400 in response to the voltage applied to the switch gates 1304, 1404 can be controlled by selecting appropriate dopant species and concentrations in the second doped regions 1305b, 1405b. For example, by selecting appropriate dopants, the second doped regions 1305b, 1405b can be made to operate in an enhancement mode or a depletion mode. In this way, the second doped regions 1305b, 1405b can determine whether the transistors 1300, 1400 are normally on or normally off when no voltage is applied to the switch gates 1304, 1404.

[0105] Depending on the embodiment, the first doped regions 1305a, 1405a and the second doped regions 1305b, 1405b may operate in the same mode or may operate in different modes. For example, in one embodiment, the first doped regions 1305a, 1405a may operate in an enhancement mode and the second doped regions 1305b, 1405b may operate in a depletion mode, or vice versa.

[0106] By providing Fig.13 and 14The separate first doped regions 1305a, 1405a and second doped regions 1305b, 1405b shown, and by appropriate selection of dopant species and concentrations, many different combinations of device behaviors can be achieved. This provides greater flexibility for circuit designers. For example, when a dopant that causes the semiconductor region in the channel 1307, 1407 to operate in a "normally open" mode is selected for the second doped regions 1305b, 1405b, a negative voltage exceeding the threshold switching voltage is applied to the switch gates 1304, 1404 will cause the transistors 1300, 1400 to turn off. This type of behavior may be expected in a circuit in which the current flow is turned off when the control voltage applied to the switch gates 1304, 1404 becomes negative. As another example, in an embodiment in which multiple current control gates and / or multiple switch gates are provided, different doped regions (e.g., using different dopant species and / or different dopant concentrations) may be provided for different gates in the multiple gates.

[0107] Additionally, in some embodiments, the first doped regions 1305a, 1405a may be omitted, and the multi-gate transistor may include only the doped regions 1305b, 1405b in the channels 1307, 1407. Doping semiconductors in the channels 1307, 1407 may be used to control the threshold voltage of the switch gates 1304, 1404, in other words, the voltage at which the transistors 1300, 1400 are turned on or off. As another alternative, in some embodiments, the second doped regions 1305b, 1405b may be omitted, and the multi-gate transistor may include only the first doped regions 1305a, 1405a above the source. The first doped regions 1305a, 1405a above the source may have the effect of changing the energy barrier height so as to provide a barrier of suitable height for desired results such as increased charge injection, linearity, or temperature dependence, depending on the desired application.

[0108] In such Fig.15 and 16 In other embodiments shown, Fig.15 and 16 As shown in the embodiment of FIG. 1 , a single doped region 1505a, 1605a may be provided that extends across the source 1501, 1601 and the channel 1507, 1607. In contrast to embodiments using more than one doped region (such as Fig.13 and 14 Using only a single doped region can provide a simplified manufacturing process compared to those shown in FIG. Fig.15 As shown, the doped region may extend across the entire thickness of the semiconductor region, while in other embodiments, as shown Fig.16 As shown, the doped region may extend only partially across the thickness of the semiconductor region.

[0109] picture Figure 1 , 13 As in the embodiment of 14, Fig.15 and 16 The embodiment includes a source 1501, 1601, a drain 1502, 1602, a current control gate 1503, 1603, a switch gate 1504, 1604, and an insulating layer 1506, 1606. For the sake of brevity, the description of Figure 1 and 13 Detailed description of features common to the embodiments of 1 to 16. It will be appreciated that references such as those made herein Fig.15 and 16 Individual doped regions such as those described herein may also be used in any of the other embodiments described herein and thus may be used in conjunction with regions not described herein. Figure 1 , 15 Combined with the features of other embodiments shown in 16.

[0110] Reference now Fig.17 , shows a multi-gate transistor according to an embodiment of the present invention. Figure 1 The same as the example, Fig.17 The multi-gate transistor 1700 includes a source 1701, a drain 1702, a current control gate 1703, a switch gate 1704a, a semiconductor region 1705 and an insulating layer 1706a, and the detailed description of similar features will not be repeated here. It will be understood that it can also be used in combination with the features of any other described embodiments herein. Fig.17 In some embodiments, with Figures 10 to 12 In a similar manner to the embodiments of the multiple switch gates, the multi-gate transistor may include multiple auxiliary gates.

[0111] exist Fig.17 In an embodiment of the invention, the transistor 1700 further includes an auxiliary gate 1704b disposed on a side of the channel 1707 opposite to the switch gate 1704a. In this embodiment, the auxiliary gate 1704b is separated from the semiconductor material in the channel 1707 by an insulator 1706b. The threshold voltage of the switch gate 1704a, which may also be referred to as the switching voltage, may be adjusted by changing the voltage applied to the auxiliary gate electrode 1704b. In other words, the threshold voltage at which the switch gate 1704a allows current to flow between the source 1701 and the drain 1702 depends on the voltage applied to the auxiliary gate 1704b. In another embodiment, the auxiliary gate may be in direct contact with the semiconductor between the source and the drain. In such an embodiment, the energy barrier at the interface between the auxiliary gate and the semiconductor may ensure that no current flows from the gate to the semiconductor in a manner similar to a MESFET, while still allowing the conductance of the semiconductor between the source and the drain to be modulated by applying a potential to the auxiliary gate.

[0112] In this manner, the auxiliary gate electrode 1704b can perform the same as above with reference to Fig.13 and 14 The functions of the second doped regions 1305b, 1405b described above are similar. However, using the auxiliary gate electrode 1704b instead of semiconductor doping to control the switching voltage of the switch gate 1704a has the additional advantage that the switching voltage can be adjusted dynamically rather than being fixed for any given device. In some embodiments, the auxiliary gate electrode 1704b can be used in conjunction with the second doped regions 1305b, 1405b.

[0113] Reference now Fig.18 , according to an embodiment of the present invention, a multi-gate transistor including field mitigation structures in the source and drain is shown. Figure 1 The same as the example, Fig.18 The multi-gate transistor 1800 includes a source 1801, a drain 1802, a current control gate 1803, a switch gate 1804, a semiconductor region 1805 and a first insulating layer 1806a, and the detailed description of similar features will not be repeated here. It will be understood that it can also be used in combination with the features of any other described embodiments herein. Fig.18 Describe the characteristics.

[0114] exist Fig.18 In an embodiment of the present invention, the transistor 1800 includes a second insulating layer 1806b disposed between the substrate and the source 1801 and the drain 1802. In addition, the source 1801 and the drain 1802 each include a respective field mitigation structure 1801a, 1802a, which extends partially below the channel. An insulator 1806c (which is referred to herein as a "field mitigation insulator") is disposed between the field mitigation structures 1801a, 1802a and the semiconductor region to isolate the field mitigation structures 1801a, 1802a from the semiconductor region in the channel. The first insulating layer 1806a, the second insulating layer 1806b, and the field mitigation insulator 1806c can be formed of the same insulating material or of different materials.

[0115] In some embodiments, transistor 1800 may include only a field mitigation structure 1801a on source 1801, and field mitigation structure 1802a on drain 1802 may be omitted. However, it may be easier to manufacture both field mitigation structures 1801a, 1802a together, since forming field mitigation structure 1801a only on source 1801 may require additional processing steps. For example, in order to have only a source field mitigation structure 1801a without a corresponding structure 1802a on the drain, it may be necessary to mask source 1801, drain 1802, and source field mitigation structure 1801a, and then etch away drain field mitigation structure 1802a.

[0116] The source field mitigation structure 1801a extends beyond the edge of the source 1801 closest to the drain 1802 in a direction toward the drain 1802. In this way, the source field mitigation structure 1801a serves to at least partially shield the source 1801 from the lateral electric field in the channel generated by the presence of the drain 1802, so that the behavior of the source 1801 is not affected by the field from the drain 1802.

[0117] As Fig.18 In an alternative to the source field mitigation structure 1801 in FIG. 1 , in another embodiment, as will now be referred to Fig.19 As described above, separate field mitigation electrodes may be provided to perform similar functions. Figure 1 The same as the example, Fig.19 The multi-gate transistor 1900 includes a source 1901, a drain 1902, a current control gate 1903, a switch gate 1904, a semiconductor region 1905 and an insulating layer 1906a, and the detailed description of similar features will not be repeated here. It will be understood that it can also be used in combination with the features of any other described embodiments herein. Fig.19 Describe the characteristics.

[0118] The field mitigation electrode 1901a is disposed below one end of the source 1901 adjacent to the channel 1907. Fig.19 As shown, field mitigation electrode 1901a partially overlaps source 1901 and also partially overlaps channel 1907. In addition, field mitigation electrode 1901a is separated from source 1901 and channel 1907 by insulating material 1706b. Fig.18 Like the source field mitigation structure 1801a, Fig.19 The field mitigation electrode 1901a extends beyond the edge of the source 1901 closest to the drain 1902 in a direction toward the drain 1902. In this way, the field mitigation electrode 1901a serves to at least partially shield the source 1901 from the lateral electric field in the channel 1907 generated by the presence of the drain 1902, so that the behavior of the source 1901 is not affected by the field from the drain 1902.

[0119] As referenced above Figure 1 As described above, a potential barrier between the source and semiconductor regions can be provided by suitable selection of materials or by doping the source and / or semiconductor or by forming a heterojunction. Figures 20 to 22 Embodiments of the present invention are described that include a physical barrier between the source and the semiconductor region. Depending on the embodiment, the physical barrier may be used alone or in combination with a suitable form of potential barrier such as those described above. The various forms of physical barriers and potential barriers described herein all act as energy barriers between the source and the semiconductor region, thereby preventing current from flowing between the source and the semiconductor at low source-gate voltages.

[0120] Fig. 20 A multi-gate transistor 2000 is shown, which includes a tunnel layer 2005a disposed between a source 2001 and a semiconductor region 2005. The tunnel layer 2005a includes a layer of material that is thin enough to allow electrons or holes to "tunnel" from one side of the layer to the other side when a sufficiently high electric field is applied across the tunnel layer 2005a. The tunnel layer 2005a may include an electrically insulating material, or may include a material having an energy band structure that provides a suitable energy barrier. In this way, the tunnel layer 2005a performs a function similar to a potential barrier by preventing current from flowing from the source 2001 into the semiconductor region 2005 at a low source-gate voltage. In the present embodiment, the tunnel layer 2005a also extends across the source 2005, the substrate in the channel 2007, and the drain 2002. However, in another embodiment, the tunnel layer 2005a may be disposed only on the source 2001, and may not extend across the channel 2007 or the drain 2002.

[0121] Fig.21 A multi-gate transistor 2100 is shown that includes an energy barrier formed by a region 2105a of doped semiconductor 2105 above a source 2101. In this embodiment, the doped region 2105a is separated from the source 2101 by an undoped semiconductor material region 2105. In another embodiment, the doped region 2105a may be immediately adjacent to the source 2101.

[0122] In this embodiment, the doped region 2105a extends beyond the end of the source 2101 closest to the drain 2102 so that the doped region 2105a extends partially into the channel 2107. In this way, the portion of the doped region 2105a that extends beyond the edge of the source 2101 can perform with the source 2101 by ensuring that the behavior of the source 2101 is not affected by the field above the channel 2107. Fig.18 The source field mitigation structure 1801a and Fig.19However, in another embodiment, doped region 2105a may extend only to the edge of source 2101 and may not extend into channel 2107.

[0123] Fig. 22 A multi-gate transistor 2200 including a heterostructure energy barrier according to an embodiment of the present invention is shown. In this embodiment, the energy barrier is provided in the form of a heterostructure including two different semiconductor materials. The semiconductor region separating the source 2201 from the current control gate 2203 includes a first semiconductor material 2205, and a second semiconductor material 2205a is disposed on the source 2201 between the source 2201 and the first semiconductor 2205. In this way, the interface between the two different semiconductors forms a heterojunction and acts as an energy barrier to the current flowing between the source 2201 and the first semiconductor 2205.

[0124] Reference now Fig.23 , according to an embodiment of the present invention, a multi-gate transistor 2300 including a switch gate electrode and a floating current control gate is shown. Figure 6 The floating gate transistor shown differs in that only one of the two gates is a floating gate. In this embodiment, the current control gate 2303 is a floating gate, and the transistor 2300 includes a gate terminal 2308 disposed over at least a portion of the current control gate 2303. Figure 6 Unlike the embodiment of , gate terminal 2308 does not extend above switch gate 2304. Instead, voltage is applied directly to switch gate 2304.

[0125] In this embodiment, only the current control gate is embodied as a floating gate, allowing the floating gate function of the source to be separated from the switch function. In another embodiment, the gate terminal 2308 may be provided only above the switch gate 2304, and may not extend above the current control gate 2303. In this case, the switch gate 2304 behaves as a floating gate, and the voltage may be applied directly to the current control gate 2303. Using a floating switch gate in this manner may enable the transistor to be locked in an "on" or "off" state.

[0126] Despite Fig.23 23. A single gate terminal 2308 is shown in FIG. 23, but in some embodiments, the gate terminal 2308 may be divided into multiple gate terminals that are spaced apart from each other and separated by an insulator. For example, in one embodiment, the gate terminal 2308 may be divided into Fig.23 Multiple individual terminals spaced apart from each other in the horizontal direction.

[0127] Alternatively, the gate terminal 2308 may be divided into Fig.23 A plurality of individual terminals spaced apart in the direction of the plane of the drawing. Fig.24 An example of such an embodiment is shown in FIG, which shows a multi-gate transistor 2400 including a plurality of input terminals 2408a, 2408b disposed above a floating current control gate 2403. Like the transistors of the other embodiments described above, Fig.24 The transistor 2400 shown also includes a source 2401, a drain 2402, a switch gate 2404, a semiconductor region 2405 and an insulating layer 2406, and detailed descriptions of similar features will not be repeated here.

[0128] By applying different voltages to each of the input terminals 2408a, 2408b, the transistor 2400 of the present embodiment can be made to perform various functions. For example, the transistor 2400 can be used to sum multiple analog input voltages by applying each input voltage to a different input terminal among the multiple input terminals 2408a, 2408b. Fig.24 Only two input terminals 2408a, 2408b are shown in FIG. 1 , but it will be appreciated that in other embodiments, any number of input terminals 2408a, 2408b may be provided, depending on the requirements of a particular application. In this embodiment, each input terminal 2408a, 2408b has the same area and overlaps the floating current control gate 2403 by the same amount, so that each input terminal 2408a, 2408b has the same degree of influence on the output current. In this manner, the output current generated by the transistor is related to the linear sum of the input voltages.

[0129] In such Fig.24 In the embodiment shown, each of the plurality of gate terminals 2408a, 2408b may extend across the entire width of the current control gate 2403, or may extend across only a portion of the width of the current control gate 2403. By varying the overlap area between one of the gate terminals 2408a, 2408b and the current control gate 2403, the effect of the gate terminals 2408a, 2408b on the magnitude of the current flowing between the source 2401 and the drain 2402 may be controlled.

[0130] Now refer to Fig.25 Describe the relevant embodiments. Although it is not a floating gate transistor, Fig.25 The multi-gate transistor 2500 shown is similar to Fig.24 As shown, because transistor 2500 includes a transistor having a Figure 12503a, 2503b, 2503c are spaced apart from each other in the direction of the drawing plane in FIG. In other words, the plurality of current control gates 2503a, 2503b, 2503c are spaced apart in a direction parallel to the edge of the source 2501 adjacent to the channel between the source 2501 and the drain 2502. Like the transistors of the other embodiments described above, Fig.25 The transistor 2500 shown also includes a switch gate 2504, a semiconductor region 2505 and an insulating layer 2506, and a detailed description of similar features will not be repeated here.

[0131] In this embodiment, transistor 2500 is configured to function as a digital-to-analog converter. In this embodiment, a total of three current control gates 2503a, 2503b, 2503c are shown, each of which has a different overlap area with source 2501, such as Fig.25 As shown. Specifically, the overlapping area of ​​the second current control gate 2503b and the source 2501 is twice the overlapping area of ​​the first current control gate 2503a and the source 2501, and the overlapping area of ​​the third current control gate 2503c and the source 2501 is twice the overlapping area of ​​the second current control gate 2503b and the source 2501. In this way, each bit of the 3-bit input digital codeword can be applied to the corresponding gate among the current control gates 2503a, 2503b, and 2503c. The least significant bit is applied to the first current control gate 2503a, the middle bit is applied to the second current control gate 2503b, and the most significant bit is applied to the third current control gate 2503c. Since the overlapping area of ​​each current control gate is different, the input codewords '011', '101', and '110' will produce different analog output voltages.

[0132] It will be understood that a 3-bit input codeword is described purely as an example, and additional current control gates can be added according to a similar pattern according to the number of required input bits. In general, if the input digital codeword includes n bits and the multi-gate transistor includes n current control gates, each current control gate has a different overlapping area with the source, then the overlapping area of ​​the current control gate increases from the first current control gate to the nth current control gate and follows a geometric series of common ratio r=2. In the present embodiment, the common ratio 2 is used to determine the relative area of ​​n current control gates because the input digit is a bit (binary digit). In other embodiments, the digit of the input digital codeword can be represented by a base other than 2, and a suitable common ratio can be selected accordingly. For example, when using octal digits (base 8), the overlapping area of ​​the current control gate can follow a geometric series of common ratio r=8. Similarly, when using hexadecimal digits (base 16), the overlapping area of ​​the current control gate can follow a geometric series of common ratio r=16.

[0133] In the above embodiments, planar transistor structures are shown, which can be manufactured by depositing a series of layers on top of each other. In some embodiments of the present invention, the same principles disclosed above can be applied to circular or concentric transistor structures, examples of which will now be referred to. Figures 26 to 28 Give a description.

[0134] Fig.26 With Figure 1 A cross section similar to the embodiment of FIG. 2 shows a transistor structure 2600, including a source 2601, a drain 2602, a current control gate 2603, a switch gate 2604, a semiconductor region 2605 and an insulating layer 2606. However, Figure 1 Unlike the embodiment of the present invention, in this embodiment, the source 2601 and the drain 2602 are arranged on opposite sides of the semiconductor region 2605, wherein the drain 2602 and the current control gate 2603 and the switch gate 2604 are arranged on the same side of the semiconductor region 2605.

[0135] In some embodiments, similar to the Corbino device, a transistor can be manufactured using a concentric circular structure. The structure of this embodiment can be understood as being equivalent to Fig.26 The cross section shown is rotated 360° about the y-axis. Alternatively, in another embodiment, a transistor may be fabricated, for example, based on semiconductor nanowires using a structure equivalent to Fig.26 The cross section shown is rotated 360° about the x-axis.

[0136] Reference now Fig. 27 and 28 , according to one example, a nanowire-based multi-gate transistor 2700 is shown, wherein a current control gate 2703 and a switch gate 2704 are arranged on the same side of a semiconductor region 2705 as a source 2701 and a drain 2702 . Fig.28 A cross section through transistor 2700 from A to A' is shown. For example, transistor 2700 can be fabricated by depositing source 2701 and drain 2702 on the surface of semiconductor nanowire 2705, then depositing insulating layer 2706 around nanowire 2705, source 2701 and drain 2702, and then depositing current control gate 2703 and switch gate 2704 around insulating layer 2706. It will also be appreciated that the transistor 2700 can be fabricated by rotating about either of the axes labeled A and A'. Fig. 27 The cross section shown is used to obtain a circular transistor structure.

[0137] Although certain embodiments of the invention have been described herein with reference to the accompanying drawings, it will be understood that many changes and modifications will be possible without departing from the scope of the invention as defined in the appended claims.

Claims

1. A multi-gate transistor, comprising: source; a drain electrode, spaced apart from the source electrode; A semiconductor region, disposed between the source and the drain; An insulating region, disposed on the semiconductor region; a current control gate, for controlling the magnitude of a current flowing between the source and the drain through the semiconductor region according to a first electric field applied to the current control gate, the current control gate being separated from the source by the semiconductor region and the insulating region; and a switch gate for allowing current to flow between the source and the drain through the semiconductor region according to a second electric field applied to the switch gate, the switch gate being arranged to span at least a portion of a first gap between the source and the drain, and The source is arranged at one side of the first gap, and the current control gate is arranged at the same side of the first gap as the source.

2. The multi-gate transistor according to claim 1, wherein: The drain is laterally spaced apart from the source, the semiconductor region is disposed over the source and the drain, and the current control gate and the switch gate are disposed on a side of the semiconductor region opposite the source and the drain.

3. The multi-gate transistor according to claim 2, wherein: The current control gate and the switch gate are disposed at the same height above the source and drain, wherein the current control gate or the switch gate further includes a portion extending above a second gap separating the current control gate from the switch gate.

4. The multi-gate transistor according to claim 3, wherein: The portion of the current control gate or the switch gate extends at least to the same lateral position as an adjacent edge of the other of the current control gate and the switch gate, and wherein the portion of the current control gate or the switch gate is longitudinally separated from the edge of the other of the current control gate and the switch gate.

5. The multi-gate transistor according to claim 2, wherein: The current control gate is longitudinally offset from the switch gate.

6. The multi-gate transistor according to claim 5, wherein: The current control gate extends at least to an edge of the switch gate in a lateral direction, and the current control gate is longitudinally separated from the switch gate by an electrical insulation region.

7. A multi-gate transistor as claimed in any preceding claim, wherein: The switch gate is configured to cause a conductive layer to be generated in a portion of the semiconductor region between the source and the drain when the second electric field is applied to the switch gate.

8. The multi-gate transistor of claim 1 , further comprising: a gate terminal disposed above at least a portion of the current control gate and at least a portion of the switch gate, wherein a third electric field sufficient to generate the first electric field and the second electric field is applied to the gate terminal, and wherein the current control gate and the switch gate act as floating gates.

9. The multi-gate transistor of claim 8, wherein: The gate terminal extends across the length of the current control gate and the switch gate.

10. The multi-gate transistor of any one of claims 1 to 6, comprising: a plurality of switch gates including the switch gate, Wherein, each of the multiple switch gates is electrically isolated from other switch gates of the multiple switch gates, so that current is allowed to flow between the source and the drain through the semiconductor region only when the voltage applied to each of the multiple switch gates is equal to or greater than the corresponding switching threshold voltage of the switch gate of the multiple switch gates.

11. The multi-gate transistor of claim 10, further comprising: a plurality of inputs, each input connected to a respective switch gate of the plurality of switch gates; and An output connected to the drain such that the multi-gate transistor is configured to perform an AND function by allowing current to flow at the output only if the voltages at all of the plurality of inputs are equal to or greater than a switching threshold voltage.

12. The multi-gate transistor of any one of claims 1 to 6, comprising: a plurality of current control gates including the current control gate, In which, the multiple current control gates are spaced apart from each other in a direction parallel to the edge of the source adjacent to the channel between the source and the drain, and each is configured to receive a corresponding input voltage among a plurality of input voltages, so that the magnitude of the current flowing between the source and the drain depends on the plurality of input voltages.

13. The multi-gate transistor of claim 12, wherein: Each current control gate of the plurality of current control gates is configured to receive a corresponding digit of an input digital codeword comprising a plurality of digits such that the multi-gate transistor is configured to convert the input digital codeword into an analog output current at the drain.

14. The multi-gate transistor of claim 13, wherein: The plurality of digits of the input digital codeword include n bits, and the multi-gate transistor includes n current control gates, each current control gate having a different overlap area with the source, and The overlapping areas of the current control gates increase in a geometric series from the first current control gate to the nth current control gate following a common ratio r=2.

15. The multi-gate transistor according to any one of claims 1 to 6, wherein: The semiconductor region comprises: a first doped region between the source and the current control gate; and The second doped region is arranged in the channel between the source and the drain.

16. The multi-gate transistor of claim 15, wherein: The first doped region is configured to operate in a normally-on mode, and the second doped region is configured to operate in a normally-off mode, or Wherein, the first doped region is configured to operate in a normally-off mode, and the second doped region is configured to operate in a normally-on mode.

17. The multi-gate transistor of any one of claims 1 to 6, comprising: An auxiliary gate is disposed on a side of the semiconductor region opposite to the switch gate, wherein a threshold electric field at which the switch gate allows current to flow between the source and the drain depends on an electric field applied to the auxiliary gate.

18. The multi-gate transistor of any one of claims 1 to 6, comprising: A field mitigation element is configured to extend beyond an edge of the source closest to the drain in a direction toward the drain so as to at least partially shield the source from an electric field in a channel between the source and the drain.

19. The multi-gate transistor according to any one of claims 1 to 6, wherein: The first electric field and / or the second electric field is an applied voltage, or an electric field generated by incident electromagnetic radiation via the photovoltaic effect, or an electric field generated by chemical adsorption.

20. A method of operating a multi-gate transistor, the multi-gate transistor comprising: source; a drain electrode spaced apart from the source electrode; a semiconductor region disposed between the source and the drain; an insulating region disposed above the semiconductor region; a current control gate, for controlling the magnitude of a current flowing between the source and the drain through the semiconductor region according to a first electric field applied to the current control gate, the current control gate being separated from the source by the semiconductor region and the insulating region; and a switch gate for allowing current to flow between the source and the drain through the semiconductor region according to a second electric field applied to the switch gate, the switch gate being arranged to span at least a portion of a first gap between the source and the drain, wherein the source is arranged on one side of the first gap, and the current control gate is arranged on the same side of the first gap as the source, the method comprising: applying the second electric field to the switch gate to allow current to flow in the semiconductor region between the source and the drain; and The current control gate is used to control the magnitude of a current flowing in the semiconductor region between the source and the drain.

21. The method of claim 20, wherein: The second applied electric field is greater than or equal to a threshold switching electric field.

22. The method of claim 21, wherein: Using the current control gate to control the magnitude of the current includes: applying the first electric field to the current control gate, and wherein the multi-gate transistor is subsequently turned on by increasing the second electric field applied to the switch gate to at least the threshold switch field.

23. The method according to claim 21 or 22, wherein: The multi-gate transistor includes a plurality of switch gates including the switch gate, each of the plurality of switch gates being electrically isolated from other switch gates of the plurality of switch gates, so that current is allowed to flow between the source and the drain through the semiconductor region only when a corresponding second electric field applied to each of the plurality of switch gates is equal to or greater than a corresponding switching electric field of the switch gate of the plurality of switch gates, the method further comprising: A respective second electric field greater than or equal to a respective threshold switching electric field is applied to each of the plurality of switch gates.

24. The method of claim 23, wherein: Each of the multiple inputs is connected to a corresponding switch gate of the multiple switch gates and the output is connected to the drain, so that the multi-gate transistor is configured to perform an "AND" function by allowing current to flow at the output only when the corresponding second electric field at all of the multiple inputs is equal to or greater than the corresponding switch electric field.

25. The method of any one of claims 20 to 22, wherein: The first electric field and / or the second electric field is an applied voltage, or an electric field generated by incident electromagnetic radiation via the photovoltaic effect, or an electric field generated by chemical adsorption.

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