A SRAM-PUF unit structure, memory and power-on mode control method
By designing control circuits, feedback circuits and switching circuits in the SRAM-PUF unit structure to form and stabilize the voltage difference, the problem that the existing SRAM-PUF unit structure is susceptible to noise is solved, and the reliability of power-on results is improved.
Patent Information
- Application Number
- CN202110820015.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-07-20
- Publication Date
- 2025-02-25
- Estimated Expiration
- 2041-07-20
AI Technical Summary
The existing SRAM-PUF unit structure is susceptible to noise, resulting in inconsistent power-on results and reduces reliability.
A SRAM-PUF unit structure is designed, including a control circuit, a feedback circuit and a switching circuit. When the first control signal is input at the input end of the control circuit, the switch circuit is turned on, and the two output ends of the feedback circuit form a voltage difference; when the control signal remains unchanged and the switch circuit is turned off, the voltage difference gradually increases to the preset The difference is stable and unchanged.
Through this design, noise influence is avoided and the stability and reliability of power-on results are ensured.
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Figure CN113689907B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a SRAM-PUF unit structure, a memory, and a control method for a power-on mode. Background Art
[0002] SRAM is Static Random Access Memory, and PUF is Physical Unclonable Function.
[0003] The SRAM-based PUF format is used for security authentication and key management in the Internet of Things. Its advantages are low cost and low power consumption, and the keys generated on-site cannot be cloned.
[0004] The existing SRAM-PUF cell structure forms a randomly changing power-on initial value based on the threshold voltage difference of the transistors inside the cell during production. However, since this structure is extremely susceptible to noise, which changes the power-on result, the multiple power-on results of the same cell structure are inconsistent, and the reliability is reduced. Summary of the invention
[0005] In view of the above problems, the present invention is proposed to provide a SRAM-PUF cell structure, a memory, and a power-on mode control method that overcome the above problems or at least partially solve the above problems.
[0006] In a first aspect, the present invention provides a SRAM-PUF unit structure, comprising:
[0007] A control circuit, a feedback circuit, and a switch circuit between the control circuit and the feedback circuit;
[0008] When a first control signal is input to the input end of the control circuit and the switch circuit is controlled to be turned on, a voltage difference is formed at two output ends of the feedback circuit;
[0009] When the first control signal is maintained unchanged at the input end of the control circuit and the switch circuit is controlled to be turned off, the voltage difference gradually increases to a preset difference value and remains stable at the preset difference value.
[0010] Preferably, the control circuit comprises: a first transistor and a second transistor, a source of the first transistor and a source of the second transistor are both connected to a power supply voltage;
[0011] The gate of the first transistor is connected to the gate of the second transistor and serves as a first input terminal for inputting the first control signal.
[0012] Preferably, the value of the first control signal is less than or equal to half the value of the power supply voltage.
[0013] Preferably, the switch circuit comprises: a third transistor, the source and the drain of the third transistor are correspondingly connected between the drain of the first transistor and the drain of the second transistor, and the gate of the third transistor serves as a second input terminal for inputting a second control signal.
[0014] Preferably, when the second control signal is at a low level, the switch circuit is turned on;
[0015] When the second control signal is at a high level, the switch circuit is turned off.
[0016] Preferably, the feedback circuit includes: a fourth transistor and a fifth transistor, the source of the fourth transistor is connected to one end of the switch circuit and to the gate of the fifth transistor as a first power-on node, the gate of the fourth transistor is connected to the source of the fifth transistor and to the other end of the switch circuit as a second power-on node, and the drain of the fifth transistor and the drain of the fourth transistor are both grounded.
[0017] Preferably, it also includes:
[0018] a sixth transistor and a seventh transistor;
[0019] The source of the sixth transistor is connected to one end of the switch circuit, the drain of the sixth transistor is connected to the bit line, and the gate of the sixth transistor is connected to the word line;
[0020] The source of the seventh transistor is connected to the other end of the switch circuit, the drain of the seventh transistor is connected to the ground bit line, and the gate of the seventh transistor is connected to the word line.
[0021] In a second aspect, the present invention further provides a memory, comprising:
[0022] The SRAM-PUF unit structure as described in any one of the first aspects.
[0023] In a third aspect, the present invention further provides a method for controlling a power-on mode, which is applied to the SRAM-PUF unit structure in the first aspect, comprising:
[0024] When a first control signal is input to the input end of the control circuit and the control switch circuit is turned on, a voltage difference is formed at two output ends of the feedback circuit;
[0025] When the first control signal is maintained unchanged at the input end of the control circuit and the switch circuit is controlled to be closed, the voltage difference gradually increases to a preset difference value and remains stable at the preset difference value.
[0026] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:
[0027] The present invention provides an SRAM-PUF unit structure, comprising: a control circuit, a feedback circuit and a switch circuit between the control circuit and the feedback circuit, wherein a first control signal is inputted at an input end of the control circuit, and when the control switch circuit is turned on, a voltage difference is formed at two output ends of the feedback circuit; the first control signal is maintained unchanged at the input end of the control circuit, and when the control switch circuit is turned off, the voltage difference gradually increases to a preset difference value, and remains stable at the preset difference value, thereby preventing the power-on result from changing due to noise, thereby improving the reliability of the unit structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Also, throughout the accompanying drawings, the same reference figures are used to represent the same components. In the drawings:
[0029] Figure 1 A schematic diagram of the structure of an SRAM-PUF unit in the related art is shown;
[0030] Figure 2 A schematic diagram of a power-on waveform of an SRAM-PUF unit structure in the related art is shown;
[0031] Figure 3 A schematic diagram of the structure of the SRAM-PUF unit structure in an embodiment of the present invention is shown;
[0032] Figure 4 A schematic diagram of a power-on waveform of an SRAM-PUF unit structure in an embodiment of the present invention is shown;
[0033] Figure 5 A schematic flow chart of the steps of a method for controlling a power-on mode in an embodiment of the present invention is shown. DETAILED DESCRIPTION
[0034] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0035] SRAM (Static Random Access Memory) is a memory with static access function, which can save the data stored inside it without refreshing the circuit. When SRAM is used in a chip, when the chip system detects unauthorized illegal access, the chip system can cut off the power supply of SRAM to prevent attackers from stealing data.
[0036] In the related art, the SRAM-PUF cell structure is as follows Figure 1 As shown, it includes a cross-coupled first inverter and a second inverter; after the first inverter and the second inverter are cross-coupled, a first storage node Q1 and a second storage node QB1 are formed, wherein the first storage node Q1 and the second storage node QB1 are used to store one bit of binary information 0 or 1.
[0037] The circuit structures of the first inverter 101 and the second inverter 102 are axially symmetrical along the central axis of the memory cell.
[0038] The first inverter 101 includes a first P-type transistor P1 and a first N-type transistor N1; the first P-type transistor and the source are electrically connected to the power supply terminal VDD, the drain of the first P-type transistor P1 and the drain of the first N-type transistor N1 are electrically connected to the first storage node Q1, the source of the first N-type transistor N1 is grounded (electrically connected to the ground terminal GND), and the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1 are electrically connected to the second storage node QB1.
[0039] The second inverter 102 includes a second P-type transistor P2 and a second N-type transistor N2, the source of the second P-type transistor P2 is electrically connected to the power supply terminal VDD, the drain of the second P-type transistor P2 and the drain of the second N-type transistor N2 are electrically connected to the second storage node QB1, the source of the second N-type transistor N2 is grounded (electrically connected to the ground terminal GND), and the gate of the second P-type transistor P2 and the gate of the second N-type transistor N2 are electrically connected to the first storage node Q1.
[0040] The power-on waveform of the SRAM-PUF unit structure is as follows: Figure 2 As shown, specifically, after the power supply voltage VDD is powered on, the voltages of the first storage node Q1 and the second storage node QB1 begin to rise. Due to the difference in transistor threshold voltages, the voltage rise rates of the first storage node Q1 and the second storage node QB1 are different. Then, a gradually increasing voltage difference is formed. When the voltage difference reaches a certain threshold, the node voltages of the first storage node Q1 and the second storage node QB1 quickly enter a stable level state and no longer change.
[0041] However, in actual situations, this startup mode has certain defects. This is mainly because when the voltage difference between the first storage node Q1 and the second storage node QB1 reaches the threshold during the rising process, it is easily affected by noise, thereby changing the power-on result, making the multiple power-on results of the same unit inconsistent, and thus reducing reliability.
[0042] Embodiment 1
[0043] An embodiment of the present invention provides a SRAM-PUF unit structure, such as Figure 3 As shown, it includes: a control circuit 301 , a feedback circuit 303 , and a switch circuit 302 between the control circuit 301 and the feedback circuit 303 .
[0044] When the first control signal is input to the input end of the control circuit 301 and the control switch circuit 302 is turned on, a voltage difference is formed at the two output ends of the feedback circuit 303; when the first control signal is maintained unchanged at the input end of the control circuit 301 and the control switch circuit 302 is turned off, the voltage difference gradually increases to a preset difference value and remains stable at the preset difference value.
[0045] Specifically, the control circuit 301 includes: a first transistor P1 and a second transistor P2, the source of the first transistor P1 and the source of the second transistor P2 are both connected to the power supply voltage VDD, the gate of the first transistor P1 and the gate of the second transistor P2 are connected and serve as a first input terminal for inputting a first control signal EN1.
[0046] The value of the first control signal EN1 is less than or equal to half of the value of the power supply voltage, that is, the value of the first control signal EN1 is [0, 1 / 2 VDD].
[0047] The switch circuit 302 includes: a third transistor P3, the source and drain of the third transistor P3 are connected between the drain of the first transistor P1 and the drain of the second transistor P2 respectively, and the gate of the third transistor P3 is used as a second input terminal for inputting a second control signal EN2.
[0048] When the second control signal EN2 is at a low level, the switch circuit is turned on; when the second control signal EN2 is at a high level, the switch circuit is turned off.
[0049] The feedback circuit includes: a fourth transistor N1 and a fifth transistor N2, the source of the fourth transistor N1 is connected to one end of the switch circuit and to the gate of the fifth transistor as a first power-on node Q; the gate of the fourth transistor N1 is connected to the source of the fifth transistor N2 and to the other end of the switch circuit as a second power-on node QB, and the drain of the fifth transistor N2 and the drain of the fourth transistor N1 are both grounded.
[0050] The feedback circuit has positive feedback and negative feedback functions.
[0051] The SRAM-PUF unit structure further includes: a sixth transistor N3 and a seventh transistor N4, wherein the source of the sixth transistor N3 is connected to one end of the switch circuit, the drain of the sixth transistor N3 is connected to the bit line BL, and the gate of the sixth transistor N3 is connected to the word line WL.
[0052] The source of the seventh transistor N4 is connected to the other end of the switch circuit, the drain of the seventh transistor N4 is connected to the ground terminal BLB, and the gate of the seventh transistor N4 is connected to the word line WL.
[0053] The above-mentioned transistors can specifically be P-type transistors or N-type transistors, which is not limited here. In the figure, the first transistor, the second transistor, and the third transistor are P-type transistors as an example, and the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are N-type transistors as an example.
[0054] The power-on mode of the SRAM-PUF cell structure is as follows:
[0055] In the first stage, the power supply voltage VDD is powered on, and a first control signal is input to the first input terminal of the control circuit, and the first control signal is any fixed level between 0 and 1 / 2 VDD; the switch circuit is turned on, that is, the gate of the third transistor P3 is at a low level. At this time, the first transistor P1 and the second transistor P2 are both turned on, and the third transistor P3 is also turned on. Due to the different threshold voltage mismatch between the first transistor P1 and the second transistor P2, there is a voltage difference between the first power-on node Q and the second power-on node QB. Under the negative feedback of the feedback circuit, the voltage difference remains unchanged at a fixed level value, and the circuit reaches a monostable state.
[0056] Specifically, when the potential of the first power-on node Q rises, the potential of the gate of the fifth transistor N2 will also rise, that is, the potential of the second power-on node QB will be pulled down, and the third transistor P3 is in the on state, forming a negative feedback effect, preventing the potential of the second power-on node QB from continuing to be pulled down, thereby forming a monostable state.
[0057] In the second stage, the power supply voltage maintains the VDD power-on state, and the first input terminal of the control circuit maintains the input of the first control signal, that is, any fixed level between 0 and 1 / 2VDD; the switch circuit is turned off, that is, the gate of the third transistor P3 is at a high level, that is, VDD. At this time, because the switch circuit is turned off, under the positive feedback of the feedback circuit, the voltage difference between the first power-on node Q and the second power-on node QB gradually increases until the voltage of the first power-on node Q reaches VDD and the voltage of the second power-on node QB reaches 0, so that the voltage difference remains unchanged at the preset difference value, and the circuit is in a bistable state.
[0058] Specifically, in the second stage, the third transistor P3 is in the off state, and the potential of the second power-on node QB is pulled down. Since the third transistor P3 is in the off state, the potential of the gate of the fourth transistor N1 is pulled down, and the potential of the first power-on node Q will continue to rise, thereby forming a positive feedback, and the potential of the second power-on node QB continues to decrease, and the circuit forms a bistable state.
[0059] Thus, the circuit startup is completed, and the power-on result is read from the first power-on node Q and the second power-on node QB.
[0060] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:
[0061] The present invention provides an SRAM-PUF unit structure, comprising: a control circuit, a feedback circuit and a switch circuit between the control circuit and the feedback circuit, wherein a first control signal is inputted at an input end of the control circuit, and when the control switch circuit is turned on, a voltage difference is formed at two output ends of the feedback circuit; the first control signal is maintained unchanged at the input end of the control circuit, and when the control switch circuit is turned off, the voltage difference gradually increases to a preset difference value, and remains stable at the preset difference value, thereby preventing the power-on result from changing due to noise, thereby improving the reliability of the unit structure.
[0062] Embodiment 2
[0063] Based on the same inventive concept, the present invention also provides a memory, including the SRAM-PUF unit structure described in the first embodiment, to realize a static access function.
[0064] Embodiment 3
[0065] Based on the same inventive concept, the present invention also provides a power-on mode control method, which is applied to the SRAM-PUF unit structure described in the first embodiment. Figure 5 As shown, the method includes:
[0066] S501, inputting a first control signal to an input terminal of a control circuit, and when the control switch circuit is turned on, a voltage difference is formed at two output terminals of a feedback circuit;
[0067] S502, maintaining the first control signal unchanged at the input end of the control circuit, and when the control switch circuit is closed, the voltage difference gradually increases to a preset difference value, and remains stable at the preset difference value.
[0068] The power-on mode control method provided by the present invention has the same technical effect as the SRAM-PUF unit structure provided by the embodiment of the present invention, and will not be described in detail here.
[0069] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.
[0070] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.
Claims
1. A SRAM-PUF cell structure, characterized in that: include: A control circuit, a feedback circuit, and a switch circuit between the control circuit and the feedback circuit; When a first control signal is input to the input end of the control circuit and the switch circuit is controlled to be turned on, a voltage difference is formed at two output ends of the feedback circuit; When the first control signal is maintained unchanged at the input end of the control circuit and the switch circuit is controlled to be turned off, the voltage difference gradually increases to a preset difference value and remains stable at the preset difference value; The control circuit comprises: a first transistor and a second transistor, wherein a source of the first transistor and a source of the second transistor are both connected to a power supply voltage; The gate of the first transistor is connected to the gate of the second transistor and serves as a first input terminal for inputting the first control signal; The value of the first control signal is less than or equal to half the value of the power supply voltage; The switch circuit comprises: a third transistor, a source and a drain of the third transistor are connected between the drain of the first transistor and the drain of the second transistor respectively, and a gate of the third transistor is used as a second input terminal for inputting a second control signal; When the second control signal is at a low level, the switch circuit is turned on; When the second control signal is at a high level, the switch circuit is turned off; The feedback circuit includes: a fourth transistor and a fifth transistor, the source of the fourth transistor is connected to one end of the switch circuit and to the gate of the fifth transistor as a first power-on node, the gate of the fourth transistor is connected to the source of the fifth transistor and to the other end of the switch circuit as a second power-on node, and the drain of the fifth transistor and the drain of the fourth transistor are both grounded.
2. The SRAM-PUF cell structure according to claim 1, characterized in that: Also includes: a sixth transistor and a seventh transistor; The source of the sixth transistor is connected to one end of the switch circuit, the drain of the sixth transistor is connected to the bit line, and the gate of the sixth transistor is connected to the word line; The source of the seventh transistor is connected to the other end of the switch circuit, the drain of the seventh transistor is connected to the ground bit line, and the gate of the seventh transistor is connected to the word line.
3. A memory, characterized in that: include: The SRAM-PUF cell structure as claimed in any one of claims 1 to 2.
4. A control method for a power-on mode, characterized in that: The SRAM-PUF cell structure as claimed in claims 1 to 3 comprises: When a first control signal is input to the input end of the control circuit and the control switch circuit is turned on, a voltage difference is formed at two output ends of the feedback circuit; A second control signal is inputted into the input terminal of the switch circuit, and when the second control signal is at a low level, the switch circuit is turned on; when the second control signal is at a high level, the switch circuit is turned off; When the first control signal is maintained unchanged at the input end of the control circuit and the switch circuit is controlled to be closed, the voltage difference gradually increases to a preset difference value and remains stable at the preset difference value.
Citation Information
Patent Citations
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