Semiconductor structure and method for forming the same
By forming a second dielectric layer with high hardness in the semiconductor structure and etching the interconnection trenches and through holes, the problem of parasitic capacitance increases caused by the reduction of the conductive structure spacing is solved, and the performance of the semiconductor structure is improved.
Patent Information
- Application Number
- CN202010425635.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-05-19
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2040-05-19
AI Technical Summary
In the existing semiconductor structures, due to the decrease in the spacing between the conductive structures, the parasitic capacitance increases, the power consumption and resistance capacitance delay (RC delay) increase, affecting performance.
The first dielectric layer and the second dielectric layer are formed in sequence on the semiconductor substrate. The hardness of the second dielectric layer is greater than that of the first dielectric layer. The etching forms interconnection trenches and through holes. The interconnection structure exposes the electrical connection structure to avoid interlayers. The dielectric layer collapses to ensure the stable shape of the interconnect structure.
It effectively reduces parasitic capacitance, reduces power consumption and resistance capacitance delay, and improves the performance of semiconductor structures.
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Figure CN113690174B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] With the rapid development of semiconductor manufacturing technology, the integration of semiconductor structures (or integrated circuits, semiconductor chips) is getting higher and higher, making the size and gap between components or elements in the semiconductor structure smaller and smaller. For adjacent conductive structures, when the distance between the conductive structures is reduced, the parasitic capacitance between the adjacent conductive structures will become larger and larger, and the increased parasitic capacitance will lead to an increase in power consumption and an increase in resistance and capacitance delay (RC delay), thereby affecting the performance of the semiconductor structure.
[0003] In the back-end-of-line (BEOL) process of integrated circuit manufacturing, it is necessary to form an interconnection structure to electrically connect the independent components in the semiconductor structure and realize signal transmission between the components. In the existing process, the interconnection structure is usually formed in a through hole of a low dielectric constant material, so that the low dielectric constant material between the formed interconnection structures reduces the parasitic capacitance between the interconnection structures.
[0004] However, the performance of semiconductor structures formed by existing processes needs to be improved. Summary of the invention
[0005] An embodiment of the present invention provides a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.
[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising:
[0007] Providing a semiconductor substrate, wherein an active device is formed in the semiconductor substrate, and an electrical connection structure of the active device is exposed on a surface of the semiconductor substrate;
[0008] forming a first dielectric layer and a second dielectric layer in sequence on the semiconductor substrate, wherein the second dielectric layer has a greater hardness than the first dielectric layer;
[0009] Sequentially etching the second dielectric layer and the first dielectric layer to form an interconnection groove in the second dielectric layer, and forming an interconnection through hole in the first dielectric layer that is connected to the interconnection groove, wherein the interconnection through hole exposes at least a portion of the electrical connection structure of the active device;
[0010] An interconnect structure is formed in the interconnect via and the interconnect trench.
[0011] An embodiment of the present invention further provides a semiconductor structure, including:
[0012] A semiconductor substrate, wherein an active device is disposed in the semiconductor substrate, and an electrical connection structure of the active device is exposed on a surface of the semiconductor substrate;
[0013] A first dielectric layer located on the semiconductor substrate, wherein the first dielectric layer is provided with interconnection through holes, wherein the interconnection through holes expose at least a portion of the electrical connection structure of the active device;
[0014] a second dielectric layer located on the first dielectric layer, the second dielectric layer having a harderness than the first dielectric layer, an interconnection groove being arranged in the second dielectric layer, the interconnection groove being connected to the interconnection through hole;
[0015] An interconnect structure is located within the interconnect via and the interconnect trench.
[0016] An embodiment of the present invention also provides another semiconductor structure, including:
[0017] A semiconductor substrate, wherein an active device is disposed in the semiconductor substrate, and an electrical connection structure of the active device is exposed on a surface of the semiconductor substrate;
[0018] A first dielectric layer located on the semiconductor substrate, wherein the first dielectric layer is provided with interconnection through holes, and the interconnection through holes expose at least a portion of the electrical connection structure of the active device;
[0019] A third dielectric layer is located on the first dielectric layer, wherein an interconnection structure is disposed in the third dielectric layer, and the interconnection structure extends to the interconnection through hole and is connected to the electrical connection structure.
[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0021] In an embodiment of the present invention, a method for forming a semiconductor structure is provided, the method comprising: providing a semiconductor substrate, an active device is formed in the semiconductor substrate, and the surface of the semiconductor substrate exposes the electrical connection structure of the active device; forming a first dielectric layer and a second dielectric layer on the semiconductor substrate in sequence, the hardness of the second dielectric layer being greater than that of the first dielectric layer; forming an interconnection groove in the second dielectric layer, forming an interconnection through hole connected to the interconnection groove in the first dielectric layer, the interconnection through hole exposing at least part of the electrical connection structure of the active device; forming an interconnection structure in the interconnection through hole and the interconnection groove. It can be seen that in the embodiment of the present invention, the hardness of the second dielectric layer used to open the interconnection groove is relatively large, thereby avoiding the problem of easy collapse of the interlayer dielectric layer between the interconnection grooves, thereby avoiding deformation of the interconnection structure formed in the interconnection groove, and improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figures 1 to 14It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention;
[0023] Figures 15 to 20 is a schematic structural diagram corresponding to each step of etching the second dielectric layer and the first dielectric layer in an embodiment of the present invention;
[0024] Fig.21 is a structural schematic diagram corresponding to a semiconductor structure according to an embodiment of the present invention;
[0025] Fig. 22 It is a structural schematic diagram corresponding to another semiconductor structure of an embodiment of the present invention. DETAILED DESCRIPTION
[0026] As can be seen from the background technology, the performance of the semiconductor structure formed in the existing process needs to be improved. Now, the reason why the performance needs to be improved is analyzed in combination with a method for forming a semiconductor structure.
[0027] In existing technology processes, as the size of integrated chip components continues to scale down, the spacing between independent components in the semiconductor structure in the back-end of the line (BEOL) continues to decrease. As the distance between independent components in the semiconductor structure decreases, the parasitic capacitance generated between independent components in the semiconductor structure increases, which leads to higher power consumption and greater resistance and capacitance delay (RC delay) of the integrated chip. In order to improve performance and reduce parasitic capacitance between independent components in the semiconductor structure in the BEOL, integrated chip manufacturers use interlayer dielectric layers (IMDs) including materials with low dielectric constants (k).
[0028] For example, in recent technology processes, interlayer dielectric layers (IMDs) generally use dielectric materials with a dielectric constant (k) of low dielectric constant or ultra-low dielectric constant. However, interlayer dielectric layers formed of low dielectric constant materials, especially ultra-low dielectric constant materials, such as porous materials, have low hardness, which makes it easy for the interlayer dielectric layer located between the interconnection trenches to collapse during the process of etching to form interconnection trenches, thereby causing deformation of the interconnection structure subsequently formed in the interconnection trenches, thereby causing the performance of the device to be reduced.
[0029] An embodiment of the present invention relates to a method for forming a semiconductor structure, the method comprising: providing a semiconductor substrate, wherein an active device is formed in the semiconductor substrate, and the surface of the semiconductor substrate exposes the electrical connection structure of the active device; forming a first dielectric layer and a second dielectric layer on the semiconductor substrate in sequence, wherein the hardness of the second dielectric layer is greater than that of the first dielectric layer; forming an interconnection groove in the second dielectric layer, and forming an interconnection through hole connected to the interconnection groove in the first dielectric layer, wherein the interconnection through hole exposes at least part of the electrical connection structure of the active device; and forming an interconnection structure in the interconnection through hole and the interconnection groove. It can be seen that in the embodiment of the present invention, the hardness of the second dielectric layer used to open the interconnection groove is relatively large, thereby avoiding the problem that the interlayer dielectric layer between the interconnection grooves is prone to collapse, thereby avoiding deformation of the interconnection structure formed in the interconnection groove, and improving the performance of the device.
[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0031] Figures 1 to 14 It is a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure provided in an embodiment of the present invention.
[0032] See also Figure 1 , a semiconductor substrate 100 is provided, an active device 101 is formed in the semiconductor substrate 100 , and an electrical connection structure 102 of the active device 101 is exposed on a surface of the semiconductor substrate 100 .
[0033] The semiconductor substrate 100 is used to provide a process basis for subsequently forming an interconnection structure.
[0034] Specifically, the semiconductor substrate 100 may be a semiconductor substrate known in the art, such as a silicon substrate, a germanium substrate, or a germanium silicon substrate, and an active device 101 may be formed in the semiconductor substrate 100. The active device 101 is an electronic component for realizing a specific function. Optionally, the active device 101 may be a semiconductor structure such as an electron tube, a transistor, or an integrated circuit, and those skilled in the art may configure it according to actual needs.
[0035] See also Figure 2 , a first dielectric layer 110 and a second dielectric layer 120 are sequentially formed on the semiconductor substrate 100 , and the hardness of the second dielectric layer 120 is greater than that of the first dielectric layer 110 .
[0036] Optionally, the first dielectric layer 110 and the second dielectric layer 120 are used to provide a process basis for subsequently forming an interconnect structure. In order for the second dielectric layer 120 to play a supporting role in subsequently forming an interconnect structure 161 , the hardness of the second dielectric layer 120 is greater than that of the first dielectric layer 110 .
[0037] The material of the first dielectric layer 110 may be a low dielectric constant (k) material or an ultra-low dielectric constant (k) material, wherein the ultra-low dielectric constant material may be a material with a dielectric constant less than 2.6. Specifically, the material of the first dielectric layer 110 may be one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON.
[0038] In an embodiment of the present invention, the first dielectric layer 110 is a porous material of an ultra-low dielectric constant (k) material. The porous material can be formed by a deposition process. By making appropriate adjustments in the formation process, a porous material with low density and pores can be formed.
[0039] The material of the second dielectric layer 120 can be one or more of SiO 2 and SiN.
[0040] Optionally, the density of the material of the second dielectric layer 120 is greater than the density of the material of the first dielectric layer 110 , and correspondingly, the hardness of the second dielectric layer 120 is greater than the hardness of the first dielectric layer 110 .
[0041] The thickness of the first dielectric layer 110 and the second dielectric layer 120 may be 5 nm to 150 nm. Optionally, the second dielectric layer 120 may be formed by a deposition process.
[0042] It should be noted that, in the embodiment of the present invention, a first etch stop layer 111 is further formed between the semiconductor substrate 100 and the first dielectric layer 110, and a second etch stop layer 121 is further formed between the first dielectric layer 110 and the second dielectric layer 120. Specifically, this step may include: forming a first etch stop layer 111 on the semiconductor substrate 100; forming a first dielectric layer 110 on the first dielectric layer 111; forming a second etch stop layer 121 on the first dielectric layer 110; and forming a second dielectric layer 120 on the second etch stop layer 121, wherein the first etch stop layer 111 is different from the second etch stop layer 121.
[0043] Optionally, the first etch stop layer 111 is used as a stop layer in the process of etching to form interconnection through holes, so as to prevent the etching process from damaging the semiconductor substrate 100; the second etch stop layer 121 is used as a stop layer in the process of etching to form interconnection grooves, so as to prevent the etching process from damaging the first dielectric layer 110. When the first etch stop layer 111 is subsequently etched, the second etch stop layer 121 is exposed in the interconnection groove. In order to avoid damaging the second etch stop layer 121, in an embodiment of the present invention, the first etch stop layer 111 is different from the second etch stop layer 121.
[0044] The thickness of the first etch stop layer 111 and the second etch stop layer 121 may be 2 nm-8 nm.
[0045] The material of the first etch stop layer 111 may be one or more of AlN, Al2O3, WC, SiN, HfO2, La2O3, and Ta2O5; the material of the second etch stop layer 121 may be one or more of AlN, Al2O3, WC, SiN, HfO2, La2O3, and Ta2O5.
[0046] Optionally, the first etch stop layer 111 and the second etch stop layer 121 may be formed by a deposition process.
[0047] See also Figures 3 to 8 , the second dielectric layer 120 and the first dielectric layer 110 are etched in sequence, an interconnection groove 122 is formed in the second dielectric layer 120, and an interconnection through hole 112 connected to the interconnection groove 120 is formed in the first dielectric layer 110, wherein the interconnection through hole exposes at least a portion of the electrical connection structure 102 of the active device.
[0048] The interconnection through hole 112 is connected to the interconnection groove 122 to provide a process space for a subsequent interconnection structure to form an interconnection structure connected to the electrical connection structure.
[0049] Specifically, in order to etch the corresponding interconnection grooves and interconnection through holes, the step of etching the interconnection grooves can be formed by one-step etching, which can specifically include the following process:
[0050] See also Figure 3 to Figure 4 , a patterned hard mask layer 131 is formed on the second dielectric layer, wherein the hard mask layer exposes the second dielectric layer for forming a portion of the interconnect trench.
[0051] The hard mask layer 131 is used for patterning the second dielectric layer, and the second dielectric layer for forming the interconnection trench portion is a preset second dielectric layer for forming the interconnection trench region.
[0052] It should be noted that the preset area for forming the interconnection groove completely covers the preset area for forming the interconnection through-hole, so that the subsequently formed interconnection groove is connected to the interconnection through-hole. Optionally, the preset area for forming the interconnection groove is larger than the preset area for forming the interconnection through-hole, and the preset area for forming the interconnection through-hole is located within the preset area for forming the interconnection groove.
[0053] Furthermore, the area preset for forming the interconnection through-hole covers at least a portion of the area where the electrical connection structure of the active device is located, so that the interconnection through-hole formed subsequently exposes at least a portion of the electrical connection structure of the active device.
[0054] In this step, refer to Figure 3 , a hard mask material layer 130 may be formed first.
[0055] The hard mask material layer 130 may specifically be a dielectric hard mask material layer or a metal hard mask material layer. The material of the dielectric hard mask material layer may be one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide and carbon-containing silicon nitride. The material of the metal hard mask material layer may be titanium nitride, copper nitride or aluminum nitride.
[0056] Specifically, the hard mask material layer 130 may be formed by a chemical vapor deposition process.
[0057] Next, refer to Figure 4 , patterning the hard mask material layer to expose the second dielectric layer used to form the interconnect trench portion, and using the remaining hard mask material layer as the hard mask layer 131.
[0058] The hard mask layer is used to define a preset region of the second dielectric layer for forming an interconnection trench, so that in subsequent steps, the interconnection trench can be formed based on the hard mask layer.
[0059] Specifically, dry etching, wet etching or a combination of the two methods can be used to etch the hard mask material layer to form a patterned hard mask layer. Different etching parameters or etching solutions can be used to implement corresponding processes for different layer materials, which will not be described in detail here.
[0060] Specifically in this embodiment, a wet etching process can be used to etch the hard mask material layer. Specifically, in the wet etching process, the etching solution is a DHF solution or an EKC solution. Among them, the DHF solution is a hydrofluoric acid solution. Specifically, in the embodiment of the present invention, a dilute hydrofluoric acid solution can be used, such as a volume ratio less than or equal to 20%, such as 10%, 5% or 2%; EKC solution is an etching solution whose main components are hydroxylamine (HDA), 2-(2-aminoethoxy)ethanol (DGA), and catechol (Catechol).
[0061] See also Figure 5 An initial opening W1 is formed in the exposed second dielectric layer 120 , and the initial opening W1 exposes the second etch stop layer 121 for forming an interconnection through hole portion.
[0062] The initial opening W1 is used to define a preset area of the second etch stop layer for forming interconnection through holes, so that in subsequent steps, interconnection through holes can be formed based on the second etch stop layer.
[0063] In this step, the patterned photoresist layer can be used as a mask to etch the second dielectric layer (not shown in the figure). The second dielectric layer exposed by the patterned photoresist mask is the second dielectric layer used to form the interconnection through hole region.
[0064] In the embodiment of the present invention, dry etching, wet etching or a combination of the two methods may be used to etch the initial opening W1.
[0065] See also Figure 6 , the second etch stop layer at the bottom of the initial opening W1 is etched away.
[0066] Specifically, an etching process with a relatively high selectivity for etching the second etch stop layer can be used to directly etch the second etch stop layer exposed at the bottom of the initial opening W1 to obtain an exposed portion of the first dielectric layer. Alternatively, a patterned photoresist layer formed in the initial opening W1 can be used as a mask to etch the second etch stop layer exposed at the bottom of the initial opening W1 to obtain an exposed portion of the first dielectric layer.
[0067] It should be noted that, based on the initial opening W1, a preset area of the second etch stop layer for forming interconnection through holes is defined. The etching step in this step corresponds to the area defined by the initial opening W1, and the exposed portion of the first dielectric layer is also the area for forming interconnection through holes.
[0068] See also Figure 7 , using the hard mask layer 131 as a mask, etching the second dielectric layer to form interconnect trenches 122 in the second dielectric layer 120 .
[0069] After the second etch stop layer at the bottom of the initial opening is removed by etching, an etching step of the second dielectric layer may be performed to form an interconnection trench 122 in the second dielectric layer 120 .
[0070] Furthermore, in this step, the first dielectric layer 110 at the bottom of the initial opening is also etched away to form an interconnection through hole 112 in the first dielectric layer 110, so that the interconnection groove 122 and the interconnection through hole 112 are simultaneously formed in the etching process of this step.
[0071] It should be noted that, in this embodiment, the first dielectric layer and the second dielectric layer may be further set to be the same material, and the difference in hardness may be achieved by setting the material to have different densities, thereby facilitating the etching process in this step.
[0072] See also Figure 8 , the first etch stop layer at the bottom of the interconnection through hole 112 is removed by etching to expose at least a portion of the electrical connection structure 102 of the active device 101 .
[0073] Since the interconnection through hole 112 is located opposite to the electrical connection structure 102 of the active device 101 , the electrical connection structure 102 of the active device 101 can be exposed after the first etch stop layer 111 exposed at the bottom of the interconnection through hole 112 is removed by etching.
[0074] See also Figures 9 to 11 , forming an interconnection structure in the interconnection through hole and the interconnection trench.
[0075] After the interconnection through hole and the interconnection trench are formed based on the aforementioned etching of the second dielectric layer and the first dielectric layer, an interconnection structure is formed in the structure where the interconnection through hole and the interconnection trench are connected.
[0076] In an embodiment of the invention, in order to form an interconnection structure, this step may include the following process:
[0077] See also Fig. 9 , a barrier material layer 140 and a seed material layer 150 are sequentially formed to conformally cover the hard mask layer 131 , the interconnection via 112 , and the interconnection trench 122 .
[0078] Optionally, the barrier material layer 140 conformally covers the hard mask layer 131, the interconnection through hole 112 and the interconnection groove 122, and the selective etching ratio of the barrier material layer 140 and the second dielectric layer 120 is relatively large. For example, the selective etching ratio can be greater than or equal to 10:1, so that the barrier material layer 140 will not be affected when the second dielectric layer is subsequently removed.
[0079] In an optional implementation of the embodiment of the present invention, a deposition process can be used to form a barrier material layer 140 that conformally covers the hard mask layer 131, the interconnection through hole 112, and the surface of the interconnection groove 122 to protect the second dielectric layer 120, and then in the subsequent process of forming a seed layer, the second dielectric layer is protected from being diffused by the conductive material in the seed layer.
[0080] Specifically, the barrier material layer 140 is made of AlN, TiN, RuO2, TiO2, HfN, ZfO2, Al2O3, W, Ru or a metal alloy material. Correspondingly, the barrier material layer 140 can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) process.
[0081] The material of the barrier material layer 140 is different from that of the second dielectric layer 120 .
[0082] The thickness of the barrier material layer 140 should not be too large or too small. If it is too large, the semiconductor structure performance will be unstable, and if it is too small, it will not play a corresponding protective role. Therefore, in this embodiment, the thickness of the barrier material layer 140 is set to 10-200.
[0083] Optionally, the seed material layer 150 is formed on the barrier material layer 140 to conformally cover the seed material layer 150 . The seed material layer 150 can be used to provide a growth surface with good adhesion for the interconnect material layer during the process of forming the interconnect material layer.
[0084] Specifically, the seed material layer 150 may be made of Cu, which may be formed on the barrier material layer 140 by a damascene process. In other embodiments of the present invention, the seed material layer 150 may also be formed by an electroplating process or the like.
[0085] The thickness of the seed material layer 150 should not be too large or too small. The seed material layer 150 is located between the formed interconnect structure and the barrier material layer 140. The thickness of the seed material layer 150 should not be too large or too small. If the thickness of the seed material layer 150 is too small, the oxygen atoms in the barrier material layer 140 may diffuse into the seed material layer 150, causing part of the thickness of the seed material layer 150 to be oxidized, which may not provide a good growth surface for the formation of the interconnect material layer, thereby affecting the role of the seed material layer 150. If the thickness of the seed material layer 150 is too large, it may affect the electrical properties of the semiconductor structure, and may also cause material waste and increase the difficulty of the process. In this embodiment, the thickness of the seed material layer 150 can be 10 to 200.
[0086] See also Fig.10 , an interconnect material layer 160 is formed on the seed material layer 150 to completely fill the interconnect through hole and the interconnect trench.
[0087] Optionally, the interconnect material layer is formed on the seed material layer, wherein the interconnect material layer completely fills the interconnect through holes and the interconnect grooves, and the thickness of the interconnect material layer is not limited, specifically based on completely filling the interconnect through holes and the interconnect grooves.
[0088] The material of the interconnect material layer 160 may be one or more of W, Al, Ag, Cr, Co, Ni, Pt, Ti, Ta, Ru or Cu, which is not specifically limited in the present invention. Specifically, in this embodiment, the interconnect material layer 160 may be copper.
[0089] The interconnect material layer 160 may be formed by an electrochemical plating process.
[0090] See also Fig.11 , the hard mask layer and the barrier material layer, the seed material layer and the interconnect material layer located on the hard mask layer are removed by grinding, so that the remaining interconnect material layer in the interconnect through hole and the interconnect trench serves as the interconnect structure 161.
[0091] Optionally, the hard mask layer and the barrier material layer located on the hard mask layer are removed by grinding simultaneously, and the remaining barrier material layer is used as the barrier layer 141 , and the hard mask layer and the seed material layer located on the hard mask layer are removed by grinding simultaneously, and the remaining seed material layer is used as the seed layer 151 .
[0092] In this embodiment, in this step, the hard mask layer is removed by grinding while removing the barrier material layer, the seed material layer and the interconnect material layer, so that it is not necessary to set up other process steps to remove the hard mask layer, thus simplifying the process.
[0093] The barrier layer 141 is formed based on the barrier material layer, and the material of the barrier layer 141 is the material of the barrier material layer. Correspondingly, the material of the barrier layer 141 can also be AlN, TiN, RuO2, TiO2, HfN, ZfO2, Al2O3, W, Ru or a metal alloy material.
[0094] The seed layer 151 is formed based on the barrier material layer. The material of the seed layer 151 is the same as the material of the seed material layer. Correspondingly, the material of the seed layer may also be Cu.
[0095] The interconnect structure 161 is formed based on the interconnect material layer. The material of the interconnect structure 161 is the material of the interconnect material layer. Correspondingly, the interconnect structure 161 can be one or more of W, Al, Ag, Cr, Co, Ni, Pt, Ti, Ta, Ru or Cu. The present invention does not specifically limit this. Specifically, in this embodiment, the material of the interconnect structure can be copper.
[0096] Specifically, the grinding may be performed by a mechanical chemical grinding process, which is not specifically limited in the present invention.
[0097] In other optional implementations of the embodiment of the present invention, it may also include that a third dielectric layer is formed in the interconnect structure 161, and the dielectric constant of the third dielectric layer is smaller than that of the second dielectric layer.
[0098] In the embodiment of the present invention, the second dielectric layer may be further replaced by a third dielectric layer having a lower dielectric constant. Figure 12 to Figure 14 , which is a schematic diagram corresponding to each step of forming a third dielectric layer in an interconnect structure in an embodiment of the present invention.
[0099] See also Fig.12 , remove the second dielectric layer between the interconnect structures 161.
[0100] The second dielectric layer is removed to provide a process space for forming a third dielectric layer.
[0101] Specifically, the second dielectric layer may be removed by using a wet etching process or a dry etching process.
[0102] See also Figure 13 to Figure 14 , forming a third dielectric layer between the interconnect structures, wherein the dielectric constant of the third dielectric layer is smaller than that of the second dielectric layer.
[0103] The third dielectric layer having a dielectric constant smaller than that of the second dielectric layer is formed to reduce the parasitic capacitance between interconnect structures.
[0104] Specifically, refer to Fig.13 , forming a third dielectric material layer 170 that completely covers the interconnect structure.
[0105] The third dielectric material layer 170 may be a material layer used to form a third dielectric layer in an interconnect structure. The third dielectric material layer may be used to isolate the interconnect structure. Specifically, the third dielectric material layer 170 may be deposited on the interconnect structure.
[0106] Among them, the material of the third dielectric material layer can be the same as that of the first dielectric material layer, and the material of the third dielectric material layer can also be one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. The material of the third dielectric material layer can be the same as that of the first dielectric material layer, thereby simplifying the process difficulty and reducing process consumption.
[0107] In the embodiment of the present invention, the third dielectric material layer may be a porous material in an ultra-low dielectric constant material, and may be formed by a deposition process.
[0108] Optionally, a hole structure 172 may be formed in the third dielectric material layer 170. The third dielectric material layer is formed between and above the interconnect structures. When the distance between the interconnect structures is small, the parasitic capacitance is large, which increases power consumption and resistance and capacitance delay (RC delay); in this embodiment, the material of the third dielectric material layer itself may be a low dielectric constant (k) material, and the hole structure 172 formed in the third dielectric material layer may further reduce its dielectric constant, thereby reducing the parasitic capacitance of the interconnect structure, reducing the increase in power consumption and resistance and capacitance delay (RC delay), and thus improving the performance of the semiconductor structure.
[0109] The hole structure 172 can further reduce the material density of the third dielectric material layer by setting corresponding parameters when forming the third dielectric material layer, thereby causing holes to appear in the third dielectric material layer.
[0110] It should be noted that the holes are only formed between the interconnection structures, but not formed above the interconnection structures or at a position flush with the interconnection structures, so as to avoid poor surface morphology of the third dielectric layer formed subsequently.
[0111] See also Fig.14 , the third dielectric material layer on the interconnect structure 161 is removed by grinding, and the remaining third dielectric material layer is used as the third dielectric layer 171 .
[0112] Optionally, the removal of the third dielectric material layer on the interconnect structure by grinding may be achieved by a chemical mechanical grinding process, which will not be described in detail here.
[0113] An embodiment of the present invention relates to a method for forming a semiconductor structure, the method comprising: providing a semiconductor substrate, wherein an active device is formed in the semiconductor substrate, and the surface of the semiconductor substrate exposes the electrical connection structure of the active device; forming a first dielectric layer and a second dielectric layer on the semiconductor substrate in sequence, wherein the hardness of the second dielectric layer is greater than that of the first dielectric layer; forming an interconnection groove in the second dielectric layer, and forming an interconnection through hole connected to the interconnection groove in the first dielectric layer, wherein the interconnection through hole exposes at least part of the electrical connection structure of the active device; and forming an interconnection structure in the interconnection through hole and the interconnection groove. It can be seen that in the embodiment of the present invention, the hardness of the second dielectric layer used to open the interconnection groove is relatively large, thereby preventing the interlayer dielectric layer between the interconnection grooves from easily collapsing, preventing the interconnection structure formed in the interconnection groove from being deformed, and improving the performance of the device.
[0114] Furthermore, based on the interconnect structure that has been formed, after removing the second dielectric layer, a third dielectric layer with a low dielectric constant is refilled between the interconnect structures, and a hole structure is also formed in the third dielectric layer. Based on the low dielectric constant of the dielectric material of the third dielectric layer, the hole structure further reduces the dielectric constant between the interconnect structures. The third dielectric layer reduces power consumption and resistance-capacitance delay (RC delay) in the device while ensuring that the interconnect structure is not deformed.
[0115] In the above embodiment, the interconnection groove and the interconnection through hole can be formed in the same etching step. In another embodiment of the present invention, the interconnection groove and the interconnection through hole can also be formed by different etching steps. Specifically, based on the above embodiment, the step of sequentially etching the second dielectric layer and the first dielectric layer can also include:
[0116] In an optional implementation, see Figure 15 to Figure 16 , forming a patterned hard mask layer on the second dielectric layer, wherein the hard mask layer exposes the second dielectric layer for forming a portion of the interconnect trench.
[0117] See also Fig.15 , a hard mask material layer 130 covering the second dielectric layer may be formed on the second dielectric layer 120 first.
[0118] The hard mask material layer 130 may specifically be a dielectric hard mask material layer or a metal hard mask material layer. The material of the dielectric hard mask material layer may be one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide and carbon-containing silicon nitride. The material of the metal hard mask material layer may be titanium nitride, copper nitride or aluminum nitride.
[0119] Specifically, the hard mask material layer 130 may be formed by a chemical vapor deposition process.
[0120] Next, refer to Fig.16 , patterning the hard mask material layer to form a second dielectric layer exposing a portion for forming an interconnect trench, and using the remaining hard mask material layer as a hard mask layer 131 .
[0121] The hard mask layer 131 is used for patterning the second dielectric layer, and the second dielectric layer forming the interconnection trench portion is a second dielectric layer preset for forming the interconnection trench region.
[0122] Specifically, the hard mask material layer may be etched by dry etching, wet etching or a combination of the two methods. Different etching parameters or etching solutions may be used to implement corresponding processes for different layer materials, which will not be described in detail here.
[0123] See also Fig.17The second dielectric layer 120 is etched using the etched hard mask layer 131 as a mask to form an interconnection trench 122 in the second dielectric layer that exposes the second etch stop layer.
[0124] In the embodiment of the present invention, dry etching, wet etching or a combination of the two methods may be used to etch the interconnection grooves.
[0125] See also Fig.18 , a portion of the second etch stop layer 121 at the bottom of the interconnect trench 122 is etched to expose the first dielectric layer used to form the interconnect through hole portion.
[0126] The second etch stop layer at the bottom of the interconnection groove is partially removed by etching to expose the first dielectric layer forming the interconnection through hole portion, and a preset area of the second etch stop layer for forming the interconnection through hole is defined, so that in subsequent steps, the interconnection through hole can be formed based on the second etch stop layer.
[0127] See also Fig.19 After etching a portion of the second etch stop layer at the bottom of the interconnect trench, the first dielectric layer 110 exposed by the second etch stop layer is etched to form an interconnect through hole 112 in the first dielectric layer that exposes the first etch stop layer.
[0128] The etched second etch stop layer may expose the first dielectric layer for forming an interconnection through hole portion, and the exposed first dielectric layer is etched to form an interconnection through hole 112 in the first dielectric layer 110 that exposes the first etch stop layer 111 .
[0129] See also Fig. 20 , the first etch stop layer 111 at the bottom of the interconnection through hole 112 is removed by etching to expose at least a portion of the electrical connection structure 102 of the active device 101 .
[0130] Since the interconnection through hole 112 is located opposite to the electrical connection structure 102 of the active device 101 , the electrical connection structure 102 of the active device 101 can be exposed after the first etch stop layer 111 at the bottom of the interconnection through hole 112 is removed by etching.
[0131] In the embodiment of the present invention, the interconnection grooves and the interconnection through holes are formed by different etching steps, so the process control precision is high and the control difficulty is low.
[0132] See also Fig.21 The embodiment of the present invention further provides a semiconductor structure, the semiconductor structure comprising:
[0133] A semiconductor substrate 200, wherein an active device 201 is disposed in the semiconductor substrate, and an electrical connection structure 202 of the active device 201 is exposed on a surface of the semiconductor substrate;
[0134] A first dielectric layer 210 located on the semiconductor substrate 200, wherein the first dielectric layer 210 is provided with interconnection through holes 212, wherein the interconnection through holes 212 expose at least a portion of the electrical connection structure 202 of the active device 201;
[0135] A second dielectric layer 220 located on the first dielectric layer 210, wherein the second dielectric layer has a harder hardness than the first dielectric layer, and an interconnection groove 222 is provided in the second dielectric layer, wherein the interconnection groove 222 is connected to the interconnection through hole 212;
[0136] The interconnection structure 261 is located in the interconnection through hole 212 and the interconnection groove 222 .
[0137] Specifically, the semiconductor substrate 200 may be a semiconductor substrate known in the art, such as a silicon substrate, a germanium substrate, or a germanium silicon substrate, and an active device 201 may be disposed in the semiconductor substrate 200, and the active device 201 is used to realize an electronic component with a specific function. Optionally, the active device 201 may be a semiconductor structure such as an electron tube, a transistor, or an integrated circuit, and those skilled in the art may configure it according to actual needs.
[0138] The material of the first dielectric layer 210 may be a low dielectric constant (k) material or an ultra-low dielectric constant (k) material, wherein the ultra-low dielectric constant material may be a material having a dielectric constant less than 2.6. Specifically, the material of the first dielectric layer 210 may be one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON.
[0139] In the embodiment of the present invention, the first dielectric layer 210 is a porous material in an ultra-low dielectric constant material. The porous material can be formed by a deposition process. By making appropriate adjustments in the formation process, a porous material with low density and pores can be formed.
[0140] The material of the second dielectric layer 220 can be one or more of SiO 2 and SiN.
[0141] Optionally, the density of the material of the second dielectric layer 220 is greater than the density of the material of the first dielectric layer 210 , and correspondingly, the hardness of the second dielectric layer 220 is greater than the hardness of the first dielectric layer 210 .
[0142] The thickness of the first dielectric layer 210 and the second dielectric layer 220 may be 5 nm-150 nm.
[0143] Optionally, a first etch stop layer 211 is further disposed between the semiconductor substrate 200 and the first dielectric layer 210 , and a second etch stop layer 221 is further formed between the first dielectric layer 210 and the second dielectric layer 220 .
[0144] Optionally, the first etch stop layer 211 is used as a stop layer in the process of etching to form interconnection through holes, so as to prevent the etching process from damaging the semiconductor substrate 200, and the second etch stop layer 221 is used as a stop layer in the process of etching to form interconnection grooves, so as to prevent the etching process from damaging the first dielectric layer 210. When etching the first etch stop layer 211, the second etch stop layer 221 is exposed in the interconnection groove. In order to avoid damaging the second etch stop layer 221, in an embodiment of the present invention, the first etch stop layer 211 is different from the second etch stop layer 221.
[0145] The thickness of the first etch stop layer 211 and the second etch stop layer 221 may be 2 nm-8 nm.
[0146] The material of the first etch stop layer 211 may be one or more of AlN, Al2O3, WC, SiN, HfO2, La2O3, and Ta2O5; the material of the second etch stop layer 221 may be one or more of AlN, Al2O3, WC, SiN, HfO2, La2O3, and Ta2O5.
[0147] The material of the interconnect structure 261 may be one or more of W, Al, Ag, Cr, Co, Ni, Pt, Ti, Ta, Ru or Cu, which is not specifically limited in the embodiment of the present invention. Specifically, in this embodiment, the material of the interconnect structure may be copper.
[0148] In an optional implementation, it further includes: a seed layer 251 and a barrier layer 241 located below the interconnect structure 261 and between the interconnect via and the interconnect trench.
[0149] Specifically, the material of the barrier layer 241 is AlN, TiN, RuO2, TiO2, HfN, ZfO2, Al2O3, W, Ru or a metal alloy material.
[0150] The thickness of the barrier layer 241 should not be too large or too small. If it is too large, the semiconductor structure performance will be unstable, and if it is too small, it will not play a corresponding protective role. Therefore, in this embodiment, the thickness of the barrier layer 241 is set to 10-200.
[0151] The thickness of the seed layer 251 should not be too large or too small. The seed layer 251 is located between the formed interconnect structure and the barrier layer 241. The thickness of the seed layer 251 should not be too large or too small. If the thickness of the seed layer 251 is too small, the oxygen atoms in the barrier layer 241 may diffuse into the seed layer 251, causing part of the thickness of the seed layer 251 to be oxidized, affecting the function of the seed layer 251. If the thickness of the seed layer 251 is too large, it may affect the electrical properties of the semiconductor structure, and may also cause material waste and increase the difficulty of the process. In this embodiment, the thickness of the seed layer 251 can be 10 to 200.
[0152] In the semiconductor structure provided by the embodiment of the present invention, the second dielectric layer used to form the interconnection trenches has a relatively high hardness, thereby preventing the interlayer dielectric layer between the interconnection trenches from easily collapsing and preventing the interconnection structure formed in the interconnection trenches from deforming, thereby improving the performance of the device.
[0153] See also Fig. 22 , an embodiment of the present invention further provides another semiconductor structure, the semiconductor structure comprising:
[0154] A semiconductor substrate 300 , in which an active device 301 is disposed, and an electrical connection structure 302 of the active device 301 is exposed on a surface of the semiconductor substrate 301 ;
[0155] A first dielectric layer 310 located on the semiconductor substrate 300 , wherein the first dielectric layer 310 is provided with interconnection through holes 312 , and the interconnection through holes 312 expose at least a portion of the electrical connection structure 302 of the active device 301 ;
[0156] A third dielectric layer 371 is located on the first dielectric layer 310 . An interconnection structure 361 is disposed in the third dielectric layer 371 . The interconnection structure 361 extends to the interconnection through hole 312 and is connected to the electrical connection structure 302 .
[0157] Specifically, a first etch stop layer 311 is disposed between the semiconductor substrate 300 and the first dielectric layer 310 , and a second etch stop layer 321 is disposed between the first dielectric layer 310 and the third dielectric layer 371 , wherein the first etch stop layer 311 is different from the second etch stop layer 322 .
[0158] Among them, in the embodiment of the present invention, Fig.21 The description of the same names can be found in the previous text and will not be repeated here.
[0159] The following is an embodiment of the present invention Fig.21The differences are described below, wherein the material of the third dielectric layer 371 may be the same as the material of the first dielectric layer 310, and the material of the third dielectric layer may also be one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. The material of the third dielectric layer may be the same as that of the first dielectric layer, thereby simplifying the process difficulty and reducing process consumption.
[0160] In the embodiment of the present invention, the material of the third dielectric layer may be a porous material in ultra-low dielectric constant materials.
[0161] Optionally, a hole structure 372 is provided in the third dielectric layer 371. The third dielectric material layer is provided between the interconnect structures and above the interconnect structures. When the distance between the interconnect structures is small, the parasitic capacitance is large, which increases power consumption and resistance and capacitance delay (RC delay); in this embodiment, the material of the third dielectric material layer itself can be a low dielectric constant (k) material, and the hole structure 372 is provided in the third dielectric material layer to further reduce its dielectric constant, thereby reducing the parasitic capacitance of the interconnect structure, reducing the increase in power consumption and resistance and capacitance delay (RC delay), and thus improving the performance of the semiconductor structure.
[0162] The holes can be formed by setting corresponding parameters when forming the third dielectric material layer, so that the density of the material of the third dielectric layer is further reduced, thereby causing holes to appear in the third dielectric layer.
[0163] It should be noted that the holes are only arranged between the interconnection structures, but not arranged above the interconnection structures or at a position flush with the interconnection structures, so as to avoid poor surface morphology of the arranged third dielectric layer.
[0164] Furthermore, in the semiconductor structure disclosed in the embodiment of the present invention, a third dielectric layer with a low dielectric constant is re-set between the interconnection structures. A hole structure is also set in the third dielectric layer. Based on the fact that the dielectric constant of the material of the third dielectric layer is low, the hole structure further reduces the dielectric constant between the interconnection structures. The third dielectric layer can reduce the power consumption and resistance-capacitance delay (RC delay) in the device while ensuring that the interconnection structure is not deformed.
[0165] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, please refer to the corresponding description in the above embodiment, which will not be repeated here.
[0166] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein an active device is formed in the semiconductor substrate, and an electrical connection structure of the active device is exposed on a surface of the semiconductor substrate; forming a first dielectric layer and a second dielectric layer in sequence on the semiconductor substrate, wherein the second dielectric layer has a greater hardness than the first dielectric layer; Sequentially etching the second dielectric layer and the first dielectric layer to form an interconnection groove in the second dielectric layer, and forming an interconnection through hole in the first dielectric layer that is connected to the interconnection groove, wherein the interconnection through hole exposes at least a portion of the electrical connection structure of the active device; forming an interconnect structure in the interconnect through hole and the interconnect trench; After the step of forming the interconnection structure, the method further includes: removing the second dielectric layer with a full thickness between the interconnection structures; A third dielectric layer is formed between the interconnect structures, and the dielectric constant of the third dielectric layer is smaller than that of the second dielectric layer.
2. The method for forming a semiconductor structure according to claim 1, wherein: A hole structure is formed in the third dielectric layer.
3. The method for forming a semiconductor structure according to claim 1, wherein: The first dielectric layer and / or the third dielectric layer is made of ultra-low dielectric constant material.
4. The method for forming a semiconductor structure according to claim 1, wherein: In the step of sequentially forming the first dielectric layer and the second dielectric layer on the semiconductor substrate, a first etch stop layer is also formed between the semiconductor substrate and the first dielectric layer, and a second etch stop layer is also formed between the first dielectric layer and the second dielectric layer, wherein the first etch stop layer is different from the second etch stop layer.
5. The method for forming a semiconductor structure according to claim 4, wherein: The step of sequentially etching the second dielectric layer and the first dielectric layer comprises: forming a patterned hard mask layer on the second dielectric layer, wherein the hard mask layer exposes the second dielectric layer for forming a portion of the interconnect trench; forming an initial opening in the exposed second dielectric layer, wherein the initial opening exposes a second etch stop layer for forming an interconnection through hole portion; Etching and removing the second etch stop layer at the bottom of the initial opening; After etching away the second etch stop layer at the bottom of the initial opening, etching the second dielectric layer using the hard mask layer as a mask to form an interconnection trench in the second dielectric layer; In the step of etching the second dielectric layer, the first dielectric layer at the bottom of the initial opening is also etched away to form interconnection through holes in the first dielectric layer; The first etch stop layer at the bottom of the interconnection through hole is removed by etching to expose at least a portion of the electrical connection structure of the active device.
6. The method for forming a semiconductor structure according to claim 4, wherein: The step of sequentially etching the second dielectric layer and the first dielectric layer comprises: forming a patterned hard mask layer on the second dielectric layer, wherein the hard mask layer exposes the second dielectric layer for forming a portion of the interconnect trench; Using the hard mask layer as a mask, etching the second dielectric layer to form an interconnection trench exposing the second etch stop layer in the second dielectric layer; Etching a portion of the second etch stop layer at the bottom of the interconnect trench to expose the first dielectric layer used to form an interconnect through hole portion; After etching a portion of the second etch stop layer at the bottom of the interconnection trench, etching the first dielectric layer exposed by the second etch stop layer to form an interconnection through hole in the first dielectric layer that exposes the first etch stop layer; The first etch stop layer at the bottom of the interconnection through hole is removed by etching to expose at least a portion of the electrical connection structure of the active device.
7. The method for forming a semiconductor structure according to claim 5 or 6, characterized in that: The step of forming an interconnection structure in the interconnection through hole and the interconnection trench comprises: sequentially forming a barrier material layer and a seed material layer conformally covering the hard mask layer, the interconnection via and the interconnection trench; forming an interconnect material layer on the seed material layer that completely fills the interconnect via and the interconnect trench; The hard mask layer and the barrier material layer, the seed material layer and the interconnect material layer located on the hard mask layer are removed by grinding, so that the interconnect material layer remaining in the interconnect through hole and the interconnect trench serves as an interconnect structure.
8. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a third dielectric layer between the interconnect structures comprises: forming a third dielectric material layer completely covering the interconnect structure; The third dielectric material layer on the interconnect structure is removed by grinding, and the remaining third dielectric material layer is used as the third dielectric layer.
9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first dielectric layer is one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. The material of the third dielectric layer is one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON. One or more of SiON.
10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second dielectric layer is one or more of SiO2 and SiN.
11. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the first dielectric layer is 5nm-150nm, and the thickness of the second dielectric layer is 5nm-150nm.
12. The method for forming a semiconductor structure according to claim 4, wherein: The materials of the first etch stop layer and the second etch stop layer are one or more of AlN, Al2O3, WC, SiN, HfO2, La2O3, and Ta2O5, and the materials of the first etch stop layer and the second etch stop layer are different.
13. The method for forming a semiconductor structure according to claim 4, wherein: The thickness of the first etch stop layer is 2nm-8nm, and the thickness of the second etch stop layer is 2nm-8nm.
14. A semiconductor structure, characterized in that: include: A semiconductor substrate, wherein an active device is disposed in the semiconductor substrate, and an electrical connection structure of the active device is exposed on a surface of the semiconductor substrate; A first dielectric layer located on the semiconductor substrate, wherein the first dielectric layer is provided with interconnection through holes, and the interconnection through holes expose at least a portion of the electrical connection structure of the active device; A third dielectric layer is located on the first dielectric layer, wherein an interconnection structure is arranged in the third dielectric layer, wherein the interconnection structure extends to the interconnection through hole and is connected to the electrical connection structure, wherein the top of the third dielectric layer is flush with the top of the interconnection structure, wherein a hole structure is formed in the third dielectric layer, and wherein the hole structure is arranged only between the interconnection structures.
15. The semiconductor structure according to claim 14, wherein: The first dielectric layer and / or the third dielectric layer is made of ultra-low dielectric constant material.
16. The semiconductor structure according to claim 14, wherein: A first etch stop layer is further disposed between the semiconductor substrate and the first dielectric layer, and a second etch stop layer is further disposed between the first dielectric layer and the third dielectric layer, wherein the first etch stop layer is different from the second etch stop layer.