Electronic device, electronic package and packaging substrate thereof

Abstract

The present invention relates to an electronic device, an electronic package, and a package substrate thereof. The package substrate of the electronic package has a ground pad and a power pad, and the power pad surrounds the ground pad in at least three directions to increase the area occupied by the power pad on the package substrate, thereby preventing the electronic components connected to the package substrate from being broken and effectively reducing voltage drop.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to an electronic device capable of improving voltage drop, an electronic package and a package substrate thereof. Background Art

[0002] Currently, chip packaging uses a Flip Chip Land Grid Array (FCLGA) process. Chips used in this FCLGA process must meet low voltage (e.g., 0.3V to 0.5V) and high current (e.g., 20A to 50A) specifications. Therefore, the voltage drop (IR drop) in the power supply system connected to the FCLGA process affects chip performance. A greater IR drop results in lower chip performance.

[0003] like Figure 1 and Figure 1A As shown, the conventional FCLGA semiconductor package 1 is configured by flip-chipping a semiconductor chip 11 on a die-laying surface 10b of a package substrate 10 via a plurality of conductive bumps 110, and then the semiconductor chip 11 is covered with a package layer 12. The lower surface 10a of the package substrate 10 is provided with a signal pad 100, a ground pad 101 and a power pad 102, which is then connected to a circuit board (not shown) so that a power system transmits power from the power pad 102 to the semiconductor chip 11 via the circuit board.

[0004] However, the vertical projection area B of the semiconductor chip 11 toward the lower surface 10a is located correspondingly between the ground pad 101 and the power pad 102. Figure 1 and Figure 1A As shown, the semiconductor chip 11 is arranged across the ground pad 101 and the power pad 102 at the same time. Therefore, the package substrate 10 is often deformed due to thermal expansion and contraction during the thermal cycle of the packaging process, causing it to warp and even crack the semiconductor chip 11.

[0005] In addition, although the industry has changed the occupied area of ​​the ground pad 101 ′ and the power pad 102 ′ on the lower surface 10 a, such as Figure 1B The package substrate 10' shown in FIG. 1 is a package substrate 10' with an enlarged ground pad 101'.

[0006] The area occupied by the lower surface 10a is reduced, and the area occupied by the power pad 102' on the lower surface 10a is reduced, so that the vertical projection area B of the semiconductor chip 11 facing the lower surface 10a is correspondingly located in the ground pad 101' rather than in the power pad 102'. This prevents the semiconductor chip 11 from being broken due to warping of the package substrate 10'. However, reducing the area occupied by the power pad 102' on the lower surface 10a will result in a significant reduction in the current provided by the power pad 102' to the semiconductor chip 11, thereby significantly increasing the voltage drop (IR drop), resulting in poor performance of the semiconductor chip 11.

[0007] Therefore, how to overcome the various problems of the above-mentioned prior art has become a difficult problem that needs to be overcome urgently in the industry. Summary of the Invention

[0008] In view of the above-mentioned defects of the prior art, the present invention provides an electronic device, an electronic package and a package substrate thereof, which can avoid the problem of the electronic component being broken.

[0009] A first aspect of an embodiment of the present invention provides a packaging substrate, comprising: a substrate body having a first surface and a second surface relative to each other; a grounding pad formed on the first surface of the substrate body; and a power pad formed on the first surface of the substrate body and surrounding at least three positions of the grounding pad.

[0010] In the aforementioned packaging substrate, the power pad is horseshoe-shaped or U-shaped.

[0011] In the aforementioned package substrate, the second surface of the substrate body defines a die placement area. For example, a vertical projection area of ​​the die placement area toward the first surface corresponds to being located in the ground pad, but not in the power pad. Furthermore, the power pad surrounds the vertical projection area.

[0012] In the aforementioned packaging substrate, the substrate body has at least one electrical contact pad formed on the first surface and / or the second surface.

[0013] A second aspect of the embodiments of the present invention provides an electronic package, comprising: the package substrate as described in the first aspect; and an electronic component disposed on the second surface of the package substrate and electrically connected to the ground pad and the power pad.

[0014] In the aforementioned electronic package, the vertical projection area of ​​the electronic component toward the first surface is correspondingly located in the ground pad, but not in the power pad. For example, the power pad surrounds the vertical projection area.

[0015] In the aforementioned electronic package, the electrical contact pad is electrically connected to the electronic component.

[0016] A third aspect of an embodiment of the present invention provides an electronic device comprising: a plurality of packaging substrates as described in the first aspect; a first wire electrically connected to a ground pad of each of the packaging substrates; and a second wire electrically connected to a power pad of each of the packaging substrates.

[0017] The aforementioned electronic device further includes an electronic component disposed on the second surface of the package substrate and electrically connected to the ground pad and the power pad. For example, a vertical projection of the electronic component toward the first surface corresponds to the ground pad and is not located within the power pad. Furthermore, the power pad surrounds the vertical projection.

[0018] In the aforementioned electronic device, the substrate body has at least one electrical contact pad formed on the first surface and / or the second surface, and the electrical contact pad is electrically connected to the electronic component.

[0019] As can be seen from the above, the electronic device, electronic package, and packaging substrate of the present invention mainly increase the area occupied by the power pad on the substrate body by surrounding the ground pad in at least three directions via the power pad. Therefore, compared with the prior art, the present invention can not only avoid the problem of electronic component fragmentation, but also effectively reduce voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package.

[0021] Figure 1A for Figure 1 3D schematic diagram of .

[0022] Figure 1B A schematic plan view of an existing packaging substrate.

[0023] Figure 2A It is a schematic cross-sectional side view of the electronic package of the present invention.

[0024] Figure 2B for Figure 2A 3D schematic diagram of .

[0025] Figure 2C for Figure 2A Schematic diagram of the floor plan.

[0026] Figure 3 FIG. 1 is a schematic side view of the electronic device of the present invention.

[0027] Figure 3 'for Figure 3 Partial floor plan.

[0028] Description of Reference Numerals

[0029] 1 Semiconductor Package

[0030] 10,10',2a package substrate

[0031] 10a Lower surface

[0032] 10b crystal plane

[0033] 100 signal pads

[0034] 101,101',201 grounding pad

[0035] 102,102',202 Power Pad

[0036] 11. Semiconductor Chips

[0037] 110,210 conductive bumps

[0038] 12,22 Encapsulation Layer

[0039] 2 Electronic packaging

[0040] 20 substrate body

[0041] 20a First surface

[0042] 20b Second surface

[0043] 200 first electrical contact pad

[0044] 200' second electrical contact pad

[0045] 201a Main pad

[0046] 201b External part

[0047] 202a End

[0048] 21 Electronic components

[0049] 3 Electronic devices

[0050] 30 circuit boards

[0051] 31 First conductor

[0052] 32 Second wire

[0053] A,B,21' vertical projection area

[0054] S is the crystal area. DETAILED DESCRIPTION

[0055] The following describes the embodiments of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0056] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical content disclosed in the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, terms such as "on" and "a" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be considered as the scope of the implementation of the present invention without substantially changing the technical content.

[0057] Figures 2A to 2C Schematic diagram of the electronic package 2 of the present invention. Figures 2A to 2C As shown, the electronic package 2 includes: a package substrate 2 a , an electronic component 21 and a package layer 22 . The package substrate 2 a includes a substrate body 20 , at least one ground pad 201 and at least one power pad 202 .

[0058] The substrate body 20 is roughly rectangular. Figure 2B As shown, it has a first surface 20a and a second surface 20b opposite to each other.

[0059] In this embodiment, the substrate body 20 may be a package substrate (substrate) having a core layer and a circuit portion or a coreless circuit structure, which includes at least one insulating layer and at least one circuit layer combined with the insulating layer, such as at least one fan-out type redistribution layer (RDL for short). For example, the circuit layer includes the ground pad 201 and the power pad 202. Specifically, the circuit layer of the substrate body 20 further includes a plurality of first electrical contact pads 200 formed on the first surface 20a as signal pads, and the circuit layer of the substrate body 20 may also include a plurality of second electrical contact pads 200' formed on the second surface 20b (such as the crystal placement area S), such as Figure 2A It should be understood that the substrate body 20 can also be other chip-carrying plates, such as a silicon interposer, or other plates with metal routing, and is not limited to the above.

[0060] Furthermore, the substrate body 20 can be manufactured using a variety of substrate carrier processes. For example, a wafer-based process can be used to form the circuit layer, with silicon nitride or silicon oxide formed as the insulating layer via chemical vapor deposition (CVD). Alternatively, a conventional wafer-based process can be used to form the circuit layer, where a relatively low-cost polymer dielectric material, such as polyimide (PI), polybenzoxazole (PBO), prepreg (PP), molding compound, photosensitive dielectric layer, or other materials, can be used as the insulating layer via coating.

[0061] In addition, the second surface 20b of the substrate body 20 defines a crystallization region S, such as Figure 2A For example, the die placement area S is substantially rectangular, and its vertical projection area A toward the first surface 20a is correspondingly located in the ground pad 201, but not in the power pad 202. Specifically, as Figure 2C As shown, the power pad 202 surrounds three edges of the vertically projected area A.

[0062] In addition, the first electrical contact pads 200 are spaced apart from each other along one edge of the first surface 20a, such as Figure 2B and Figure 2C shown.

[0063] The ground pad 201 is formed on the first surface 20 a of the substrate body 20 and is electrically connected to the second electrical contact pad 200 ′.

[0064] In this embodiment, the ground pad 201 is substantially T-shaped or a variation thereof, such as Figure 2B For example, the ground pad 201 is defined as a main pad portion 201a corresponding to the vertical projection area A and an external portion 201b arranged along the edge of the first surface 20a. Specifically, the main pad portion 201a is substantially rectangular and located in the middle of the first surface 20a, and the external portion 201b is arranged along two adjacent edges of the first surface 20a and is in a crutch or L-shape, as shown in FIG. Figure 2C shown.

[0065] The power pads 202 are formed on the first surface 20 a of the substrate body 20 and surround at least three locations of the ground pad 201 (main pad portion 201 a ) and are electrically connected to the second electrical contact pad 200 ′.

[0066] In this embodiment, the power pad 202 is in a horseshoe shape, a U shape or a variation thereof, such as Figure 2BFor example, the power pad 202 surrounds three edges of the main pad portion 201a of the ground pad 201. Specifically, as Figure 2C As shown, the two end portions 202a of the power pad 202 are spaced apart from the external connection portion 201b of the ground pad 201, so that the shape of the power pad 202 and the shape of the ground pad 201 complement each other, so as to maximize the area occupied by the power pad 202 and the ground pad 201 on the first surface 20a. Figure 2C shown.

[0067] The electronic component 21 is disposed on the die-slot region S of the second surface 20 b of the package substrate 2 a and is electrically connected to the ground pad 201 and the power pad 202 via the second electrical contact pad 200 ′.

[0068] In this embodiment, the electronic component 21 is an active component, a passive component, or a combination thereof, and the active component is, for example, a semiconductor chip, while the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 21 is disposed on the second surface 20b of the substrate body 20 in a flip-chip manner via a plurality of conductive bumps 210 such as solder material and electrically connected to the second electrical contact pad 200', and the conductive bumps 210 can be optionally coated with a primer (omitted); alternatively, the electronic component 21 is electrically connected to the second electrical contact pad 200' via a plurality of bonding wires such as gold wires (omitted); or, the electronic component 21 can directly contact the second electrical contact pad 200' to electrically connect to the second electrical contact pad 200'. However, the method for electrically connecting the electronic component 21 to the circuit layer is not limited to the above.

[0069] Furthermore, the electronic component 21 is generally rectangular, with its vertical projection area 21' toward the first surface 20a correspondingly located within the ground pad 201 and not within the power pad 202. For example, the power pad 202 surrounds the vertical projection area 21' of the electronic component 21. Specifically, the area of ​​the main pad portion 201a of the ground pad is greater than or equal to the area of ​​the vertical projection area 21' of the electronic component 21 toward the first surface 20a.

[0070] The packaging layer 22 is formed on the second surface 20 b of the packaging substrate 2 a to cover the electronic component 21 and the conductive bumps 210 .

[0071] In this embodiment, the encapsulation layer 22 is an insulating material, such as polyimide (PI), dry film, or an encapsulant or molding compound such as epoxy. For example, the encapsulation layer 22 can be formed on the substrate body 20 using a liquid compound, injection, lamination, or compression molding. Specifically, the electronic package 2 utilizes a flip chip land grid array (FCLGA) packaging process line to encapsulate the package substrate 2a, electronic component 21, and encapsulation layer 22.

[0072] Therefore, the electronic package 2 or package substrate 2a of the present invention mainly increases the area occupied by the power pad 202 on the first surface 20a by surrounding the ground pad 201 in at least three directions via the power pad 202, thereby significantly increasing the amount of current provided by the power pad 202 to the electronic component 21 and shortening the power supply path. Therefore, compared with the prior art, the electronic package 2 or package substrate 2a of the present invention can effectively reduce the voltage drop (IR drop). Specifically, as shown in the table below, the overall voltage drop of the electronic package 2 or package substrate 2a of the present invention is improved by about 60% (i.e., a comparison ratio of 0.39X) compared to the prior art, wherein the Figure 1A The overall voltage drop of the package substrate 10 is taken as a reference X, and X=13.98.

[0073] Figure 1A Figure 1B The present invention Power signal (VDD) voltage drop (unit: mV) 5.18 13.42 5.02 Ground signal (VSS) voltage drop (unit: mV) 8.8 0.41 0.4 Overall voltage drop 13.98 13.83 5.42 Comparison ratio X 0.99X 0.39X

[0074] In addition, since the power pad 202 surrounds at least three directions of the ground pad 201 , the electronic package 2 or the package substrate 2 a can provide the power required by the electronic component 21 in multiple directions.

[0075] In addition, the vertical projection area 21' of the electronic component 21 toward the first surface 20a is not located in the power pad 202, so the electronic component 21 does not span the ground pad 201 and the power pad 202. Therefore, compared with the prior art, the electronic component 21 of the electronic package 2 of the present invention will not be broken due to the warping of the packaging substrate 2a.

[0076] In addition, if Figure 3 and Figure 3 As shown in FIG. 1 , in subsequent applications, multiple package substrates 2 a or electronic packages 2 may be serially connected on a printed circuit board (PCB) 30 to form an electronic device 3 .

[0077] In this embodiment, the package substrate 2a or electronic package 2 is attached to the circuit board 30 with its first surface 20a, and the electronic device 3 includes a first conductive wire 31 electrically connected to each ground pad 201 and a second conductive wire 32 electrically connected to each power pad 202. For example, the first conductive wire 31 and the second conductive wire 32 may be surface wiring layers of the circuit board 30; alternatively, the first conductive wire 31 and the second conductive wire 32 may be wires soldered to contacts on the circuit board 30. Specifically, the external connection portions 201b of the ground pads 201 are connected in series via a first conductive wire 31, and the power pads 202 are connected in series via a second conductive wire 32.

[0078] Therefore, the electronic device 3 of the present invention surrounds the ground pad 201 in at least three directions via the power pad 202 , so that the circuit board 30 or the power system (not shown) can provide the power required by the electronic component 21 in multiple directions.

[0079] In summary, the electronic device, electronic package, and packaging substrate of the present invention increase the area occupied by the power pad on the substrate body by surrounding the ground pad in at least three directions. Therefore, the present invention not only prevents the problem of electronic component breakage but also effectively reduces voltage drop, thereby significantly improving the reliability of the electronic component.

[0080] The above embodiments are intended only to illustrate the principles and effects of the present invention and are not intended to limit the present invention. Any skilled artisan may modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the appended claims.

Claims

1. A packaging substrate, characterized in that: include: A substrate body having a first surface and a second surface opposite to each other; a ground pad formed on the first surface of the substrate body; as well as a power pad formed on the first surface of the substrate body and surrounding at least three locations of the ground pad; A die placement area is defined on the second surface of the substrate body, and a vertical projection area of ​​the die placement area toward the first surface is correspondingly located in the ground pad but not in the power pad.

2. The packaging substrate according to claim 1, wherein The power pad is horseshoe-shaped or U-shaped.

3. The packaging substrate according to claim 1, wherein The power pad surrounds the vertically projected area.

4. The packaging substrate according to claim 1, wherein: The substrate body has at least one electrical contact pad formed on the first surface and / or the second surface.

5. An electronic package, characterized in that: include: The packaging substrate according to claim 1; as well as The electronic component is disposed on the second surface of the package substrate and is electrically connected to the ground pad and the power pad.

6. The electronic package according to claim 5, wherein: A vertical projection area of ​​the electronic component toward the first surface is correspondingly located in the ground pad but not in the power pad.

7. The electronic package according to claim 6, wherein: The power pad surrounds the vertically projected area.

8. The electronic package according to claim 5, wherein: At least one electrical contact pad is formed on the first surface and / or the second surface of the substrate body, and the electrical contact pad is electrically connected to the electronic component.

9. An electronic device, characterized in that: include: A plurality of packaging substrates according to claim 1; a first conductive line electrically connected to the ground pads of each package substrate; as well as The second wire is electrically connected to the power pads of each packaging substrate.

10. The electronic device according to claim 9, wherein: The power pad is horseshoe-shaped or U-shaped.

11. The electronic device according to claim 9, wherein: The power pad surrounds the vertically projected area.

12. The electronic device according to claim 9, wherein: The substrate body has at least one electrical contact pad formed on the first surface and / or the second surface.

13. The electronic device according to claim 9, wherein: The electronic device further comprises an electronic element which is arranged on the second surface of the packaging substrate and electrically connected to the ground pad and the power pad.

14. The electronic device according to claim 13, wherein: A vertical projection area of ​​the electronic component toward the first surface is correspondingly located in the ground pad but not in the power pad.

15. The electronic device according to claim 14, wherein: The power pad surrounds the vertically projected area.

16. The electronic device according to claim 13, wherein: At least one electrical contact pad is formed on the first surface and / or the second surface of the substrate body, and the electrical contact pad is electrically connected to the electronic component.

Images