A chip and method for implementing an equihash algorithm

Abstract

A chip and a method for implementing an Equihash algorithm, the chip comprising: a pingpong structure data storage memory comprising a ping memory and a pong memory; and a processing module configured to, in the process of processing each nonce, alternately use a first memory and a second memory to store intermediate data and an intermediate serial number generated in a current round, and / or use the memory used in a previous round to read intermediate data and an intermediate serial number generated in the previous round, and sequentially write the read intermediate serial number; the first memory is the ping memory, and the second memory is the pong memory; or the first memory is the pong memory, and the second memory is the ping memory; the embodiments of the present application can enable the Equihash algorithm to be implemented in a pipeline manner, and improve the processing efficiency of the Equihash algorithm.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of encryption algorithm and chip design, and particularly relates to a chip and a method for implementing an Equihash algorithm. BACKGROUND

[0002] As a shared database, the data or information stored in the blockchain has the characteristics of "unforgeable", "full trace", "traceable", "open and transparent", and "collective maintenance". Based on these characteristics, the blockchain technology lays a solid foundation for "trust" and creates a reliable "cooperation" mechanism, which has a broad application prospect. The Equihash algorithm is a memory-oriented proof-of-work algorithm developed by the SnT (Security, Reliability and Trust) Interdisciplinary Center of the University of Luxembourg, and its theoretical basis is a famous computational science and cryptography problem: the generalized birthday paradox problem. The implementation process of the Equihash algorithm is to first construct the input condition, that is, the block header and parameters of the last block in the blockchain, then convert the input condition into the general form of the generalized birthday paradox problem, analyze the problem and judge the difficulty of the obtained solution, and if the algorithm condition and difficulty condition are met, the solution is successful, the proof of work is completed, and a new block is generated; otherwise, adjust the parameters and re-operate.

[0003] The Equihash(n, k) algorithm has its distinctive features: on the one hand, it is memory-based, and on the other hand, it is easy to verify. The generalized birthday paradox is to find two k colliding data samples in N n-bit data samples, N = 2 n / (k+1)+1 , the data sample X 1 ..N is generated by the block header block header and nonce; wherein nonce is an arbitrary or non-repeating random number value that is only used once.

[0004] In an example, the block header includes a 4-byte block version number nVersion, which indicates which block verification rule to follow; a 32-byte hashPrevBlock, which represents the block header block header of the previous block; a 32-byte hashMerkleRoot, which allows adjustment by adding, deleting, or changing the order of transactions contained in the block, or modifying the input field of the Coinbase transaction; a 32-byte hashReserved, which is a reserved field; a 4-byte nTime, which is generally the Unix timestamp when the machine starts hashing the header; a 4-byte nBits, which is determined by the total network computing power, and is adjusted once for each new block; a 32-byte nNonce, which provides 2 256A value that can be taken by changing nNonce to change the block header to eventually produce a hash less than or equal to the target. So hashMerkleRoot and nNonce are two fields that play the degree of freedom.

[0005] An effective Equihash solution should satisfy the following conditions: A: generalized birthday paradox condition, that is, 2 k The XOR result of the sample is 0; B: for the rth round (0 k After arranging the 2 r Sample data in dictionary order, the XOR of every 2

[0006] In order to find an effective Equihash solution, Wagner algorithm is generally used: after generating N X i , sort X i , find all X i , X j with the first n / (k+1) bit collision, and save the XOR result X ij between them; then sort all X ij , find the next X ij , X mn with n / (k+1) collision; repeat the above process for k-1 rounds, until there are only 2n / (k+1) bits without collision. In the last step, find the result X with the last 2n / (k+1) bit collision, which is the final Equihash solution.

[0007] Taking the Equihash(200, 9) algorithm calculation process as an example, N=2 21 ; for each nonce, it is divided into initialization round, 8 intermediate rounds and final round, a total of 10 rounds of calculation process. As shown in Figure 1 , including the following steps 101-105:

[0008] Among them, 101-102 are initialization rounds, 101, the algorithm calculates 2 21 200-bit original data through the blake 2B data generator module according to the data of several bytes transmitted from outside; 102, according to the low 20 bits of the original data, the original data is classified and stored in the memory according to a certain rule, as the intermediate data and intermediate serial number used in the first intermediate round.

[0009] 103-104 are performed for 8 rounds, corresponding to 8 intermediate rounds, and the calculation characteristics of the 8 intermediate rounds are similar; 103, all or part of the data stored in the last round are read out, and the intermediate sequence numbers in the data are sequentially stored, and the same type of data in the read data is calculated by XOR according to the classification result, to generate the intermediate data and the intermediate sequence number of the current round; 104, according to the next 20 bits of the intermediate data as the calculation result, the intermediate data is classified, and the classified intermediate data and the intermediate sequence number are stored in the memory. If it is not the 8th intermediate round, 104 is executed and then returns to 103, and if it is the 8th intermediate round, 104 is executed and then 105 is performed.

[0010] 105 is the final round, all or part of the intermediate data stored in the last round (i.e. the 8th intermediate round) are read out, and the same type of data is calculated by XOR according to the classification result, if the calculation result is equal to binary all 0, the intermediate sequence numbers saved in the 8 intermediate rounds are read according to a certain rule to generate the required data combination that needs to be found, until all the data are read.

[0011] The calculation process of other Equihash algorithms is similar, only the parameters in the calculation process according to n and k will change, for example, for Equihash (144, 5) algorithm, N=25, 2 25 original data are generated first, 4 intermediate rounds are performed, and classification is performed according to 24 bits.

[0012] The calculation speed of the Equihash algorithm will affect the generation speed of the new block in the blockchain, at present, how to improve the calculation speed of the Equihash algorithm is a problem to be studied. SUMMARY

[0013] The following is a summary of the subject matter of the detailed description of the present application. This summary is not intended to limit the scope of protection.

[0014] The present application provides a chip and a method for implementing the Equihash algorithm, which can improve the processing speed of the Equihash algorithm through improvement on hardware.

[0015] In one aspect, the present application provides a chip for implementing the Equihash algorithm, comprising:

[0016] pingpong structure data storage, including ping memory and pong memory;

[0017] the processing module is configured to, in processing each nonce, alternately use the first memory and the second memory to store intermediate data and intermediate serial numbers generated in the current round, and / or use the memory used in the last round to read intermediate data and intermediate serial numbers generated in the last round and sequentially write the read intermediate serial numbers;

[0018] The first memory is a ping memory, and the second memory is a pong memory, or the first memory is a pong memory, and the second memory is a ping memory.

[0019] Optionally, the chip further comprises:

[0020] The selector is configured to select one of the ping memory and the pong memory as the first memory and the other as the second memory according to preset processing parameters.

[0021] The first memory and the second memory of two adjacent nonces are different.

[0022] Optionally, the processing module is further configured to, when performing a final round of an Nth nonce, perform an initialization round of an N+1th nonce in parallel; N≥1.

[0023] Optionally, the processing module, when performing a final round of an Nth nonce, performing an initialization round of an N+1th nonce in parallel comprises:

[0024] When the processing module uses the ping memory to read in the final round of the nonce N, the initialization round of the nonce N+1 is simultaneously started, and the pong memory is used for storage in the initialization round; or when the processing module uses the pong memory to read in the final round of the nonce N, the initialization round of the nonce N+1 is simultaneously started, and the ping memory is used for storage in the initialization round.

[0025] Optionally, the preset processing parameter is a nonce serial number.

[0026] The selector selects one of the ping memory and the pong memory as the first memory and the other as the second memory according to preset processing parameters.

[0027] The selector selects the ping memory as the first memory and the pong memory as the second memory when the nonce serial number is odd, and selects the pong memory as the first memory and the ping memory as the second memory when the nonce serial number is even.

[0028] Alternatively, the selector selects the pong memory as the first memory and the ping memory as the second memory when the nonce number is odd; and selects the ping memory as the first memory and the pong memory as the second memory when the nonce number is even.

[0029] Optionally, the selector comprises a data reading path selector and a data storage path selector.

[0030] The data reading path selector is configured to select one of the ping memory and the pong memory as a reading memory according to preset processing parameters when the processing module reads the intermediate data and the intermediate number generated in the last round.

[0031] The data storage path selector is configured to select one of the ping memory and the pong memory as a first writing memory for storing the intermediate data and the intermediate number generated in the current round according to preset processing parameters when the processing module stores the intermediate data and the intermediate number generated in the current round, and to select one of the ping memory and the pong memory as a second writing memory for sequentially storing the intermediate number read after the processing module reads the intermediate data and the intermediate number generated in the last round according to preset processing parameters.

[0032] In this way, the reading memory selected in the final round for a previous nonce and the first writing memory selected in the initial round for a next nonce are different memories.

[0033] In another aspect, the present application also provides a method for implementing an Equihash algorithm, which is applied to the chip for implementing the Equihash algorithm.

[0034] The nonce is processed; in the process of processing each nonce, a first memory and a second memory are alternately used to store the intermediate data and the intermediate number generated in the current round, and / or the memory used in the last round is used to read the intermediate data and the intermediate number generated in the last round, and the read intermediate number is sequentially written.

[0035] In this way, the reading memory selected in the final round for a previous nonce and the first writing memory selected in the initial round for a next nonce are different memories.

[0036] Optionally, the method further comprises:

[0037] determine the first memory and the second memory according to preset processing parameters;

[0038] wherein the first memory and the second memory of two adjacent nonces are different.

[0039] Optionally, the method further comprises:

[0040] when a final round of the Nth nonce is performed, an initialization round of the (N+1)th nonce is performed in parallel; N≥1.

[0041] Optionally, the preset processing parameter is a nonce serial number.

[0042] the when a final round of the Nth nonce is performed, an initialization round of the (N+1)th nonce is performed in parallel comprises:

[0043] when a read is performed on the final round of nonce N using the ping memory, an initialization round of nonce N+1 is started at the same time, and the pong memory is used for storage of the initialization round; or when a read is performed on the final round of nonce N using the pong memory, an initialization round of nonce N+1 is started at the same time, and the ping memory is used for storage of the initialization round.

[0044] Compared with the related art, the embodiment of the application ingeniously applies the pingpong structure memory to implement the Equihash algorithm, and in the processing process of one nonce, different memories in the pingpong structure memory are alternately used, the processing efficiency of the Equihash algorithm is improved, and the Equihash algorithm can be implemented in a pipeline manner.

[0045] Other aspects can be appreciated upon reading and understanding the attached figures and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0046] The accompanying drawings are used to provide an understanding of the technical solutions of the application, and constitute a part of the specification, and are used together with the embodiments of the application to explain the technical solutions of the application, and do not constitute a limitation on the technical solutions of the application.

[0047] Figure 1 is an implementation process diagram of an Equihash (200, 9) algorithm;

[0048] Figure 2 is a schematic diagram of a chip for implementing the Equihash algorithm provided by the embodiment of the application;

[0049] Figure 3is a schematic diagram of a chip for implementing an Equihash algorithm according to an example embodiment of the present application;

[0050] Figure 4 is a schematic diagram of data storage in the implementation process of Equihash (200, 9) algorithm in Example One;

[0051] Figure 5 is a schematic diagram of data storage in the implementation process of Equihash (200, 9) algorithm in Example Two. DETAILED DESCRIPTION

[0052] The present application describes a number of embodiments, but the description is exemplary rather than limiting and it will be apparent to those of ordinary skill in the art that numerous more embodiments and implementations are possible within the scope of the embodiments described in the present application. Although a number of possible combinations of features have been set forth in the appended figures and discussed above, many other combinations of the disclosed features are possible. Unless specifically intended otherwise, any feature or element of any embodiment can be used in combination with any other feature or element of any other embodiment, or in combination with any other feature or element of the same embodiment.

[0053] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in the present application can be implemented alone or in any suitable combination. Moreover, various modifications and changes can be made within the scope of protection.

[0054] Furthermore, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on more than one step, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps can be possible, depending on the implementation, without departing from the spirit and scope of the present application. Thus, the particular sequence of steps set forth in the specification is not a limitation of the application. Other steps can be utilized without departing from the spirit and scope of the present application, and not all steps described are required for the practice or implementation of the application.

[0055] In addition, the descriptions such as "first", "second" and the like in the present application are only used for differentiation in the description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise explicitly and specifically limited.

[0056] The chip for implementing the Equihash algorithm provided in the embodiments of the present application can implement the Equihash algorithm in a pipelined manner, improve the calculation efficiency of the Equihash algorithm, and further improve the generation speed of blocks in a blockchain system.

[0057] The chip of the present embodiment is shown in Figure 2 The chip of the present embodiment is shown in

[0058] The pingpong structure data storage 21 includes a ping memory 211 and a pong memory 212.

[0059] The processing module 22 is configured to, in the process of processing each nonce, alternately use the first memory and the second memory to store the intermediate data and the intermediate sequence number generated in the current round, and / or use the memory used in the last round to read the intermediate data and the intermediate sequence number generated in the last round, and sequentially write the read intermediate sequence number

[0060] The first memory is the ping memory 211, and the second memory is the pong memory 212; or the first memory is the pong memory 212, and the second memory is the ping memory 211.

[0061] In the process of processing one nonce, the present embodiment alternately uses different memories in the pingpong structure memory, improves the processing efficiency of the Equihash algorithm, and enables the Equihash algorithm to be implemented in a pipelined manner. The present embodiment further improves the generation efficiency of new blocks for a blockchain system using the Equihash algorithm.

[0062] In the present embodiment, the pingpong structure data storage 21 is used. Under the premise that each memory can provide one read port and one write port, the pingpong structure can provide one read port for reading the intermediate data and the intermediate sequence number generated in the last round, and two write ports, one of which is on the same memory as the read port for reading the data in the last round, for sequentially storing the read intermediate sequence number, and the other write port can be used to store the intermediate data and the intermediate sequence number generated in the current round.

[0063] The chip implementing the Equihash algorithm provided in the embodiment may be, but is not limited to, an ASIC (Application Specific Integrated Circuit) chip.

[0064] The pingpong structure memory is ingeniously applied to implement the Equihash algorithm in the embodiment, the processing procedure of each intermediate round in the algorithm is divided into two parts, reading and writing (reading the intermediate data and the intermediate serial number generated in the last round and sequentially writing the read intermediate serial number) and writing (writing the intermediate data and the intermediate serial number generated in the current round), and different memories in the pingpong structure memory are accessed respectively, so that the read intermediate serial number, the intermediate data and the intermediate serial number generated in the current round can be written in parallel, the two writing procedures are isolated and do not affect each other, and the processing efficiency of the intermediate round is improved; in adjacent intermediate rounds, different memories are alternately used for storing the intermediate data and the intermediate serial number (the ping memory is used for storing in the current round, and the pong memory is used for storing in the last round / next round; or the pong memory is used for storing in the current round, and the ping memory is used for storing in the last round / next round), and correspondingly, different memories are alternately used for reading the data generated in the last round (the memory storing the data generated in the last round is the memory used for reading in the current round), so that the intermediate data and the intermediate serial number generated in the last round can be directly read in the current round without changing the memory, and implementation is more rapid.

[0065] In an example embodiment, alternately using the first memory and the second memory to store the intermediate data and the intermediate serial number generated in the current round, and / or using the memory used in the last round to read the intermediate data and the intermediate serial number generated in the last round and sequentially writing the read intermediate serial number can include:

[0066] The initialization round is performed, and the generated data is stored in the first memory;

[0067] The odd round and the even round of the intermediate round are alternately performed, the odd round reads the intermediate data and the intermediate serial number generated in the last round from the first memory, sequentially saves the intermediate serial number in the first memory, and stores the intermediate data and the intermediate serial number generated in the current round in the second memory; the even round reads the intermediate data and the intermediate serial number generated in the last round from the second memory, sequentially saves the intermediate serial number in the second memory, and stores the intermediate data and the intermediate serial number generated in the current round in the first memory;

[0068] After the intermediate round is completed, the data generated in the last intermediate round is read from the first memory to perform the processing of the final round.

[0069] In one example embodiment, the chip implementing the Equihash algorithm can further include:

[0070] a selector configured to select one of the ping memory and the pong memory as the first memory and the other as the second memory according to preset processing parameters;

[0071] wherein the first memory for two adjacent nonces is different (e.g., the first memory for nonce N is the ping memory and the first memory for nonce N+1 is the pong memory; or the first memory for nonce N is the pong memory and the first memory for nonce N+1 is the ping memory); correspondingly, the second memory is also different.

[0072] In this embodiment, since the final round and the initialization round for adjacent nonces use different memories, the final round and the initialization round for adjacent nonces can be fully or partially overlapped in processing time, thereby speeding up the processing.

[0073] In one implementation of this embodiment, the processing module 22 can be further configured to perform the initialization round for nonce N+1 in parallel when performing the final round for nonce N; N≥1.

[0074] This implementation includes two cases:

[0075] Case 1: When the ping memory 211 is used for reading for the final round of nonce N, the initialization round for nonce N+1 is started at the same time, and the pong memory 212 is used for storing the initialization round.

[0076] Case 2: When the pong memory 212 is used for reading for the final round of nonce N, the initialization round for nonce N+1 is started at the same time, and the ping memory 211 is used for storing the initialization round.

[0077] In this embodiment, the processing module 22 can perform the final round of the previous nonce and the initial round of the next nonce in parallel, and access different memories respectively, for example, while the final round of the previous nonce uses the ping memory to read intermediate data, the initial round of the next nonce has started to work and write data into the pong memory, or while the final round of the previous nonce uses the pong memory to read intermediate data, the initial round of the next nonce has started to work and write classified data into the ping memory. In this way, the final round and the initial round of two adjacent nonces can be performed at the same time, isolated from each other and not affecting each other, so that the pipeline processing process is increased by multiplexing, becoming a pipeline multiplexing mode.

[0078] The embodiment finds and ingeniously utilizes the characteristics that the initial round only performs data storage operation and the final round only performs data reading operation through careful observation and research on the Equihash algorithm process, designs a scheme that can perform pipeline multiplexing in the process of performing the Equihash algorithm, time-multiplexes the final round of the previous nonce calculation and the initial round of the next nonce calculation, realizes the maximum utilization of the memory, and improves the calculation efficiency and the logical resource utilization rate.

[0079] In an embodiment of the present embodiment, the preset processing parameter can be a nonce serial number.

[0080] The selector selects one of the ping memory and the pong memory as the first memory and the other as the second memory according to the preset processing parameter, and the method comprises the steps of:

[0081] The selector selects the ping memory as the first memory and the pong memory as the second memory when the nonce serial number is odd, and selects the pong memory as the first memory and the ping memory as the second memory when the nonce serial number is even.

[0082] Alternatively, the selector selects the pong memory as the first memory and the ping memory as the second memory when the nonce serial number is odd, and selects the ping memory as the first memory and the pong memory as the second memory when the nonce serial number is even.

[0083] In an embodiment of the present embodiment, the implementation of the Equihash algorithm is as shown in the following figure: Figure 3 The selector can include a data reading path selector 23 and a data storage path selector 24.

[0084] The data read path selector 23 is used to select one of the ping memory 211 and the pong memory 212 as the read memory when the processing module 22 reads the intermediate data and intermediate sequence number generated in the previous round.

[0085] The data storage path selector 24 is used to select one of the ping memory 211 and the pong memory 212 according to preset processing parameters when the processing module 22 stores the intermediate data and intermediate sequence number generated in the current round, and to use it as the first write memory for storing the intermediate data and intermediate sequence number generated in the current round; and to select one of the ping memory 211 and the pong memory 212 according to preset processing parameters after the processing module 22 reads the intermediate data and intermediate sequence number generated in the previous round, and to use it as the second write memory for sequentially storing the read intermediate sequence number.

[0086] Among them, for two adjacent nonces, the read memory selected in the final round of the previous nonce and the first write memory selected in the initial round of the next nonce are different memories.

[0087] In this embodiment, the first write memory of the initialization wheel, the read memory of the final wheel, the read memory and second write memory of each odd-numbered intermediate wheel, and the first write memory of each even-numbered intermediate wheel are the same memory, namely the first memory; the first write memory of each odd-numbered intermediate wheel, the read memory and second write memory of each even-numbered intermediate wheel are the same memory, namely the second memory.

[0088] In this embodiment, the memory to be used is selected separately during each round of processing. An alternative to this embodiment is that the first and second memories for each nonce can be determined based on preset processing parameters at the beginning of each nonce's processing. This eliminates the need to select a memory during each round of processing for that nonce. For example, if the first memory for a certain nonce is determined to be the ping memory, then the initialization round, the final round, the read / write operations of odd-numbered intermediate rounds, and the write operations of even-numbered intermediate rounds for the data generated in this round all use the ping memory.

[0089] In this embodiment, the selected preset processing parameters should ensure that the memory selected in each round meets the following conditions:

[0090] (1) The read memory and the second write memory selected in the same intermediate wheel are the same, and the first write memory is a different memory;

[0091] (2) The read memory used by adjacent intermediate wheels is different from each other; combined with condition (1), it can be seen that the first and second write memory used by adjacent intermediate wheels will also be different from each other accordingly;

[0092] (3) The write memory of the initialization round, the read memory of the first intermediate round, the write memory of the eighth intermediate round, and the read memory of the final round are the same.

[0093] (4) The write memories of adjacent nonce initialization rounds are different from each other. In combination with condition (3), the read memory of the first intermediate round, the write memory of the eighth intermediate round, and the read memory of the final round of adjacent nonce are also different accordingly.

[0094] In the embodiment, the read memory, the first and second write memories can be selected according to the preset processing parameters, or any one of the three memories can be determined according to the preset processing parameters, and then the other two memories can be determined according to condition (1). For example, after determining that the read memory of the current intermediate round is the ping memory, the intermediate serial number read is sequentially written to the ping memory, and the intermediate data and the intermediate serial number generated in the current round are written to the pong memory.

[0095] In the embodiment, for the initialization round and the final round, the preset processing parameter can be the nonce serial number of the current processing; for the intermediate round, the preset processing parameter can be the sum of the nonce serial number and the current round number.

[0096] In one case, the first write memory of the initialization round and the read memory of the final round are the ping memory when the nonce serial number is odd; the first write memory of the initialization round and the read memory of the final round are the pong memory when the nonce serial number is even. For the intermediate round, when the sum of the nonce serial number and the current round number is even, the read memory and the second write memory are the ping memory, and the first write memory is the pong memory; when the sum is odd, the read memory and the second write memory are the pong memory, and the first write memory is the ping memory.

[0097] For example, in the implementation of Equihash (200, 9) algorithm, for nonce1, the initialization round and the final round use ping memory; the 1st, 3rd, 5th, 7th intermediate rounds, the sum of nonce serial number and current round number is even, ping memory is used for reading and writing (reading the intermediate data and intermediate serial number generated in the last round, sequentially writing the read intermediate serial number), pong memory is used for writing the data generated in the current round (including the intermediate data and intermediate serial number generated in the current round); the 2nd, 4th, 6th, 8th intermediate rounds, the sum of nonce serial number and current round number is odd, pong memory is used for reading and writing, ping memory is used for writing the data generated in the current round. Correspondingly, for nonce2, the initialization round and the final round use pong memory; the 1st, 3rd, 5th, 7th intermediate rounds, the sum of nonce serial number and current round number is odd, pong memory is used for reading and writing, ping memory is used for writing the data generated in the current round; the 2nd, 4th, 6th, 8th intermediate rounds, the sum of nonce serial number and current round number is even, ping memory is used for reading and writing, pong memory is used for writing the data generated in the current round. The case of Equihash using other n, k combinations can be analogized, which is not described here.

[0098] In another case, the first write memory of the initialization round and the read memory of the final round are pong memories when the nonce serial number is odd; the first write memory of the initialization round and the read memory of the final round are ping memories when the nonce serial number is even. For the intermediate rounds, when the sum of nonce serial number and current round number is even, the read memory and the second write memory are pong memories, and the first write memory is a ping memory; when the sum is odd, the read memory and the second write memory are ping memories, and the first write memory is a pong memory.

[0099] For example, in the implementation of the Equihash (200, 9) algorithm, for nonce1, the initialization round and the final round use the pong memory; the 1st, 3rd, 5th, and 7th intermediate rounds, the sum of the nonce serial number and the current round number is even, use the pong memory to read and write, and use the ping memory to write the data generated in the current round; the 2nd, 4th, 6th, and 8th intermediate rounds, the sum of the nonce serial number and the current round number is odd, use the ping memory to read and write, and use the pong memory to write the data generated in the current round. Correspondingly, for nonce2, the initialization round and the final round use the ping memory; the 1st, 3rd, 5th, and 7th intermediate rounds, the sum of the nonce serial number and the current round number is odd, use the ping memory to read and write, and use the pong memory to write the data generated in the current round; the 2nd, 4th, 6th, and 8th intermediate rounds, the sum of the nonce serial number and the current round number is even, use the pong memory to read and write, and use the ping memory to write the data generated in the current round. The Equihash with other n, k combinations can be similarly deduced, which is not described here.

[0100] The embodiment of the present application also provides a method for implementing the Equihash algorithm, applied to the chip for implementing the Equihash algorithm provided by any of the above embodiments; the method comprises:

[0101] processing the nonce; in the process of processing each nonce, alternately using the first memory and the second memory to store the intermediate data and the intermediate serial number generated in the current round, and / or using the memory used in the last round to read the intermediate data and the intermediate serial number generated in the last round, and sequentially writing the read intermediate serial number;

[0102] wherein the first memory is a ping memory, and the second memory is a pong memory; or the first memory is a pong memory, and the second memory is a ping memory.

[0103] In an example embodiment, in the process of processing each nonce, alternately using the first memory and the second memory to store the intermediate data and the intermediate serial number generated in the current round, and / or using the memory used in the last round to read the intermediate data and the intermediate serial number generated in the last round, and sequentially writing the read intermediate serial number comprises:

[0104] performing the initialization round, and storing the generated data in the first memory;

[0105] The odd-numbered rounds and the even-numbered rounds of the intermediate rounds are alternately performed, the odd-numbered rounds read the intermediate data and the intermediate sequence number generated in the last round from the first memory, save the intermediate sequence number in the first memory in sequence, and store the intermediate data and the intermediate sequence number generated in the current round in the second memory; the even-numbered rounds read the intermediate data and the intermediate sequence number generated in the last round from the second memory, save the intermediate sequence number in the second memory in sequence, and store the intermediate data and the intermediate sequence number generated in the current round in the first memory.

[0106] The data generated in the last intermediate round is read from the first memory for processing in the final round.

[0107] In an example embodiment, the method of implementing the Equihash algorithm can further include:

[0108] The first memory and the second memory are determined according to preset processing parameters.

[0109] The first memory and the second memory of the two adjacent nonces are different.

[0110] In an example embodiment, the method of implementing the Equihash algorithm can further include:

[0111] When the final round of the Nth nonce is performed, the initialization round of the (N+1)th nonce is performed in parallel; N≥1.

[0112] In the present embodiment, optionally, the preset processing parameter is the nonce sequence number.

[0113] When the final round of the Nth nonce is performed, the initialization round of the (N+1)th nonce is performed in parallel, including:

[0114] When the final round of the nonce N is read using the ping memory, the initialization round of the nonce N+1 is started at the same time, and the pong memory is used for storage of the initialization round; or, when the final round of the nonce N is read using the pong memory, the initialization round of the nonce N+1 is started at the same time, and the ping memory is used for storage of the initialization round.

[0115] Two examples are used below to illustrate the embodiments of the present application. The two examples below are both processes of implementing the Equihash (200, 9) algorithm, but the scheme of the embodiments of the present application is not limited to the Equihash (200, 9) algorithm, and is applicable to Equihash algorithms with any combination of n and k.

[0116] Example One

[0117] The example provides a pipeline implementation method of Equihash (200, 9) algorithm, and it is assumed that two consecutive nonces 1 and nonce2 are calculated in the example. The implementation process in the example is divided into the following two cases.

[0118] In case 1, the initialization round storage and the final round reading are both for the ping memory, and the intermediate data and the intermediate sequence number generated in the last round are read from the ping memory in the odd intermediate round. The read intermediate sequence number is sequentially stored in the ping memory, and the intermediate data and the intermediate sequence number generated in the current round are saved in the pong memory. The intermediate data and the intermediate sequence number generated in the last round are read from the pong memory in the even intermediate round, and the intermediate sequence number is sequentially stored in the pong memory. The intermediate data and the intermediate sequence number generated in the current round are saved in the ping memory. The schematic diagram of data storage in the implementation process of the Equihash algorithm in this case is shown in FIG. 1. Figure 4

[0119] In case 1, the implementation process of the Equihash algorithm includes the following steps 201-208.

[0120] 201, the initialization round is performed for nonce1, the generated original data is classified and stored as intermediate data in the ping memory, and then steps 202 and 203 are alternately performed.

[0121] 202, the odd rounds (1st, 3rd, 5th, and 7th rounds) of the intermediate round are performed for nonce1, and the intermediate data and the intermediate sequence number in the ping memory are read. The read intermediate sequence number is sequentially stored in the ping memory, and then the same data in the read intermediate data is calculated by XOR according to the classification result, to generate the intermediate data and the intermediate sequence number in the current round. After classifying the generated intermediate data, the intermediate sequence number is stored in the pong memory.

[0122] 203, the even rounds (2nd, 4th, 6th, and 8th rounds) of the intermediate round are performed for nonce1, and the intermediate data and the intermediate sequence number in the pong memory are read. The read intermediate sequence number is sequentially stored in the pong memory, and then the same data in the read intermediate data is calculated by XOR according to the classification result, to generate the intermediate data and the intermediate sequence number in the current round. After classifying the generated intermediate data, the intermediate sequence number is stored in the ping memory. After the 8th round, step 204 is performed.

[0123] ​204. Perform the final round for nonce1, read all or part of the intermediate data from the ping memory, XOR the same type of data in the read intermediate data according to the classification result, if the calculation result is binary all 0, then generate data combination according to the intermediate sequence number stored in the first to eighth intermediate rounds, for subsequent calculation.

[0124] 205-208 correspond to 201-204 one by one, the difference is that the processing object changes from nonce1 to nonce2, and the others are the same.

[0125] Case 2, in this case, whether for nonce1 or nonce2, the initialization round storage and the final round reading are all for the pong memory, the odd intermediate rounds read the intermediate data and the intermediate sequence number generated by the previous round from the pong memory; the read intermediate sequence number is sequentially stored into the pong memory, and the intermediate data and the intermediate sequence number generated by this round are saved into the ping memory; the even intermediate rounds read the intermediate data and the intermediate sequence number generated by the previous round from the ping memory, and the intermediate sequence number is sequentially stored into the ping memory, and the intermediate data and the intermediate sequence number generated by this round are saved into the pong memory for the final round reading.

[0126] In case 2, the implementation process of the Equihash algorithm includes steps 301-308:

[0127] 301. Perform the initialization round for nonce1, generate the original data and perform classification, and store the intermediate data into the pong memory; then alternately perform steps 302 and 303.

[0128] 302. Perform the odd rounds (1st, 3rd, 5th, 7th rounds respectively) of the intermediate rounds for nonce1, read the intermediate data and the intermediate sequence number in the pong memory; the read intermediate sequence number is sequentially stored into the pong memory, and then XOR the same type of data in the read intermediate data according to the classification result, to generate the intermediate data and the intermediate sequence number of this round; after classifying the generated intermediate data, store it into the ping memory together with the generated intermediate sequence number.

[0129] 303. Perform the even rounds (2nd, 4th, 6th, 8th rounds respectively) of the intermediate rounds for nonce1, read the intermediate data and the intermediate sequence number in the ping memory; the read intermediate sequence number is sequentially stored into the ping memory, and then XOR the same type of data in the read intermediate data according to the classification result, to generate the intermediate data and the intermediate sequence number of this round; after classifying the generated intermediate data, store it into the pong memory together with the generated intermediate sequence number; after the 8th round, perform step 304.

[0130] 304. The final round is performed for nonce1, all or part of the intermediate data is read from the pong memory, and the same type of data in the read intermediate data is XOR calculated according to the classification result. If the calculation result is binary all 0, the data combination is generated according to the intermediate sequence number stored in the first to eighth intermediate rounds, for subsequent calculation.

[0131] 305-308 are one-to-one corresponding to 301-304, the difference is that the processing object is changed from nonce1 to nonce2, and the others are the same.

[0132] It can be seen that in Example One, no matter which case, the nonce1 and nonce2 use the same way to use the ping memory and the pong memory, such as the initialization round writing and the final round reading are all using the same memory (such as using the ping memory or the pong memory); such as the reading and writing in the intermediate odd round (reading the data of the last round, and sequentially writing the read intermediate sequence number) are all using the same memory. From Figure 4 It can also be seen that the memory accessed by nonce2 (the box filled with slashes in Figure 4 ) in different rounds and different operations is exactly the same as the memory accessed by nonce1 (the box without filling in Figure 4 ) in different rounds and different operations.

[0133] In Example One, by using the ping-pong structure memory, the pipeline implementation of the Equihash algorithm can be realized; because the read intermediate sequence number is sequentially written, the read intermediate data can be XOR calculated in parallel to generate the intermediate data and the intermediate sequence number of the current round and classified and stored, so the processing speed is accelerated.

[0134] Example Two

[0135] This example provides a pipeline multiplexing implementation method of Equihash (200, 9) algorithm, the difference between this example and Example One is that in this example, the initialization round of the N+1th nonce and the final round of the Nth nonce are executed in parallel, N≥1; and in this example, the memory used by each intermediate round is determined according to the parity of the sum of the sequence number of the nonce and the current intermediate round number, and the memory used by the initialization round and the final round is determined according to the parity of the sequence number of the nonce.

[0136] This example is also divided into the following two cases.

[0137] In case 1, when the nonce number is odd, the initial round write and the final round read are initialized in the ping memory, and when the nonce number is even, the initial round write and the final round read are initialized in the pong memory. For the intermediate rounds, when the sum of the nonce number and the current intermediate round number is even, such as the odd intermediate rounds (1st, 3rd, 5th, 7th intermediate rounds) of nonce 1 or the even intermediate rounds (2nd, 4th, 6th, 8th intermediate rounds) of nonce 2, the ping memory is used for reading and writing (reading the intermediate data and the intermediate number of the previous round and sequentially storing the read intermediate number in the ping memory), and the pong memory is used for writing (storing the intermediate data and the intermediate number generated in the current round); when the sum of the nonce number and the current intermediate round number is odd, such as the even intermediate rounds of nonce 1 or the odd intermediate rounds of nonce 2, the pong memory is used for reading and writing, and the ping memory is used for writing.

[0138] In case 2, the cases in case 1 are reversed, that is, when the nonce number is odd, the initial round write and the final round read are initialized in the pong memory, and when the nonce number is even, the initial round write and the final round read are initialized in the ping memory. For the intermediate rounds, when the sum of the nonce number and the current intermediate round number is odd, the ping memory is used for reading and writing, and the pong memory is used for writing; when the sum of the nonce number and the current intermediate round number is even, the pong memory is used for reading and writing, and the ping memory is used for writing.

[0139] It can be seen that in example two, the use of the ping memory and the pong memory by adjacent two nonces is opposite in any case, and the memory usage of two nonces with the same odd number or the same even number is the same. For example, assuming that the initial round write and the final round read of the Nth nonce use the ping memory, then the initial round write and the final round read of the (N-1)th and (N+1)th nonces use the ping memory; therefore, the final round read of the Nth nonce and the initial round write of the (N+1)th nonce can be performed in parallel.

[0140] For example Figure 5 The memory used in the process of performing the Equihash algorithm on the consecutive nonces 1, 2, and 3 in case 1 in the present example is shown. It can be seen that the processing process of nonce 1 (the leftmost block in the figure) Figure 5 and the processing process of nonce 3 (the rightmost block in the figure) Figure 5In the grid-filled boxes (represented by boxes), the ping memory is used for writing the initial round and reading the final round, while the nonce2 processing ( Figure 5 The boxes filled with diagonal lines (represented by squares in the middle) use the pong memory for writing the initialization round and reading the final round; the initialization round writing of nonce2 and the final round reading of nonce1 are parallel, and the final round reading of nonce2 and the initialization round writing of nonce3 are parallel. Since different memories are used in parallel, the processing time can overlap but does not affect each other, forming pipeline multiplexing.

[0141] Compare with Example 1 Figure 4 And this example Figure 5 It can be observed that, Figure 4 The processing of nonce1 plus nonce2 requires a total of 20 rounds, and each new nonce adds 10 rounds to the processing; while Figure 5 In this example, the processing of nonce1 and nonce2 only requires 19 rounds, and adding nonce3 makes it 28 rounds. That is, starting from the second nonce, each additional nonce only adds 9 rounds of processing, thus further shortening the processing time compared to Example 1.

[0142] Those of ordinary skill in the art will realize and understand that all or some of the steps in the methods disclosed above and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the components can be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer-readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by a computer. Furthermore, it is common and well understood by those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and can include any information delivery media.

Claims

1. A chip implementing an Equihash algorithm, characterized in that, Comprise: pingpong structure data storage, including ping memory and pong memory; processing module, for alternately using first memory and second memory to store intermediate data and intermediate serial number generated in this round in the process of processing each nonce, and / or using the memory used in the last round to read intermediate data and intermediate serial number generated in the last round, and sequentially writing the read intermediate serial number, including: performing initialization round, storing the generated data in the first memory; alternately performing odd and even rounds of intermediate rounds, the odd round reading the intermediate data and intermediate serial number generated in the last round from the first memory, sequentially saving the intermediate serial number in the first memory, and storing the intermediate data and intermediate serial number generated in this round in the second memory; the even round reads the intermediate data and intermediate serial number generated in the last round from the second memory, sequentially saves the intermediate serial number in the second memory, and stores the intermediate data and intermediate serial number generated in this round in the first memory; after the intermediate round is completed, the last intermediate round generated data is read from the first memory for final round processing; in each of the intermediate rounds, the read intermediate serial number and the intermediate data and intermediate serial number generated in this round are written in parallel; Wherein, the first memory is the ping memory, and the second memory is the pong memory; or, the first memory is the pong memory, and the second memory is the ping memory; the first memory and the second memory of adjacent two nonces are different; The processing module is also used for, when using the first memory to read the final round of the Nth nonce, using the second memory to write the initialization round of the N+1th nonce in parallel; N≥1.

2. The chip of claim 1, wherein, Also include: selector, for selecting one of the ping memory and the pong memory as the first memory and the other as the second memory according to the preset processing parameter.

3. The chip of claim 1, wherein, When the processing module uses the first memory to read the final round of the Nth nonce, it uses the second memory to write the initialization round of the N+1th nonce in parallel, including: When the processing module uses the ping memory to read the final round for nonce N, it simultaneously starts the initialization round for nonce N+1, and uses the pong memory to store the initialization round; or, when the processing module uses the pong memory to read the final round for nonce N, it simultaneously starts the initialization round for nonce N+1, and uses the ping memory to store the initialization round.

4. The chip of claim 2, wherein: The preset processing parameter is the nonce serial number; The selector selects one of the ping memory and the pong memory as the first memory and the other as the second memory according to the preset processing parameter, including: the selector selects the ping memory as the first memory and the pong memory as the second memory when the nonce number is odd, and selects the pong memory as the first memory and the ping memory as the second memory when the nonce number is even; or, the selector selects the pong memory as the first memory and the ping memory as the second memory when the nonce number is odd, and selects the ping memory as the first memory and the pong memory as the second memory when the nonce number is even.

5. The chip of claim 2, wherein, the selector comprises a data reading path selector and a data storage path selector; the data reading path selector is configured to select one of the ping memory and the pong memory as a reading memory according to preset processing parameters when the processing module reads intermediate data and intermediate numbers generated in a previous round; the data storage path selector is configured to select one of the ping memory and the pong memory as a first writing memory for storing intermediate data and intermediate numbers generated in a current round according to preset processing parameters when the processing module stores the intermediate data and the intermediate numbers generated in the current round; and select one of the ping memory and the pong memory as a second writing memory for sequentially storing the intermediate numbers read after the processing module reads the intermediate data and the intermediate numbers generated in the previous round according to preset processing parameters; wherein, for two adjacent nonces, the reading memory selected in a final round of a former nonce and the first writing memory selected in an initial round of a latter nonce are different memories.

6. A method of implementing an Equihash algorithm, characterized in that, application in a chip for implementing an Equihash algorithm as claimed in any one of claims 1-5; the method comprises: The nonce is processed; in the process of processing each nonce, the first memory and the second memory are alternately used to store the intermediate data and the intermediate serial number generated in the current round, and / or the intermediate data and the intermediate serial number generated in the last round are read from the memory used in the last round, and the read intermediate serial numbers are sequentially written, including: performing an initialization round, storing the generated data in the first memory; alternately performing odd and even rounds of intermediate rounds, the odd round reading the intermediate data and the intermediate serial number generated in the last round from the first memory, sequentially saving the intermediate serial number in the first memory, and storing the intermediate data and the intermediate serial number generated in the current round in the second memory; the even round reads the intermediate data and the intermediate serial number generated in the last round from the second memory, sequentially saves the intermediate serial number in the second memory, and stores the intermediate data and the intermediate serial number generated in the current round in the first memory; after the intermediate round is completed, the data generated in the last intermediate round is read from the first memory for final round processing; in each of the intermediate rounds, the read intermediate serial numbers and the intermediate data and the intermediate serial number generated in the current round are written in parallel; Wherein, the first memory is a ping memory, and the second memory is a pong memory; or, the first memory is a pong memory, and the second memory is a ping memory; the first memory and the second memory of two adjacent nonces are different; when the first memory is used for reading the final round of the Nth nonce, the second memory is used in parallel for writing the initialization round of the N+1th nonce; N≥1.

7. The method of claim 6, wherein, Further comprising: Determine the first memory and the second memory according to the preset processing parameters.

8. The method of claim 7, wherein, The preset processing parameters are nonce serial numbers. When the first memory is used for reading the final round of the Nth nonce, the second memory is used in parallel for writing the initialization round of the N+1th nonce, including: When the ping memory is used for reading the final round of nonce N, the initialization round of nonce N+1 is started at the same time, and the pong memory is used for storing the initialization round; or, when the pong memory is used for reading the final round of nonce N, the initialization round of nonce N+1 is started at the same time, and the ping memory is used for storing the initialization round.

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