Fin diode structure and method thereof

Abstract

A method and structure for forming a fin bottom diode includes providing a substrate having a plurality of fins extending therefrom. Each of the plurality of fins includes a substrate portion and an epitaxial layer portion over the substrate portion. A first doped layer is formed on sidewalls of a first region of the substrate portion of each of the plurality of fins. After forming the first doped layer, a first anneal process is performed to form a first diode region within the first region of the substrate portion. A second doped layer is formed on sidewalls of a second region of the substrate portion of each of the plurality of fins. After forming the second doped layer, a second anneal process is performed to form a second diode region within the second region of the substrate portion of each of the plurality of fins. Embodiments of the invention also relate to fin diode structures and methods thereof.

Description

[0001] This application is a divisional application of patent application number 201810584631.0 filed on June 08, 2018 entitled "Fin Diode Structure and Method Thereof". TECHNICAL FIELD

[0002] Embodiments of the present invention relate to a fin diode structure and method thereof. BACKGROUND

[0003] The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices capable of supporting a greater number of increasingly complex and sophisticated functions simultaneously. Accordingly, there has been a continued trend in the semiconductor industry to manufacture integrated circuits (ICs) that are low cost, high performance, and low power. To date, these goals have been largely achieved by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and reducing associated costs. However, such scaling has also resulted in increased complexity for semiconductor manufacturing processes. Accordingly, realization of continued progress in semiconductor ICs and devices requires similar progress in semiconductor manufacturing processes and techniques.

[0004] Recently, multi-gate devices have been introduced in an attempt to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effects (SCE). One such multi-gate device that has been introduced is the fin field effect transistor (FinFET). FinFETs are named for the fin-like structure that extends from a substrate in which the FinFET is formed and which is used to form the FinFET channel. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their three-dimensional structure allows them to be scaled aggressively while maintaining gate control and mitigated SCE. Unfortunately, in some cases, aggressively scaled FinFETs can also suffer from excessive leakage current near the bottom of the fin-like structure. To attempt to reduce such leakage current, an ion implantation process can be performed to create a P-N diode near the bottom of the fin-like structure of the FinFET device. However, the ion implantation process can directly contribute to the formation of defects, introduction of impurities, and can affect a wider substrate area than desired. As a result, FinFET device performance can be adversely affected.

[0005] Therefore, the existing techniques have not proven entirely satisfactory in all respects. SUMMARY

[0006] Embodiments of the present invention provide a method of fabricating a semiconductor device, comprising: providing a substrate having a plurality of fins extending from the substrate, wherein each of the plurality of fins includes a substrate portion and an epitaxial layer portion located above the substrate portion; forming a first doped layer on sidewalls of a first region of the substrate portion of each of the plurality of fins; after forming the first doped layer, performing a first anneal process to form a first diode region within the first region of the substrate portion of each of the plurality of fins; forming a second doped layer on sidewalls of a second region of the substrate portion of each of the plurality of fins; and after forming the second doped layer, performing a second anneal process to form a second diode region within the second region of the substrate portion of each of the plurality of fins.

[0007] Another embodiment of the present invention provides a method of fabricating a semiconductor device, comprising: providing a substrate having a first fin structure, a second fin structure, and a recess between the first fin structure and the second fin structure, wherein each of the first fin structure and the second fin structure includes a first region and a second region formed above the first region; conformally forming a first doped layer above each of the first fin structure, the second fin structure, and on a bottom surface of the recess between the first fin structure and the second fin structure; after forming the first doped layer, forming a first oxide layer within the recess and performing a first etch-back process to expose sidewalls of the second regions of the first fin structure and the second fin structure and a first portion of the first regions of the first fin structure and the second fin structure, wherein the first doped layer remains on sidewalls of a second portion of the first regions of the first fin structure and the second fin structure; and after performing the first etch-back process, performing a first anneal process to diffuse first dopant species from the first doped layer into the second portion of the first regions, wherein the second portion of the first regions defines a first diode region.

[0008] Yet another embodiment of the invention provides a semiconductor device comprising: a substrate having a first fin and a second fin extending from the substrate, wherein each of the first fin and the second fin comprises a substrate portion and an epitaxial layer portion located above the substrate portion; and a P-N diode formed within the substrate portion of each of the first fin and the second fin; wherein the P-N diode comprises a first dopant species in a first region of the substrate portion of each of the first fin and the second fin, wherein the P-N diode comprises a second dopant species in a second region of the substrate portion of each of the first fin and the second fin, and wherein the first and second regions of the substrate portion are adjacent to each other; and wherein a portion of the substrate between the first fin and the second fin remains undoped by the first and second dopant species. BRIEF DESCRIPTION OF DRAWINGS

[0009] When taken in conjunction with the following Figure One Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings in which: It should be noted that the various components are not necessarily drawn to scale. Indeed, the dimensions of the various components can be arbitrarily increased or decreased for the sake of discussion.

[0010] Figure 1 isometric view of one embodiment of a FinFET device according to one or more aspects of the invention;

[0011] Figure 2 flowchart of a method of forming a fin-bottom diode according to some embodiments;

[0012] Figures 3 to 12 provides a cross-sectional view of a device at an intermediate stage of fabrication and processing according to the method of Figure 2

[0013] Figure 13 is a flowchart of an alternative method of forming a fin-bottom diode according to some embodiments; and

[0014] Figures 14 to 25 provides a cross-sectional view of a device at an intermediate stage of fabrication and processing according to the method of Figure 13 DETAILED DESCRIPTION

[0015] ​​The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first component over or on a second component as described below can include embodiments in which the first and second components are formed in direct contact, and can also include embodiments in which additional components are formed between the first and second components such that the first and second components do not directly contact. Additionally, the present disclosure can repeat reference numerals and / or letters in different examples and / or aspects of the present disclosure. This repetition of reference numerals and / or letters is for the purpose of simplicity and clarity and does not necessarily indicate a common function between different embodiments and / or arrangements of the present disclosure.

[0016] Further, as used in the description of the embodiments, the following terms shall have the given meanings: "coupled" means either directly connected to or via one or more intervening components or interfaces; "connection" means either direct or via one or more intervening components or interfaces; and "in communication" means either direct or via one or more intervening components or interfaces.

[0017] It should also be noted that the present disclosure presents embodiments in the form of multi-gate transistors or fin-type multi-gate transistors, referred to herein as FinFET devices. Such devices can include P-type metal-oxide-semiconductor FinFET devices or N-type metal-oxide-semiconductor FinFET devices. FinFET devices can be dual-gate devices, tri-gate devices, bulk devices, silicon-on-insulator (SOI) devices, and / or other configurations. Those of ordinary skill in the art can appreciate other examples of semiconductor devices that can benefit from aspects of the present disclosure. For example, some embodiments described herein can also apply to gate-all-around (GAA) devices, Omega-gate (Ω-gate) devices, or Pi-gate (Π-gate) devices.

[0018] Reference Figure 1According to some embodiments, a FinFET device 150 is shown. By way of example, the FinFET device 150 includes one or more fin-based multi-gate field effect transistors (FETs). The FinFET device 150 includes a substrate 152, at least one fin element 154 extending from the substrate 152, an isolation region 156, and a gate structure 158 disposed on and around the fin element 154. The substrate 152 can be a semiconductor substrate such as a silicon substrate. The substrate 152 can include various layers including conductive or insulating layers formed on the substrate 152. The substrate 152 can include different doping configurations depending on design needs known in the art. The substrate 152 can also include other semiconductors such as gallium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Optionally, the substrate 152 can include compound and / or alloy semiconductors, further, in some embodiments, the substrate 152 can include an epi-layer, the substrate 152 can be strained for performance enhancement, the substrate 152 can include a silicon-on-insulator (SOI) structure, and / or the substrate 152 can have other suitable enhancements.

[0019] Similar to the substrate 152, the fin element 154 can include one or more epitaxially grown layers and can contain silicon or another elemental semiconductor such as gallium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or a combination of the foregoing. The fin 154 can be fabricated using suitable processes including photolithography and etching processes. The photolithography process can include forming a photoresist layer (photoresist) overlying the substrate (e.g., on a silicon layer), exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a mask element including the photoresist. In some embodiments, the patterned photoresist can be performed using an e-beam photolithography process to form the mask element. The mask element can then be used to protect areas of the substrate while an etching process forms a recess in the silicon layer, leaving the extended fin 154. The recess can be etched using dry etching (e.g., chemical oxide removal), wet etching, and / or other suitable processes. Many other embodiments of the method of forming the fin 154 on the substrate 152 can also be used.

[0020] Each of the plurality of fins 154 also includes a source region 155 and a drain region 157, where the source / drain regions 155, 157 are formed in, on, and / or around the fin 154. The source / drain regions 155, 157 can be epitaxially grown over the fin 154. Additionally, the channel region of the transistor is along substantially the same plane as the source / drain regions 155, 157 under the gate structure 158. The source / drain regions 155, 157 can be formed using a variety of methods including epitaxial growth, ion implantation, and / or other suitable methods. Figure 1A plane parallel to the plane defined by cross-section AA' in FIG. 1 is disposed within fin 154. In some examples, the FinFET channel region includes silicon (Si) and / or a high mobility material such as germanium, which can be epitaxially grown as any of a variety of compound semiconductors or alloy semiconductors known in the art. High mobility materials include those materials having a larger electron and / or hole mobility than silicon (Si), which has a mobility of approximately 1350 cm2 / V-s at room temperature (300 K) and a mobility of approximately 480 cm2 / V-s at room temperature (300 K) for holes. 2 2

[0021] Isolation regions 156 can be shallow trench isolation (STI) features. Alternatively, field oxide, LOCOS features, and / or other suitable isolation features can be implemented on and / or within substrate 152. Isolation regions 156 can be composed of silicon oxide, silicon nitride, silicon oxynitride, doped fluorine silicate glass (FSG), low-k dielectrics, combinations of the above, and / or other suitable materials known in the art. In one embodiment, isolation regions 156 are STI features and are formed by etching trenches in substrate 152. The trenches can then be filled with an isolation material, followed by a chemical mechanical polishing (CMP) process. However, other embodiments are possible. In some embodiments, isolation regions 156 can include a multi-layer structure, e.g., having one or more liner layers.

[0022] ​​The gate structure 158 includes a gate stack having an interface layer 160 formed over the channel region of the fin 154, a gate dielectric layer 162 formed over the interface layer 160, and a metal layer 164 formed over the gate dielectric layer 162. In some embodiments, the interface layer 160 can include a silicon dioxide layer (SiO2) or a silicon oxynitride (SiON) layer, where such an interface layer can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In some embodiments, the gate dielectric layer 162 includes a high-k dielectric layer, such as hafnium dioxide (HfO2). Optionally, the high-k dielectric layer can include other high-k dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON), combinations of the above, or other suitable materials. High-k dielectrics used and described herein include dielectric materials having a high dielectric constant, e.g., greater than that of thermal oxide silicon (3.9). In other embodiments, the gate dielectric layer 162 can include silicon dioxide or other suitable dielectrics. The gate dielectric layer 162 can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. In some embodiments, the metal layer 164 can be deposited as part of a gate-first or gate-last (e.g., replacement gate) process. In different embodiments, the metal layer 164 includes a conductive layer, such as W, Ti, TiN, TiAl, TiAlN, Ta, TaN, WN, Re, Ir, Ru, Mo, Al, Cu, Co, CoSi, Ni, NiSi, combinations of the above, and / or other suitable components. In some examples, the metal layer 164 can include a first metal material for N-type transistors and a second metal material for P-type transistors. Thus, the FinFET device 150 can include a dual work function metal gate configuration. For example, the first metal material (e.g., for N-type devices) can include a metal having a work function that substantially matches that of a conduction band of a substrate or at least substantially matches that of a conduction band of a channel region of the device 150. Similarly, the second metal material (e.g., for P-type devices) can include a metal having a work function that substantially matches that of a valence band of a substrate or at least substantially matches that of a valence band of a channel region of the device 150. Thus, the metal layer 164 can provide a gate electrode for the device 150, including N-type and P-type devices. In some embodiments, the metal layer 164 can optionally or additionally include a polysilicon layer.In various examples, the metal layer 164 can be formed using PVD, CVD, e-beam evaporation, and / or other suitable processes. In some embodiments, a sidewall spacer is formed on sidewalls of the gate structure 158. The sidewall spacer can include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a combination thereof.

[0023] In various cases, aggressively scaled FinFETs can suffer from excessive leakage current, in some cases, at the bottom of the fin structure. In some examples, electrostatic control of leakage current near the bottom of the fin structure is challenging because the bottom of the fin structure is a weak point for applied electric fields. Such electric field weakness can become even weaker for tapered fin structures (e.g., from a narrower width at the top of the fin structure to a wider width at the bottom of the fin structure). To attempt to reduce such leakage current, and in at least some existing approaches, an ion implantation process can be performed to create a P-N diode near the bottom of the fin structure of a FinFET device. In operation, and in some cases, the P-N diode can be reverse biased, thus reducing leakage current at the bottom of the fin structure. However, forming such a P-N diode using an ion implantation process can directly promote the formation of defects, introduction of impurities, and can affect a wider substrate area than desired. As a result, FinFET device performance can be adversely affected. Thus, existing approaches have not proven entirely satisfactory in all respects.

[0024] Embodiments of the present invention provide benefits over the prior art, although it should be understood that other embodiments can provide different benefits and not all embodiments need to provide benefits discussed herein and particular benefits need not be present for all embodiments. For example, embodiments discussed herein include methods of forming diodes for multi-gate devices (e.g., FinFET devices) and related structures. In at least some embodiments, diode structures are formed at the bottom of individual fin structures to effectively reduce leakage current for FinFET devices manufactured using individual fin structures. In some examples, the diode structures disclosed herein can be referred to as "fin-bottom diodes" or "fin-bottom P-N diodes." Additionally, and in contrast to some existing processes, the fin-bottom diodes disclosed herein can be formed without using an ion implantation process (e.g., a Si substrate pre-implantation process), thus avoiding issues associated with ion implantation processes. In various examples, the fin-bottom diodes disclosed herein can also be designed and / or adjusted as needed for each fin of a plurality of fins disposed on a substrate. Further details of embodiments of the present invention are provided below, and additional benefits and / or other benefits will be apparent to persons of ordinary skill in the art having the benefit of this disclosure.

[0025] Reference will now be made to Figure 2, a method 200 of forming a fin bottom diode is shown in accordance with some embodiments. In some embodiments, the method 200 can be used to manufacture a semiconductor device structure 300 as described below with reference to Figures 3 to 12 Figure 1 One or more aspects of the method 200 and the device structure 300 can also be applied to the multi-gate device structure 150 as discussed above with reference to Figures 3 to 12 Figure 2 A cross-sectional view of an exemplary semiconductor device structure 300 manufactured according to one or more steps of the method 200 is provided.

[0026] It should be appreciated that portions of the method 200 and / or the device structure 300 can be manufactured by a widely known complementary metal-oxide-semiconductor (CMOS) technology process flow, and thus some processes are only briefly described herein. Further, the device structure 300 can include various other devices and components, such as additional transistors, bipolar junction transistors, resistors, capacitors, diodes, fuses, and the like, although simplified for better understanding of the inventive concept of the present invention. Further, in some embodiments, the semiconductor device structure 300 includes a plurality of semiconductor devices (e.g., transistors) that can be interconnected.

[0027] The device structure 300 can be an intermediate device manufactured during processing of an integrated circuit or portion thereof, which can include static random access memory (SRAM) and / or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as P-channel field effect transistors (PFETs), N-channel field effect transistors (NFETs), metal-oxide-semiconductor field effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, or a combination thereof. Further, it should be noted that the process steps of the method 200 described with reference to Figures 3 to 12 The process steps of the method 200 described with reference to

[0028] The method 200 begins at block 202 by providing a substrate including a fin structure. Reference is made to Figure 3 , and in one embodiment of block 202, a device structure 300 is provided having a substrate 302 and including a fin structure 304. In some embodiments, the substrate 302 can include a Si substrate. In some cases, the substrate 302 can be substantially the same as the substrate 152 described above with reference to Figure 1 In some embodiments, the fin structure 304 can be substantially similar to the fin structure 304 described above with reference to Figure 1 ​​The fin 154 is fabricated as described above. For example, in some embodiments, an epitaxial layer 306 (e.g., a Si or Ge epitaxial layer) may be formed over a substrate 302, and a capping layer 308 may be formed over the epitaxial layer 306. Subsequently, using a combination of photolithography and etching processes, the substrate 302, the epitaxial layer 306, and the capping layer 308 may be patterned to form the fin structure 304 and the recess 305 for inserting the fin structure 304. By way of example, in various embodiments, each of the fin structures 304 thus includes a substrate portion 302A, an epitaxial layer portion 306A, and a capping layer portion 308A. In various examples, the channel region of the device 300 (e.g., the channel region of a FinFET) may be formed within the epitaxial layer portion 306A. In some embodiments, the capping layer 308, and therefore the capping layer portion 308A, has a thickness of approximately 100 to 500 angstroms. In some cases, the epitaxial layer 306, and therefore epitaxial layer portion 306A, has a thickness of approximately 300 to 1000 angstroms. In various examples, the substrate portion 302A has a thickness of approximately 1 to 2 micrometers.

[0029] Method 200 then proceeds to block 204, where a first doped layer is deposited. (See reference...) Figure 3 and Figure 4 In one embodiment of block 204, as shown in the example, a doped layer 402 is deposited over device 300. In various examples, doped layer 402 may comprise an N-type or P-type doped layer, for example, depending on the type of device 300 to be fabricated and the type of finned bottom diode to be fabricated. In some embodiments, doped layer 402 may comprise phosphosilicate glass (PSG), borosilicate glass (BSG), or borophosphosilicate glass (BPSG) that can be deposited by atomic layer deposition (ALD). In some cases, doped layer 402 may optionally be deposited by spin coating, chemical vapor deposition (CVD), or another suitable method. In some embodiments, doped layer 402 is conformally deposited over each of the fin structures 304, including conformally deposited on the sidewalls of the fin structure 304 within the recess 305. In some embodiments, doped layer 402 may have a thickness of approximately 5 to 20 angstroms.

[0030] Method 200 then proceeds to block 206, where a first oxide layer is deposited. (See reference...) Figure 4 and Figure 5In one embodiment of block 206, an oxide layer 502 is deposited over the device 300. In various examples, the oxide layer 502 can include a low temperature oxide (LTO) deposited over the device 300, including over the doped layer 402 and within the recess 305. In some cases, the oxide layer 502 includes a silicon dioxide layer (Si02) or other appropriate LTO. In some embodiments, the oxide layer 502 includes an oxide layer deposited at a temperature less than 300 degrees Celsius. In some examples, the oxide layer 502 includes an oxide layer deposited at a temperature less than 100 degrees Celsius. In various embodiments, solid phase diffusion of dopants from the doped layer 402 does not occur during deposition of the oxide layer 502. In some cases, the oxide layer 502 is deposited by an ALD process. Alternatively, in some embodiments, the oxide layer 502 can be deposited by a CVD or another appropriate process. In some examples, following deposition of the oxide layer 502, a chemical mechanical polishing (CMP) process can be performed to remove excess material and planarize a top surface of the device 300. In some embodiments, the CMP process can stop on a top surface of the fin structure 304 and thereby expose the top surface of the fin structure 304. In various cases, the CMP process can or can not remove the doped layer 402 from the top surface of the fin structure 304.

[0031] The method 200 then proceeds to block 208, performing a first etch-back process. Referring to Figure 5 and Figure 6 In one embodiment of block 208, an etch-back process is performed to remove a portion of the oxide layer 502 and expose a portion of the sidewall of the fin structure 304, resulting in a recessed oxide layer 502A. In various embodiments, the etch-back process facilitates exposure of the cap layer portion 308A, the side of the epitaxial layer portion 306A, and a portion of the substrate portion 302A, while another portion of the substrate portion 302A (302A’) remains covered by the doped layer 402 and the recessed oxide layer 502A. In some embodiments, the etch-back process of block 208 can include a dry etch process, a wet etch process, or a combination thereof. In some examples, the recess depth is controlled (e.g., by controlling the etch time so as to produce a desired height H of the exposed portion of the fin structure 304.

[0032] The method 200 then proceeds to block 210, performing a first anneal process. Referring to Figure 6 and Figure 7In one embodiment of block 210, as exemplified in the example, the first annealing process may be performed at a temperature between approximately 450 and 900°C. In some examples, other annealing temperatures may be used depending on various process conditions and / or device requirements known in the art. By way of example, the first annealing process provides solid-phase diffusion of the dopant from the doped layer 402. In some embodiments, and because the doped layer 402 covers the sidewalls of portion 302A' of the substrate portion 302A and the bottom surface of the recess 305, the first annealing process causes the dopant from the doped layer 402 to diffuse into portion 302A' of the substrate portion 302A and into the portion of the substrate 302 below the doped layer 402 at the bottom of the recess 305. In other words, as exemplified in the example Figure 7 As shown, the first annealing process produces the doped region 702. In various examples, and depending on the material used for the doped layer 402, the doped region 702 may comprise an N-type or P-type doped region. Additionally, it should be noted that, according to different embodiments, a portion 302A' of the substrate portion 302A included within the doped region 702 will form one of the N-type or P-type regions of the diode. In some embodiments, the doping concentration of the doped region 702 and the portion 302A' of the substrate portion 302A is greater than approximately 1 x 10⁻⁶. 10 atoms / cm 3 Up to approximately 1x10 20 atoms / cm 3 .

[0033] Method 200 then proceeds to block 212, where a second doped layer is deposited. (See reference) Figure 7 and Figure 8 In one embodiment of block 212, a doped layer 802 is deposited over device 300. In various examples, doped layer 802 may comprise an N-type or P-type doped layer, for example, depending on the type of device 300 to be fabricated and the type of finned bottom diode to be fabricated. In some embodiments, doped layer 802 may comprise phosphosilicate glass (PSG), borosilicate glass (BSG), or borophosphosilicate glass (BPSG) that can be deposited by atomic layer deposition (ALD). In some cases, doped layer 802 may optionally be deposited by spin coating, chemical vapor deposition (CVD), or another suitable method. In some embodiments, doped layer 802 is conformally deposited over each of the fin structures 304, including conformally deposited on the sidewalls of the fin structure 304 within the recess 305 and on the recessed oxide layer 502A. In some embodiments, doped layer 802 may have a thickness of approximately 5 to 20 angstroms.

[0034] Method 200 then proceeds to block 214, where the second oxide layer is deposited. (See reference) Figure 8 and Figure 9In one embodiment of block 214, an oxide layer 902 is deposited over the device 300. In various examples, the oxide layer 902 can include a low temperature oxide (LTO) deposited over the device 300, including over the doped layer 802 and within the recess 305. In some cases, the oxide layer 902 includes a silicon dioxide layer (Si02) or other appropriate LTO. In some embodiments, the oxide layer 902 includes an oxide layer deposited at a temperature less than 300 degrees Celsius. In some examples, the oxide layer 902 includes an oxide layer deposited at a temperature less than 100 degrees Celsius. In various embodiments, solid phase diffusion of dopants from the doped layer 802 does not occur during deposition of the oxide layer 902. In some cases, the oxide layer 902 is deposited by an ALD process. Alternatively, in some embodiments, the oxide layer 902 can be deposited by a CVD or another appropriate process. In some examples, after deposition of the oxide layer 902, a chemical mechanical polishing (CMP) process can be performed to remove excess material and planarize a top surface of the device 300.

[0035] The method 200 then proceeds to block 216, performing a second etch-back process. Referring to Figure 9 and Figure 10 In one embodiment of block 216, an etch-back process is performed to remove a portion of the oxide layer 902 and expose a portion of the sidewall of the fin structure 304, resulting in a recessed oxide layer 902A. In various embodiments, the etch-back process facilitates exposing a portion of the cap layer portion 308A, the epitaxial layer portion 306A, and the substrate portion 302A, while another portion of the substrate portion 302A (302A”) remains covered by the doped layer 802 and the recessed oxide layer 902A. Alternatively, in some embodiments, the second etch-back process can not expose a portion of the substrate portion 302A. In some embodiments, the etch-back process of block 216 can include a dry etch process, a wet etch process, or a combination thereof. In some examples, the recess depth is controlled (e.g., by controlling the etch time) so as to result in a desired height H’ of the exposed portion of the fin structure 304.

[0036] The method 200 then proceeds to block 218, performing a second anneal process. Referring to Figure 10 and Figure 11In one embodiment of block 218, as illustrated in the example, the second annealing process may be performed at a temperature of approximately 450 to 900°C. In some examples, other annealing temperatures may be used depending on various process conditions and / or device requirements known in the art. Through the example method, the second annealing process provides solid-phase diffusion of the dopant from the doped layer 802. In some embodiments, and because the doped layer 802 covers the sidewalls of portion 302A” of the substrate portion 302A, the second annealing process causes the dopant from the doped layer 802 to diffuse into portion 302A” of the substrate portion 302A. In other words, as... Figure 11 As shown, the second annealing process produces the doped region 1102. In various examples, and depending on the material used for the doped layer 802, the doped region 1102 may include an N-type or P-type doped region. Additionally, it should be noted that, according to different embodiments, a portion 302A” of the substrate portion 302A, which is part of the doped region 1102, will form one of the N-type or P-type regions of the diode. In some embodiments, the doping concentration of the doped region 1102 and the portion 302A” of the substrate portion 302A is greater than approximately 1 x 10⁻⁶. 10 atoms / cm 3 Up to approximately 1x10 20 atoms / cm 3 Therefore, the doped portion 302A' of the substrate portion 302A forms one of the N-type or P-type regions of the diode, and the doped portion 302A” of the substrate portion 302A forms the other of the N-type or P-type regions of the diode, effectively forming a PN diode 1104 at the bottom of each of the fin structures 304.

[0037] Method 200 then proceeds to block 220, where the remaining portion of the oxide layer and doped layer is removed. (See reference) Figure 11 and Figure 12 In one embodiment of block 220, an etching process is performed to remove the recessed oxide layer 902A, the doped layer 802, the recessed oxide layer 502A, and the doped layer 402. Thus, the etching process of block 220 exposes the sidewalls of fin structure 304. Additionally, in some embodiments, the etching process of block 220 exposes the sidewalls of the PN diode 1104 at the bottom of each of the fin structures 304 and the doped region 702 of the substrate 302 at the bottom of the recess 305. In various embodiments, the etching process of block 220 may include a dry etching process, a wet etching process, or a combination thereof. In some embodiments, after the etching process of block 220, shallow trench isolation (STI) components may be formed to electrically isolate each of the fin structures 304 from each other.

[0038] Semiconductor device 300 can undergo further processes to form various components and regions known in the art. For example, subsequent processes can form gate stacks (e.g., high-K / metal gate stacks), sidewall spacers, source / drain components (e.g., epitaxially grown source / drain components), etch stop layers, interlayer dielectric (ILD) layers, contact openings, contact metals, and various contact / via / line and multilayer interconnect components (e.g., metal layers and interlayer dielectrics) on substrate 302, structured to connect various components to form functional circuitry that can include one or more FinFET devices. In further examples, the multilayer interconnects can include vertical interconnects such as vias or contacts, and horizontal interconnects such as metal lines. Various interconnect components can employ various conductive materials including copper, tungsten, and / or silicides. In one example, a damascene process and / or dual damascene process is used to form copper-related multilayer interconnect structures. Moreover, additional process steps can be implemented before, during, and after method 200, and some of the process steps described above can be replaced or omitted, according to different embodiments of method 200.

[0039] Referring now to Figure 13 , an optional method 1300 is shown for forming a fin-type bottom diode, according to some embodiments. In some embodiments, method 1300 can be used to manufacture semiconductor device structure 1400 described below with reference to Figures 14 to 25 . One or more aspects of the multiple gate device structure 150 described with reference to Figure 1 or the semiconductor device structure 300 described with reference to Figures 3 to 12 may also be applied to method 1300 and device structure 1400 as discussed above. Additionally, Figures 14 to 25 a cross-sectional view of an exemplary semiconductor device structure 1400 manufactured according to one or more steps of method 1300 in Figure 13 is provided.

[0040] It is to be understood that portions of method 1300 and / or device structure 1400 can be manufactured by well-known complementary metal-oxide-semiconductor (CMOS) technology process flows, and thus some processes are only briefly described herein. Additionally, various aspects of method 1300 can be only briefly discussed as substantially the same as method 200. Further, device structure 1400 can include various other devices and components such as additional transistors, bipolar junction transistors, resistors, capacitors, diodes, fuses, etc., however simplified for better understanding of the inventive concept of the present invention. Further, in some embodiments, semiconductor device structure 1400 includes multiple semiconductor devices (e.g., transistors) that can be interconnected.

[0041] Device structure 1400 may be an intermediate device manufactured during the process of an integrated circuit or a portion thereof. The integrated circuit or portion thereof may include static random access memory (SRAM) and / or other logic circuitry, passive components such as resistors, capacitors, and inductors, and active components such as P-channel field-effect transistors (PFETs), N-channel field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and / or combinations thereof. Furthermore, it should be noted that references... Figures 14 to 25 Any process steps of method 1300 described herein are merely exemplary and are not intended to be limited to the scope expressly stated in the following claims.

[0042] Method 1300 begins at block 1302 and provides a substrate including a fin structure. (Reference) Figure 14 In one embodiment of block 1302, a device structure 1400 is provided having a substrate 1402 and including a fin structure 1404. In some embodiments, the substrate 1402 may include a Si substrate. In some cases, the substrate 1402 is substantially the same as a reference. Figure 1 The substrate 152 discussed above is the same. In some embodiments, the fin structure 1404 may be substantially similar to the reference. Figure 1 The fin 154 is fabricated as described above. For example, in some embodiments, an epitaxial layer 1406 (e.g., a Si or Ge epitaxial layer) may be formed over a substrate 1402, and a capping layer 1408 may be formed over the epitaxial layer 1406. Subsequently, using a combination of photolithography and etching processes, the substrate 1402, the epitaxial layer 1406, and the capping layer 1408 may be patterned to form fin structures 1404 and recesses 1405 between the fin structures 1404. By way of example, in various embodiments, each of the fin structures 1404 thus includes a substrate portion 1402A, an epitaxial layer portion 1406A, and a capping layer portion 1408A. In various examples, a channel region of the device 1400 (e.g., a FinFET channel region) may be formed within the epitaxial layer portion 1406A. In some embodiments, the capping layer 1408, and therefore the capping layer portion 1408A, has a thickness of approximately 100 to 500 angstroms. In some cases, the epitaxial layer 1406, and therefore epitaxial layer portion 1406A, has a thickness of approximately 300 to 1000 angstroms. In various examples, the substrate portion 1402A has a thickness of approximately 1 to 2 micrometers.

[0043] Method 1300 then proceeds to block 1304, where a first doped layer is deposited. (See reference...) Figure 14 and Figure 15In one embodiment of block 1304, the doped layer 1502 is deposited over the device 1400, in accordance with the examples in FIGS. 15A and 15B. In various examples, the doped layer 1502 can include an N-type doped layer or a P-type doped layer, for example, depending on the type of device 1400 to be fabricated and depending on the type of fin bottom diode to be fabricated. In some embodiments, the doped layer 1502 can include phosphosilicate glass (PSG), borosilicate glass (BSG), or borophosphosilicate glass (BPSG), which can be deposited by atomic layer deposition (ALD). In some cases, the doped layer 1502 is optionally deposited by spin-on, chemical vapor deposition (CVD), or by another suitable method. In some embodiments, the doped layer 1502 is deposited conformally over each of the fin structures 1404, including conformally on the sidewalls of the fin structures 1404 within the recesses 1405. In some embodiments, the doped layer 1502 can have a thickness of approximately 5 to 20 Angstroms.

[0044] The method 1300 then proceeds to block 1306, etching a portion of the first doped layer. Referring to Figure 15 and Figure 16 In one embodiment of block 1306, the etching process 1602 is performed to remove portions of the doped layer 1502 disposed on the top surfaces of each of the fin structures 1404 and on the bottom surface of the recesses 1405, while the doped layer 1502 remains on the sidewalls of the fin structures 1404, in accordance with the examples in FIGS. 15A and 15B. In some embodiments, the etching process 1602 includes a dry etch. Thus, in contrast to the method 200, the method 1300 provides for removal of the doped layer along the bottom surface of the recesses 1405. As a result, during a subsequent anneal process, the portion of the substrate 1402 at the bottom of the recesses 1405 will remain substantially free of solid phase diffusion doping from the doped layer 1502.

[0045] The method 1300 then proceeds to block 1308, performing a cleaning process. Referring to Figure 16 and Figure 17In one embodiment of block 1308, a cleaning process can be performed to clean exposed surfaces of the device 1400, such as the top surface of the cap layer 1408A, portions of the doped layer 1502 disposed on sidewalls of the fin structure 1404, and exposed portions of the substrate 1402 along the bottom surface of the recess 1405. In some embodiments, the cleaning process of block 1308 can include a wet clean in a standard clean- 1 (SC-1) solution, a standard clean-2 (SC-2) solution, an HF solution, a deionized (DI) water, a solvent, or other appropriate cleaning liquid. In some embodiments, the wet cleaning liquid can include a specific reagent that reacts with the doped layer 1502. For example, when the doped layer 1502 includes an ALD deposited layer, the specific reagent of the wet clean can react with exposed ligands of the ALD precursor or decomposed ALD precursor. In at least some embodiments, ALD precursors of PSG, BSG, or BPSG can be etched or cleaned by a wet cleaning liquid such as the SC-1 solution or the HF solution as described above.

[0046] The method 1300 then proceeds to block 1310, depositing a first oxide layer. Referring to Figure 17 and Figure 18 In one embodiment of block 1310, the oxide layer 1802 is deposited over the device 1400. In various embodiments, the oxide layer 1802 can include a low temperature oxide (LTO) deposited over the device 1400 and within the recess 1405. In some cases, the oxide layer 1802 includes a silicon dioxide layer (Si02) or other appropriate LTO. In some embodiments, the oxide layer 1802 includes an oxide layer deposited at a temperature less than 300 degrees Celsius. In some examples, the oxide layer 1802 includes an oxide layer deposited at a temperature less than 100 degrees Celsius. In various embodiments, solid phase diffusion of dopants from the doped layer 1502 does not occur during deposition of the oxide layer 1802. In some cases, the oxide layer 1802 is deposited by an ALD process. Alternatively, in some embodiments, the oxide layer 1802 can be deposited by CVD or by another appropriate process. In some examples, after deposition of the oxide layer 1802, a chemical mechanical polishing (CMP) process can be performed to remove excess material and planarize a top surface of the device 1400. In some embodiments, the CMP can stop on a top surface of the fin structure 304 including the top surface of the cap layer portion 1408A and thereby expose the top surface of the fin structure 304.

[0047] The method 1300 then proceeds to block 1312, performing a first etch-back process. Referring to Figure 18 and Figure 19In one embodiment of block 1312, a back-etch process is performed to remove a portion of the oxide layer 1802 and expose a portion of the sidewall of the fin structure 1404, resulting in a recessed oxide layer 1802A. In various embodiments, the back-etch process facilitates exposing the overlayer portion 1408A, the side of the epitaxial layer portion 1406A, and a portion of the substrate portion 1402A, while another portion (1402A') of the substrate portion 1402A remains covered by the doped layer 1502 and the recessed oxide layer 1802A. In some embodiments, the back-etch process of block 1312 can include a dry etch process, a wet etch process, or a combination thereof. In some examples, the recess depth is controlled (e.g., by controlling the etch time) so as to produce a desired height J of the exposed portion of the fin structure 1404.

[0048] The method 1300 then proceeds to block 1314, where a first anneal process is performed. Referring to Figure 19 and Figure 20 In one embodiment of block 1314, the first anneal process can be performed at a temperature of about 450 to 900 °C. By way of example, the first anneal process provides solid phase diffusion of dopants from the doped layer 1502. In some embodiments, and because the doped layer 1502 covers the sidewall of the portion 1402A' of the substrate portion 1402A, the first anneal process causes the dopants from the doped layer 1502 to diffuse into the portion 1402A' of the substrate portion 1402A, while the portion of the substrate 1402 at the bottom of the recess 1405 will remain substantially undoped by the solid phase diffusion from the doped layer 1502. In other words, the first anneal process results in a doped region 2002, as shown in 20. In various examples, and depending on the material used for the doped layer 1502, the doped region 2002 can include an N-type or a P-type doped region. Additionally, it should be noted that, according to different embodiments, the portion 1402A' of the substrate portion 1402A that is a portion of the doped region 2002 will form one of the N-type or P-type regions of a diode. In some embodiments, the doped region 2002, and thus the portion 1402A' of the substrate portion 1402A, has a doping concentration greater than about 1 x 1018atoms / cm3to about 1 x 1020atoms / cm3. 10 3 20 3 .

[0049] The method 1300 then proceeds to block 1316, where a second doped layer is deposited. Referring to Figure 20 and Figure 21 ​​​In one embodiment of block 1316, a doped layer 2102 is deposited over the device 1400, in accordance with examples. In various examples, the doped layer 2102 can include an N-type doped layer or a P-type doped layer, for example, depending on the type of device 1400 to be fabricated, and depending on the type of fin bottom diode to be fabricated. In some embodiments, the doped layer 2102 can include a phosphosilicate glass (PSG), borosilicate glass (BSG), or borophosphosilicate glass (BPSG) that can be deposited by atomic layer deposition (ALD). In some cases, the doped layer 2102 is optionally deposited by spin-on, chemical vapor deposition (CVD), or by another appropriate method. In some embodiments, the doped layer 2102 is conformally deposited over each of the fin structures 1404, including conformally on the sidewalls of the fin structures 1404 within the recesses 1405 and on the recessed oxide layer 1802A. In some embodiments, the doped layer 2102 can have a thickness of approximately 5 to 20 Angstroms.

[0050] The method 1300 then proceeds to block 1318, depositing a second oxide layer. Referring to Figure 21 and Figure 22 In one embodiment of block 1318, an oxide layer 2202 is deposited over the device 1400, in accordance with examples. In various examples, the oxide layer 2202 can include a low temperature oxide (LTO) deposited over the device 1400, including over the doped layer 2102 and within the recesses 1405. In some cases, the oxide layer 2202 includes a silicon dioxide layer (Si02) or other appropriate LTO. In some embodiments, the oxide layer 2202 includes an oxide layer deposited at a temperature less than 300 degrees Celsius. In some examples, the oxide layer 2202 includes an oxide layer deposited at a temperature less than 100 degrees Celsius. In various embodiments, solid phase diffusion of dopants from the doped layer 2102 does not occur during deposition of the oxide layer 2202. In some cases, the oxide layer 2202 is deposited by ALD. Optionally, in some embodiments, the oxide layer 2202 can be deposited by CVD or by another appropriate process. In some examples, after deposition of the oxide layer 2202, a chemical mechanical polish (CMP) can be performed to remove excess material and to planarize a top surface of the device 1400.

[0051] The method 1300 then proceeds to block 1320, performing a second etch-back process. Referring to Figure 22 and Figure 23In one embodiment of block 1320, a back-etching process is performed to remove a portion of the oxide layer 2202 and expose a portion of the sidewalls of the fin structures 1404, resulting in a recessed oxide layer 2202A. In various embodiments, the back-etching process facilitates exposing a portion of the cap layer portion 1408A, the epitaxial layer portion 1406A, and the substrate portion 1402A, while another portion (1402A') of the substrate portion 1402A remains covered by the doped layer 2102 and the recessed oxide layer 2202A. Optionally, in some embodiments, the second back-etching process can not expose a portion of the substrate portion 1402A. In some embodiments, the back-etching process of block 1320 can include a dry etching process, a wet etching process, or a combination thereof. In some examples, the depth of the recess is controlled (e.g., by controlling the etching time) so as to result in a desired height J' of the exposed portion of the fin structures 1404.

[0052] The method 1300 proceeds to block 1322, where a second annealing process is performed. Referring to the example of FIGS. 13A and 13B, in one embodiment of block 1322, the second annealing process can be performed at a temperature between approximately 450 and 900 °C. By way of example, the second annealing process provides a solid phase diffusion of dopants from the doped layer 2102. In some embodiments, and because the doped layer 2102 covers the sidewalls of the portion 1402A" of the substrate portion 1402A, the second annealing process causes the dopants from the doped layer 2102 to diffuse into the portion 1402A" of the substrate 1402A. In other words, as shown in FIG. 13B, the second annealing process results in a doped region 2402. Figure 23 Figure 24 In one embodiment of block 1322, the second annealing process can be performed at a temperature between approximately 450 and 900 °C. By way of example, the second annealing process provides a solid phase diffusion of dopants from the doped layer 2102. In some embodiments, and because the doped layer 2102 covers the sidewalls of the portion 1402A" of the substrate portion 1402A, the second annealing process causes the dopants from the doped layer 2102 to diffuse into the portion 1402A" of the substrate 1402A. In other words, as shown in FIG. 13B, the second annealing process results in a doped region 2402. Figure 24 In various examples, and depending on the material used for the doped layer 2102, the doped region 2402 can include an N-type or a P-type doped region. Additionally, it should be noted that, according to different embodiments, the portion 1402A" of the substrate portion 1402A that is part of the doped region 2402 will form one of the N-type or P-type regions of the diode. In some embodiments, the doped region 2402, and thus the portion 1402A" of the substrate portion 1402A, has a doping concentration greater than approximately 1 x 1018atoms / cm3to approximately 1 x 1020atoms / cm3. 10 3 20 3 Thus, the doped portion 1402A' of the substrate portion 1402A forms one of the N-type or P-type regions of the diode, and the doped portion 1402A" of the substrate portion 1402A forms the other of the N-type or P-type regions of the diode, effectively forming a P-N diode 2404 at the bottom of each of the fin structures 1404.

[0053] ​​​​Method 1300 then proceeds to block 1324, removing the remaining portion of the oxide and doped layers. (See reference) Figure 24 and Figure 25 In one embodiment of block 1324, an etching process is performed to remove the recessed oxide layer 2202A, doped layer 2102, recessed oxide layer 1802A, and doped layer 1502. Thus, the etching process of block 1324 exposes the sidewalls of fin structure 1404. Additionally, in some embodiments, the etching process of block 1324 exposes the sidewalls of the PN diode 2404 at the bottom of each of the fin structures 1404 and a portion of the substrate 1402 at the bottom of the recess 1405. In various embodiments, the etching process of block 1324 may include a dry etching process, a wet etching process, or a combination thereof. In some embodiments, after the etching process of block 1324, shallow trench isolation (STI) components may be formed to electrically isolate each of the fin structures 1404 from each other.

[0054] Semiconductor device 1400 may undergo further processes to form various components and regions known in the art. For example, subsequent processes may form gate stacks (e.g., high-k / metal gate stacks), sidewall spacers, source / drain components (e.g., epitaxially grown source / drain components), etch stop layers, interlayer dielectric (ILD) layers, contact openings, contact metals, and various contacts / vias / lines, as well as multilayer interconnect components (e.g., metal layers and interlayer dielectrics) on substrate 1402, configured to connect the various components to form a functional circuit that may include one or more FinFET devices. In a further example, the multilayer interconnects may include vertical interconnects such as vias or contacts and horizontal interconnects such as metal lines. The various interconnect components may employ different conductive materials including copper, tungsten, and / or silicides. In one example, damascene and / or dual damascene processes are used to form copper-associated multilayer interconnect structures. Furthermore, depending on different embodiments of method 1300, additional process steps may be performed before, during, or after method 1300, and some process steps as described above may be replaced or omitted.

[0055] The various embodiments described herein provide several benefits over the prior art. It should be appreciated that not all benefits need be discussed herein, and no particular benefit is required for all embodiments, and other embodiments can provide different benefits. As one example, embodiments discussed herein include methods and structures for forming a fin-bottom diode and related structures for a multi-gate device (e.g., a FinFET device). In at least some embodiments, a diode structure is formed at a bottom of a separate fin structure to effectively reduce leakage current for a FinFET device fabricated using the separate fin structure. Additionally, and in contrast to some prior processes, the fin-bottom diode disclosed herein can be formed without using an ion implantation process (e.g., a Si substrate pre-implantation process), thereby avoiding issues associated with ion implantation processes. In various embodiments, the fin-bottom diode disclosed herein can also be designed and / or adjusted according to needs of each fin of a plurality of fins disposed on a substrate. Thus, the various embodiments disclosed herein provide a more robust FinFET device designed to reduce at least some issues associated with aggressive scaling of IC devices.

[0056] Accordingly, one embodiment of the present invention describes a method for fabricating a semiconductor device including providing a substrate having a plurality of fins extending from the substrate, wherein each of the plurality of fins includes a substrate portion and an epitaxial layer portion on the substrate portion. In some embodiments, a first doped layer is formed on sidewalls of a first region of the substrate portion of each of the plurality of fins. In some cases, and after forming the first doped layer, a first anneal process is performed to form a first diode region within the first region of the substrate portion of each of the plurality of fins. In some embodiments, a second doped layer is formed on sidewalls of a second region of the substrate portion of each of the plurality of fins. In some examples, and after forming the second doped layer, a second anneal process is performed to form a second diode region within the second region of the substrate portion of each of the plurality of fins.

[0057] In the above method, wherein each of the plurality of fins includes the substrate portion, the epitaxial layer portion above the substrate portion, and a cap layer portion above the epitaxial layer portion.

[0058] In the above method, further comprising forming the first doped layer on sidewalls of the first region of the substrate portion of each of the plurality of fins and on a bottom surface of a trench between the plurality of fins.

[0059] In the above method, further comprising forming an oxide layer within the trench between the plurality of fins prior to forming the second doped layer, wherein the oxide layer is disposed above the first doped layer.

[0060] In the above method, further comprising: forming an oxide layer within the recesses between the plurality of fins prior to forming the second doped layer, wherein the oxide layer is disposed above the first doped layer, further comprising: etching the oxide layer within the recesses to expose a side of the epitaxial layer portion and a third region of the substrate portion of each of the plurality of fins after forming the oxide layer; and performing the second anneal process to form the second diode region after etching the oxide layer.

[0061] In the above method, further comprising: forming an oxide layer within the recesses between the plurality of fins prior to performing the second anneal process, wherein the oxide layer is disposed above the second doped layer.

[0062] In the above method, further comprising: forming an oxide layer within the recesses between the plurality of fins prior to performing the second anneal process, wherein the oxide layer is disposed above the second doped layer, further comprising: etching the oxide layer within the recesses to expose a side of the epitaxial layer portion and a third region of the substrate portion of each of the plurality of fins after forming the oxide layer; and performing the second anneal process to form the second diode region after etching the oxide layer.

[0063] In the above method, wherein the first doped layer and the second doped layer comprise phosphosilicate glass (PSG), borosilicate glass (BSG), or borophosphosilicate glass (BPSG).

[0064] In the above method, wherein the first doped layer and the second doped layer comprise phosphosilicate glass (PSG), borosilicate glass (BSG), or borophosphosilicate glass (BPSG), wherein the first doped layer and the second doped layer are deposited by atomic layer deposition (ALD).

[0065] In the above method, wherein the first diode region is formed by diffusing a first dopant species from the first doped layer into the first region of the substrate portion of each of the plurality of fins, and wherein the second diode region is formed by diffusing a second dopant species from the second doped layer into the second region of the substrate portion of each of the plurality of fins.

[0066] In the above method, wherein the first diode region is formed by diffusing a first dopant species from the first doped layer into the first region of the substrate portion of each of the plurality of fins, and wherein the second diode region is formed by diffusing a second dopant species from the second doped layer into the second region of the substrate portion of each of the plurality of fins, wherein the epitaxial layer portion of each of the plurality of fins comprises a FinFET channel region.

[0067] In another example, discussed is a method in which a substrate having a first fin structure, a second fin structure, and a recess between the first and second fin structures is provided. In some cases, each of the first and second fin structures includes a first region and a second region formed over the first region. In various examples, a first doped layer is conformally formed over each of the first fin structure, the second fin structure, and a bottom surface of the recess between the first and second fin structures. In some examples, and after forming the first doped layer, a first oxide layer is formed within the recess, and a first etch-back process is performed to expose sidewalls of the second regions of the first and second fin structures and a first portion of the first regions of the first and second fin structures, wherein the first doped layer remains on sidewalls of a second portion of the first regions of the first and second fin structures. In some embodiments, and after performing the first etch-back process, a first anneal process is performed to diffuse a first dopant species from the first doped layer into the second portion of the first regions, wherein the second portion of the first regions defines a first diode region.

[0068] In the above method, further comprising: prior to forming the first oxide layer, removing the first doped layer from a top surface of each of the first fin structure and the second fin structure, and from a bottom surface of the recess; and after removing the first doped layer from the top surface and the bottom surface, forming the first oxide layer within the recess.

[0069] In the above method, further comprising: after performing the first anneal process, conformally forming a second doped layer over each of the first fin structure and the second fin structure; and after forming the second doped layer, forming a second oxide layer within the recess, and performing a second etch-back process to expose sidewalls of the second regions of the first and second fin structures and a third portion of the first regions of the first and second fin structures, wherein the second doped layer remains on sidewalls of the first portion of the first regions of the first and second fin structures, and after performing the second etch-back process, performing a second anneal process to diffuse a second dopant species from the second doped layer into the first portion of the first regions, wherein the first portion of the first regions defines a second diode region.

[0070] In the above method, further comprising: prior to forming the first oxide layer, removing the first doped layer from a top surface of each of the first fin structure and the second fin structure and from a bottom surface of the recess; and after removing the first doped layer from the top surface and the bottom surface, forming the first oxide layer within the recess, further comprising: after removing the first doped layer from the top surface and the bottom surface, and prior to forming the first oxide layer within the recess, cleaning exposed surfaces of the semiconductor device.

[0071] In the above method, further comprising: after performing the first anneal process, conformally forming a second doped layer over each of the first fin structure and the second fin structure; after forming the second doped layer, forming a second oxide layer within the recess, and performing a second etch-back process to expose a second region of the first fin structure and the second fin structure and a sidewall of a third portion of the first region of the first fin structure and the second fin structure, wherein the second doped layer remains on a sidewall of a first portion of the first region of the first fin structure and the second fin structure, and after performing the second etch-back process, performing a second anneal process to diffuse second dopant species from the second doped layer into the first portion of the first region, wherein the first portion of the first region defines a second diode region, further comprising: after performing the second anneal process, removing the first doped layer, the second doped layer, the first oxide layer, and remaining portions of the second oxide layer.

[0072] In the above method, further comprising: after performing the first anneal process, conformally forming a second doped layer over each of the first fin structure and the second fin structure; after forming the second doped layer, forming a second oxide layer within the recess, and performing a second etch-back process to expose a second region of the first fin structure and the second fin structure and a sidewall of a third portion of the first region of the first fin structure and the second fin structure, wherein the second doped layer remains on a sidewall of a first portion of the first region of the first fin structure and the second fin structure, and after performing the second etch-back process, performing a second anneal process to diffuse second dopant species from the second doped layer into the first portion of the first region, wherein the first portion of the first region defines a second diode region, wherein the first doped layer and the second doped layer comprise atomic layer deposition (ALD) deposited phosphosilicate glass (PSG), borosilicate glass (BSG), or borophosphosilicate glass (BPSG).

[0073] In the above method, further comprising: after performing the first anneal process, conformally forming a second doped layer over each of the first fin structure and the second fin structure; and after forming the second doped layer, forming a second oxide layer within the recess, and performing a second etch-back process to expose a second region of the first fin structure and the second fin structure and a sidewall of a third portion of the first region of the first fin structure and the second fin structure, wherein the second doped layer remains on a sidewall of a first portion of the first region of the first fin structure and the second fin structure, and after performing the second etch-back process, performing a second anneal process to diffuse second dopant species from the second doped layer into the first portion of the first region, wherein the first portion of the first region defines a second diode region, wherein the first anneal process and the second anneal process are performed at a temperature of 450 to 900 °C.

[0074] In yet another embodiment, discussed is a semiconductor device including a substrate having a first fin and a second fin extending from the substrate, wherein each of the first and second fins includes a substrate portion and an epitaxial layer portion located above the substrate portion. In some cases, the semiconductor device further includes a recess between the first and second fins, and a P-N diode formed within the substrate portion of each of the first and second fins. In some embodiments, the P-N diode includes a first dopant species in a first region of the substrate portion of each of the first and second fins, the P-N diode includes a second dopant species in a second region of the substrate portion of each of the first and second fins, and the first and second regions of the substrate portion are adjacent to each other. In some examples, a portion of the substrate disposed below a floor of the recess remains substantially undoped by the first and second dopant species.

[0075] In the above semiconductor device, further comprising a cap layer portion formed over the epitaxial layer portion of each of the first fin and the second fin.

[0076] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the various aspects of the present application. Those skilled in the art should appreciate that they can readily use the present application as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same benefits therefrom as introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present application and that various changes can be made to what is described in the foregoing without departing from the scope of the present application.

Claims

1. A method of fabricating a semiconductor device, comprising: providing a substrate having a plurality of fins extending from the substrate, wherein each of the plurality of fins includes a substrate portion and an epitaxial layer portion located above the substrate portion; forming a first doped layer on sidewalls of a first region of the substrate portion of each of the plurality of fins; after forming the first doped layer, performing a first anneal process to form a first diode region within the first region of the substrate portion of each of the plurality of fins; forming a second doped layer on sidewalls of a second region of the substrate portion of each of the plurality of fins; and after forming the second doped layer, performing a second anneal process to form a second diode region within the second region of the substrate portion of each of the plurality of fins, the first diode region and the second diode region forming a P-N diode, wherein, prior to forming the second doped layer, a first oxide layer is formed within a recess between the plurality of fins, wherein the first oxide layer is disposed above the first doped layer, after forming the first oxide layer, the first oxide layer within the recess is etched and recessed to expose the epitaxial layer portion and a side of the second region of the substrate portion of each of the plurality of fins, wherein, after etching and recessing the first oxide layer and prior to performing the first anneal process, the recessed first oxide layer and the first doped layer remain on sidewalls within the first region of the substrate portion, wherein, after performing the first anneal process and prior to performing the second anneal process, the second doped layer is conformally deposited on sidewalls of the plurality of fins within the recess and on the recessed first oxide layer, and a second oxide layer is formed within a recess between the plurality of fins, wherein the second oxide layer is disposed above the second doped layer.

2. The method of claim 1, wherein, each of the plurality of fins includes the substrate portion, the epitaxial layer portion located above the substrate portion, and a cap layer portion located above the epitaxial layer portion.

3. The method of claim 1, further comprising: forming the first doped layer on sidewalls of the first region of the substrate portion of each of the plurality of fins and on a floor of a recess between the plurality of fins.

4. The method of claim 1, wherein, the first oxide layer includes a low temperature oxide.

5. The method of claim 1, wherein, after etching the first oxide layer, the second doped layer is formed on the exposed side of the second region of the substrate portion of each of the plurality of fins.

6. The method of claim 1, wherein, the first diode region includes a first dopant species, the second diode region includes a second dopant species different from a conductivity type of the first dopant species, and wherein the first diode region and the second diode region are vertically adjacent to each other.

7. The method of claim 1, further comprising: after forming the second oxide layer, etching the second oxide layer within the recess to expose a side of a third region of the substrate portion and the epitaxial layer portion of each of the plurality of fins, the second region being between the epitaxial layer portion and the third region; and after etching the second oxide layer, performing the second anneal process to form the second diode region.

8. The method of claim 1, wherein, The first and second doped layers comprise phosphosilicate glass, borosilicate glass, or borophosphosilicate glass.

9. The method of claim 8, wherein, The first and second doped layers are deposited by atomic layer deposition.

10. The method of claim 1, wherein, The first diode region is formed by diffusing a first dopant species from the first doped layer into the first region of the substrate portion of each of the plurality of fins, and wherein the second diode region is formed by diffusing a second dopant species from the second doped layer into the second region of the substrate portion of each of the plurality of fins.

11. The method of claim 10, wherein, The epitaxial layer portion of each of the plurality of fins comprises a FinFET channel region.

12. A method of fabricating a semiconductor device, comprising: providing a substrate having a first fin structure, a second fin structure, and a recess between the first and second fin structures, wherein each of the first and second fin structures comprises a first region and a second region formed above the first region; conformally forming a first doped layer above each of the first and second fin structures and on a bottom surface of the recess between the first and second fin structures; after forming the first doped layer, forming a first oxide layer within the recess and performing a first etch-back process to expose a sidewall of the second region of the first and second fin structures and a first portion of the first region of the first and second fin structures and cause recessed first oxide layer, wherein after performing the first etch-back process and prior to performing a first anneal process, the first doped layer and recessed first oxide layer remain on a sidewall of a second portion of the first region of the first and second fin structures, after the first anneal process, a second doped layer is conformally deposited on the sidewall of the first and second fin structures and on recessed first oxide layer within the recess; and after performing the first etch-back process, performing the first anneal process to diffuse a first dopant species from the first doped layer into the second portion of the first region, wherein the second portion of the first region defines a first diode region of a P-N diode.

13. The method of claim 12, further comprising: prior to forming the first oxide layer, removing the first doped layer from a top surface of each of the first and second fin structures and from a bottom surface of the recess; and after removing the first doped layer from the top and bottom surfaces, forming the first oxide layer within the recess.

14. The method of claim 12, further comprising: forming a second oxide layer within the recess after forming the second doped layer, and performing a second etch-back process to expose sidewalls of a second region of the first and second fin structures and a third portion of the first region of the first and second fin structures, the third portion being between the first portion and an epitaxial layer portion located above the first portion, wherein the second doped layer remains on sidewalls of the first portion of the first region of the first and second fin structures, and performing a second anneal process to diffuse second dopant species from the second doped layer into the first portion of the first region after performing the second etch-back process, wherein the first portion of the first region defines a second diode region of the P-N diode.

15. The method of claim 13, further comprising: cleaning exposed surfaces of the semiconductor device after removing the first doped layer from the top and bottom surfaces and before forming the first oxide layer within the recess.

16. The method of claim 14, further comprising: removing remaining portions of the first doped layer, the second doped layer, the first oxide layer, and the second oxide layer after performing the second anneal process.

17. The method of claim 14, wherein, the first and second doped layers comprise atomic layer deposited phosphosilicate glass, borosilicate glass, or borophosphosilicate glass.

18. The method of claim 14, wherein, the first and second anneal processes are performed at a temperature of 450 to 900 °C.

19. A method of fabricating a semiconductor device, comprising: etching a multilayer substrate to form a multilayer fin structure and a recess adjacent to the multilayer fin structure; forming a first P-N diode region within a first layer of the multilayer fin structure, wherein the first P-N diode region comprises a first dopant species; and forming a second P-N diode region within the first layer of the multilayer fin structure, the first P-N diode region and the second P-N diode region forming a P-N diode, wherein the second P-N diode region is adjacent to the first P-N diode region, and wherein the second P-N diode region comprises a second dopant species different from the first dopant species; wherein, after forming the first P-N diode region and the second P-N diode region, a bottom surface of the recess adjacent to the multilayer fin structure remains substantially undoped by the first and second dopant species; wherein forming the first P-N diode region within the first layer of the multilayer fin structure comprises forming a first dopant layer and an oxide layer within a recess between the multilayer fins, wherein the oxide layer is disposed above the first dopant layer, After forming the first dopant layer and the oxide layer, a back-etching process is performed to expose a first portion of the sidewall of the multi-layer fin structure and to cause the recessed oxide layer, wherein, after performing the back-etching process and before performing a first annealing process, the first dopant layer and the recessed oxide layer remain on the sidewall of a second portion of the sidewall of the multi-layer fin structure that is not exposed by the back-etching process, and after the first annealing process, a second dopant layer is deposited conformally on the sidewall of the multi-layer fin structure within the recess and on the recessed oxide layer.

20. The method of claim 19, wherein, Forming the first P-N diode region within the first layer of the multi-layer fin structure includes diffusing the first dopant species from the first dopant layer into the first P-N diode region, and wherein forming the second P-N diode region within the first layer of the multi-layer fin structure includes diffusing the second dopant species from the second dopant layer into the second P-N diode region.

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