Semiconductor structure and method for forming the same

Abstract

The method includes forming a plurality of dielectric layers above a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner above the first liner. The second liner extends into the opening. The method also includes filling a conductive material into the opening to form a through hole, and forming a conductive component on an opposite side of the semiconductor substrate. The conductive components are electrically interconnected through the through hole. Embodiments of the present application also relate to a semiconductor structure and a method for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] Through Silicon Vias (TSVs) are used as electrical paths in a device die, so that conductive features on opposite sides of the device die can be interconnected. The formation process of TSVs includes: etching a semiconductor substrate to form an opening; filling the opening with a conductive material to form the TSV; performing a backside grinding process to remove a portion of the semiconductor substrate from the backside; and forming an electrical connector on the backside of the semiconductor substrate to connect to the TSV. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming multiple dielectric layers above a semiconductor substrate; etching the multiple dielectric layers and the semiconductor substrate to form an opening; depositing a first liner extending into the opening; depositing a second liner above the first liner, wherein the second liner extends into the opening; filling the conductive material into the opening to form a through hole; and forming conductive components on opposite sides of the semiconductor substrate, wherein the conductive components are electrically interconnected through the through hole.

[0004] Other embodiments of the present application provide a semiconductor structure, including: a semiconductor substrate; a plurality of dielectric layers located above the semiconductor substrate; a first conductive component located above the plurality of dielectric layers; a second conductive component located below the semiconductor substrate; a through hole penetrating the semiconductor substrate and the plurality of dielectric layers, wherein the through hole electrically interconnects the first conductive component and the second conductive component; a first liner surrounding the through hole; and a second liner surrounding the first liner, wherein the second liner has a higher density than the first liner.

[0005] Some other embodiments of the present application provide a semiconductor structure, comprising: a tube core, wherein the tube core comprises: a semiconductor substrate; a plurality of low-k dielectric layers located above the semiconductor substrate; a through hole penetrating the semiconductor substrate and the plurality of low-k dielectric layers; a first pad surrounding the through hole, wherein the first pad extends to the top and bottom ends of the through hole; a second pad surrounding the first pad, wherein the second pad is shorter than the through hole; a first electrical connector located above the semiconductor substrate and at the top surface of the tube core; and a second electrical connector located below the semiconductor substrate and at the bottom surface of the tube core, wherein the first electrical connector and the second electrical connector are electrically interconnected through the through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figures 4 to 13 , Fig.14A , Fig. 14B , Fig. 14C , Fig.14D , Fig.14E , Fig.14F and Figure 14G A cross-sectional view is shown of an intermediate stage in the formation of a die including vias in accordance with some embodiments.

[0008] Fig.15 A plan view of a through hole is shown in accordance with some embodiments.

[0009] Fig.16 A dielectric liner having a tapered bottom is shown in accordance with some embodiments.

[0010] Figures 17 to 19 A cross-sectional view of an intermediate stage in the packaging of a die including a through-via is shown in accordance with some embodiments.

[0011] Fig. 20 A process flow for forming a die including multi-pad vias is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] According to some embodiments, a die including a multilayer liner for a through hole and a method for forming the same are provided. The die includes a plurality of pads formed of different materials and may have different heights. For example, the outer liner may be formed of a dense material to serve as a diffusion barrier and may be thinner to reduce parasitic capacitance. The inner liner may be thicker than the outer liner and may have a lower k value than the outer liner. With a multilayer design, the liner of the through hole may have an improved ability to prevent diffusion without the parasitic capacitance between the through hole and other components such as a semiconductor substrate being adversely increased. An intermediate stage in the formation of the die is shown according to some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements.

[0015] Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figures 4 to 13 , Fig.14A , Fig. 14B , Fig. 14C , Fig.14D , Fig.14E , Fig.14F and Figure 14G 1 shows a cross-sectional view of an intermediate stage in the formation of a tube core including a through hole according to some embodiments of the present invention. The corresponding process is also schematically reflected in the following Fig. 20 In the process flow 200 shown.

[0016] Figure 1 A cross-sectional view of wafer 20 is shown. According to some embodiments of the present invention, wafer 20 is or includes a device wafer (including active devices and possibly passive devices), which is shown as an integrated circuit device 26. Wafer 20 may include a plurality of chips / dies 22 therein, of which one of chips 22 is shown. According to alternative embodiments of the present invention, wafer 20 is an interposer wafer, which has no active devices and may or may not include passive devices.

[0017] According to some embodiments of the present invention, wafer 20 includes a semiconductor substrate 24 and components formed at a top surface of semiconductor substrate 24. Semiconductor substrate 24 may include or be formed of crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. A shallow trench isolation (STI) region (not shown) may be formed in semiconductor substrate 24 to isolate active regions in semiconductor substrate 24.

[0018] According to some embodiments of the present invention, wafer 20 includes integrated circuit devices 26 formed on a top surface of semiconductor substrate 24. According to some embodiments, integrated circuit devices 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit devices 26 are not shown here. According to alternative embodiments, wafer 20 is used to form an interposer (which has no active devices), and substrate 24 may be a semiconductor substrate or a dielectric substrate.

[0019] An interlayer dielectric (ILD) 28 filling the spaces between the gate stacks of transistors (not shown) in the integrated circuit device 26 is formed over the semiconductor substrate 24. According to some embodiments, the ILD 28 is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD 28 may be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments of the present invention, the ILD 28 may also be formed using a deposition method such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0020] Contact plugs 30 are formed in ILD 28 for electrically connecting integrated circuit device 26 to the metal lines and vias above. According to some embodiments of the present invention, contact plugs 30 include or are formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. Forming contact plugs 30 may include: forming contact openings in ILD 28; filling one or more conductive materials into the contact openings; and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surface of contact plug 30 flush with the top surface of ILD 28.

[0021] There is an interconnect structure 32 above the ILD 28 and the contact plug 30. The interconnect structure 32 includes a metal line 34 and a via 36 formed in a dielectric layer 38 (also referred to as an intermetallic dielectric (IMD)) and an etch stop layer 37. Hereinafter, metal lines at the same level are collectively referred to as metal layers. According to some embodiments of the present invention, the interconnect structure 32 includes a plurality of metal layers, which include metal lines 34 interconnected by vias 36. The metal lines 34 and the vias 36 may be formed of copper or a copper alloy, and may also be formed of other metals. According to some embodiments of the present invention, the dielectric layer 38 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be lower than about 3.0. The dielectric layer 38 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to some embodiments of the present invention, forming dielectric layer 38 includes depositing a dielectric material containing a porogen in dielectric layer 38, and then performing a curing process to drive off the porogen, and thus the remaining dielectric layer 38 is porous. Etch stop layer 37 may include or be formed of silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, etc.

[0022] Forming metal lines 34 and vias 36 in dielectric layer 38 may include a single damascene process and / or a dual damascene process. In a single damascene process for forming metal lines or vias, a trench or via opening is first formed in one of dielectric layers 38, and then the trench or via opening is filled with a conductive material. A planarization process such as a CMP process is then performed to remove the excess portion of the conductive material above the top surface of the dielectric layer, thereby leaving a metal line or via in the corresponding trench or via opening. In a dual damascene process, trenches and via openings are formed in the dielectric layer, wherein the via opening is located below the trench and connected to the trench. Conductive material is then filled into the trench and via opening to form metal lines and vias, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metal material above the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0023] Metal lines 34 include top conductive (metal) features such as metal lines, metal pads, or vias (denoted as 34A) in a top dielectric layer (denoted as dielectric layer 38A), which is the top layer of dielectric layer 38. According to some embodiments, dielectric layer 38A is formed of a low-k dielectric material similar to the material of lower dielectric layer 38. Metal lines 34 in top dielectric layer 38A may also be formed of copper or a copper alloy, and may have a dual damascene structure or a single damascene structure.

[0024] According to some embodiments, an etch stop layer 40 is deposited on the top dielectric layer 38A and the top metal layer. The etch stop layer 40 may include or be formed of silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, or the like.

[0025] A passivation layer 42 (sometimes referred to as passivation-1 or pass-1) is formed over the etch stop layer 40. According to some embodiments, the passivation layer 42 is formed of a non-low-k dielectric material having a dielectric constant equal to or greater than about the dielectric constant of silicon oxide. The passivation layer 42 may include or be formed of an inorganic dielectric material, which may include a material selected from, but not limited to, undoped silicate glass (USG), silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbide (SiC), etc., combinations thereof, and / or multilayers thereof. According to some embodiments, the top surfaces of the top dielectric layer 38A and the metal line 34 are flush with each other. Therefore, the passivation layer 42 may be a planar layer.

[0026] According to some embodiments, a dielectric layer 44 is deposited over the passivation layer 42. The corresponding process is shown as Fig. 20 Process 202 of process flow 200 is shown. Dielectric layer 44 includes or is formed of a material different from that of passivation layer 42, and may include or be formed of SiC, SiN, SiON, SiOC, or the like.

[0027] refer to Figure 2 , forming and then patterning an etch mask 46. According to some embodiments, the etch mask 46 includes a photoresist and may or may not include a hard mask formed of TiN, BN, etc. An anisotropic etching process is then performed to form an opening penetrating the dielectric layers including the dielectric layer 44, the passivation layer 42, the etch stop layer 40, the IMD 38, the etch stop layer 37, the ILD 28, etc. The semiconductor substrate 24 is further etched so that the opening 48 extends to the middle level of the substrate 24, wherein the middle level is located between the top surface 24A and the bottom surface of the semiconductor substrate 24. Thus, the opening 48 is formed. The corresponding process is shown as Fig. 20 The process 204 in the process flow 200 is shown. The opening 48 is used to form a through semiconductor via (TSV, sometimes also referred to as a through silicon via), and is therefore referred to as TSV opening 48 hereinafter. The anisotropic etching process includes a plurality of etching processes, which employ different etching gases to etch dielectric layers formed of different materials and to etch the semiconductor substrate 24.

[0028] According to some embodiments, TSV opening 48 has a top width W1 and a bottom width W2 that are smaller than top width W1. TSV opening 48 may have inclined and straight edges 48E, wherein an inclination angle α of straight edge 48E is less than 90 degrees, for example, in a range between about 80 degrees and about 90 degrees. According to some embodiments, an aspect ratio H1 / W1 of opening 48 may be in a range between about 2 and about 10. After forming TSV opening 48, etching mask 46 is removed, for example, by an ashing process.

[0029] Reference Figure 3A , depositing the first liner 50. The corresponding process is shown as Fig. 20 Process 206 in process flow 200 is shown. Liner 50 includes a horizontal portion located outside TSV opening 48 and a vertical portion extending into TSV opening 48. According to some embodiments, liner 50 includes or is formed of a dielectric material, such as silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, etc., or a combination thereof. According to alternative embodiments, liner 50 includes or is formed of a conductive material, such as Ti, TiN, Ta, TaN, etc., or a combination thereof. The thickness T1 of liner 50 is small so that liner 50, which may have a high k value, does not cause an undesirable increase in the parasitic capacitance of the parasitic capacitor. For example, the thickness T1 of liner 50 may be about 1000 Å. Peace In the range between , wherein the thickness T1 can be measured at the middle height of the vertical portion. The deposition method may include plasma enhanced chemical vapor deposition (PECVD), final atomic layer deposition (ALD), physical vapor deposition (PVD), etc. For example, when SiN is to be formed, the precursor used to form the liner 50 may include a silicon-containing precursor such as SiCl4, SiH2Cl2, Si2Cl6, Si3Cl8, etc., and a nitrogen-containing precursor such as NH3. According to some embodiments, the liner 50 has a good ability to prevent diffusion and can prevent undesirable substances from penetrating through it.

[0030] According to some embodiments, the process conditions for the deposition of the liner 50 are adjusted so that the liner 50 is a non-conformal layer and the liner 50 covers the sidewalls of the top of the TSV opening 48, while the sidewalls of the bottom of the TSV opening 48 are not covered. According to some embodiments, PECVD is used, and some process conditions are adjusted to achieve the desired profile of the liner 50. The adjusted process conditions may include the pressure of the process gas, the Si / N gas flow ratio, etc., wherein the Si / N gas flow ratio is the ratio of the flow of the silicon-containing gas to the flow of the nitrogen-containing gas. For example, increasing the pressure of the process gas may cause the liner 50 to extend less toward the bottom of the TSV opening 48 (thereby reducing the height H2), while reducing the pressure may cause the liner 50 to extend more toward the bottom of the TSV opening 48. Increasing the Si / N gas flow ratio may cause the liner 50 to extend less toward the bottom of the TSV opening 48, while reducing the Si / N gas flow ratio may cause the liner 50 to extend more toward the bottom of the TSV opening 48. By selecting appropriate process conditions, including an appropriate combination of pressure and Si / N gas flow ratio, the bottom of the liner 50 can be located at a desired height. Figure 3A As shown, the bottom portion 50bot is at a level flush with (or substantially flush with) the top surface 24T of the semiconductor substrate 24 , for example, the height difference thereof is less than about 100 nm.

[0031] Figure 3B Illustrates the formation of the liner 50 according to an alternative embodiment, where the bottom 50bot of the liner 50 is higher than the top surface 24T of the semiconductor substrate 24. For example, the sidewalls of the top layer of the dielectric layer 38 are covered by the liner 50, while the sidewalls of some of the lower layers of the dielectric layer 38 are not covered by the liner 50. These embodiments can be applied when the bottom layer of the dielectric layer 38 has a higher k-value than the top layer of the dielectric layer 38. Thus, the liner 50 is formed to cover the sidewalls of the dielectric layer 38 having a lower k-value (e.g., having a k-value less than 3.8 or less than about 3.5 or about 3.0), while the sidewalls of the dielectric layer 38 having a higher k-value (e.g., greater than about 3.5 or 3.8) are not protected. It should be understood that parasitic capacitors may be formed between the resulting TSV and the surrounding conductive or semiconductor materials, and the parasitic capacitance between the TSV and the semiconductor substrate 24 is the main contributor to the parasitic capacitance. Thus, as Figure 3A and Figure 3B shown, since the liner 50 (having a higher k-value than the subsequently formed liner 52 ( Figure 4 )) does not extend into the semiconductor substrate 24, the parasitic capacitance can be reduced.

[0032] Figure 3C Illustrates the formation of the liner 50 according to another alternative embodiment, where the bottom 50bot of the liner 50 is lower than the top surface 24T of the semiconductor substrate 24 and higher than the bottom of the TSV opening 48. As described above, the liner 50 in Figure 3C can be achieved by selecting appropriate process conditions.

[0033] Figure 3D Illustrates the formation of the liner 50 according to another alternative embodiment, where the liner 50 covers all surfaces exposed to the TSV opening 48, including the bottom surface of the TSV opening 48. According to some embodiments, Figure 3D the liner 50 in

[0034] can be formed using PECVD and can be achieved by selecting appropriate process conditions, as discussed above. According to alternative embodiments, the liner 50 can be formed using conformal deposition methods such as ALD, CVD, etc. Thus, the resulting liner 50 can be conformal, e.g., the thickness variation of the horizontal and vertical portions is less than about 20% or about 10%. Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D shown, the liner 50 can be a single-layer dielectric liner or a composite liner, such as a bilayer liner. Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D Illustrates an exemplary bilayer liner 50 including dielectric (electronic) liners 50A and 50B. It should be understood that Figure 3A, Figure 3B , Figure 3C and Figure 3D The liner 50 in may also be a single layer liner. Therefore, the lines separating the liners 50A and 50B are represented by dashed lines to indicate that these lines may or may not exist. According to some embodiments, the liners 50A and 50B are formed of different materials or the same material with different compositions. For example, both dielectric liners may be formed of silicon nitride or silicon oxynitride, but the nitrogen atomic percentage of the liner 50A may be higher or lower than the nitrogen atomic percentage in the liner 50B. The liners 50A and 50B may be formed in separate processes, may (may not) be formed in the same process chamber, and may (may not) be formed in situ without a vacuum break between them. Therefore, although Figure 3A , Figure 3B , Figure 3C and Figure 3D Not shown in detail, but according to some example embodiments, the pads 50A and 50B may extend to different depths, such as Figure 3E , Figure 3F and Figure 3G shown.

[0035] Figure 3E , Figure 3F and Figure 3G According to some embodiments, Figure 3A , Figure 3B , Figure 3C and Figure 3D 4. Some details of dual-layer liner 50 are shown. It should be understood that the bottom levels shown for liner 50A and 50B are examples, and the bottom of each of liner 50A and 50B may be at any level between the top and bottom of TSV opening 48 in any combination. For example, the bottom of each of liner 50A and 50B may be at Figure 3A , Figure 3B , Figure 3C and Figure 3D Any level shown. Figure 3E An embodiment is shown in which liner 50B extends deeper into TSV opening 48 than liner 50A. Figure 3F An embodiment is shown in which liner 50B extends to the same depth into TSV opening 48 as liner 50A. Figure 3G An embodiment is shown in which liner 50B extends less into TSV opening 48 than liner 50A.

[0036] exist Figures 3A to 3G In the illustrated embodiment, because liner 50 (and sublayers 50A and 50B) are deposited to different depths, process variations may cause different portions of liner 50 to extend to the same or different depths. Figures 3A to 3GIn each of the embodiments, the portion of the liner 50 on the left side of the opening 48 may extend to the same depth as the portion of the liner 50 on the right side of the opening 48, may extend to a greater depth, or a lesser depth than the portion of the liner 50 on the right side of the opening 48. In addition, the bottom end portion of the liner 50 may have a gradually decreasing thickness (rather than a uniform thickness). For example, Fig.16 The bottom of the pad 50 is shown with a gradually decreasing thickness. Fig.16 It is shown that different portions of dielectric liner 50 may extend to different depths into TSV opening 48. In accordance with some embodiments, depth difference ΔH may be greater than about 100 nm.

[0037] Reference Figure 4 , a second liner 52 is deposited on the first liner 50. The corresponding process is shown as Fig. 20 Process 208 in process flow 200 is shown. According to some embodiments, dielectric liner 52 may be formed of a material different from liner 50. For example, dielectric liner 52 may include or be formed of a dielectric material such as silicon oxide, silicon oxynitride, etc. Therefore, liner 52 may alternatively be referred to as dielectric liner 52. Dielectric liner 52 is deposited as a conformal layer so that the horizontal portion and the vertical portion of dielectric liner 52 have thicknesses that are close to each other, for example, the variation is less than about 20% or 10%. The deposition method may include atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. The thickness T2 of dielectric liner 52 may be about 1000 mm / s. Peace The liners 50 and 52 are also collectively referred to as multilayer liners. According to some embodiments, the ratio T1:T2 may be in a range between about 0.001:1 and about 0.5:1.

[0038] The liner 50 and 52 may have different densities. According to some embodiments, the dielectric liner 50 is denser than the liner 52. For example, the liner 50 may have a density of about 3 g / cm 3 and about 10g / cm 3 The dielectric liner 52 may have a density DS 50 in the range of about 2.5 g / cm 3 and about 4g / cm 3 The density difference (DS52-DS50) can be greater than about 0.5 g / cm 3 , and can be around 0.5g / cm 3 and about 7g / cm 3 in the range between.

[0039] Figure 5 The deposition of the metal seed layer 54 is shown. The corresponding process is shown as Fig. 20Process 210 in process flow 200 is shown. According to some embodiments, metal seed layer 54 is formed by physical vapor deposition (PVD). Metal seed layer 54 may be a single layer, for example, formed of copper, or may include multiple layers, for example, including a conductive barrier layer and a copper layer located on the conductive barrier layer. The conductive barrier layer may be formed of or include TiN, Ti, TaN, Ta, etc.

[0040] Figure 6 The deposition of a conductive material 56 is shown, which may be a metal material such as copper or a copper alloy. The corresponding process is shown as Fig. 20 Process 212 in process flow 200 is shown. The deposition process may be performed using electrochemical plating (ECP), electroless plating, etc. Plating is performed until the top surface of the plated conductive material 56 is higher than the top surface of the liner 50 or 52 .

[0041] Figure 7 , which may be a CMP process or a mechanical grinding process, is implemented to planarize the top surface of the conductive material 56. The corresponding process is shown as Fig. 20 The process 214 in the process flow 200 is shown. Figure 7 As shown, according to some embodiments, the planarization process is performed using dielectric layer 42 as a stop layer. According to an alternative embodiment, a dielectric layer 44 ( Figure 6 ) is implemented as a CMP stop layer. Therefore, the top surface of the remaining conductive material 56 will be coplanar with the top surface of the dielectric layer 44. The remaining portion of the metal seed layer 54 and the conductive material 56 are collectively referred to as the through hole 61 below.

[0042] Figures 7 to 13 The formation of the upper component according to some embodiments is shown. It should be understood that these processes are examples and the present disclosure contemplates any other connection schemes. Further reference Figure 7 , forming a via 58 to connect to the top metal line / pad 34. The corresponding process is shown as Fig. 20 Process 216 in process flow 200 is shown. According to some embodiments, via 58 is formed by a single damascene process. The formation process may include: etching passivation layer 42 and underlying etch stop layer 37 to form an opening; depositing a conductive barrier layer (e.g., formed of titanium, titanium nitride, tantalum, tantalum nitride, etc.); and plating a conductive material such as copper, tungsten, etc. A CMP process may then be performed to remove excess material, leaving via 58.

[0043] refer to Figure 8 According to some embodiments, a dielectric isolation layer 60 is deposited. The corresponding process is shown as Fig. 20The process 218 in the process flow 200 is shown. The material of the isolation layer 60 can be selected from the same group of candidate materials used to form the liner 50, and can be the same as or different from the material of the liner 50. For example, when the liner 50 is formed of silicon nitride, the isolation layer 60 can be formed of silicon nitride or silicon carbide.

[0044] refer to Fig. 9 , the isolation layer 60 is etched, and a metal pad 62 is formed on the passivation layer 42. The corresponding process is shown as Fig. 20 Process 220 in process flow 200 is shown. Metal pad 62 may be an aluminum pad or an aluminum-copper pad, and other metal materials may be used. The formation process may include: depositing a metal layer; and then patterning the metal layer to leave metal pad 62. According to some embodiments, metal pad 62 may also have some portions extending directly over isolation layer 60. Then, passivation layer 64 (sometimes referred to as passivation-2) is formed. The corresponding process is shown as Fig. 20 Process 222 of process flow 200 is shown. Passivation layer 64 may be a single layer or a composite layer, and may be formed of a non-porous material such as silicon oxide, silicon nitride, USG, silicon oxynitride, or the like.

[0045] Next, passivation layer 64 is patterned so that some portions of passivation layer 64 cover edge portions of metal pad 62 and some portions of metal pad 62 are exposed through openings in passivation layer 64. Polymer layer 66 is then formed, for example, by dispensing polymer layer 66 in a flowable form and then curing polymer layer 66. Polymer layer 66 is patterned to expose metal pad 62. The corresponding process is also shown as Fig. 20 The process flow 200 is shown as process 222. The polymer layer 66 may be formed of polyimide, polybenzoxazole (PBO), or the like.

[0046] Then, an under bump metallization (UBM) 68 and a conductive region 70 are formed to electrically connect to the underlying metal pad 62, such as Fig.10 The corresponding process is shown as Fig. 20Process 224 in process flow 200 is shown. The process of forming UBM 68 and conductive region 70 may include: depositing a blanket metal seed layer extending into the openings in passivation layer 64 and polymer layer 66; forming a patterned plating mask on the metal seed layer; plating conductive region 70; removing the plating mask; and etching the portion of the blanket metal seed layer previously covered by the plating mask. The remaining portion of the blanket metal seed layer is referred to as UBM 68. The metal seed layer may include a titanium layer and a copper layer located above the titanium layer. The conductive region 70 may include copper, nickel, palladium, aluminum, gold, alloys thereof, and / or multiple layers thereof. Each of the conductive regions 70 may include a copper region that may or may not be covered with a solder region that may be formed of SnAg or a similar material. According to some embodiments, the conductive region 70 protrudes above the top surface of the top dielectric layer in wafer 20 and may be used for solder bonding, direct metal-to-metal bonding, etc. According to an alternative embodiment, dielectric layer 71 is formed to have a top surface coplanar with a top surface of conductive region 70 and may be used for hybrid bonding.

[0047] Figures 11 to 13 A process for forming features on the back side of semiconductor substrate 24 is shown. The corresponding process is shown as Fig. 20 The process 226 in the process flow 200 is shown. Fig.11 , a backside grinding process is performed to remove a portion of the substrate 24 until the TSV 61 is exposed. Next, as Fig.12 As shown, semiconductor substrate 24 is slightly recessed (eg, by etching) such that TSVs 61 protrude from the back side of semiconductor substrate 24 .

[0048] Next, if Fig.12 As shown, a dielectric layer 72 is deposited, followed by a CMP process or a mechanical grinding process to re-expose the TSV 61. The TSV 61 thus penetrates the dielectric layer 72. The layer 72 is formed of silicon oxide, silicon nitride, etc. Fig.13 , forming RDL 74 including a pad portion contacting TSV 61. According to some embodiments, RDL 74 may be formed of aluminum, copper, nickel, titanium, or the like.

[0049] Fig.14AThe formation of dielectric layer 76 and electrical connector 78 is shown. According to some embodiments, electrical connector 78 includes a solder area that can be formed by plating solder balls on pads of RDL 74 and reflowing the solder balls. According to optional embodiments, electrical connector 78 is formed of a non-reflowable (non-solderable) metal material. For example, electrical connector 78 can be formed as a copper pad or pillar and may or may not include a nickel capping layer. Electrical connector 78 can protrude from the surrounding dielectric layer and can be used for solder bonding or direct metal-to-metal bonding. Optionally, the bottom surface of electrical connector 78 can be coplanar with the bottom surface of dielectric layer 76, so that device 22 can be used for hybrid bonding. Dielectric layer 71 located on the front side of wafer 14 is also Fig.14A It is shown with dashed lines to indicate that it may or may not be formed. Fig. 14B , Fig. 14C , Fig.14D , Fig.14E , Fig.14F and Figure 14G The dielectric layer 71 is not shown in the figures, but may also be formed in the structures shown in these figures. According to some embodiments, the wafer 20 is singulated by a sawing process, for example, by cutting the scribe lines 80 .

[0050] Fig. 14B , Fig. 14C , Fig.14D , Fig.14E , Fig.14F and Figure 14G They are shown based on Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F and Figure 3G The structure shown in the figure is formed by the structure shown in the figure. Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F and Figure 3G Discussion and Figures 4 to 13 The discussion can reveal the formation of Fig. 14B , Fig. 14C , Fig.14D , Fig.14E , Fig.14F and Figure 14G Details of the construction process and materials are shown. Fig.14A , Fig. 14B , Fig. 14C and Fig.14DIn each of the above, a dotted line is drawn in the pad 50, indicating that the pad 50 may be a single-layer pad or a double-layer pad including sub-pads 50A and 50B. Also, the bottom of the pad 50A may be lower than the bottom of the corresponding pad 50B, flush with the bottom of the corresponding pad 50B, or higher than the bottom of the corresponding pad 50B. Fig.14A , the pad 50 has a bottom end 50bot flush with the top surface 24T of the semiconductor substrate 24. When the pad 50 has two subpads 50A and 50B, one of the subpads 50A and 50B has a bottom end 50bot flush with the top surface 24T, and the bottom end 50bot of the other may be higher than the top surface 24T of the semiconductor substrate 24, lower than the top surface 24T of the semiconductor substrate 24, or flush with the top surface 24T of the semiconductor substrate 24. Fig. 14B The bottom end 50bot of the pad 50 (or at least one of the subpads 50A and 50B) is shown to be higher than the top surface 24T. Fig. 14C The bottom end of the pad 50 (or at least one of the subpads 50A and 50B) is shown to be lower than the top surface 24T. Fig.14D The bottom end of pad 50 (and subpads 50A and 50B) is shown extending to the bottom surface of semiconductor substrate 24 . Fig.14E The bottom of subpad 50A is shown to be higher than the bottom of subpad 50B. Fig.14F Subpad 50A is shown extending to the same level as subpad 50B. Figure 14G Subpad 50A is shown extending below subpad 50B.

[0051] In the examples discussed above, the top ends of TSVs 61 are flush with the top surface of passivation layer 42. According to alternative embodiments, the top ends of TSVs 61 may be at any other level (when applicable) below the top surface of passivation layer 42. For example, the top surfaces of TSVs 61 may be coplanar with the top surface of the top metal layer in interconnect structure 32, coplanar with the top surface of any other dielectric layer in interconnect structure 32, coplanar with the top surface of ILD 28, or coplanar with the top surface of substrate 24.

[0052] Fig.15 A plan view of TSV 61 is shown. According to some embodiments, each of pads 50A and 50B and dielectric liner 52 forms a ring, which may have a circular shape, a polygonal shape (eg, a hexagonal shape or an octagonal shape), etc. Metal seed layer 54 (if including a material different from that of conductive material 56 ) may be distinguishable.

[0053] Fig.16TSV 61 and liners 50 and 52 are shown according to some embodiments. The bottom end of liner 50 (and sublayers 50A and 50B) may have a gradually decreasing thickness, where the upper portion is thicker than the corresponding bottom portion. As described above, due to process variations, different portions of liner 50 may extend to different heights. Moreover, there may or may not be certain portions 50' of substrate 50 separated from the upper portion of substrate 50 to form discrete islands.

[0054] Figures 17 to 19 The package 81 ( Fig.19 ) is an intermediate stage in the formation of a package including a device 22. It should be understood that the device 22 is shown schematically and that details of the device 22 (such as the pads of the TSV) can be found with reference to the disclosures cited above. Fig.17 , bonding device 22 to device 82. Bonding may be performed by hybrid bonding, where dielectric layer 71 and electrical connector (conductive region) 70 are bonded to surface dielectric layer 84 and bonding pad 86 of device 82, respectively. Device 82 may be a device die, a package substrate, an interposer, a package, etc.

[0055] Fig.18 FIG. 2 shows the structure after the backside grinding process is performed on the semiconductor substrate 24 and the semiconductor substrate 24 is recessed by etching. Therefore, the TSV 61 protrudes higher than the back side of the semiconductor substrate 24. Fig.19 As shown, a dielectric layer 72 is deposited, followed by a planarization process to make the dielectric layer 72 flush with the top surface of the TSV 61. Then a gap fill region 90 is formed, which can be formed of or include a molding compound, silicon nitride, silicon oxide, etc. or a combination thereof. Then an interconnect structure 92 including electrical connectors 78 is formed over the device 22 and the gap fill region 90. The interconnect structure 92 is electrically connected to the device 82 through the TSV 61.

[0056] Embodiments of the present invention have some advantageous features. By forming more than one dielectric liner for a through hole, the electrical performance of the corresponding device is more stable. The liner can be selectively formed on the sidewalls of some parts of the TSV (such as a part that is not in the semiconductor substrate), thereby reducing parasitic capacitance.

[0057] According to some embodiments of the present invention, a method includes forming a plurality of dielectric layers over a semiconductor substrate; etching the plurality of dielectric layers and the semiconductor substrate to form an opening; depositing a first liner extending into the opening; depositing a second liner over the first liner, wherein the second liner extends into the opening; filling a conductive material into the opening to form a through hole; and forming conductive features on opposite sides of the semiconductor substrate, wherein the conductive features are electrically interconnected through the through hole. In an embodiment, depositing the first liner is implemented using a non-conformal deposition method. In an embodiment, depositing the second liner is implemented using a conformal deposition method. In an embodiment, the first liner is deposited to have a first bottom higher than a second bottom of the opening. In an embodiment, the first bottom is flush with a top surface of the semiconductor substrate. In an embodiment, the first bottom is higher than the top surface of the semiconductor substrate. In an embodiment, the first bottom is lower than the top surface of the semiconductor substrate. In an embodiment, depositing the first liner includes depositing a conductive liner, and depositing the second liner includes depositing a dielectric liner. In an embodiment, depositing the first liner includes depositing silicon nitride, and depositing the second liner includes depositing silicon oxide. In an embodiment, depositing the first liner includes depositing silicon carbide, and depositing the second liner includes depositing silicon oxide.

[0058] According to some embodiments of the present invention, a structure includes a semiconductor substrate; a plurality of dielectric layers located above the semiconductor substrate; a first conductive component located above the plurality of dielectric layers; a second conductive component located below the semiconductor substrate; a through hole penetrating the semiconductor substrate and the plurality of dielectric layers, wherein the through hole electrically interconnects the first conductive component and the second conductive component; a first liner surrounding the through hole; a second liner surrounding the first liner, wherein the second liner has a higher density than the first liner. In an embodiment, the first liner is in physical contact with the top of the through hole, and the second liner is in physical contact with the bottom of the through hole. In an embodiment, the bottom end of the second liner is flush with the top surface of the semiconductor substrate. In an embodiment, the bottom end of the second liner is higher than the top surface of the semiconductor substrate. In an embodiment, the bottom end of the second liner is lower than the top surface of the semiconductor substrate. In an embodiment, the first liner includes silicon oxide, and the second liner includes silicon nitride. In an embodiment, the second liner includes a first sublayer and a second sublayer surrounding the first sublayer, and wherein the bottom ends of the first sublayer and the second sublayer are at different heights.

[0059] According to some embodiments of the present invention, a structure includes a tube core. The tube core includes a semiconductor substrate; a plurality of low-k dielectric layers located above the semiconductor substrate; a through hole penetrating the semiconductor substrate and the plurality of low-k dielectric layers; a first pad surrounding the through hole, wherein the first pad extends to the top and bottom ends of the through hole; a second pad surrounding the first pad, wherein the second pad is shorter than the through hole; a first electrical connector located above the semiconductor substrate and at the top surface of the tube core; and a second electrical connector located below the semiconductor substrate and at the bottom surface of the tube core, wherein the first electrical connector and the second electrical connector are electrically interconnected through the through hole. In an embodiment, the second pad is denser than the first pad. In an embodiment, the second pad is thinner than the first pad.

[0060] The parts of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor structure, comprising: forming a plurality of dielectric layers over the semiconductor substrate; etching the plurality of dielectric layers and the semiconductor substrate to form an opening, the opening passing through a top surface of the semiconductor substrate but not penetrating to a bottom surface of the semiconductor substrate; Depositing a first liner extending into the opening, wherein a bottom of the first liner is higher than a bottom of the opening and higher than a bottom surface of the semiconductor substrate; depositing a second liner over the first liner, wherein the second liner extends into the opening; filling the opening with a conductive material to form a through-hole; as well as forming conductive features on opposite sides of the semiconductor substrate, wherein the conductive features are electrically interconnected through the vias, The bottom of the first pad is higher or lower than the top surface of the semiconductor substrate. The first pad includes a first sublayer and a second sublayer surrounding the first sublayer, and the bottom ends of the first sublayer and the second sublayer are at different heights.

2. The method according to claim 1, wherein: Depositing the first liner is performed using a non-conformal deposition method.

3. The method according to claim 2, wherein: Depositing the second liner is performed using a conformal deposition method.

4. The method according to claim 1, wherein: The first liner is denser than the second liner.

5. The method according to claim 1, wherein: The thickness of the first liner ranges between 2 Å and 500 Å.

6. The method according to claim 1, wherein: The first liner is a dielectric liner.

7. The method according to claim 1, wherein: The first liner is a composite liner.

8. The method according to claim 1, wherein: Depositing the first liner includes depositing a conductive liner, and depositing the second liner includes depositing a dielectric liner.

9. The method according to claim 1, wherein: Depositing the first liner includes depositing silicon nitride, and depositing the second liner includes depositing silicon oxide.

10. The method according to claim 1, wherein: Depositing the first liner includes depositing silicon carbide, and depositing the second liner includes depositing silicon oxide.

11. A semiconductor structure comprising: Semiconductor substrate; a plurality of dielectric layers disposed above the semiconductor substrate; a first conductive component disposed above the plurality of dielectric layers; A second conductive component, located below the semiconductor substrate; a through hole penetrating the semiconductor substrate and the plurality of dielectric layers, wherein the through hole electrically interconnects the first conductive component and the second conductive component; A first gasket surrounding the through hole; and a second liner surrounding the first liner, wherein the second liner has a higher density than the first liner, and the second liner does not surround a portion of a sidewall of the through hole located in the semiconductor substrate, Wherein, the bottom end of the second pad is higher or lower than the top surface of the semiconductor substrate, The second pad includes a first sublayer and a second sublayer surrounding the first sublayer, and the bottom ends of the first sublayer and the second sublayer are at different heights.

12. The semiconductor structure according to claim 11, wherein: The first pad is in physical contact with a top portion of the through-hole, and the second pad is in physical contact with a bottom portion of the through-hole.

13. The semiconductor structure according to claim 12, wherein: The second liner has a thickness in a range between 2 Å and 500 Å.

14. The semiconductor structure according to claim 12, wherein: The second liner is a dielectric liner.

15. The semiconductor structure according to claim 12, wherein: The second liner is a composite liner.

16. The semiconductor structure according to claim 11, wherein: The first liner includes silicon oxide, and the second liner includes silicon nitride.

17. The semiconductor structure according to claim 11, wherein: The second liner is thinner than the first liner.

18. A semiconductor structure comprising: A tube core, the tube core comprising: Semiconductor substrate; a plurality of low-k dielectric layers located above the semiconductor substrate; a through hole penetrating the semiconductor substrate and the plurality of low-k dielectric layers; a first liner surrounding the through hole, wherein the first liner extends to the top and bottom ends of the through hole; a second pad surrounding the first pad, wherein the second pad is shorter than the through hole; a first electrical connection located above the semiconductor substrate and at a top surface of the die; and a second electrical connection member located below the semiconductor substrate and at the bottom surface of the die, wherein the first electrical connection member and the second electrical connection member are electrically interconnected through the through hole, Wherein, the bottom end of the second pad is higher or lower than the top surface of the semiconductor substrate, The second pad includes a first sublayer and a second sublayer surrounding the first sublayer, and the bottom ends of the first sublayer and the second sublayer are at different heights.

19. The semiconductor structure according to claim 18, wherein: The second liner is denser than the first liner.

20. The semiconductor structure of claim 18, wherein: The second liner is thinner than the first liner.

Images