Electronic circuits and sensor systems

Abstract

The present invention provides an electronic circuit capable of externally identifying a disconnected state when a power supply line is disconnected. To this end, the electronic circuit includes: a load provided between a power supply line and an output terminal in the electronic circuit; a transistor provided between the load and the output terminal; a current generating circuit for generating a current using a power supply voltage of the power supply line in the electronic circuit; and a control circuit for controlling the transistor using a control voltage that varies with the current generated by the current generating circuit.

Description

Technical Field

[0001] The present invention relates to electronic circuits and sensor systems, for example, to semiconductor electronic circuits and sensor systems for vehicle use. Background Art

[0002] Semiconductor electronic circuits equipped with output circuits that output signals measured by sensors are widely used. For example, the output circuits in vehicle-mounted semiconductor electronic circuits are sometimes transmitted to ECUs (Engine Control Units) via output wiring. In semiconductor electronic circuits such as sensors, power supply lines are generally connected to supply power from the outside.

[0003] As a prior art in this technical field, there is Patent Document 1. Patent Document 1 discloses a structure in which, for the purpose of preventing erroneous detection of the output being in the power supply voltage state, when the load is open, the output terminal voltage is limited to a voltage generated using a current source and a clamp circuit so that it is not erroneously detected as the power supply voltage.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2016-122965 Summary of the invention

[0007] Problems to be solved by the invention

[0008] However, Patent Document 1 does not consider the case where the power supply line is disconnected.

[0009] When the power supply line is disconnected, it is necessary to be able to identify the disconnection on the ECU side. More specifically, when the ECU side is connected to the power supply through a pull-up resistor, it is required that the output impedance of the output circuit becomes high impedance when the power supply is disconnected to prevent current from flowing into the output terminal, and the output terminal voltage becomes a voltage substantially equal to the power supply voltage. In this way, by making the output terminal voltage substantially equal to the power supply voltage, the ECU side can identify that the power supply line has been disconnected.

[0010] However, when the power supply line is disconnected, there is a path in the output circuit where current flows through the output terminal and the power supply line, so sometimes current flows from the output terminal into the output circuit and the output terminal voltage becomes an intermediate potential. In order to recognize the power supply line disconnection on the ECU side, it is necessary to suppress the current inflow and the intermediate potential, make the output impedance high, and make the output terminal voltage high.

[0011] In addition, even when the power supply line is disconnected, sometimes there is residual charge in the power supply line in the output circuit, and the power supply voltage does not drop to the ground level, or it takes a very long time for the power supply voltage to drop. Therefore, even when the power supply line is disconnected, the power supply voltage becomes an intermediate potential, so it is difficult to use the power supply voltage for the control voltage. In the case where the power supply voltage is an intermediate potential, there is also a problem of suppressing the current inflow from the output terminal to the power supply line in the output circuit and the intermediate potential of the output terminal and outputting a high level.

[0012] The present invention has been completed in view of such a situation, and its purpose is to provide an electronic circuit and a sensor system that, when a power supply line provided to a semiconductor circuit is disconnected, suppresses the current flowing from an output terminal to a power supply line in an output circuit and the intermediate potential of the output terminal, makes the output impedance high impedance, and makes the output terminal voltage substantially equal to the voltage connected to the external circuit side.

[0013] Technical solutions to solve problems

[0014] In view of the above-mentioned background technology and problems, the present invention cites an example of an electronic circuit, including: a load arranged between a power line and an output terminal in the electronic circuit; a transistor arranged between the load and the output terminal; a current generating circuit that generates current using the power supply voltage of the power line in the electronic circuit; and a control circuit that controls the transistor using a control voltage that varies with the current generated by the current generating circuit.

[0015] Effects of the Invention

[0016] According to the present invention, it is possible to provide an electronic circuit and a sensor system with improved accuracy in disconnection detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the structure of the sensor system in Example 1.

[0018] Figure 2 This is a schematic diagram of the structure of a conventional output circuit.

[0019] Figure 3 This is a waveform diagram of the operation of the conventional output circuit and when the power supply line is disconnected.

[0020] Figure 4 This is a schematic diagram of the electronic circuit in Example 1.

[0021] Figure 5 This is an operation waveform diagram when the output circuit in Example 1 is operating and when the power supply line is disconnected.

[0022] Figure 6 This is a schematic diagram of the electronic circuit in Example 2.

[0023] Figure 7 This is a schematic diagram of the electronic circuit in Example 3.

[0024] Figure 8 This is a schematic diagram of the electronic circuit in Example 4.

[0025] Fig. 9 This is a schematic diagram of the electronic circuit in Example 5.

[0026] Fig.10 This is a schematic diagram of the electronic circuit in Example 6. DETAILED DESCRIPTION

[0027] The embodiments of the present invention are described in detail below using the accompanying drawings. The circuit elements constituting each functional block of the embodiments are not particularly limited and are formed on a semiconductor substrate such as single crystal silicon using known integrated circuit technology such as CMOS (complementary MOS) transistors.

[0028] (Example 1)

[0029] Figure 1 It is a schematic structural diagram of the sensor system in this embodiment. Figure 1 The sensor system shown is, for example, a vehicle-mounted sensor system, and includes a sensor element 101 , a semiconductor electronic circuit 102 , and an ECU 107 .

[0030] The sensor element 101 is an element whose electrical characteristics change according to a physical quantity, and outputs an electrical signal corresponding to the change of the detection object. The sensor element 101 is, for example, an air flow sensor as an element for measuring the amount of air inhaled by an engine, but is not particularly limited thereto. That is, the sensor element 101 converts a physical quantity such as air flow, temperature, humidity, and pressure into an electrical signal and outputs it.

[0031] The semiconductor electronic circuit 102 includes a power supply circuit 103, an analog circuit 104, a processor 105, and an output circuit 106, and is composed of, for example, a single semiconductor chip. The semiconductor electronic circuit 102 mainly processes the electrical signal from the sensor element 101, and outputs the processing result as a SENT (Single Edge Nibble Transmission) signal or a frequency modulated output signal via the output circuit 106. In addition, it is sometimes a circuit that outputs a NAND signal voltage.

[0032] The analog circuit 104 performs amplification, filtering, analog / digital conversion, digital / analog conversion, and other processing on the electrical signal from the sensor element 101. The processor 105 processes digital data, controls peripheral circuits, and the like. The power supply circuit 103 generates an internal power supply from an external power supply and distributes it to each circuit. The output circuit 106 receives the processing result from the analog circuit 104 or the processor 105, and outputs the output signal to the ECU 107 (e.g., SENT signal) VOUT via the output terminal 112 and the output wiring 109. In addition, the power supply POWER is provided from the ECU 107 or other external devices via the power supply line 108 and the power supply terminal 111, and is connected to the ground GND via the ground terminal 113. In addition, 110 is a ground wiring.

[0033] Figure 2 This is an example of an existing output circuit. The output circuit 201 is composed of a control circuit 202, loads 203, 204, a power supply terminal 111, and an output terminal 112. The power supply terminal 111 is connected to the power supply line 108, and power is provided from the outside such as the ECU. In addition, the output line is connected to the output terminal 206 to transmit the output signal to an external controller such as the ECU. The output line is connected to a specified voltage via a pull-up resistor 120 in the interface circuit of the ECU. The specified pull-up resistor 120 is, for example, 1 kΩ to several tens of kΩ. During normal operation, in order to output data reflecting sensor signals, etc., the loads 203 and 204 are controlled by the control circuit 202.

[0034] Here, the power supply line 108 may be disconnected due to external physical force, aging degradation, or the like. Figure 3 This shows the voltage waveform when the power supply line is disconnected from the operating state. Figure 3 In FIG. 1 , the upper waveform indicates the voltage of the power supply terminal, and the lower waveform indicates the voltage of the output terminal, which indicates the waveform when the power supply line is disconnected from the operating state to the time 305.

[0035] When the power supply line 108 is disconnected, the output circuit 201 is not powered. However, the output line is connected to a predetermined voltage via the pull-up resistor 120 on the ECU side, so Figure 2 As shown, the current flows from the output terminal to the power supply line in the output circuit via the load. In addition, when the load is a PMOSFET, there is also a case where the current flows via the parasitic diode between the drain and the back gate. The output resistance of the output terminal is designed to be several tens of Ω to 1 kΩ in order to drive the output line or enhance noise resistance. Therefore, since it is a low resistance compared to the pull-up resistor, the output terminal voltage does not become the specified voltage to be pulled up, but becomes an intermediate potential (304).

[0036] Sensor electronic circuits require a diagnostic function in the event of a fault. When the power supply line is disconnected and the sensor electronic circuit is not powered, it is necessary to identify that the disconnection is caused by an external circuit. More specifically, the disconnection can be identified by making the output signal high and fixed at a potential different from the normal level.

[0037] On the ECU side, when the power supply line is disconnected, in order to identify the disconnected state, the output terminal voltage is required to be a predetermined voltage. Specifically, the output resistance of the output circuit is required to be a high resistance, and the pull-up voltage is substantially equal to the voltage connected to the pull-up resistor. By reaching this pull-up voltage, it is possible to identify that the power supply line is disconnected, but as described above, in the circuit of the prior art, it becomes an intermediate potential and cannot identify that the power supply line is disconnected.

[0038] In addition, if Figure 3 As shown, when the power supply line is disconnected from the state where the sensor circuit is operating while the power is supplied, charge is accumulated in the power supply of the output circuit, so at the power supply terminal, although the voltage drops to a certain extent from the power supply voltage (301), it takes a considerable time to drop to the ground level (303). That is, the power supply terminal voltage also becomes an intermediate potential state (302). On the ECU side, it is necessary to recognize that the power supply line is in a disconnected state, so it is necessary to make the output terminal voltage a high level without waiting for the power supply terminal voltage to drop. That is, the subject is to recognize that the power supply line is disconnected even when the power supply terminal voltage is in an intermediate potential state.

[0039] Figure 4 FIG. 1 is a schematic diagram of the electronic circuit equipped with an output circuit in this embodiment. Figure 4 In the figure, the electronic circuit 400 is composed of a load 401, a transistor 402, a current generating circuit 403, a current-voltage conversion circuit 404, a power supply terminal 111, and an output terminal 112. In addition, the current-voltage conversion circuit 404 is composed of a current mirror circuit composed of PMOS FETs 407 and 408, a resistor 409, an NMOS FET 410, and a PMOS FET 411.

[0040] In normal operation, the current generating circuit 403 generates a current IREF that serves as a reference using the power from the power supply terminal 111. The reference current is mirrored by the current mirror circuit, and the current is converted into a voltage through the resistor 409. The control signal VCTL during operation becomes a high level. Since the voltage is inverted by the NMOS FET 410, the gate voltage of the transistor 402 is controlled by a low-level signal, so the transistor 402 is turned on. In addition, the gate voltage of the PMOS FET 411 becomes a high level, so it is turned off.

[0041] Therefore, during normal operation, the transistor 402 is controlled to be on, the output line is driven through the load 401 , and a signal is output from the output terminal 112 .

[0042] Next, the operation in the case of a power supply line disconnection is described. In the case of a power supply line 108 disconnection, the electronic circuit continues to operate for a certain period of time using the charge accumulated in the capacitor on the electronic circuit side of the power supply line disconnection portion. Then, since the electronic circuit consumes charge through the circuit, the power supply voltage decreases, and as the power supply voltage decreases, the circuit becomes unable to operate. When the output circuit stops operating, the current consumption decreases sharply. Specifically, the circuit operation stops referring to the power supply voltage in the electronic circuit dropping to a voltage near the threshold voltage corresponding to the number of levels of the vertically stacked transistors. If the current consumption decreases, it is difficult for the voltage itself to drop further.

[0043] In this way, when the power supply voltage in the electronic circuit drops and the circuit operation stops, the current value of the reference current IREF as the output of the current generating circuit 403 decreases and approaches zero. Along with this, the output current of the current mirror circuit also decreases, the voltage drop in the resistor 409 becomes smaller, and the control signal VCTL becomes a low level. In addition, the gate potential of the NMOS FET410 becomes a low level, so it becomes cut off. In addition, the PMOS FET411 is turned on, so the gate voltage of the transistor 402 becomes a voltage substantially equal to the output terminal voltage. Therefore, the transistor 402 is cut off, and the impedance from the output terminal 112 to the power supply line in the electronic circuit becomes high, which can suppress the current inflow from the output terminal 112 to the power supply line in the electronic circuit, so the intermediate potential of the output terminal 112 can be suppressed. Therefore, the potential of the output terminal 112 becomes a voltage substantially equal to the voltage pulled up on the ECU107 side, and it can be recognized that the power supply line is disconnected. That is, the PMOS FET411 becomes a switch for connecting the gate terminal of the transistor 402 to the wiring connected to the output terminal when the line is disconnected.

[0044] Figure 5 This is a waveform diagram of the operation of the electronic circuit in this embodiment when it is in operation and when the power supply line is disconnected. Figure 5 In, with Figure 3 The same functions are denoted by the same reference numerals, and their descriptions are omitted. Figure 5 The upper waveform represents the voltage at the power supply terminal, and the middle waveform represents Figure 4The current IREF in the circuit is , and the waveform below represents the voltage of the output terminal. The power supply voltage is provided during operation, and an output signal is output. In addition, a reference current IREF (503) is generated, and the control voltage VCTL becomes a high level. If the power supply line is disconnected (305), the power supply terminal voltage drops to a certain level due to the current consumption of the circuit (502). Therefore, the reference current IREF decreases and becomes approximately zero (503). Along with this, the control voltage VCTL becomes a low level, the transistor 402 becomes cut off, and the output terminal voltage becomes a high level voltage approximately equal to the pull-up voltage.

[0045] In this way, by using the voltage connected to the power supply line in the electronic circuit to generate current, and using the voltage that changes according to the current to control the transistor, the intermediate potential of the output terminal when the power supply line is disconnected can be suppressed, and the output impedance can be made high impedance, resulting in a high-level output. In addition, by using the current, even if the power supply terminal voltage does not fall below a certain level due to the power supply line being disconnected during operation, the output terminal can be made high level.

[0046] As described above, the electronic circuit in this embodiment generates the control voltage VCTL by using the pull-down resistor, thereby making the voltage become the ground level even in a state where the power supply is cut off.

[0047] In addition, in this embodiment, the case where the load is a transistor is described, but it is not limited to this, and it can also be a resistor. By setting the resistor as the load, the output resistance can be made to be a roughly constant resistance value independent of the output voltage. In addition, the positional relationship between the load and the transistor is not limited to this.

[0048] Furthermore, during standby when the circuit operation is unnecessary, the reference current IREF is cut off, thereby achieving low power consumption.

[0049] Next, the power supply voltage, the current value of the current mirror, the resistance value and the operation thereof are explained, but since this is an example, it is not limited to this. The power supply voltage is set to 5V. The reference current IREF, the mirror current and the pull-down resistor are set as follows. For example, 10μA is used as the reference current IREF. The mirror ratio can be 1:1, or it can be set to 1:4 with a gain of, for example, 4 times. When the mirror current is set to 40μA, if the pull-down resistor is set to 300kΩ, then if a current of 40uA flows through the pull-down resistor, the voltage becomes 12V. In fact, the power supply voltage is 5V, so the voltage between the source and drain of the PMOS FET becomes low and enters the non-saturation region. The control voltage becomes a value close to the power supply voltage, which is less than 5V. That is, during normal operation, the control voltage becomes 5V, which is approximately equal to the power supply voltage. On the other hand, when the power supply line is disconnected, the power supply terminal voltage drops and the mirror current decreases. If the threshold voltage of the NMOS FET is set to 0.9V, when the current decreases to about 3μA, it falls below the threshold voltage of the NMOS FET and the NMOS FET is turned off.

[0050] In this way, by designing the product of the output current of the current mirror and the pull-down resistor to be sufficiently higher than the power supply voltage, the control voltage can be set to a high level during normal operation, and the transistor can be reliably turned on.

[0051] The current generating circuit 403 uses a circuit that generates a current output by using a bandgap reference circuit or the like. Alternatively, a circuit that generates a current by using a voltage converted by a regulator or the like as a power source instead of directly using the voltage supplied to the power supply terminal may be used.

[0052] Furthermore, the positional relationship between the load and the transistor in this embodiment may be reversed, that is, a transistor may be provided between the load and the power supply line in the electronic circuit for control.

[0053] In addition, the current-voltage conversion circuit 404 has been described as a configuration using a current mirror and a resistor, but the invention is not limited thereto. Specifically, for example, the control voltage may be generated by a current-voltage conversion circuit using an operational amplifier and a resistor.

[0054] Thus, according to this embodiment, since the on / off state of the transistor is controlled by using a control voltage that changes according to a change in the current generated using the power terminal voltage, the transistor can be properly controlled when the power supply line is broken, so that a circuit that can output a high-level potential when a break occurs and improve the accuracy of break detection can be provided.

[0055] (Example 2)

[0056] Figure 6 FIG. 1 is a schematic diagram of the electronic circuit equipped with an output circuit in this embodiment. Figure 6 In, with Figure 4 The same functions are denoted by the same reference numerals, and their descriptions are omitted. Figure 6 In the embodiment, the electronic circuit 600 is composed of a load 401, a transistor 402, a current generating circuit 403, a current-voltage conversion circuit 404, a power supply terminal 111, an output terminal 112, and a substrate control circuit 604. The substrate control circuit 604 is composed of PMOS FETs 601 and 602. When the transistor 402 is composed of a PMOS FET, a parasitic diode exists between the drain terminal and the back gate terminal, and between the source terminal and the back gate terminal. Therefore, in order to prevent the parasitic diode from being turned on and flowing current, it is necessary to connect the back gate terminal of the transistor 402 to a high potential. Specifically, the back gate terminal of the transistor 402 is controlled in such a way that it is connected to the power supply voltage during operation and connected to the output voltage of the output terminal when the power supply line is disconnected. During operation, since the control voltage VCTLB is at a low level, the PMOS FET 601 is turned on, and the back gate terminal of the transistor 402 is connected to the power supply voltage to maintain the power supply voltage. When the power supply line is disconnected, the output terminal voltage is higher than the power supply voltage, so the PMOS FET 601 is turned off and the PMOS FET 602 is turned on to connect the back gate terminal voltage of the transistor 402 to the output terminal voltage.

[0057] In addition, the gate voltage of the transistor 402 is controlled using the current of the current generating circuit 403 that generates the current using the power from the power supply line in the electronic circuit and the voltage after the current-voltage conversion by the current-voltage conversion circuit 404. In this way, by controlling the back gate terminal voltage of the transistor 402 and controlling the gate voltage using the voltage via the current generating circuit 403 and the current-voltage conversion circuit 404, it is possible to control the electronic circuit at the output terminal to be in a high impedance state and output a high level when the power supply line is disconnected.

[0058] (Example 3)

[0059] Figure 7 FIG. 1 is a schematic diagram of the electronic circuit equipped with an output circuit in this embodiment. Figure 7 In, with Figure 4 The same functions are denoted by the same reference numerals, and their descriptions are omitted. Figure 7In the figure, the electronic circuit 700 is composed of loads 703, 706, a transistor 402, a current generating circuit 403, a current-voltage conversion circuit 404, a power supply terminal 111, and an output terminal 112. Loads 703 and 706 are current mirror circuits that drive the output with a constant current. In the current mirror circuit for output, the sink side is a load 706, which is composed of NMOS FETs 704 and 705, and the source side is a load 703, which is composed of PMOS FETs 701 and 702. Current mirror circuits are respectively provided on the sink side and the source side to drive the output signal to rise and fall with a certain current drive. By performing a constant current output, the output load can be appropriately driven. For example, it is driven with a current of several mA to 10 mA. If the amplitude of the output signal is set to 5V and the output current is set to 5mA, the output resistance when the potential difference is 5V is 1kΩ. In addition, for example, the output resistance when the potential difference is 1V is 200Ω. The value of this output resistance is smaller than the pull-up resistor. Therefore, when the power supply line is disconnected, it is necessary to turn off the transistor 402 or turn it into a high impedance state. By generating a current by the current generating circuit 403, converting the current into a voltage by the current voltage conversion circuit 404, and controlling the gate voltage of the transistor 402, the transistor 402 is controlled to be turned on and turned into a low output impedance state during operation, and the transistor 402 is controlled to be turned off and turned into a high output impedance state when the power supply line is disconnected. In this way, when the power supply line is disconnected, the current flowing into the output terminal is suppressed, and a high-level output can be performed.

[0060] (Example 4)

[0061] Figure 8 FIG. 1 is a schematic diagram of the electronic circuit equipped with an output circuit in this embodiment. Figure 8 In, with Figure 4 The same functions are denoted by the same reference numerals, and their descriptions are omitted. Figure 8 In, with Figure 4 The difference is that the load 801 is a resistor. In this way, the load may not be an active element such as a transistor, but may be a passive element such as a resistor. In addition, it may also be a structure combining a transistor and a resistor.

[0062] (Example 5)

[0063] Fig. 9 FIG. 1 is a schematic diagram of the electronic circuit equipped with an output circuit in this embodiment. Fig. 9 In, with Figure 7 The same functions are denoted by the same reference numerals, and their descriptions are omitted. Fig. 9 In, with Figure 7The difference is that the current-voltage conversion circuit 910 is composed of a current mirror circuit 905 connected in a cascode manner. Specifically, the current mirror circuit 905 is composed of PMOS FETs 901, 902, 903, and 904. When the power supply voltage is reduced due to the cascode connection, the PMOSFET is likely to operate in a non-saturated region, and the mirrored current is reduced at an early stage, and the potential of the control voltage VCTL decreases due to the pull-down resistor. Along with this, the gate voltage of the transistor 402 is controlled by the control voltage VCTLB to be cut off.

[0064] By making the current mirror circuit cascode connected in this way, the number of vertically stacked stages increases, and when the power supply line is disconnected and the voltage at the power supply terminal drops, the current can be reliably cut off to perform a high-level output. By using the current mirror circuit to cut off the current earlier than the current supply capacity of the current generating circuit 403, it is possible to prevent the current generating circuit from being operated by the current flowing from the output terminal to the power supply line in the electronic circuit.

[0065] (Example 6)

[0066] Fig.10 FIG. 1 is a schematic diagram of the electronic circuit equipped with an output circuit in this embodiment. Fig.10 In, with Figure 7 The same functions are denoted by the same reference numerals, and their descriptions are omitted. Fig.10 In the embodiment, the electronic circuit 1000 is composed of loads 703 and 706, a transistor 402, and a control voltage generating circuit 1001. Even when the power supply terminal voltage does not drop when the power supply line is disconnected, the PMOS FET 1002 connected by the diode lowers the potential for control, thereby making it possible to make the potential of the control voltage VCTL a voltage lower than the threshold voltage of the NMOS FET 410. Therefore, even when the power supply terminal voltage does not drop when the power supply line is disconnected, the gate voltage of the transistor 402 can be controlled, and the transistor 402 can be turned off to suppress the intermediate potential of the output terminal voltage.

[0067] The element is not limited to the PMOS FET, and a constant voltage diode or the like may be used. Alternatively, a resistor may be used to perform control using a voltage obtained by dividing the power supply voltage.

[0068] The above embodiments are described, but the present invention is not limited to the above embodiments, and includes various modified examples. For example, the above embodiments are described in detail to explain the present invention in an easy-to-understand manner, and are not limited to including all the structures described. In addition, a part of the structure of a certain embodiment can be replaced with the structure of other embodiments, and the structure of other embodiments can be added to the structure of a certain embodiment. In addition, for a part of the structure of each embodiment, other structures can be added, deleted, or replaced.

[0069] Description of Reference Numerals

[0070] 101: sensor element; 102: semiconductor electronic circuit; 103: power supply circuit; 104: analog circuit; 105: processor; 106, 201: output circuit; 400, 600, 700, 800, 900, 1000: electronic circuit; 107: ECU; 108: power supply line; 109: output wiring; 110: ground wiring; 111: power supply terminal; 112: output terminal; 113: ground terminal; 202: control circuit; 203, 204, 401, 703, 706, 801: load; 402: transistor; 403: current generation circuit; 404, 910: current-voltage conversion circuit; 407, 408, 411, 601, 602, 701, 702, 901, 902, 903, 904, 1002: PMOS FET; 409: resistor; 410, 704, 705: NMOS FET; 604: substrate control circuit; 905: current mirror circuit; 1001: control voltage generation circuit.

Claims

1. An electronic circuit, characterized in that: include: a load disposed between a power line and an output terminal in the electronic circuit; a transistor disposed between the load and the output terminal; a current generating circuit for generating a current using a power supply voltage of a power supply line in the electronic circuit; and a control circuit for controlling the transistor using a control voltage that varies with the current generated by the current generating circuit, A current mirror circuit and a pull-down resistor are provided between the current generating circuit and the transistor, which change the control voltage based on the change of the current generated by the current generating circuit. The pull-down resistor is connected between the output of the current mirror circuit and a ground line.

2. The electronic circuit according to claim 1, characterized in that: The power supply voltage of the power supply line in the electronic circuit changes due to a disconnection of a power supply line connected to the power supply line in the electronic circuit, The control circuit controls on and off of the gate terminal of the transistor using the control voltage.

3. The electronic circuit according to claim 2, characterized in that: The control circuit controls the gate terminal of the transistor so that the transistor is turned on when the electronic circuit is operating and the transistor is turned off when the line is broken.

4. The electronic circuit according to claim 3, characterized in that: When the line is disconnected, the transistor is turned off when the power supply voltage reaches a predetermined voltage higher than the ground level.

5. The electronic circuit according to claim 2, characterized in that: The back gate terminal of the transistor is controlled so as to be connected to the power supply voltage when the electronic circuit is operating and to be connected to the output voltage of the output terminal when the circuit is disconnected.

6. The electronic circuit according to claim 1, wherein: The product of the designed output current value of the current mirror circuit and the resistance value of the pull-down resistor is higher than the voltage supplied to the power line during operation.

7. The electronic circuit according to claim 1, wherein: The current mirror circuit is a structure in which a PMOS FET is connected in a common source and common gate manner.

8. The electronic circuit according to claim 2, wherein: When the line is disconnected, the output current of the current mirror circuit decreases faster than the current generated by the current generating circuit.

9. The electronic circuit according to claim 2, characterized in that: A switch is provided for connecting the gate terminal of the transistor to the wiring connected to the output terminal when the wiring is disconnected.

10. A sensor system comprising: A sensor element that outputs an electrical signal corresponding to changes in the detected object; and an electronic circuit for processing the electrical signal and outputting the result of the processing via an output circuit, wherein the sensor system is characterized in that: The output circuit comprises: a load disposed between a power line and an output terminal in the electronic circuit; a transistor disposed between the load and the output terminal; A current generating circuit for generating a current using a power supply voltage of a power supply line in the electronic circuit; and a control circuit for controlling the transistor using a control voltage that varies with the current generated by the current generating circuit, A current mirror circuit and a pull-down resistor are provided between the current generating circuit and the transistor, which change the control voltage based on the change of the current generated by the current generating circuit. The pull-down resistor is connected between the output of the current mirror circuit and a ground line.

11. The sensor system according to claim 10, characterized in that: The signal output by the output circuit is a SENT signal.

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