Linearization of digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) and related methods

Abstract

This embodiment introduces a method for designing a perfectly linear DAC using non-ideal components. This method eliminates the non-linearity of the DAC and removes the traditional trade-off between performance and complexity. One embodiment includes receiving an input digital signal, segmenting the input digital signal into multiple segments, each segment being encoded by a thermometer, generating a redundant representation of each of the multiple segments, defining multiple redundant segments, performing redundant mapping of the multiple segments, defining redundant mapped segments, assigning probability assignments to the redundant mapped segments, converting each redundant mapped segment into an analog signal by a sub-digital-to-analog converter (DAC), and combining the analog signals to define an output analog signal.

Description

Technical Field

[0001] The present invention relates to systems and methods for processing and storing digital information. Background Art

[0002] Modern electronic systems process and store information digitally. However, due to the analog nature of the world, the conversion between the analog and digital domains is always required and performed by data converters. An analog-to-digital converter (ADC) is used to convert an analog signal (voltage, current, etc.) into a digital code word. On the other hand, a digital-to-analog converter (DAC) is used to convert a digital code word into an analog signal (voltage, current, etc.).

[0003] A DAC is a device that converts a digital number in a high-precision digital format (usually a finite-length binary format number) into an analog electrical quantity such as voltage, current, or charge. To construct an analog signal signal, there are two basic types of DAC output formats: non-return-to-zero (NRZ) and return-to-zero (RZ). As shown in FIG. 1, for NRZ, the DAC updates its analog output according to its digital input at fixed time intervals of Ts and holds the output, where Ts is referred to as the update and sampling period. For RZ, after updating the output at each time interval Ts, the DAC only holds the output for a certain time (Th), and then returns to zero. In both cases, the output of the DAC is held for a certain time Th, where 0 < Th <= Ts, which is called zero-order hold. The output of the DAC is usually a stepped or pulsed analog signal and can be low-pass filtered to construct the desired analog signal, as shown in FIG. 1.

[0004] The deviation of the actual DAC output f(x) from the ideal DAC output can be characterized by the following metrics, for example: 1) offset and gain errors; 2) differential nonlinearity (DNL); 3) integral nonlinearity (INL); 4) spurious-free dynamic range (SFDR); and 5) signal-to-noise ratio (SNR).

[0005] The offset error of a DAC is defined as the deviation of the linearized transfer curve of the DAC output from the ideal zero. The linearized transfer curve is based on the actual DAC output, a simple min-max line connecting the minimum and maximum DAC output values or the best-fit line of all the output values of the DAC. Since offset and gain errors do not introduce nonlinearity, they have no effect on the spectral performance of the DAC.

[0006] Differential nonlinearity (DNL) is defined as the deviation of the actual step size from the ideal step size (LSB), known as its ideal size (1 LSB), between any two adjacent digital output codes. Therefore, DNL results in unequal step sizes in the transfer function. Integral nonlinearity (INL) is defined as the deviation of the actual DAC output from the linearized transfer curve of each code, as shown in Figure 2. INL is also described as the accumulation of previous DNL errors. To ensure monotonicity, the conditions DNL < 0.5 LSB and INL < 1 LSB must be met.

[0007] Spurious-free dynamic range (SFDR) is a measure of the nonlinearity of a DAC and is the ratio of the number of single tones that generate the highest unwanted components in the Nyquist band. SFDR is usually expressed in decibels (dB).

[0008] Signal-to-noise ratio (SNR) is defined as the ratio of the power of the measured output signal to the integrated power of the noise floor in the Nyquist band ([0, sample frequency / 2], excluding DC and harmonics). SNR values ​​are also typically expressed in decibels (dB).

[0009] Mismatches in analog circuits have an impact. Thermal noise, quantization noise, mismatch, and nonlinearity are major contributors to inaccuracies in analog circuits and impose minimum requirements on device area and power. Thermal noise is white and can benefit from averaging. Similarly, a well-designed quantizer has white quantization noise. Quantization noise also benefits from averaging and oversampling. Both thermal noise and quantization noise are expressed in dBc / Hz, which is a measure of how the noise power is distributed spectrally across the Nyquist bandwidth. For narrowband systems, thermal noise and quantization noise integrated over the receiver bandwidth are directly related to the receiver's SNR. Typically, sources of nonlinearity are input buffers, amplifiers, and output drivers, whose linearity can be modeled as low-order smoothed polynomial functions. Spurious emissions from the smoothed polynomial approximation result in predictable harmonics at multiples of the fundamental frequency. Their effects in narrowband systems can be mitigated through proper frequency planning.

[0010] Mismatch is a phenomenon where devices of the same design (resistors, capacitors, MOS transistors) are not identical. Threshold voltage difference ΔVT and current factor difference Δβ are the primary sources of device mismatch. Both ΔVT and Δβ are unknown during design but are fixed after manufacturing (and remain unknown). Anecdotal evidence and extensive measurement data suggest that mismatch generally improves with increasing device area. Therefore, quadrupling the area will reduce mismatch by 1 bit. However, adjusting the size of current-source transistors to match more than 14 bits is impractical and results in large parasitic capacitances.

[0011] Nonlinearity is primarily caused by mismatches, which can be random, systematic, or a combination of both. Mismatches can arise from differences between wafers, wafer-to-wafer differences, intra-chip differences, or differences between devices. Mismatches can be systematic (following gradients) or completely random. While systematic mismatches can often be mitigated by the choice of layout methods and circuit architecture, random mismatches due to the random nature of physical geometry and doping cannot be avoided. Furthermore, the strong temperature dependence of current sources greatly exacerbates the problem. Random mismatches lead to predictably unpredictable performance.

[0012] In analog circuits, receiver sensitivity is defined as the minimum signal that can be correctly processed in the presence of noise. Devices need to be sizing to meet RX sensitivity specifications. Increasing size negatively impacts speed and power consumption due to the larger capacitance. For a given bandwidth and accuracy, the limitation on minimum power consumption imposed by device matching is approximately two orders of magnitude larger than the limitation imposed by noise from deep submicron CMOS processes. Therefore, it is device mismatch, rather than thermal noise, that sets the limit on the minimum analog signal that can be processed.

[0013] This background information is provided to disclose information that the applicant believes may be relevant to the present invention. It is not necessarily intended, nor should it be construed, that any of the foregoing information constitutes prior art contrary to the present invention. Attached Figure Description

[0014] Figure 1 shows the curves of a typical DAC output (stepwise NRZ and RZ) and the curves obtained by applying a low-pass filter known in the art.

[0015] Figure 2 is a graph showing the differential nonlinearity and integral nonlinearity compared to the ideal transfer function known in the art.

[0016] Figure 3 is a diagram of a 3-bit binary DAC known in the art.

[0017] Figure 4 shows a 3-digit thermometer DAC comprising 7 unit elements according to an embodiment of the present invention.

[0018] Figure 5A shows two 6-bit DACs with 3 most significant bits and 3 least significant bits of a thermometer.

[0019] Figure 5B is a graph of the transfer function of the DAC in Figure 5A.

[0020] Figure 6 is the output spectrum of a Nyquist DAC with a single-tone sine wave input according to an embodiment of the present invention.

[0021] Figure 7 is the architecture of a single-ended 4-bit thermometer-encoded DAC according to an embodiment of the present invention.

[0022] Figure 8 is a differential DAC architecture for the complementary output DAC of Figure 7 according to an embodiment of the present invention.

[0023] Figure 9 is a plot of multiple analog output values ​​of a DAC according to an embodiment of the present invention.

[0024] Figure 10 is a schematic diagram of a 4-digit thermometer DEM DAC according to an embodiment of the present invention.

[0025] Figure 11 is a graph of the ideal transfer function and the linearized DEM DAC according to an embodiment of the present invention.

[0026] Figure 12 is a graph illustrating a higher resolution DAC achieved by combining the outputs of several smaller sub-DACs according to an embodiment of the present invention.

[0027] Figure 13 is a schematic diagram of the implementation of a multi-segment DAC according to an embodiment of the present invention.

[0028] Figure 14 This is a graph of the DAC transfer function with normal mapping according to an embodiment of the present invention.

[0029] Figure 15 This is a graph of the transfer function of a DAC with redundant mapping according to an embodiment of the present invention.

[0030] Figure 16 This is a graph showing the probability allocation between the DAC transfer function and various normal and redundant mappings according to an embodiment of the present invention.

[0031] Figure 17 This is a schematic diagram of a two-segment DAC with redundancy and probability mapping according to an embodiment of the present invention.

[0032] Figure 18 This is a schematic diagram illustrating the implementation of four-segment linearization using sequential pairwise operations according to an embodiment of the present invention.

[0033] Figure 19 This is the architecture of the B-bit successive approximation register ADC according to an embodiment of the present invention.

[0034] Figure 20 This is a representation of the SAR register values ​​generated from the 4-bit SAR time trellis of the DAC voltage according to an embodiment of the present invention. Detailed Implementation

[0035] The invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the invention are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Those skilled in the art will recognize that the following description of embodiments of the invention is illustrative and not intended to be limiting in any way. Other embodiments of the invention will readily come to mind for those who benefit from this disclosure. Similar numerals always refer to similar elements.

[0036] Before describing this disclosure in detail, it should be understood that this disclosure is not limited to the parameters of the specific systems, methods, apparatuses, products, processes, and / or kits illustrated herein, which can, of course, vary. It should also be understood that the terminology used herein is for the purpose of describing particular embodiments of this disclosure only and is not necessarily intended to limit the scope of this disclosure in any particular way. Therefore, although this disclosure will be described in detail with reference to specific embodiments, features, aspects, configurations, etc., the description is illustrative and should not be construed as limiting the scope of the claimed invention. Various modifications may be made to the illustrated embodiments, features, aspects, configurations, etc., without departing from the spirit and scope of the invention as defined by the claims. Therefore, although various aspects and embodiments have been disclosed herein, other aspects and embodiments are contemplated.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this art pertains. While many methods and materials similar to or equivalent to those described herein may be used in practice with respect to this disclosure, only certain exemplary materials and methods are described herein.

[0038] Various aspects of this disclosure, including apparatuses, systems, methods, etc., may be illustrated with reference to one or more exemplary embodiments or implementations. As used herein, the terms “embodiment,” “alternative embodiment,” and / or “exemplary implementation” mean “serving as an example, instance, or illustration” and are not necessarily to be construed as preferred or advantageous relative to other embodiments or implementations disclosed herein. Furthermore, references to “implementation” of this disclosure or invention include specific references to one or more embodiments thereof, and are intended to provide illustrative examples without limiting the scope of the invention, which is indicated by the appended claims rather than the following description.

[0039] It should be noted that, as used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include the plural forms unless explicitly specified otherwise. Thus, for example, a reference to “sensor” includes one, two, or more sensors.

[0040] As used throughout this application, the words “may” and “can” are used in a permissive sense (i.e., meaning possible) rather than a mandatory sense (i.e., meaning must). Additionally, the terms “comprising,” “having,” “involving,” “including,” “characterized by,” and variations thereof (e.g., “comprising,” “having,” and “involving with,” “containing,” etc.) and similar terms as used herein, including claims, should be inclusive and / or open-ended, should have the same meaning as the word “comprising” and its variations (e.g., “comprising” and “containing”), and illustratively do not exclude additional unrecorded elements or method steps.

[0041] Various aspects of this disclosure can be illustrated by describing components that are coupled, attached, connected, and / or combined. As used herein, the terms “coupled,” “attached,” “connected,” and / or “combined” are used to indicate a direct connection between two components, or, where appropriate, an indirect connection to each other via an intervening or intermediate component. In contrast, when a component is referred to as “directly coupled,” “directly attached,” “directly connected,” and / or “directly combined” to another component, no intervening element is present or anticipated. Therefore, as used herein, the terms “connected,” “connected,” etc., do not necessarily imply direct contact between two or more elements. Furthermore, components that are coupled, attached, connected, and / or combined are not necessarily fixed to each other (reversibly or permanently). For example, coupling, attaching, connecting, and / or combining may include placing, positioning, and / or setting components together or otherwise adjacent in some implementations.

[0042] As used herein, directional and / or arbitrary terms such as “top,” “bottom,” “front,” “back,” “left,” “right,” “upper,” “lower,” “upper part,” “lower part,” “inner,” “outer,” “internal,” “external,” “internal,” “external,” “proximal,” “farthest,” etc., may be used only to indicate relative direction and / or orientation and may not be intended to otherwise limit the scope of this disclosure, including the specification, invention, and / or claims.

[0043] Where possible, similar component designations are used in various figures. Additionally, similar designations can be used to designate similar components and / or components with similar functions. Furthermore, alternative configurations of specific components can each include a separate letter attached to the component number. Thus, the attached letter can be used to designate alternative designs, structures, functions, implementations, and / or embodiments of components or features without the attached letter. Similarly, multiple instances of a component and its parent component's child components can each include a separate letter attached to the component number. In each case, the component designation can be used without the attached letter to generally refer to an instance of the component or any alternative component. Component designations including the attached letter can be used to refer to a specific instance of the component or to distinguish or draw attention to multiple uses of the component. However, the inclusion of attached letters in component designations does not imply limitation to illustrating one or more specific and / or particular embodiments. In other words, references to specific features of one embodiment should not be construed as limiting application to that embodiment.

[0044] It should also be understood that, where a range of values ​​is disclosed or recorded (e.g., less than, greater than, at least and / or up to a certain value and / or between two recorded values), any specific value or range of values ​​falling within the range of the disclosed values ​​is also disclosed and anticipated herein.

[0045] It should also be noted that systems, methods, apparatuses, devices, products, processes, compositions, and / or kits, etc., according to certain embodiments of the present invention may include, incorporate, or otherwise include the properties, features, aspects, steps, components, elements, and / or components described in other embodiments disclosed and / or described herein. Therefore, references to specific features, aspects, steps, components, elements, etc., with respect to one embodiment should not be construed as limiting application to that embodiment. Furthermore, references to specific benefits, advantages, problems, solutions, methods of use, etc., with respect to one embodiment should not be construed as limiting application to that embodiment.

[0046] The headings used herein are for organizational purposes only and are not intended to limit the scope of the description or claims. For ease of understanding, similar reference numerals have been used where possible to designate similar elements common to the figures.

[0047] A typical 4-bit binary DAC architecture will be described with reference to Figure 3. In the binary architecture, each binary input bit corresponds to a binary weighted element (voltage, current, or charge). The advantages of the binary architecture are its simplicity and low implementation cost. However, a large ratio between the least important and most important elements can lead to a large mismatch between them. This results in large DNL and INL errors. One way to improve nonlinearity in a binary DAC architecture is to reduce the mismatch per unit element.

[0048] To overcome the drawbacks of binary DAC architectures, thermometer-encoded DAC architectures have been developed. A B-bit thermometer-encoded DAC has 2B-1 unit elements. For example, a 3-bit thermometer DAC with 7 unit elements is shown in Figure 4. These unit elements are turned on or off in a specific sequence according to the input digital code. Compared to binary-encoded architectures, thermometer-encoded architectures reduce INL / DNL at the cost of a significant increase in implementation cost.

[0049] In a segmented architecture, the input digital code is divided into multiple segments, and each segment is converted into an analog signal using a sub-DAC. The segments are scaled and combined to create the overall transfer function. The transfer function of a 2-segment DAC (e.g., a 6-bit DAC in Figure 5A) is shown in Figure 5B. The segmented architecture balances the advantages and disadvantages of LSB binary segments and thermometer MSB segments and is the most widely used architecture in DAC design. Unit components can be current sources, capacitors, or resistors, or combinations thereof.

[0050] The output spectrum of a Nyquist DAC with a single-tone sine wave input is shown in Figure 6. As illustrated in the figure, harmonics exist at integer multiples of the fundamental frequency and at numerous other frequency components due to the DAC's nonlinearity (INL and DNL). The amplitude and location of the DNL spurious signals are unpredictable and depend on the input amplitude and frequency. Therefore, nonlinearity can be a critical performance metric in DAC design.

[0051] Over the past few decades, much research has been dedicated to improving the nonlinear performance of DACs. It is well known that unit mismatch leads to unequal step size (DNL) in the DAC transfer function and results in spurious signals in the output spectrum. Dynamic element matching (DEM) is a well-known and widely used technique for linearizing thermometer DACs and eliminating DNL in the presence of mismatch.

[0052] For DEM, thermometer code T 1：N Let w represent a natural number, where w are 1s followed by Nw zeros. A thermometer-encoded DAC may include, or in some embodiments, consist of N identical unit elements U. 1：N The output of the DAC is composed of N thermometer codes representing the digital input word x, which can be turned on (activated) or off (deactivated). This is done in the unsigned representation x = w and the signed representation x = 2w - N. Table 1 shows an example of a 3-bit natural number thermometer representation. The outputs of the N unit elements are combined in the DAC output network.

[0053]

[0054]

[0055] Table 1: 3-digit thermometer code representation

[0056] For a thermometer code with weight w, w unit elements are turned on or off by a thermometer code representing the input x = w. The minimum output occurs when all unit elements are off, and the maximum output value occurs when all unit elements are on. Generally, the unit elements will not be identical and can be represented as U. k =U+ΔU k =U(1+∈ k ), where U is the nominal value, ΔU k It is the deviation from the nominal value, and ∈ k It is a relative mismatch ΔU k / U.

[0057] In a single-ended DAC, each thermometer code represents either '1' or '0', and each unit element is switched to either a load resistor or ground, as shown in Figure 7. Ideally, all unit elements are identical and for all k, U k =U. In the absence of mismatch, the single-ended output is given by the following formula:

[0058]

[0059] The input-output transfer function is a linear function.

[0060] For the complementary output DAC shown in Figure 8, each thermometer code represents a '1' when activated or a '-1' when deactivated, and the corresponding unit element is switched to a positive or negative load resistor. The complementary output is given by the following equation:

[0061]

[0062] Ideally, complementary outputs are also linear functions of inputs.

[0063] In a DEM, different thermometer codes with the same weight w are used to represent the consecutive occurrences of the same input in a random manner. In other words, a set of different w elements It is activated on consecutive occurrences of the same number input code. As shown in Figure 9, the same number... The input may have multiple analog output values ​​because there are (N) ways to activate w elements out of N elements. Scrambling ensures that the permutation is chosen consistently in a random manner. The overall average output of the permutation approximates and resembles a perfect linear DAC. DEM linearizes the average transfer function by decorrelating the errors in the DAC output and input. The average transfer function determines the spurious signals in the output spectrum. Although DEM causes a slight decrease in SNR, the improvement in SFDR can be very significant.

[0064] The 4-bit DEM DAC is shown in Figure 10. The 4-bit digital code is converted into a 15-bit thermometer code T.1:15 The number of elements activated by the thermometer bit is proportional to the input digital code. The thermometer code is scrambled (permutation operation), which randomizes the positions of the active elements but keeps the number of active elements constant. The scrambled thermometer code activates and deactivates the corresponding unit elements. The unit elements are combined in the DAC output network to create the output.

[0065] The average transfer function of the DEM DAC will be described. A simple combinatorial analysis shows that there are a total of There is a method to activate w elements out of N elements. This can be achieved by first calculating the probability P of activating the bit at position k. w (T k =1) and the probability P of deactivating the k-th position. w (T k =0) to find the expected output value when w unit elements are activated. For a thermometer code with weight w, we have There is a method to activate the element at position k. Since w elements always need to be activated, this is equivalent to activating an additional w-1 elements at the remaining N-1 potential positions once the k-th position is activated. Similarly, there are... One method is used to activate the element at the k-th position of the thermometer code. This is equivalent to activating w elements at N-1 potential positions after deactivating the k-th position. Therefore, the probability of activating or deactivating the k-th position can be calculated as:

[0066]

[0067] The output of the DAC is given by the following formula:

[0068]

[0069] By obtaining The expected value, average complementary output is:

[0070]

[0071] Substituting the probability P into equations (1) and (2) w (T k =1) and P w (T k =0)(found below) and note U k =U(1+∈ k Taking unit mismatch into account, we obtain:

[0072]

[0073] in

[0074]

[0075] or

[0076]

[0077] Here, α is the average mismatch of the unit element and is a constant for a given unit element mismatch profile. The average output of the DEMDAC is linearly proportional to its input x = 2w - N. The scaling factor (1 + α) is the gain error when compared to the output of an ideal DAC. The ideal and DEM transfer functions of the 3-bit DAC are shown in Figure 11. Since it is a linear system, the error is also proportional to the input. Without loss of generality, it is assumed that the unit element U is 1.

[0078] A fully thermometer-encoded DAC with DEM is always linear. A B-bit thermometer DAC requires 2 B -1 unit component. The cost and power consumption of a fully thermometer-encoded DAC increase exponentially with the number of bits. Therefore, fully thermometer implementations rarely use more than 8 bits. In a segmented DAC, the B-bit input digital word x is decomposed into bits B1, B2, ..., B... m m segments x1, x2, ..., x m Such that B = B1 + B2 + ... + B m The first sub-DAC processes the first B1 bit, the second sub-DAC processes the next B2 bit, and the m-th sub-DAC processes the last B1 bit. m Bits. A segmented DAC only requires... Each unit component. Therefore, segmentation can lead to a significant reduction in complexity. A higher resolution DAC can be achieved by combining the outputs of several smaller sub-DACs, as shown in Figure 12.

[0079] The B-digit input x is associated with the m-segment input, serving as a weighted sum of binary values:

[0080]

[0081] in, Furthermore, the output of the DAC is a weighted combination of the outputs of the m sub-DACs:

[0082]

[0083] When there is no mismatch, the output of each sub-DAC is equal to its input, and The output of an ideal DAC is equal to its B-bit digital input x:

[0084]

[0085] In a non-ideal implementation, each sub-DAC uses a DEM for linearization. The average output of the i-th sub-DAC is determined by y. i=x i ·(1+α i ) is given, where α i It is the average mismatch of the unit element in the i-th sub-DAC. The output of the DAC is given by the following formula:

[0086]

[0087] Because of α in each segment i Unlike the input x, the error term ε is not linearly related to the input x, meaning that for any k, ε... x Since x ≠ kx, the output is not a linear function of x.

[0088] In the presence of mismatch, the nonlinearity is reintroduced into the transfer function by combining the outputs of the sub-DACs after segmentation. Even if the individual thermometer segments are linearized by DEM, the outputs of the combined linear sub-DACs will not be linear. Therefore, for higher resolution DACs, the segmented architecture is a trade-off between accuracy, speed, cost, and power at the expense of nonlinearity.

[0089] The output of a DAC can also be written as:

[0090]

[0091] Each segment is scaled and combined with the segment preceding it. Therefore, it is useful to analyze the performance of a two-segment DAC in the presence of mismatch. The results can be extended to multiple segments by the nested nature of the calculations in equation (6).

[0092] In the two-segment DAC, the most significant B1 bit is associated with the first segment, and the remaining least significant B2 bits are associated with the second segment. In the presence of mismatch, the output of the linearized sub-DAC is given by y1 = x1(1 + β1) and y2 = x2(1 + β2), where βs represents the average unit element mismatch in each segment. N′2 = N2(1 + γ2) is the mismatch scaling factor, where γ2 represents the deviation from the ideal power-of-two value. The DAC output can be written as:

[0093]

[0094] Where a2 is a parameter that integrates the effects of all mismatches. (1+β1) is a gain factor that changes the full-scale range of the DAC without affecting its linearity. The transfer functions of the two DAC segments are shown in Figure 13.

[0095] The problem with bit segmentation into sub-DACs is a design trade-off between complexity and performance. While a perfectly linear DAC can be achieved using only one segment and DEM, this may be impractical for high-resolution DACs. Adding more bits to the MSB sub-DAC improves linearity but also increases complexity. This is due to inter-segment unit mismatch (β). i ≠β j and inter-segment scaling error The introduction of nonlinearity significantly reduces the benefits of using multiple thermometer segments with a DEM. Therefore, the most common topology is a two-segment DAC with a thermometer-encoded MSB segment and a binary-encoded LSB segment. Achieving a high-speed DAC with nonlinearity superior to 12 bits can be difficult.

[0096] refer to Figures 14-20 The present invention will describe systems, apparatuses and methods with features according to this embodiment.

[0097] This embodiment introduces the use of non-ideal components to design perfect linearity (zeroDNL). TM An innovative approach to DACs. This approach eliminates the nonlinearity of DACs and removes the traditional trade-offs between performance and complexity.

[0098] In a two-segment DAC, the input x is decomposed into two segments (x1, x2) and

[0099]

[0100] if

[0101]

[0102] Then (x′1, x′2) is a redundant representation of the input x.

[0103] Consider the mapping (x1, x2) → (x′1, x′2) defined as

[0104] x′1=x1+δx1·sgn(x2)

[0105] x′2=(|x2|-N2δx1)·sgn(x2) (6)

[0106] Substituting x′1 and x′2, we get

[0107]

[0108] x1 takes values ​​between -N1+1 and N1-1 with a step size of 2. By choosing δx1 = 2, the mapping (x1, x2) → x′1 is an incrementing or decrementing operation. For a 3-bit sub-DAC with N2 = 8 and N2·δx1 = 16, the mapping to x′2 is shown in Table 2. Since |x2| < N2·δx1, x2 and x′2 always have opposite signs.

[0109] <![CDATA[x2]]> -7 -7 -3 -1 1 3 5 7 <![CDATA[x′2]]> 9 11 13 15 -15 -13 -11 -9 <![CDATA[x′1]]> <![CDATA[x1-2]]> <![CDATA[x1-2]]> <![CDATA[x1-2]]> <![CDATA[x1-2]]> <![CDATA[x1+2]]> <![CDATA[x1+2]]> <![CDATA[x1+2]]> <![CDATA[x1+2]]>

[0110] Table 2: Redundancy Mapping

[0111] In the DAC output used for redundant inputs, the output of the DAC used for input x→(x1,x2) is given by the following equation:

[0112]

[0113] For the redundant representation x→(x′1,x′2), the output of the DAC is given by the following equation:

[0114]

[0115] The transfer functions of y'1400 and y'1500 are respectively in Figure 14 and Figure 15 As shown in the diagram. Clearly, in a DAC with a mismatch, y′≠y≠x, even though x′=x.

[0116] Let p be the probability of choosing representation (x1, x2), and p′ = 1 - p be the probability of choosing redundant representation (x′1, x′2). For any input x, the output of the DAC can be assumed to be either the value of y with probability p or the value of y' with probability p'. The average value of the DAC output is given by the expected value of y.

[0117]

[0118] As mentioned earlier, x2 and x′2 always have opposite polarities, therefore sgn(x′2) = -sgn(x2). Thus, a set of non-negative weights w and w' can be found such that the weighted sum w·x2 + w′·x′2 = 0. It is easy to see that by choosing w = |x′2| and w′ = |x2| and using the identity x = |x|·sgn(x), the weighted sum becomes |x2|·|x′2|·[sgn(x2) + sgn(x′2)], which is always zero. Furthermore, normalizing the weights... and This will also result in a zero-weighted sum, and w = 1 - w′.

[0119] By choosing probabilities p and p' as:

[0120]

[0121] The sum p·x² + p′·x′² is always zero and

[0122] y avg =E[y]=(1+β1)·x

[0123] Therefore, by selecting (x1, x2) with a probability of p = 1610 and (x′1, x′2) with a probability of p′ = 1620, the average output of the DAC, 1600, can be perfectly linear, as shown below. Figure 16 As shown in the diagram, the DAC errors e and e' are proportional to x² and x′². Therefore, the zero-weighted sum also results in a zero-average DAC error. Linearization is achieved through a combination of redundant mapping and probability assignment. The architecture of a two-segment DAC that achieves this linearization is shown in... Figure 17 As shown in the figure, and will be discussed below.

[0124] The probability p depends only on the value of x2 and not on the mismatch of the sub-DAC. Substituting x, we obtain:

[0125]

[0126] Table 3 shows the probabilities p and p' of the 3-bit DAC.

[0127] <![CDATA[x2]]> -7 -5 -3 -1 1 3 5 7 <![CDATA[x′2]]> 9 11 13 15 -15 -13 -11 -1 p 9 / 16 11 / 16 13 / 16 15 / 16 15 / 16 13 / 16 11 / 16 9 / 16 p′ 7 / 16 5 / 16 3 / 16 1 / 16 1 / 16 3 / 16 5 / 16 7 / 16

[0128] Table 3: The probability redundancy mapping and probability allocation of the 3-bit sub-DAC are given by the following equation:

[0129]

[0130] Pseudo-random numbers are generated using a linear feedback shift register (LFSR). The L bits in the L-bit LFSR represent "states," and for a properly designed feedback polynomial, the LFSR will sequentially cycle through 2L-1 states before repeating itself. Typically, all-zero or all-one states are not allowed. By choosing a sufficiently large L, each bit in the LFSR is assumed to be either '0' or '1' with a 1 / 2 probability. Therefore, uniformly distributed random numbers can be generated by grouping several bits of the LFSR together. For example, four bits of the LFSR together represent a uniformly distributed random integer variable R∈[0:15] with a uniform probability of 1 / 16. That is, Prob(R<1) = 1 / 16, Prob(R<3) = 3 / 16, Prob(R<5) = 5 / 16, Prob(R<7) = 7 / 16, and so on. The probability assignments of probabilities p and p′ can be achieved by correlating the selection with the result of a comparison between the random integer R and |x²| as follows:

[0131]

[0132] The peak amplitude of the input should be reduced so that binary codes consisting of all zeros and all ones are never encountered in the MSB sub-DAC. This ensures that both x1 and x′1 can be represented by B1-bit words without overflow. The range before and after mapping is given by the following equation:

[0133] x1∈[-N1+2:2:N1-2]

[0134] x′1∈[-N1+1:2:N1-1]

[0135] and

[0136] x2∈[-N2+1:2:N2-1]

[0137] x′2∈[-2N2+1:2:-N2-1]∪[N2+1:2:2N2-1]

[0138] For a 3-bit sub-DAC, such as Figure 17 As shown, x2∈[-7,-5,-3,-1,1,3,5,7| and x′2∈[-15,-13,-11,-9]∪[9,11,13,15]. Normal and redundant representations do not overlap. However, the range of x is doubled. Both x2 and x′2 can be implemented using a (B2+1)-bit DAC with 2N2-1 unit elements.

[0139] The following describes an extension to a multi-segment DAC. In an m-segment DAC, the input digital word x is decomposed into m segments x1, x2, ... x m The mapping is defined as:

[0140] x→(x1, x2, ..., x) m )

[0141] Redundancy mapping is given by the following equation:

[0142] x→(v1,v2,...,v m )

[0143] The variable is first defined as:

[0144] x k，m →(x k ,x k+1 , ..., x m )

[0145] x k,m The value is determined by the segment from k to m. That is to say:

[0146]

[0147] Based on the nested nature of the computation as defined in equation (6), redundant mappings can be performed sequentially on paired segments, starting from the last segment x. m It begins and ends in the first segment x1, as shown below.

[0148] The calculation of segment (m-1) to m is as follows:

[0149]

[0150] in

[0151]

[0152] And u m-1 These are intermediate values ​​used in the calculation.

[0153]

[0154] The calculation of segment (k-1) to k is as follows:

[0155]

[0156] in

[0157]

[0158] and

[0159]

[0160] The recursive process ends when k = 2 and v1 = u1.

[0161] Sequential pairwise operations in Figure 18 As shown in the diagram. Each intermediate segment 1810 undergoes two mappings x. k →u k →v k The first mapping 1802 serves as MSB segment 1806 and the second mapping 1804 serves as two LSB segments for 1806.

[0162] The resolution of the main MSB sub-DAC 1812 remains unchanged. However, the resolution of all other sub-DACs 1814, 1816, and 1818 increases by one bit. Based on the binary nature of the input decomposition, the unit elements of all LSB sub-DACs 1814, 1816, and 1818 add up to one LSB of the MSB sub-DAC 1812. Therefore, the increase in complexity is only equivalent to one LSB of the MSB sub-DAC 1812. For example, for a design with a 4-bit MSB sub-DAC, the increase in hardware complexity is only 6.25%.

[0163] We will now discuss the extension to the binary DAC. A B-bit binary DAC requires B binary-weighted elements. To achieve perfect linearity, the ratio between the weighted elements needs to be a power of 2. Any deviation from a power of 2 will result in DNL and INL errors.

[0164] A B-bit binary DAC can be considered as having B segments x1, x2, ..., x... B A segmented DAC. Each segment has 1 bit, where x i The values ​​can be -1 or 1. A B-digit input x can be represented as x i The weighted sum of binary numbers:

[0165]

[0166] The output of the DAC can be expressed as follows:

[0167]

[0168] In cases where the outcome is not ideal Where α i This is the ratio error of segment i. The output of the DAC is given by the following formula:

[0169]

[0170] In the zeroDNL implementation, each 1-bit segment is replaced by a 2-bit thermometer-encoded segment. There are segments B: v1, v2, ... v B Each segment comprises, or may alternatively consist of, three unit elements, where v i Values ​​are -3, -1, 1, and 3. Segments v1, v2, ... v B It can be obtained from the last segment v b The initial recursive process is determined as follows.

[0171] The calculation from segment (B-1) to B is as follows:

[0172]

[0173] in

[0174]

[0175] And u B-1 The intermediate value used in the next calculation:

[0176]

[0177] The calculation of segment (k-1) to k is as follows:

[0178]

[0179] in

[0180]

[0181] And u k-1 The intermediate value used in the next replacement:

[0182] x′ k-1 =x k-1 +2·sgn(u k +v k+1，B )

[0183] u′ k =u k -4·sgn(u k +v k+1，B )

[0184]

[0185] When k = 2 and v k-1 =u k-1 When the recursive process ends.

[0186] In summary: 1) Redundancy mapping probability allocation results in a perfectly linear DAC; 2) Linearization is independent of component mismatch, and the DAC is designed to be linear. Therefore, no information about mismatch is needed. However, mismatch is converted into random noise, which is uniformly distributed across the Nyquist band; 3) Linearization is feedforward and occurs in the digital domain; and 4) Linearity is maintained under process, temperature, and voltage variations.

[0187] This embodiment includes the application of a successive approximation register (SAR) ADC. SAR ADCs represent a significant portion of the medium-to-high resolution ADC market. Typical resolutions range from 10 to 18 bits, with speeds up to 20 MS / s. The SAR architecture results in low power consumption and a small footprint, making it the preferred architecture for a variety of applications. Recently, lower-resolution time-interleaved SAR has led to highly efficient multi-gigasample ADCs.

[0188] B-bit flash ADCs use a linear voltage ladder with comparators at each of the N "steps" to simultaneously compare the input voltage with a set of equally spaced reference voltages. The outputs of these comparators are fed to a digital encoder that generates binary values. The flash architecture is a highly parallel architecture with a fast conversion time of one cycle. The main drawback is that complexity increases exponentially with the number of bits, as a B-bit ADC requires N reference voltages and N comparators.

[0189] At the other end of the spectrum is a digital ramp (counter) B-bit ADC that takes up to N cycles for conversion. The ramp counter increments by one LSB with each count. The B-bit count drives the DAC, whose output is compared to the analog input. The counting process terminates when the DAC output exceeds the analog input. While this architecture is highly sequential and requires only one comparator and DAC, its sequential nature causes the conversion rate of a high-resolution ADC to slow down exponentially.

[0190] The basic architecture of the B-position SAR ADC, an improvement over the digital ramp ADC, is as follows: Figure 19 As shown in the diagram, the analog input voltage Vin 1902 is sampled and held for 1904 during the conversion duration. The decision-oriented search algorithm 1908 sequentially selects the B-bit digital input 1910 that drives the output 1912 of DAC 1904 to the value closest to the input voltage Vin. It is well known that the binary search algorithm is likely the most efficient search, finding the closest code in B = log2(N) steps.

[0191] The successive approximation register is initialized so that only the most significant bit (MSB) is equal to the digit 1. This code is then fed to the DAC, which converts the digital code into its analog equivalent. The analog voltage is supplied to the comparator for comparison with the sampled input voltage. If the analog voltage exceeds Vin, the comparator resets the bit on the SAR; otherwise, the bit remains 1. The next bit is then set to 1, and the analog equivalent of the digital code supplied by the DAC is... like Figure 20 As shown in the diagram. Therefore, in each cycle, the ADC compares Vin with the most recent simulated estimate and guides the search based on the polarity of the comparison. The binary search continues until every bit in the SAR has been used. The resulting code is a digital approximation of the sampled input voltage.

[0192] Two key components of a SAR ADC are the comparator and the DAC. The sample-and-hold block can often be embedded in the DAC (e.g., in a capacitor DAC) and may not be explicit circuitry. Noise in the comparator can be considered white and is not a source of nonlinearity. However, without amplification, the comparator needs to maintain B-bit accuracy, so the input reference noise of the comparator is designed to be less than LSB.

[0193] SAR creates a “virtual” voltage reference ladder, where each voltage step is generated sequentially via a DAC. If the voltages generated by the DAC are not spaced out consistently, this results in unequal step sizes (or bins), and the signal is non-uniformly quantized. DNL is a measure of the difference between each step size and the nominal step size.

[0194] Typically, the DAC output is monitored as a function of time, and all possible trajectories are mapped. These trajectories form a "time trellis," as shown below. Figure 20 As shown in the diagram. The final stage of this time trellis may include, or in some embodiments, consist of a set of voltages that are uniformly spaced across the input voltage range. The linearity of the ADC is a function of how accurately the DAC can generate this set of equally spaced voltages. Therefore, the linearity of the ADC is determined solely by the linearity of the DAC.

[0195] If the DAC unit component size is determined by matching linearity requirements rather than thermal noise, high-resolution SAR ADCs tend to occupy a large area. Due to constraints on component matching (capacitors, resistors, current sources), high-resolution SAR DACs require trimming. However, trimming cannot compensate for changes in voltage and temperature. Therefore, continuous online calibration is necessary during normal operation.

[0196] A DAC employing a zeroDNL architecture with redundant mapping and probability allocation can be perfectly linear. Therefore, a zeroDNL DAC generates a set of reference voltages that are consistently spaced, resulting in a perfectly linear ADC. The zeroDNL architecture also continuously maintains linearity across process, temperature, and voltage variations.

[0197] Components may be implemented by one or more processors or computers. It is clear that the systems and / or methods described herein can be implemented in various forms of hardware, firmware, or a combination of hardware and software. The actual specialized control hardware or software code used to implement these systems and / or methods is not limiting in its implementation. Therefore, this document describes the operation and behavior of the systems and / or methods without reference to specific software code—it is understood that software and hardware can be designed to implement the systems and / or methods based on the description herein.

[0198] As may also be used herein, the terms “processor,” “module,” “processing circuitry,” and / or “processing unit” (e.g., including various modules and / or circuit systems, such as those operable, implemented, and / or used for encoding, decoding, baseband processing, etc.) can be a single processing device or multiple processing devices. Such a processing device can be a microprocessor, microcontroller, digital signal processor, microcomputer, central processing unit, field-programmable gate array, programmable logic device, state machine, logic circuit system, analog circuit system, digital circuit system, and / or any device that manipulates signals (analog and / or digital) based on hard-coded and / or operational instructions of the circuit system. Processing modules, modules, processing circuitry, and / or processing units can have associated memory and / or integrated memory elements, which can be a single memory device, multiple memory devices, and / or an embedded circuit system of processing modules, modules, processing circuitry, and / or processing units. Such memory devices can be read-only memory (ROM), random access memory (RAM), volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and / or any device storing digital information. Note that if the processing module, module, processing circuit, and / or processing unit includes more than one processing device, the processing device can be centrally located (e.g., directly coupled together via a wired and / or wireless bus structure) or distributed (e.g., via a local area network and / or a wide area network via indirectly coupled cloud computing). Also note that if the processing module, module, processing circuit, and / or processing unit implements one or more of its functions via a state machine, analog circuit system, digital circuit system, and / or logic circuit system, then the memory and / or memory element storing the corresponding operation instructions can be embedded inside or outside the circuit system, analog circuit system, digital circuit system, and / or logic circuit system including the state machine. It should still be further noted that the memory element can store, and the processing module, module, processing circuit, and / or processing unit executes, hard-coded and / or operation instructions corresponding to at least some of the steps and / or functions shown in one or more figures. Such a memory device or memory element can be included in the article of manufacture.

[0199] The invention has been described above by way of method steps illustrating the execution of specified functions and their relationships. For ease of description, the boundaries and sequences of these functional building blocks and method steps have been arbitrarily defined herein. Alternative boundaries and sequences can be defined as long as the specified functions and relationships are properly performed. Therefore, any such alternative boundaries or sequences are within the scope and spirit of the claimed invention. Furthermore, for ease of description, the boundaries of these functional building blocks have been arbitrarily defined. Alternative boundaries can be defined as long as certain important functions are properly performed. Similarly, flowchart blocks have also been arbitrarily defined herein to illustrate certain important functions. Within the scope used, flowchart block boundaries and sequences can be defined in other ways and still perform certain important functions. Therefore, such alternative definitions of both functional building blocks and flowchart blocks and sequences are also within the scope and spirit of the claimed invention. Those skilled in the art will also recognize that functional building blocks and other illustrative blocks, modules, and components herein can be implemented as shown or by discrete components, application-specific integrated circuits, processors executing suitable software, or combinations thereof.

[0200] The invention may also be described at least in part in terms of one or more embodiments. Embodiments of the invention are used herein to illustrate the invention, its aspects, its features, its concepts, and / or examples thereof. Physical embodiments of the apparatus, articles of manufacture, machines, and / or processes for implementing the invention may include one or more aspects, features, concepts, examples, etc., described with reference to one or more embodiments discussed herein. Furthermore, from figure to figure, embodiments may incorporate functions, steps, modules, etc., with the same or similar names that may be used with the same or different reference numerals, and such functions, steps, modules, etc., may be the same or similar functions, steps, modules, etc., or may be different.

[0201] The above description provides specific details, such as material types and processing conditions, to provide a thorough description of the exemplary embodiments. However, those skilled in the art will understand that the embodiments can be practiced without using these specific details.

[0202] Some illustrative aspects of the invention may be helpful in solving the problems described herein and other undiscussed problems that may be discovered by those skilled in the art. While the above description contains multiple specificities, these should not be construed as limiting the scope of any embodiment, but rather as illustrative examples of the embodiments presented. Many other consequences and variations are possible within the teachings of the various embodiments. Although the invention has been described with reference to exemplary embodiments, those skilled in the art will understand that various changes can be made and equivalents can be substituted for its elements without departing from the scope of the invention. In addition, many modifications can be made to adapt particular situations or materials to the teachings of the invention without departing from its basic scope. Therefore, it is intended that the invention be limited to the specific embodiments best disclosed or the only modes contemplated for carrying out the invention, but that the invention will include all embodiments falling within the scope of the appended claims. Furthermore, exemplary embodiments of the invention have been disclosed in the drawings and description, and although specific terminology may have been used, they are used only in a general and descriptive sense and not for limiting purposes unless otherwise stated, and therefore the scope of the invention is not limited thereto. Moreover, the use of the terms first, second, etc., does not indicate any order or importance, but rather the terms first, second, etc., are used to distinguish one element from another. Furthermore, the use of the terms "one," "an," etc., does not imply a limitation on quantity, but rather indicates the presence of at least one referenced item. Therefore, the scope of the invention should be determined by the appended claims and their legal equivalents, rather than by the examples given.

Claims

1. A method for linearizing digital-to-analog conversion, comprising: Receive input digital signals; The input digital signal is segmented into multiple segments, and each segment is encoded by a thermometer. Generate a redundant representation for each of the multiple segments, and define multiple redundant segments; Perform redundancy mapping on the multiple segments and define redundant mapping segments; Assign probability allocations to redundant mapping segments; Each redundant mapped segment is converted into an analog signal by a digital-to-analog converter (DAC); and Combine the analog signals to define the output analog signal; in: The plurality of segments includes m segments, and the first segment x1, the second segment x2 to the m-th segment x m The sum of these values ​​equals the input digital signal, as shown in the following equation. Where N i It is able to provide for segment x i The number of associated sub-DAC activated components; The redundant mapping of the input digital signal includes m segments, from the first segment v1, the second segment v2 to the mth segment v m The sum of these values ​​equals the input digital signal, as shown in the following equation. Make at least one segment x i The value is not equal to the mapping v i A redundant mapping, where i has integer values ​​between 1 and m.

2. The method of claim 1, wherein performing the redundancy mapping comprises sequentially performing a recursive redundancy mapping on segment pairs for each of the plurality of segments and the plurality of redundant segments.

3. The method of claim 2, wherein performing the recursive redundancy mapping comprises: Calculate the first pair (x) m x m-1 Redundant mapping (x′) m , x′ m-1 ); According to x m and x′ m Determine the m-th segment v m The final value; According to x m-1 and x′ m-1 Determine the intermediate value u m-1 ; Calculate the intermediate pair (u) m-1 x m-2 Redundant mapping (u′) m-1 , x′ m-2 ); According to u m-1 and u′ m-1 Determine the (m-1)th segment v m-1 The final value, and according to x m-2 and x′ m-2 Determine the intermediate value u m-2 ; as well as Recursively compute the redundant mapping of intermediate pairs and their intermediate values ​​until x. m-n =x1.

4. The method of claim 3, wherein x (k，m) The variables are determined by segments k to m and are defined by the following formula. Where N k It is able to provide for segment x k The number of associated sub-DAC activated elements; where the recursive computation of redundant mappings is performed from the last segment x. m The execution proceeds sequentially up to the first segment x1; where segments m–1 to m are defined as... Where (u m-1 , v m ) is defined as Where x′ m-1 Defined as x′ m-1 =x m-1 +δx m-1 ·sgn(x m ) Where x′ m Defined as x′ m =x m -N m ·δx m-1 ·sgn(x m ) Where N m It is able to provide for segment x m The number of associated sub-DAC activated elements, and furthermore, where p′ m-1 and p m-1 Defined as The segment from k–1 to k is defined as Where (u k-1 , v k ) is defined as Where x′ k-1 Defined as x′ k-1 =x k-1 +δx k-1 ·sgn(x k,m ) Where u′ k Defined as u′ k =u k -N k ·δx k-1 ·sgn(x k，m ) Where N k It is able to be used for segment u k The number of associated sub-DAC activated elements, and furthermore, where p′ k-1 and p k-1 Defined as Redundancy mapping is completed when k = 2 and v1 = u1.

5. The method according to claim 3, wherein, Each sub-DAC associated with the intermediate segment pair has a resolution one bit greater than the resolution of the sub-DAC of the first segment pair.

6. A system for linearizing analog-to-digital conversion, comprising: The comparator is configured to receive an analog signal as its first input; The successive approximation register is positioned to receive the output of the comparator as input and is configured to generate an output including B bits. and The digital-to-analog converter (DAC) is configured as follows: Receive input digital signals; The input digital signal is segmented into multiple segments, and each segment is encoded by a thermometer. Generate a redundant representation for each of the multiple segments, and define multiple redundant segments; Perform redundancy mapping on the multiple segments and define redundant mapping segments; Assign probability allocations to the redundant mapping segments; Each redundant mapped segment is converted into an analog signal by a sub-digital-to-analog converter; and Combine the analog signals to define the output analog signal. The comparator is configured to receive a combined analog signal as a second input; in: The plurality of segments includes m segments, from the first segment x1, the second segment x2 to the mth segment x... m The sum of these values ​​equals the input digital signal, as shown in the following equation. Where N i It is able to provide for segment x i The number of associated sub-DAC activated components; The redundant mapping of the input digital signal includes m segments, from the first segment v1, the second segment v2 to the mth segment v m The sum of these values ​​equals the input digital signal, as shown in the following equation. Make at least one segment x i The value is not equal to the mapping v i A redundant mapping, where i has integer values ​​between 1 and m.

7. The system according to claim 6, wherein, Performing the redundancy mapping involves sequentially performing a recursive redundancy mapping on each of the plurality of segments and the plurality of redundant segments on the segment pairs.

8. The system of claim 7, wherein performing the recursive redundancy mapping comprises: Calculate the first pair (x) m x m-1 Redundant mapping (x′) m , x′ m-1 ); According to x m and x′ m Determine the m-th segment v m The final value; According to x m-1 and x′ m-1 Determine the intermediate value u m-1 ; Calculate the intermediate pair (u) m-1 x m-2 Redundant mapping (u′) m-1 , x′ m-2 ); According to u m-1 and u′ m-1 Determine the (m-1)th segment v m-1 The final value, and according to x m-2 and x′ m-2 Determine the intermediate value u m-2 ; as well as Recursively compute the redundant mapping of intermediate pairs and their intermediate values ​​until x. m-n =x1.

9. The system according to claim 8, wherein x (k，m) The variables are determined by segments k to m and are defined by the following formula. Where N k It is able to provide for segment x k The number of associated sub-DAC activated elements; where the recursive computation of redundant mappings is performed from the last segment x. m The execution proceeds sequentially up to the first segment x1; where segments m–1 to m are defined as... Where (u m-1 , v m ) is defined as Where x′ m-1 Defined as x′ m-1 =x m-1 +δx m-1 ·sgn(x m ) Where x′ m Defined as x′ m =x m -N m ·δx m-1 ·sgn(x m ) Where N m It is able to provide for segment x m The number of associated sub-DAC activated elements, and furthermore, where p′ m-1 and p m-1 Defined as The segment from k–1 to k is defined as Where (u k-1 , v k ) is defined as Where x′ k-1 Defined as x′ k-1 =x k-1 +δx k-1 ·sgn(x k，m ) Where u′ k Defined as u′ k =v k -N k ·δx k-1 ·sgn(x k，m ) Where N k It is able to be used for segment u k The number of associated sub-DAC activated elements, and furthermore, where p′ k-1 and p k-1 Defined as Redundancy mapping is completed when k = 2 and v1 = u1.

10. A method for linearizing digital-to-analog conversion, comprising: Receive input digital signals; The input digital signal is segmented into multiple segments, and each segment is encoded by a thermometer. Generate a redundant representation for each of the multiple segments, and define multiple redundant segments; Perform redundancy mapping on the multiple segments and define redundant mapping segments; Assign probability allocations to redundant mapping segments; Each redundant mapped segment is converted into an analog signal by a digital-to-analog converter (DAC); and Combine the analog signals to define the output analog signal; Each of the plurality of segments x n The value is within the range defined by the following formula. x n ∈[-N n +2:2:N n -2] Where N n It is able to provide for segment x n The number of associated sub-DAC activated components; Among them, segment x n Redundant representation of x′ n It has values ​​within the range defined by the following formula. x′ n ∈[-N n +1:2:n-1] Among them, segment x n The mapping x p It has values ​​within the range defined by the following formula. x p ∈[-N p +1:2:N p -1]; as well as Among them, the redundant segment x′ n The mapping x′ p It has values ​​within the range defined by the following formula. x′ p ∈[-2N p +1:2:-N p -1]∪[N p +1:2:2N p -1]。 11. A method for linearizing digital-to-analog conversion, comprising: Receive input digital signals; The input digital signal is segmented into multiple segments, and each segment is encoded by a thermometer. Generate a redundant representation for each of the multiple segments, and define multiple redundant segments; Perform redundancy mapping on the multiple segments and define redundant mapping segments; Assign probability allocations to redundant mapping segments; Each redundant mapped segment is converted into an analog signal by a digital-to-analog converter (DAC); and Combine the analog signals to define the output analog signal; The plurality of segments includes B segments, from the first segment x1, the second segment x2 to the Bth segment x. B The sum equals the input digital signal; wherein each segment includes three elements capable of activating each sub-DAC; wherein each segment has a value of -3, -1, 1, or 3; and wherein performing the redundancy mapping includes: Calculate the first pair (x) B x B-1 Redundant mapping (x′) B , x′ B-1 ); According to x B and x′ B Determine segment B v B The final value; According to x B-1 and x′ B-1 Determine the intermediate value u B-1 ; Calculate the intermediate pair (u) B-1 x B-2 Redundant mapping (x′) B-1 , x′ B-2 ); According to u B-1 and u′ B-1 Determine the (B-1)th segment v B-1 The final value, and according to x B-2 and x′ B-2 Determine the intermediate value u B-2 ;as well as Recursively compute the redundant mapping of intermediate pairs and their intermediate values ​​until x. B-n =x1.

12. The method of claim 11, wherein the variable x (k，m) Determined from segment k to B and defined by the following formula Where N k It is able to provide for segment x k The number of associated sub-DAC activated elements; where the recursive computation of redundant mappings is performed from the last segment x. B The execution proceeds sequentially up to the first segment x1; where segment B–1 to B is defined as... (x B-1 ,x B )→(u B-1 ,v B ) Where (u B-1 ,v B ) is defined as Where x′ B-1 Defined as x′ B-1 =x B-1 +2·sgn(x B ) Where x′ B Defined as x′ B =x B -4·sgn(x B ) Where p′ B-1 and p B-1 Defined as The segment from k–1 to k is defined as Where (u k-1 , v k ) is defined as Where x′ k-1 Defined as x′ k-1 =x k-1 +2·sgn(u k +v k+1，B ) Where u′ k Defined as u′ k =u k -4·sgn(u k +v k+1，B ) Where p′ k-1 and p k-1 Defined as Where k = 2 and v k-1 =u k-1 Redundancy mapping is completed in time.

13. A method for linearizing digital-to-analog conversion, comprising: Receive input digital signals; The input digital signal is segmented into multiple segments, and each segment is encoded by a thermometer. Generate a redundant representation for each of the multiple segments, and define multiple redundant segments; Perform redundancy mapping on the multiple segments and define redundant mapping segments; Assign probability allocations to redundant mapping segments; Each redundant mapped segment is converted into an analog signal by a digital-to-analog converter (DAC); and Combine the analog signals to define the output analog signal; The plurality of segments includes m segments, wherein each of the plurality of segments includes a plurality of bits B; wherein segment x n B n log2N n Least significant bit and segment x n-1 B n-1 log2N n-1 Most significant bit overlap, where N is the number of bits that can overlap with segment x. n The number of associated sub-DAC activated elements; and wherein performing the redundancy mapping includes: Calculate the first pair (x) m x m-1 Redundant mapping (x′) m , x′ m-1 ); According to x m and x′ m Determine the m-th segment v m The final value; According to x m-1 and x′ m-1 Determine the intermediate value u m-1 ; Calculate the intermediate pair (u) m-1 x m-2 Redundant mapping (u′) m-1 , x′ m-2 ); According to u m-1 and u′ m-1 Determine the (m-1)th segment v m-1 The final value, and according to x m-2 and x′ m-2 Determine the intermediate value u m-2 ;as well as Recursively compute the redundant mapping of intermediate pairs and their intermediate values ​​until x. m-n =x1.

14. A method for linearizing digital-to-analog conversion, comprising: Receive input digital signals; The input digital signal is segmented into multiple segments, and each segment is encoded by a thermometer. Generate a redundant representation for each of the multiple segments, and define multiple redundant segments; Perform redundancy mapping on the multiple segments and define redundant mapping segments; Assign probability allocations to redundant mapping segments; Each redundant mapped segment is converted into an analog signal by a digital-to-analog converter (DAC); and Combine the analog signals to define the output analog signal; Among them, based on the absolute value of the redundant mapping segment, the number of elements that can be activated for the sub-DAC associated with the redundant mapping segment, and the next segment x n-1 Determine the redundant mapping segment x n The probability allocation.

15. The method of claim 14, wherein the probability function is defined as Where p′ m-1 It is a redundant representation of x′ m-1 The probability assignment of redundant mappings, p m-1 It is a segment x m-1 The probability assignment of redundant mappings, and N m It is able to be with x m The number of elements activated by the associated sub-DAC.

16. A system for linearizing analog-to-digital conversion, comprising: The comparator is configured to receive an analog signal as its first input; The successive approximation register is positioned to receive the output of the comparator as input and is configured to generate an output including B bits. and The digital-to-analog converter (DAC) is configured as follows: Receive input digital signals; The input digital signal is segmented into multiple segments, and each segment is encoded by a thermometer. Generate a redundant representation for each of the multiple segments, and define multiple redundant segments; Perform redundancy mapping on the multiple segments and define redundant mapping segments; Assign probability allocations to the redundant mapping segments; Each redundant mapped segment is converted into an analog signal by a sub-digital-to-analog converter; and Combine the analog signals to define the output analog signal. The comparator is configured to receive a combined analog signal as a second input; each of the plurality of segments x m The value is within the range defined by the following formula. x n ∈[-N n +2:2:N n -2] Where N n It is able to provide for segment x n The number of associated sub-DAC activated components; Among them, segment x n Redundant representation of x′ n It has values ​​within the range defined by the following formula. x′ n ∈[-N n +1:2:n-1] Among them, segment x n The mapping x p It has values ​​within the range defined by the following formula. x p ∈[-N p +1:2:N p -1]; as well as Among them, the redundant segment x′ n The mapping x′ p It has values ​​within the range defined by the following formula. x′ p ∈[-2N p +1:2:-N p -1]∪[N p +1:2:2N p -1]。 17. A system for linearizing analog-to-digital conversion, comprising: The comparator is configured to receive an analog signal as its first input; The successive approximation register is positioned to receive the output of the comparator as input and is configured to generate an output including B bits. and The digital-to-analog converter (DAC) is configured as follows: Receive input digital signals; The input digital signal is segmented into multiple segments, and each segment is encoded by a thermometer. Generate a redundant representation for each of the multiple segments, and define multiple redundant segments; Perform redundancy mapping on the multiple segments and define redundant mapping segments; Assign probability allocations to the redundant mapping segments; Each redundant mapped segment is converted into an analog signal by a sub-digital-to-analog converter; and Combine the analog signals to define the output analog signal. The comparator is configured to receive a combined analog signal as a second input; the plurality of segments includes B segments, from segment x1, segment x2 to segment xB. B The sum equals the input digital signal; wherein each segment includes three elements capable of activating each sub-DAC; wherein each segment has a value of -3, -1, 1, or 3; and wherein performing the redundancy mapping includes: Calculate the first pair (x) B x B-1 Redundant mapping (x′) B , x′ B-1 ); According to x B and x′ B Determine segment B v B The final value; According to x B-1 and x′ B-1 Determine the intermediate value u B-1 ; Calculate the intermediate pair (u) B-1 x B-2 Redundant mapping (u′) B-1 , x′ B-2 ); According to u B-1 and u′ B-1 Determine the (B-1)th segment v B-1 The final value, and according to x B-2 and x′ B-2 Determine the intermediate value u B-2 ;as well as Recursively compute the redundant mapping of intermediate pairs and their intermediate values ​​until x. B-n =x1.

18. The system of claim 17, wherein the variable x (k，m) Determined from segment k to B and defined by the following formula Where N k It is able to provide for segment x k The number of associated sub-DAC activated elements; where the recursive computation of redundant mappings is performed from the last segment x. B The execution proceeds sequentially up to the first segment x1; where segment B–1 to B is defined as... (x B-1 ,x B )→(u B-1 ,v B ) Where (u B-1 ,v B ) is defined as Where x′ B-1 Defined as x′ B-1 =x B-1 +2·sgn(x B ) Where x′ B Defined as x′ B =x B -4·sgn(x B ) Where p′ B-1 and p B-1 Defined as The segment from k–1 to k is defined as Where (u k-1 , v k ) is defined as Where x′ k-1 Defined as x′ k-1 =x k-1 +2·sgn(u k +v k+1，B ) Where u′ k Defined as u′ k =u k -4·sgn(u k +v k+1，B ) Where p′ k-1 and p k-1 Defined as Where k = 2 and v k-1 =u k-1 Redundancy mapping is completed in time.

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