Data processing device, method and related products

Abstract

The present disclosure relates to a data processing device and method and related products, which include a board. The board includes: a storage device, an interface device, a control device and an artificial intelligence chip including the data processing device in the present disclosure; wherein the artificial intelligence chip is connected to the storage device, the control device and the interface device respectively; the storage device is used to store data; the interface device is used to realize data transmission between the artificial intelligence chip and an external device; the control device is used to monitor the status of the artificial intelligence chip. Through the above method, the present disclosure can improve the computing efficiency of related products when performing operations on neural network models.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data processing device and method and related products. Background Art

[0002] With the continuous development of artificial intelligence technology, the amount of data and data dimensions that need to be processed are constantly increasing. In related technologies, the processor usually determines the data address by obtaining the parameters of the instruction, and then completes the reading and use of the data according to the data address. This requires technicians to set the relevant parameters of data access (such as the relationship between data or data dimensions, etc.) when designing parameters, so as to generate instructions and pass them to the processor to complete data access. This method reduces the processing efficiency of the processor. Summary of the invention

[0003] In view of this, the present disclosure proposes a data processing device and method and related products.

[0004] According to one aspect of the present disclosure, a data processing device is provided, the device comprising a control circuit, a descriptor parsing circuit, and an execution circuit.

[0005] The control circuit is configured to decode the received processing instruction to obtain an operation code and an operand in the decoded processing instruction, and the operand includes a first content of a first descriptor, and the first content of the first descriptor is used to indicate a shape of a tensor;

[0006] The descriptor parsing circuit is configured to determine a data address of data corresponding to the operand in a data storage space according to the first content;

[0007] The execution circuit is configured to execute the processing instruction according to the data address and the operation code.

[0008] According to another aspect of the present disclosure, a data processing method is provided, the method being applied to a data processing device, the method comprising:

[0009] Decoding the received processing instruction to obtain an operation code and an operand in the decoded processing instruction, wherein the operand includes a first content of a first descriptor, and the first content of the first descriptor is used to indicate a shape of a tensor;

[0010] Determine, according to the first content, a data address of the data corresponding to the operand in the data storage space;

[0011] The processing instruction is executed according to the data address and the operation code.

[0012] According to another aspect of the present disclosure, an artificial intelligence chip is provided, wherein the artificial intelligence chip includes the data processing device as described above.

[0013] According to another aspect of the present disclosure, an electronic device is provided, comprising the artificial intelligence chip as described above.

[0014] According to another aspect of the present disclosure, there is provided a board card, the board card comprising: a storage device, an interface device and a control device and the above-mentioned artificial intelligence chip;

[0015] Wherein, the artificial intelligence chip is connected to the storage device, the control device and the interface device respectively;

[0016] The storage device is used to store data;

[0017] The interface device is used to realize data transmission between the artificial intelligence chip and external equipment;

[0018] The control device is used to monitor the status of the artificial intelligence chip.

[0019] According to an embodiment of the present disclosure, a control circuit parses the contents of a descriptor in an operand of a processing instruction, a descriptor parsing circuit parses the contents of a mechanical descriptor to obtain a data address of data corresponding to the operand, and an execution circuit executes the processing instruction according to the parsed data address, so that the operand can be obtained through the descriptor when the processing instruction is executed, thereby reducing the complexity of data access, resolving the data IO bottleneck of the processor, and improving the data transmission and access efficiency of the processor.

[0020] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0022] Figure 1 A schematic diagram showing a data storage space of a data processing device according to an embodiment of the present disclosure.

[0023] Figure 2 A block diagram of a data processing device according to an embodiment of the present disclosure is shown.

[0024] Figure 3 A flow chart of a data processing method according to an embodiment of the present disclosure is shown.

[0025] Figure 4 A structural block diagram of a board according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0026] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0027] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0028] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0029] In one possible implementation, a descriptor can be used to indicate the shape of N-dimensional tensor data, where N is a positive integer, such as N=1, 2, or 3. A tensor can contain multiple forms of data composition, and a tensor can be of different dimensions. For example, a scalar can be regarded as a 0-dimensional tensor, a vector can be regarded as a 1-dimensional tensor, and a matrix can be a 2-dimensional or higher tensor. The shape of a tensor includes information such as the dimension of the tensor and the size of each dimension of the tensor. For example, for a tensor:

[0030]

[0031] The shape of the tensor can be described by the descriptor as (2, 4), that is, the two parameters indicate that the tensor is a two-dimensional tensor, and the size of the first dimension (column) of the tensor is 2, and the size of the second dimension (row) is 4. It should be noted that the present application does not limit the way in which the descriptor indicates the shape of the tensor.

[0032] In one possible implementation, the value of N can be determined according to the dimension (order) of the tensor data, or it can be set according to the usage requirements of the tensor data. For example, when the value of N is 3, the tensor data is three-dimensional tensor data, and the descriptor can be used to indicate the shape of the three-dimensional tensor data in three dimensions (e.g., offset, size, etc.). It should be understood that those skilled in the art can set the value of N according to actual needs, and the present disclosure does not limit this.

[0033] In a possible implementation, the descriptor may include an identifier of the descriptor and / or content of the descriptor. The identifier of the descriptor is used to distinguish the descriptor, for example, the identifier of the descriptor may be a number for it; the content of the descriptor may include at least one shape parameter representing the shape of the tensor data. For example, the tensor data is 3D data, and among the three dimensions of the tensor data, the shape parameters of two dimensions are fixed, and the content of its descriptor may include the shape parameter representing another dimension of the tensor data.

[0034] In one possible implementation, the identifier and / or content of the descriptor may be stored in a descriptor storage space (internal memory), such as a register, an on-chip SRAM, or other media cache. The tensor data indicated by the descriptor may be stored in a data storage space (internal memory or external memory), such as an on-chip cache or an off-chip memory. The present disclosure does not limit the specific locations of the descriptor storage space and the data storage space.

[0035] In one possible implementation, the identifier, content, and tensor data indicated by the descriptor of the descriptor can be stored in the same area of ​​the internal memory. For example, a continuous area of ​​the on-chip cache can be used to store the relevant content of the descriptor, and its address is ADDR0-ADDR1023, wherein the address ADDR0-ADDR63 can be used as a descriptor storage space to store the identifier and content of the descriptor, and the address ADDR64-ADDR1023 can be used as a data storage space to store the tensor data indicated by the descriptor. In the descriptor storage space, the identifier of the descriptor can be stored at address ADDR0-ADDR31, and the content of the descriptor can be stored at address ADDR32-ADDR63. It should be understood that the address ADDR is not limited to 1 bit or one byte, and is used here to represent an address, which is an address unit. Those skilled in the art can determine the descriptor storage space, data storage space, and their specific addresses according to actual conditions, and the present disclosure is not limited to this.

[0036] In one possible implementation, the identifier and content of the descriptor and the tensor data indicated by the descriptor can be stored in different areas of the internal memory. For example, a register can be used as a descriptor storage space to store the identifier and content of the descriptor, and an on-chip cache can be used as a data storage space to store the tensor data indicated by the descriptor.

[0037] In one possible implementation, when a register is used to store the identifier and content of a descriptor, the identifier of the descriptor may be represented by the register number. For example, when the register number is 0, the identifier of the descriptor stored therein is set to 0. When the descriptor in the register is valid, an area may be allocated in the cache space for storing the tensor data according to the size of the tensor data indicated by the descriptor.

[0038] In one possible implementation, the identifier and content of the descriptor may be stored in an internal memory, and the tensor data indicated by the descriptor may be stored in an external memory. For example, the identifier and content of the descriptor may be stored on-chip, and the tensor data indicated by the descriptor may be stored off-chip.

[0039] In one possible implementation, the data address of the data storage space corresponding to each descriptor may be a fixed address. For example, a separate data storage space may be divided for tensor data, and the starting address of each tensor data in the data storage space corresponds to the descriptor one by one. In this case, the execution circuit can determine the data address of the data corresponding to the operand in the data storage space according to the descriptor, and then execute the processing instruction.

[0040] In one possible implementation, when the data address of the data storage space corresponding to the descriptor is a variable address, the descriptor can also be used to indicate the address of N-dimensional tensor data, wherein the content of the descriptor may also include at least one address parameter representing the address of the tensor data. For example, the tensor data is 3D data, and when the descriptor points to the address of the tensor data, the content of the descriptor may include an address parameter representing the address of the tensor data, such as the starting physical address of the tensor data, or may include multiple address parameters of the address of the tensor data, such as the starting address + address offset of the tensor data, or the address parameters of the tensor data based on each dimension. Those skilled in the art may set the address parameters according to actual needs, and the present disclosure does not limit this.

[0041] In a possible implementation, the address parameter of the tensor data may include a reference address of the data reference point of the descriptor in the data storage space of the tensor data. The reference address may be different according to the change of the data reference point. The present disclosure does not limit the selection of the data reference point.

[0042] In a possible implementation, the reference address may include the starting address of the data storage space. When the data reference point of the descriptor is the first data block of the data storage space, the reference address of the descriptor is the starting address of the data storage space. When the data reference point of the descriptor is other data other than the first data block in the data storage space, the reference address of the descriptor is the address of the data block in the data storage space.

[0043] In a possible implementation, the shape parameters of the tensor data include at least one of the following: the size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertices at diagonal positions in the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address. The data description position is the mapping position of the point or area in the tensor data indicated by the descriptor. For example, when the tensor data is 3D data, the descriptor can use three-dimensional space coordinates (x, y, z) to represent the shape of the tensor data, and the data description position of the tensor data can be the position of the point or area mapped in the three-dimensional space represented by the three-dimensional space coordinates (x, y, z).

[0044] It should be understood that those skilled in the art may select shape parameters representing tensor data according to actual conditions, and the present disclosure does not limit this.

[0045] By using descriptors in the data access process, associations between data can be established, thereby reducing the complexity of data access and improving instruction processing efficiency.

[0046] In one possible implementation, the content of the descriptor of the tensor data can be determined based on the reference address of the data reference point of the descriptor in the data storage space of the tensor data, the size of the data storage space in at least one of the N dimensional directions, the size of the storage area in at least one of the N dimensional directions, and / or the offset of the storage area in at least one of the N dimensional directions. Figure 1 A schematic diagram showing a data storage space of a data processing device according to an embodiment of the present disclosure is shown. Figure 1 As shown, the data storage space 21 stores two-dimensional data in a row-first manner, which can be represented by (x, y) (where the X axis is horizontal to the right and the Y axis is vertically downward), the size in the X axis direction (the size of each row) is ori_x (not shown in the figure), the size in the Y axis direction (the total number of rows) is ori_y (not shown in the figure), and the starting address PA_start (reference address) of the data storage space 21 is the physical address of the first data block 22. The data block 23 is part of the data in the data storage space 21, and its offset 25 in the X axis direction is represented by offset_x, the offset 24 in the Y axis direction is represented by offset_y, the size in the X axis direction is represented by size_x, and the size in the Y axis direction is represented by size_y.

[0047] In a possible implementation, when a descriptor is used to define the data block 23, the data reference point of the descriptor can use the first data block of the data storage space 21, and the reference address of the descriptor can be agreed to be the starting address PA_start of the data storage space 21. Then, the content of the descriptor of the data block 23 can be determined by combining the size ori_x of the data storage space 21 on the X axis, the size ori_y on the Y axis, the offset offset_y of the data block 23 in the Y axis direction, the offset offset_x in the X axis direction, the size size_x in the X axis direction, and the size size_y in the Y axis direction.

[0048] In a possible implementation, the following formula (1) may be used to represent the content of the descriptor:

[0049]

[0050] It should be understood that, although in the above examples, the content of the descriptor represents a two-dimensional space, those skilled in the art may set the specific dimension represented by the content of the descriptor according to actual conditions, and the present disclosure does not limit this.

[0051] In one possible implementation, a reference address of the data reference point of the descriptor in the data storage space can be agreed upon, and based on the reference address, the content of the descriptor of the tensor data is determined according to the positions of at least two vertices at diagonal positions in N dimensional directions relative to the data reference point.

[0052] For example, the reference address PA_base of the data reference point of the descriptor in the data storage space can be agreed upon. For example, a data (e.g., data at position (2, 2)) can be selected in the data storage space 21 as the data reference point, and the physical address of the data in the data storage space is used as the reference address PA_base. The position of the two vertices at the diagonal position relative to the data reference point can be used to determine the reference address PA_base. Figure 1 The content of the descriptor of the data block 23 in the data block 23. First, the positions of at least two vertices at the diagonal positions of the data block 23 relative to the data reference point are determined, for example, the positions of the diagonal vertices from the upper left to the lower right direction relative to the data reference point are used, wherein the relative position of the upper left vertex is (x_min, y_min), and the relative position of the lower right vertex is (x_max, y_max), and then the content of the descriptor of the data block 23 can be determined according to the reference address PA_base, the relative position of the upper left vertex (x_min, y_min), and the relative position of the lower right vertex (x_max, y_max).

[0053] In a possible implementation, the following formula (2) may be used to represent the content of the descriptor (the base address is PA_base):

[0054]

[0055] It should be understood that although the above example uses the vertices at the upper left corner and the lower right corner to determine the content of the descriptor, those skilled in the art can set the specific vertices of at least two vertices at the diagonal positions according to actual needs, and the present disclosure does not limit this.

[0056] In a possible implementation, the content of the descriptor of the tensor data can be determined according to the reference address of the data reference point of the descriptor in the data storage space and the mapping relationship between the data description position and the data address of the tensor data indicated by the descriptor. The mapping relationship between the data description position and the data address can be set according to actual needs. For example, when the tensor data indicated by the descriptor is three-dimensional space data, the function f(x, y, z) can be used to define the mapping relationship between the data description position and the data address.

[0057] In a possible implementation, the following formula (3) may be used to represent the content of the descriptor:

[0058]

[0059] In a possible implementation, the first descriptor and the second descriptor are also used to indicate the address of N-dimensional tensor data, wherein the contents of the first descriptor and the second descriptor also include at least one address parameter representing the address of the tensor data.

[0060] The first descriptor or the second descriptor may further include at least one address parameter representing the address of the tensor data. For example, the first content or the second content may be:

[0061]

[0062] Wherein PA is an address parameter of the first content or the second content. The address parameter may be a logical address or a physical address. The descriptor parsing circuit may use PA as any vertex, middle point or preset point of the vector shape, and combine the shape parameters in the X direction and the Y direction to obtain the corresponding data address.

[0063] In a possible implementation, the address parameter of the tensor data includes a reference address of a data reference point of the descriptor in a data storage space of the tensor data, and the reference address includes a starting address of the data storage space.

[0064] In a possible implementation, the first descriptor or the second descriptor may further include at least one address parameter representing the address of the tensor data. For example, the first content or the second content may be:

[0065]

[0066] Among them, PA_start is the reference address parameter and will not be repeated here.

[0067] It should be understood that those skilled in the art may set the mapping relationship between the data description location and the data address according to actual conditions, and the present disclosure does not limit this.

[0068] In a possible implementation, an agreed reference address can be set in a task, and the descriptors in the instructions under this task all use this reference address, and the content in the descriptor content may include shape parameters based on this reference address. This reference address can be determined by setting the environmental parameters of this task. The relevant description and use of the reference address can be found in the above embodiment. In this implementation, the content of the descriptor can be mapped to a data address more quickly.

[0069] In a possible implementation, the reference address may be included in the content of each descriptor, and the reference address of each descriptor may be different. Compared with the method of setting a common reference address using environmental parameters, each descriptor in this method can describe data more flexibly and use a larger data address space.

[0070] In a possible implementation, the data address of the data corresponding to the operand of the processing instruction in the data storage space can be determined according to the content of the descriptor. The calculation of the data address is automatically completed by hardware, and the calculation method of the data address will be different when the content of the descriptor is expressed in different ways. The present disclosure does not limit the specific calculation method of the data address.

[0071] For example, the content of the descriptor in the operand is expressed using formula (1). The offsets of the tensor data indicated by the descriptor in the data storage space are offset_x and offset_y, respectively, and the size is size_x*size_y. Then, the starting data address PA1 of the tensor data indicated by the descriptor in the data storage space is (x,y) It can be determined using the following formula (4):

[0072] PA1 (x,y) =PA_start+(offset_y-1)*ori_x+offset_x (4)

[0073] The data starting address PA1 is determined according to the above formula (4) (x,y), combined with the offsets offset_x and offset_y, and the sizes size_x and size_y of the storage area, the storage area of ​​the tensor data indicated by the descriptor in the data storage space can be determined.

[0074] In one possible implementation, when the operand also includes a data description position for the descriptor, the data address of the data corresponding to the operand in the data storage space can be determined according to the content of the descriptor and the data description position. In this way, part of the data (e.g., one or more data) in the tensor data indicated by the descriptor can be processed.

[0075] For example, the content of the descriptor in the operand is expressed using formula (1). The offsets of the tensor data indicated by the descriptor in the data storage space are offset_x and offset_y, respectively, and the size is size_x*size_y. The data description position for the descriptor included in the operand is (x q ,y q ), then the data address PA2 of the tensor data indicated by the descriptor in the data storage space (x,y) It can be determined using the following formula (5):

[0076] PA2 (x,y) =PA_start+(offset_y+y q -1)*ori_x+(offset_x+x q ) (5)

[0077] Figure 2 FIG. 1 is a block diagram of a data processing device according to an embodiment of the present disclosure. Figure 2 As shown, the data processing device includes a control circuit 11, a descriptor parsing circuit 12 and an execution circuit 13, wherein:

[0078] The control circuit 11 is configured to decode the received processing instruction to obtain an operation code and an operand in the decoded processing instruction, wherein the operand includes a first content of a first descriptor, and the first content of the first descriptor is used to indicate a shape of a tensor;

[0079] The descriptor parsing circuit 12 is configured to determine a data address of data corresponding to the operand in a data storage space according to the first content;

[0080] The execution circuit 13 is configured to execute the processing instruction according to the data address and the operation code.

[0081] According to an embodiment of the present disclosure, the control circuit processes the first content of the first descriptor in the instruction operand, and the descriptor parsing circuit determines the data address of the data corresponding to the operand in the data storage space according to the first content. The execution circuit executes the processing instruction according to the data address and the operation code, so that the operand can be obtained through the descriptor when the processing instruction is executed, thereby reducing the complexity of data access and improving the data access efficiency of the processor.

[0082] In a possible implementation, the data processing device may be applied to a processor, wherein the processor may include a general-purpose processor (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)) and a special-purpose processor (e.g., an artificial intelligence processor, a scientific computing processor, or a digital signal processor). The present disclosure does not limit the type of processor.

[0083] In a possible implementation, the control circuit 11 may be configured to decode the received processing instruction to obtain a decoded processing instruction, wherein the decoded processing instruction includes an operation code and one or more operands, and the operation code is used to indicate the processing type corresponding to the processing instruction. The processing instruction may include a data access instruction, an operation instruction, a management instruction, a synchronization instruction, etc. The present disclosure does not limit the specific type of the processing instruction.

[0084] In a possible implementation, the descriptor parsing circuit may be arranged in the control circuit or the execution circuit. When the descriptor parsing circuit is arranged in the control circuit, the control circuit sends the data address and operation code corresponding to the operand obtained by parsing to the execution circuit. When the descriptor parsing circuit is arranged in the execution circuit, the control circuit sends the operation code obtained by parsing and the first content of the first descriptor to the execution circuit, and the descriptor parsing circuit in the execution circuit parses and obtains the data address corresponding to the operand.

[0085] In a possible implementation, the descriptor parsing circuit is further configured to determine a data address of data corresponding to the operand of the processing instruction in the data storage space based on the first content of the first descriptor and the second content of the second descriptor stored in the descriptor storage space.

[0086] In a possible implementation, a second descriptor may be created for a task, and the second descriptor is stored in the descriptor storage space, and is used to indicate a larger tensor or a tensor set used by the task, and the tensor or tensor set corresponding to the second descriptor may be stored in the data storage area. The operand in the instruction under this task may include the first descriptor. The first descriptor may extract the data address corresponding to the operand based on the second descriptor. The data address corresponding to the operand may be obtained according to the shape parameter in the first descriptor and the shape parameter in the second descriptor. For example, the first descriptor may include a reference address, and the second descriptor may include the shape parameter of each operand. The data address of the operand corresponding to each second descriptor may be obtained according to the above embodiment according to the reference address parameter and the shape parameter in each second descriptor. It is also possible to give a reference address by creating an environment parameter, and the shape parameter in the first descriptor gives a larger tensor, and each second descriptor intercepts data based on the first descriptor. In this way, since the data corresponding to the first descriptor has been stored in the data storage area, the operand required for the instruction under this task does not need to be transferred on-chip or off-chip, which can reduce the data IO bottleneck.

[0087] In one possible implementation, the operand also includes an identifier of a first descriptor, and the descriptor parsing circuit is further configured to determine a second descriptor corresponding to the first descriptor in the descriptor storage space based on the identifier of the first descriptor, and determine a data address in the data storage space of data corresponding to the operand of the processing instruction based on a first content of the first descriptor and a second content of the second descriptor.

[0088] In one possible implementation, multiple second descriptors can be created for a task, and each second descriptor can be distinguished by an identifier. The operand in the instruction under this task may include a first descriptor and may also include an identifier of a second descriptor corresponding to the first descriptor. In this way, the shape of the tensor described by the first descriptor may be smaller than the shape of the tensor described by the corresponding second descriptor. The shape of the tensor described by the first descriptor may also be different from the shape of the tensor described by the corresponding second descriptor but overlap.

[0089] In a possible implementation, the first descriptor may have at least one shape parameter identical to that in the corresponding second descriptor, and the identical shape parameter may not be given in the first descriptor, and only different shape parameters may be given.

[0090] In a possible implementation, after the control circuit 11 decodes the received processing instruction, when the operand of the instruction includes the identifier of the first descriptor, the control circuit 11 obtains the content of the first descriptor from the descriptor storage space according to the identifier of the first descriptor, and sends the first content of the first descriptor and the second content of the second descriptor in the operand to the descriptor parsing circuit for parsing. The descriptor parsing circuit may, based on the shape parameters in the first content and the shape parameters in the second content,

[0091] For example, when the reference address is PA_start, the first content D1 of the first descriptor and the second content D2 of the second descriptor can be respectively expressed as follows:

[0092]

[0093]

[0094] From the shape parameters in D1 and D2 above, we can see that the first content only has shape parameters in the Y direction, which means that the shape parameters in the X direction in the first content are consistent with the shape parameters in the second content. Then the actual shape parameters of D1 are:

[0095]

[0096] The descriptor parsing circuit can determine the data address of the data corresponding to the operand of the processing instruction in the data storage space according to the shape parameter of D2, and after sending the parsed data address to the execution circuit, the execution circuit performs the data processing corresponding to the processing instruction according to the data address. The data address in the data storage space can be an actual physical address or a virtual address, and the present disclosure does not limit the type of the data address.

[0097] In a possible implementation, the descriptor storage space may be a storage space in the internal memory of the control circuit 11, and the data storage space may be a storage space in the internal memory of the descriptor parsing circuit 12 or an external memory connected to the descriptor parsing circuit 12. The present disclosure does not limit this.

[0098] In a possible implementation, the processing instruction includes a data access instruction, and the operand includes source data and destination data.

[0099] In a possible implementation, the data access instruction includes one of an on-chip or off-chip data access instruction, an intra-chip data access instruction, and an inter-chip data access instruction, and at least one of a source operand or a destination operand of the data access instruction includes the first descriptor.

[0100] In a possible implementation, when the processing instruction is a data access instruction, the data access instruction may be used to access data on and off a chip, access data within a chip, and access data between chips. This disclosure does not limit this.

[0101] Figure 3 FIG. 1 is a flow chart showing a data processing method according to an embodiment of the present disclosure. Figure 3 As shown, the data processing method is applied to a data processing device, and the method includes:

[0102] Step S41, decoding the received processing instruction to obtain an operation code and an operand in the decoded processing instruction, wherein the operand includes a first content of a first descriptor, and the first content of the first descriptor is used to indicate a shape of a tensor;

[0103] Step S42, determining a data address of data corresponding to the operand in a data storage space according to the first content;

[0104] Step S43: execute the processing instruction according to the data address and the operation code.

[0105] In a possible implementation, a data address of data corresponding to an operand of the processing instruction in a data storage space is determined according to a first content of the first descriptor and a second content of a second descriptor stored in the descriptor storage space.

[0106] In a possible implementation manner, the operand further includes an identifier of the first descriptor, and the method further includes:

[0107] According to the identifier of the first descriptor, a second descriptor corresponding to the first descriptor is determined in the descriptor storage space, and according to the first content of the first descriptor and the second content of the second descriptor, a data address of the data corresponding to the operand of the processing instruction in the data storage space is determined.

[0108] In a possible implementation, the first descriptor and the second descriptor are used to indicate the shape of N-dimensional tensor data, where N is a positive integer, and the contents of the first descriptor and the second descriptor include at least one shape parameter representing the shape of the tensor data.

[0109] The shape parameter of the tensor data includes at least one of the following:

[0110] The size of the data storage space in at least one direction of the N dimensions, the size of the storage area of ​​the tensor data in at least one direction of the N dimensions, the offset of the storage area in at least one direction of the N dimensions, the positions of at least two vertices at diagonal positions in the N dimensions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address.

[0111] In a possible implementation, the first descriptor and the second descriptor are also used to indicate the address of N-dimensional tensor data, wherein the contents of the first descriptor and the second descriptor also include at least one address parameter representing the address of the tensor data.

[0112] In a possible implementation, the address parameter of the tensor data includes a reference address of a data reference point of the descriptor in a data storage space of the tensor data, and the reference address includes a starting address of the data storage space.

[0113] In a possible implementation, the processing instruction includes one of a data access instruction, a calculation instruction, a management instruction, and a synchronization instruction.

[0114] In a possible implementation, the data access instruction includes one of an on-chip or off-chip data access instruction, an intra-chip data access instruction, and an inter-chip data access instruction, and at least one of a source operand or a destination operand of the data access instruction includes the first descriptor.

[0115] In a possible implementation, an artificial intelligence chip is also disclosed, which includes the above-mentioned data processing device.

[0116] In a possible implementation, a board is also disclosed, which includes a storage device, an interface device, a control device and the above-mentioned artificial intelligence chip; wherein the artificial intelligence chip is connected to the storage device, the control device and the interface device respectively; the storage device is used to store data; the interface device is used to realize data transmission between the artificial intelligence chip and an external device; the control device is used to monitor the status of the artificial intelligence chip.

[0117] Figure 4 A structural block diagram of a board according to an embodiment of the present disclosure is shown. Figure 4 In addition to the chip 389, the board may also include other supporting components, including but not limited to: a storage device 390, an interface device 391 and a control device 392;

[0118] The storage device 390 is connected to the artificial intelligence chip via a bus for storing data. The storage device may include multiple groups of storage units 393. Each group of storage units is connected to the artificial intelligence chip via a bus. It is understood that each group of storage units may be DDR SDRAM (English: Double Data Rate SDRAM, double rate synchronous dynamic random access memory).

[0119] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. The speed of DDR is twice that of standard SDRAM. In one embodiment, the storage device may include 4 groups of storage units. Each group of storage units may include multiple DDR4 particles (chips). In one embodiment, the artificial intelligence chip may include 4 72-bit DDR4 controllers, 64 bits of the above 72-bit DDR4 controllers are used to transmit data, and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 particles are used in each group of storage units, the theoretical bandwidth of data transmission can reach 25600MB / s.

[0120] In one embodiment, each group of the storage units includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transmit data twice in one clock cycle. A controller for controlling DDR is arranged in the chip to control the data transmission and data storage of each of the storage units.

[0121] The interface device is electrically connected to the artificial intelligence chip. The interface device is used to realize data transmission between the artificial intelligence chip and an external device (such as a server or a computer). For example, in one embodiment, the interface device may be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through a standard PCIE interface to realize data transfer. Preferably, when the PCIE 3.0X 16 interface is used for transmission, the theoretical bandwidth can reach 16000MB / s. In another embodiment, the interface device may also be other interfaces. This application does not limit the specific forms of expression of the above-mentioned other interfaces, and the interface unit can realize the switching function. In addition, the calculation results of the artificial intelligence chip are still transmitted back to the external device (such as a server) by the interface device.

[0122] The control device is electrically connected to the artificial intelligence chip. The control device is used to monitor the state of the artificial intelligence chip. Specifically, the artificial intelligence chip and the control device can be electrically connected through an SPI interface. The control device may include a single-chip microcomputer (Micro Controller Unit, MCU). For example, the artificial intelligence chip may include multiple processing chips, multiple processing cores or multiple processing circuits, which can drive multiple loads. Therefore, the artificial intelligence chip can be in different working states such as multi-load and light load. The control device can realize the regulation of the working states of multiple processing chips, multiple processing and / or multiple processing circuits in the artificial intelligence chip.

[0123] In a possible implementation, an electronic device is disclosed, which includes the above-mentioned artificial intelligence chip. The electronic device includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and / or a medical device.

[0124] The transportation means include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging, ultrasound machines and / or electrocardiographs.

[0125] A1. A data processing device, comprising a control circuit, a descriptor parsing circuit and an execution circuit.

[0126] The control circuit is configured to decode the received processing instruction to obtain an operation code and an operand in the decoded processing instruction, and the operand includes a first content of a first descriptor, and the first content of the first descriptor is used to indicate a shape of a tensor;

[0127] The descriptor parsing circuit is configured to determine a data address of data corresponding to the operand in a data storage space according to the first content;

[0128] The execution circuit is configured to execute the processing instruction according to the data address and the operation code.

[0129] A2. According to the data processing device described in clause A1, the descriptor parsing circuit is also configured to determine the data address of the data corresponding to the operand of the processing instruction in the data storage space based on the first content of the first descriptor and the second content of the second descriptor stored in the descriptor storage space.

[0130] A3. A data processing apparatus according to clause A1, wherein the operand further comprises an identifier of the first descriptor,

[0131] The descriptor parsing circuit is also configured to determine a second descriptor corresponding to the first descriptor in the descriptor storage space based on the identifier of the first descriptor, and determine a data address of data corresponding to the operand of the processing instruction in the data storage space based on the first content of the first descriptor and the second content of the second descriptor.

[0132] A4. According to the data processing device described in clause A1, the descriptor parsing circuit is set in the control circuit or the execution circuit.

[0133] A5. The apparatus according to any one of clauses A1 to A4, wherein the first descriptor and the second descriptor are used to indicate the shape of N-dimensional tensor data, N is a positive integer, and the contents of the first descriptor and the second descriptor include at least one shape parameter representing the shape of the tensor data,

[0134] The shape parameter of the tensor data includes at least one of the following:

[0135] The size of the data storage space in at least one direction of the N dimensions, the size of the storage area of ​​the tensor data in at least one direction of the N dimensions, the offset of the storage area in at least one direction of the N dimensions, the positions of at least two vertices at diagonal positions in the N dimensions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address.

[0136] A6. According to the device described in clause A5, the first descriptor and the second descriptor are also used to indicate the address of N-dimensional tensor data, wherein the contents of the first descriptor and the second descriptor also include at least one address parameter representing the address of the tensor data.

[0137] A7. According to the device described in clause A6, the address parameter of the tensor data includes a reference address of the data reference point of the descriptor in the data storage space of the tensor data, and the reference address includes the starting address of the data storage space.

[0138] A8. According to the device described in any one of clauses A1-A7, the processing instruction includes one of a data access instruction, an operation instruction, a management instruction, and a synchronization instruction.

[0139] A9. According to any one of the apparatuses described in clause A8, the data access instruction comprises one of an on-chip or off-chip data access instruction, an intra-chip data access instruction, and an inter-chip data access instruction, and at least one of the source operand or the destination operand of the data access instruction comprises the first descriptor.

[0140] A10. A data processing method, applied to a data processing device, comprising:

[0141] Decoding the received processing instruction to obtain an operation code and an operand in the decoded processing instruction, wherein the operand includes a first content of a first descriptor, and the first content of the first descriptor is used to indicate a shape of a tensor;

[0142] Determine, according to the first content, a data address of the data corresponding to the operand in the data storage space;

[0143] The processing instruction is executed according to the data address and the operation code.

[0144] A11. The data processing method according to clause A10, further comprising:

[0145] A data address of data corresponding to an operand of the processing instruction in the data storage space is determined according to a first content of the first descriptor and a second content of a second descriptor stored in the descriptor storage space.

[0146] A12. The data processing method according to clause A10, wherein the operand further includes an identifier of the first descriptor, and the method further includes:

[0147] According to the identifier of the first descriptor, a second descriptor corresponding to the first descriptor is determined in the descriptor storage space, and according to the first content of the first descriptor and the second content of the second descriptor, a data address of the data corresponding to the operand of the processing instruction in the data storage space is determined.

[0148] A13. A method according to any one of clauses A10-A12, wherein the first descriptor and the second descriptor are used to indicate the shape of N-dimensional tensor data, N is a positive integer, and the contents of the first descriptor and the second descriptor include at least one shape parameter representing the shape of the tensor data,

[0149] The shape parameter of the tensor data includes at least one of the following:

[0150] The size of the data storage space in at least one direction of the N dimensions, the size of the storage area of ​​the tensor data in at least one direction of the N dimensions, the offset of the storage area in at least one direction of the N dimensions, the positions of at least two vertices at diagonal positions in the N dimensions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address.

[0151] A14. According to the method described in clause A13, the first descriptor and the second descriptor are also used to indicate the address of N-dimensional tensor data, wherein the contents of the first descriptor and the second descriptor also include at least one address parameter representing the address of the tensor data.

[0152] A15. According to the method described in clause A14, the address parameter of the tensor data includes a reference address of the data reference point of the descriptor in the data storage space of the tensor data, and the reference address includes the starting address of the data storage space.

[0153] A16. According to the method described in any one of clauses A10-A15, the processing instruction includes one of a data access instruction, an operation instruction, a management instruction, and a synchronization instruction.

[0154] A17. According to the method described in any one of clauses A16, the data access instruction includes one of an on-chip or off-chip data access instruction, an intra-chip data access instruction, and an inter-chip data access instruction, and at least one of the source operands or destination operands of the data access instruction includes the first descriptor.

[0155] A18. An artificial intelligence chip, comprising a data processing device as described in any one of clauses A1-A9.

[0156] A19. An electronic device comprising an artificial intelligence chip as described in clause A18.

[0157] A20. A board comprising: a storage device, an interface device, a control device, and an artificial intelligence chip as described in clause A19;

[0158] Wherein, the artificial intelligence chip is connected to the storage device, the control device and the interface device respectively;

[0159] The storage device is used to store data;

[0160] The interface device is used to realize data transmission between the artificial intelligence chip and external equipment;

[0161] The control device is used to monitor the status of the artificial intelligence chip.

[0162] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A data processing device, comprising a control circuit, a descriptor parsing circuit and an execution circuit, The control circuit is configured to decode the received processing instruction to obtain an operation code and an operand in the decoded processing instruction, and the operand includes a first content of a first descriptor, the first content of the first descriptor is used to indicate a shape of a tensor and at least one address parameter representing an address of the tensor, and the address parameter of the tensor includes a reference address of a data reference point of the first descriptor in a data storage space of the tensor; The first content includes at least one shape parameter representing the shape of the tensor data, and the shape parameter of the tensor data includes at least one of the following: The size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area of ​​the tensor data in at least one direction of the N dimensional directions, the positions of at least two vertices at diagonal positions in the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address; The descriptor parsing circuit is configured to determine a data address of data corresponding to the operand in a data storage space according to the first content; The execution circuit is configured to execute the processing instruction according to the data address and the operation code.

2. According to the data processing device according to claim 1, the descriptor parsing circuit is also configured to determine the data address of the data corresponding to the operand of the processing instruction in the data storage space based on the first content of the first descriptor and the second content of the second descriptor stored in the descriptor storage space.

3. The data processing apparatus according to claim 1, wherein the operand further comprises an identifier of a first descriptor. The descriptor parsing circuit is also configured to determine a second descriptor corresponding to the first descriptor in the descriptor storage space based on the identifier of the first descriptor, and determine a data address of data corresponding to the operand of the processing instruction in the data storage space based on the first content of the first descriptor and the second content of the second descriptor. 4 . The data processing device according to claim 1 , wherein the descriptor parsing circuit is provided in the control circuit or the execution circuit.

5. The data processing device according to claim 2 or 3, wherein the first descriptor and the second descriptor are used to indicate the shape of N-dimensional tensor data, where N is a positive integer. The shape parameter of the first content of the first descriptor is also include: An offset of the storage area in at least one direction of the N dimensional directions; The content of the second descriptor includes at least one shape parameter representing the shape of the tensor data, The shape parameter of the tensor data represented by the second descriptor includes at least one of the following: The size of the data storage space in at least one direction of the N dimensions, the size of the storage area of ​​the tensor data in at least one direction of the N dimensions, the offset of the storage area in at least one direction of the N dimensions, the positions of at least two vertices at diagonal positions in the N dimensions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address.

6. The data processing device according to claim 5, wherein the second descriptor is further used to indicate an address of N-dimensional tensor data. in, The content of the second descriptor also includes at least one address parameter representing the address of the tensor data. 7 . The data processing apparatus according to claim 6 , wherein the reference address comprises a start address of the data storage space.

8. The data processing device according to claim 1, wherein the processing instruction comprises one of a data access instruction, an operation instruction, a management instruction, and a synchronization instruction.

9. The data processing device according to claim 8, wherein the data access instruction comprises one of an on-chip or off-chip data access instruction, an intra-chip data access instruction, and an inter-chip data access instruction, and at least one of the source operand or the destination operand of the data access instruction comprises the first descriptor.

10. A data processing method, applied to a data processing device, the method include: Decoding the received processing instruction to obtain an operation code and an operand in the decoded processing instruction, wherein the operand includes a first content of a first descriptor, the first content of the first descriptor is used to indicate a shape of a tensor and at least one address parameter representing an address of the tensor, and the address parameter of the tensor includes a reference address of a data reference point of the first descriptor in a data storage space of the tensor; Determine, according to the first content, a data address of the data corresponding to the operand in the data storage space; executing the processing instruction according to the data address and the operation code; The first content includes at least one shape parameter representing the shape of the tensor data, and the shape parameter of the tensor data includes at least one of the following: The size of the data storage space in at least one direction of the N dimensions, the size of the storage area of ​​the tensor data in at least one direction of the N dimensions, the positions of at least two vertices at diagonal positions in the N dimensions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address.

11. The data processing method according to claim 10, further comprising: include: A data address of data corresponding to an operand of the processing instruction in the data storage space is determined according to a first content of the first descriptor and a second content of a second descriptor stored in the descriptor storage space.

12. The data processing method according to claim 10, wherein the operand further comprises an identifier of the first descriptor, and the method further comprises: include: According to the identifier of the first descriptor, a second descriptor corresponding to the first descriptor is determined in the descriptor storage space, and according to the first content of the first descriptor and the second content of the second descriptor, a data address of the data corresponding to the operand of the processing instruction in the data storage space is determined.

13. The data processing method according to claim 11 or 12, wherein the first descriptor and the second descriptor are used to indicate the shape of N-dimensional tensor data, where N is a positive integer. The shape parameter of the first content of the first descriptor is also include: An offset of the storage area in at least one direction of the N dimensional directions; The content of the second descriptor includes at least one shape parameter representing the shape of the tensor data, The shape parameter of the tensor data represented by the second descriptor includes at least one of the following: The size of the data storage space in at least one direction of the N dimensions, the size of the storage area of ​​the tensor data in at least one direction of the N dimensions, the offset of the storage area in at least one direction of the N dimensions, the positions of at least two vertices at diagonal positions in the N dimensions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address.

14. The data processing method according to claim 13, wherein the second descriptor is further used to indicate the address of N-dimensional tensor data. in, The content of the second descriptor also includes at least one address parameter representing the address of the tensor data. 15 . The data processing method according to claim 14 , wherein the reference address comprises a starting address of the data storage space. 16 . The data processing method according to claim 10 , wherein the processing instruction comprises one of a data access instruction, an operation instruction, a management instruction, and a synchronization instruction.

17. The data processing method according to claim 16, wherein the data access instruction comprises one of an on-chip or off-chip data access instruction, an intra-chip data access instruction, and an inter-chip data access instruction, and at least one of the source operand or the destination operand of the data access instruction comprises the first descriptor.

18. An artificial intelligence chip, comprising a data processing device as described in any one of claims 1 to 9.

19. An electronic device comprising the artificial intelligence chip as claimed in claim 18.

20. A board, the board include: A memory device, an interface device, a control device, and an artificial intelligence chip as claimed in claim 19; Wherein, the artificial intelligence chip is connected to the storage device, the control device and the interface device respectively; The storage device is used to store data; The interface device is used to realize data transmission between the artificial intelligence chip and external equipment; The control device is used to monitor the status of the artificial intelligence chip.

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