Interconnect structure, semiconductor structure and method for forming the same

Abstract

The present disclosure provides an interconnect structure, a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate; a first metal wire located above the substrate and extending along a first direction; a protective layer lining the sidewall of the first metal wire; a second metal wire located on the first metal wire and extending along the first direction; and a third metal wire located above the second metal wire and extending along a second direction perpendicular to the first direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to interconnect structures, semiconductor structures, and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced several generations of ICs. Each generation of circuits is smaller and more complex than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs.

[0003] Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component or line that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0004] However, as feature sizes continue to decrease, the manufacturing process continues to become more difficult to perform, and the critical dimension uniformity of the features (or lines) continues to become more difficult to control. For example, it is difficult to reduce the distance between two vias at the same level. Electrical shorts are also a thorny issue, hindering the path to achieving the minimum critical value. It is challenging to form reliable semiconductor devices at increasingly smaller sizes. Summary of the invention

[0005] According to one aspect of an embodiment of the present invention, a semiconductor structure is provided, including: a substrate; a first metal wire located above the substrate and extending along a first direction; a protective layer lining the sidewalls of the first metal wire; a second metal wire located on the first metal wire and extending along the first direction; and a third metal wire located above the second metal wire and extending along a second direction perpendicular to the first direction.

[0006] According to another aspect of an embodiment of the present invention, there is provided an interconnect structure, comprising: a substrate; a first insulating layer located above the substrate; a plurality of first metal lines located at a first level of the first insulating layer, wherein each of the plurality of first metal lines extends along a first direction; and a plurality of second metal lines, wherein each of the plurality of second metal lines extends along the first direction and is located at a second level of the first insulating layer above the first level, a first metal line among the plurality of first metal lines and a second metal line among the plurality of second metal lines are arranged in a staggered manner, a first portion of the first insulating layer is located between a bottom surface of each of the plurality of second metal lines and a top surface of each of the plurality of first metal lines, and a height of the first portion is in the range of 6 nm to 15 nm.

[0007] According to another aspect of an embodiment of the present invention, a method for forming a semiconductor structure is provided, comprising: depositing a first insulating material above a substrate, wherein the substrate includes an active area; etching the first insulating material to define a first groove extending along a first direction at a first level of the first insulating material; depositing a second insulating material to line the sidewalls of the first groove; and depositing a first metal line in the first groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1A is a top view of a semiconductor structure according to some embodiments of the present disclosure.

[0010] Figure 1B is a top view of a semiconductor structure according to some embodiments of the present disclosure.

[0011] Figure 1C is a top view of a semiconductor structure according to some embodiments of the present disclosure.

[0012] Figure 2A is a top view of a semiconductor structure according to some embodiments of the present disclosure.

[0013] Figure 2B is a top view of a semiconductor structure according to some embodiments of the present disclosure.

[0014] Figure 3 is a top view of a semiconductor structure according to some embodiments of the present disclosure.

[0015] Figure 4A is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0016] Figure 4B is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0017] Figure 5A is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0018] Figure 5B is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0019] Figure 6 A flow chart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure is shown.

[0020] 7A to 7J is a cross-sectional view of a semiconductor structure during an intermediate stage of fabrication operations according to some embodiments of the present disclosure.

[0021] Fig. 8A is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0022] Figure 8B is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0023] Fig. 9A is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0024] Fig. 9B is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0025] Fig.10 A flow chart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure is shown.

[0026] FIG. 11A to FIG. 11S is a cross-sectional view of a semiconductor structure during an intermediate stage of manufacturing operations according to some embodiments of the present disclosure.

[0027] Fig. 12A is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0028] Fig. 12B is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0029] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0030] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0031] Although the numerical ranges and parameters describing the wide range of the present invention are approximate values, the numerical values ​​described in the specific examples are reported as accurately as possible. However, any numerical value inherently contains certain errors, which must be caused by the standard deviation in each test measurement. Similarly, as used herein, the terms "substantially", "about" or "approximately" generally refer to values ​​or ranges that can be thought of by ordinary technicians in the field. Alternatively, the terms "substantially", "about" or "approximately" refer to within an acceptable standard error of the mean value when considered by ordinary technicians in the field. It can be understood by ordinary technicians in the field that acceptable standard errors can vary according to different technologies. Except in the operation / working examples, or unless otherwise explicitly stated, all numerical ranges, quantities, values ​​and percentages disclosed herein, such as the numerical ranges, quantities, values ​​and percentages of material quantity, duration, temperature, operating conditions, quantity ratios, etc., should be understood to be modified by the terms "substantially", "about" or "approximately". Therefore, unless otherwise indicated, the numerical parameters described in the present disclosure are approximate values ​​that can be changed as needed. At least, each numerical parameter should be interpreted at least according to the number of reported significant figures and by applying conventional rounding techniques. Ranges herein can be expressed from one endpoint to the other endpoint or between two endpoints. Unless otherwise stated, all ranges disclosed herein include endpoints.

[0032] With the trend of reducing the geometric size of semiconductor devices, it is possible to reduce the cell height by reducing the pitch between conductive vias, thereby increasing the device density. However, in some cases, when only the pitch between vias is reduced, problems with resistance and parasitic capacitance arise, which can reduce device performance and operating speed. In addition, since the pitch is reduced by complying with the limitations of the technology for forming the vias (e.g., photolithography operation or etching operation, etc.), the vias physically contact another adjacent via, which increases the risk of electrical short circuits.

[0033] The present disclosure provides a semiconductor structure and method to solve the above problems. In particular, Figures 1A to 3Some embodiments of routing metal lines across multiple layers in a manner that reduces the geometric size of semiconductor devices in advanced technology nodes are discussed in the disclosure. For example, some embodiments of the present disclosure provide semiconductor structures including "staggered via structures", which refers to more than one level of metal lines arranged in one insulating layer (i.e., one metal layer), wherein vias with different heights are connected from the bottom of the multiple levels of metal lines to a common structure, such as a substrate, a conductive region, or an underlying metal line extending in a vertical direction. In some embodiments, the term "staggered" refers to an alternating configuration of two elements along a direction or can be observed from a certain angle.

[0034] Some embodiments also utilize a protective layer to protect the metal lines and help mitigate the problem of metal lines that are undesirably connected to adjacent vias. This technology is applicable to the above-mentioned staggered via structure to solve the above-mentioned problems. For example, in FIG. 4A to FIG. 7J An embodiment in which a protective layer is provided on the sidewalls of the metal line is discussed; FIG. 8A to FIG. 11S An embodiment having a pad on the sidewalls of the metal line and also including a top extending above the top of the metal line is discussed in FIG. 12A to FIG. 12B An embodiment having auxiliary vias connecting multiple horizontal metal lines in one metal layer is discussed in . Figures 4A to 7G , FIG. 8A to FIG. 11S ,or FIG. 12A to FIG. 12B The embodiments discussed in Figures 1A to 3 The embodiments discussed in or similar configurations may be used, particularly in back-end-of-line (BEOL) processes.

[0035] Those skilled in the art will appreciate that the semiconductor structures discussed in this disclosure refer to the metal layers near the conductive regions (e.g., M0 to M2), which typically face the most difficult problems in terms of wiring. However, the techniques discussed in this disclosure are also applicable to other metal layers. In some embodiments, different metal layers in a device coexist and utilize Figures 4A to 7G , FIG. 8A to FIG. 11S ,or FIG. 12A to FIG. 12B The techniques discussed in .

[0036] In addition, the semiconductor structures discussed in the present disclosure provide flexibility in design rules, wherein electrical properties (such as resistivity or parasitic capacitance) can be adjusted or tuned according to specific requirements. For example, in some embodiments, power devices are designed to have lower resistivity, wherein, in some cases, some trade-offs can be achieved between resistivity and parasitic capacitance.

[0037] refer to Figures 1A to 1C , Figure 1A middle, Figure 1B and Figure 1CEach of the top views is a top view of a semiconductor structure according to some embodiments of the present disclosure. As previously discussed, with the trend of reducing the geometric size of semiconductor devices, the size of the cell 100 is reduced to a certain extent in order to comply with some technology nodes. For example, in some embodiments, the cell 100 has a cell width D along the main direction PD and a cell height W along the secondary direction SD orthogonal to the main direction PD. The cell 100 includes a gate region 109 extending along the secondary direction SD and having a length equal to the cell height W.

[0038] The unit 100 includes one or more first metal lines 102A and one or more second metal lines 102B extending along the main direction PD, wherein the first metal lines 102A and the second metal lines 102B are both in the same metal layer. In some embodiments, the first metal lines 102A and the second metal lines 102B are both disposed in the lowest metal layer M0, but the present disclosure is not limited thereto. Figure 1A , Figure 1B and Figure 1C Embodiments with three, four, and five whole metal lines (ie, excluding partial metal lines) arranged side by side in the secondary direction SD are shown, respectively. Figure 1A Taking the cell 100 in FIG. 1 as an example, one complete second metal line 102B and two complete first metal lines 102A are in the area of ​​the cell 100. Similarly, Figure 1B The illustrated unit 100 includes two complete first metal lines 102A and two complete second metal lines 102B, and Figure 1C The illustrated cell 100 includes three complete first metal lines 102A and two complete second metal lines 102B. More metal lines having similar configurations within the area of ​​the cell 100 may also be used.

[0039] Having more metal lines in the cell 100 provides the benefit of increased device density, however, further reducing the cell height W of the cell 100 with the trend of decreasing size is challenging due to issues with resistance, parasitic capacitance, and / or electrical shorts.

[0040] refer to FIG. 2A to FIG. 2B , Figure 2A and Figure 2B Each of is a top view of a semiconductor structure according to some embodiments of the present disclosure. Figure 2A and Figure 2B Shown in Figures 1A to 1C The metal lines or similar configurations discussed in are directly above and electrically connected to the first metal line 102A and the second metal line 102B. Specifically, Figure 2AAn embodiment is shown having a third metal line 112 extending in the secondary direction SD and four complete fourth and fifth metal lines 122A and 122B extending over the third metal line 112 and in the primary direction. Figure 2B An embodiment is shown with a third metal line 112 extending in the secondary direction SD and five complete fourth metal lines 122A and fifth metal lines 122B extending in the primary direction over the third metal line 112. However, adding more metal lines in the cell area will face the challenge of reducing the landing area of ​​each underlying metal line (e.g., the first metal line 102A and the second metal line 102B), and a higher density conductive structure may face challenges of resistivity, parasitic capacitance, or electrical shorts.

[0041] Reference Figure 3 , Figure 3 1 is a top view of a semiconductor structure according to some embodiments of the present disclosure. The semiconductor structure 100S includes a plurality of cells 100. In order to increase the number of metal lines extending in the main direction PD in the cell region, the cell region is defined by the boundary of the gate region 109 and has a cell width D along the main direction PD and a cell height W along the secondary direction SD along the main direction, and the adoption of a "staggered via structure" is discussed later. Specifically, the first metal line 102A and the second metal line 102B are arranged in the same metal layer (e.g., M0 layer), but at different height levels. In some embodiments, each first metal line 102A is at a first level, and each second metal line 102B is arranged at a second level above the first level. In addition, a portion of the first metal line 102A overlaps a portion of the second metal line 102B in a vertical direction. The overlapping region OVL extends along the main direction PD. In some embodiments, the cell region 100 includes more than one overlapping region OVL.

[0042] The semiconductor structure 100S includes a plurality of first vias 101A electrically connected to the bottom of the first metal line 102A and a plurality of second vias 101B electrically connected to the bottom of the second metal line 102B. The semiconductor structure 100S also includes a third metal line 112 above the first metal line 102A and the second metal line 102B and orthogonal to the first metal line 102A and the second metal line 102B, and a third via 103 connected between the third metal line 112 and the second metal line 102B or between the third metal line 112 and the first metal line 102A.

[0043] After this, in Figures 4A to 7G The embodiments discussed FIG. 8A to FIG. 11S The embodiments discussed FIG. 12A to FIG. 12B The techniques utilized in the embodiments discussed are applicable to Figure 3 Embodiment of the invention.

[0044] Reference Figure 4A and Figure 4B , according to some embodiments of the present disclosure, Figure 4A is along Figure 3 A cross-sectional view of the semiconductor structure along line AA' in FIG. Figure 4B is along Figure 3 2 . The semiconductor structure 200 includes a substrate 299. In some embodiments, the substrate 299 includes silicon, alternatively or additionally, the substrate 299 includes another material, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, or an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. In some other embodiments, the substrate 299 includes one or more III-V materials, one or more II-IV materials, or a combination thereof. In some other embodiments, the substrate 299 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some other embodiments, the substrate 299 may include an active region.

[0045] In some embodiments, the substrate 299 includes various conductive regions 299E configured according to the design specification, such as a source region or a drain region, which includes an epitaxial material doped with a dopant (such as a p-type or n-type dopant). In some embodiments, the substrate 299 also includes transistors 299X and 299Y. In some embodiments, the transistors 299X and 299Y include fins, full-ring gate (GAA) structures, nanosheet structures, or other semiconductor structures, but the present disclosure is not limited thereto. The substrate 299 also includes a gate 299G (e.g., a metal gate formed by replacing a gate operation) surrounding the transistors 299X and 299Y. In some embodiments, the substrate 299 also includes a conductive pattern 299F above the conductive region 299E. In some embodiments, the conductive pattern 299F is referred to as an "MD pattern" or "MOOD pattern", that is, a metal zero pattern above the oxide, which is configured to define an electrical connection from an active device (which may include a source / drain region). In some embodiments, the transistor 299X and the transistor 299Y are doped with different dopants, such as n-type dopants and p-type dopants, respectively.

[0046] The first insulating layer 207 is above the substrate 299. The first group of metal lines 202 extending along the main direction is arranged in the first insulating layer 207 and separated from the substrate 299. The first group of metal lines 202 includes multi-level metal lines, that is, multiple metal lines are arranged at two or more levels at different height levels. For example, the first group of metal lines 202 includes one or more first metal lines 202A arranged at a first level and one or more second metal lines 202B arranged at a second level above the first level. The first metal line 202A and the second metal line 202B are separated by a first portion of the insulating layer 207. In some embodiments, each top surface of the first metal line 202A is not physically connected to the bottom surface of each second metal line 202B through a conductive path. The bottom of the second metal line 202B is spaced apart from the top surface of the first metal line 202A in the vertical direction VD by a distance 202G (wherein the gap is filled by the first portion of the insulating layer 207), wherein the distance 202G is in the range of about 6nm to 15nm. In some embodiments, the distance 202G is less than 6nm resulting in dielectric breakdown. In some embodiments, the distance 202G is greater than 15nm, which violates certain design rules for reducing the size of the device, or in some cases, increases the height of other adjacent through holes and increases the difficulty of through hole manufacturing. The thickness T1 of the first metal line 202A is in the range of about 15nm to about 25nm, and the thickness T2 of the second metal line 202B is in the range of about 15nm to about 25nm. Thickness T1 or T2 less than 15nm may cause reliability problems. For example, dielectric breakdown or electron migration may occur. Thickness T1 or T2 greater than 25nm violates some design rules, which are intended to reduce the size of the device, cause parasitic capacitance problems, or increase the height of other adjacent through holes in some cases. In some embodiments, the material of the first metal line 202A and the second metal line 202B includes ruthenium (Ru), aluminum (Al), copper (Cu), tungsten (W) or other suitable materials with high conductivity.

[0047] In some embodiments, the first metal line 202A and the second metal line 202B are staggered, that is, at least a portion of the first metal line 202A does not overlap with the second metal line 202B in the vertical direction. Also, at least a portion of the second metal line 202B does not overlap with the first metal line 202A in the vertical direction VD; a portion of the first metal line 202A overlaps with the second metal line 202B in the vertical direction VD, thereby reducing the unit height W( Figure 3). The first conductive via 201A is electrically connected between the conductive pattern 299F and the bottom surface of the first metal line 202A, and the second conductive via 201B is electrically connected between the gate 299G and the bottom surface of the second metal line 202B. The bottom surface of the second conductive via 201B and the bottom surface of the first conductive via 201A may be connected to the top surface of the substrate 299. The height H1 of the first conductive via 201A is in the range of about 8 nm to about 20 nm, and the height H2 of the second conductive via 201B is greater than the height H1, for example, in the range of about 30 nm to about 40 nm. Forming the second conductive via 202A with a height H2 greater than 40 nm may be difficult in some cases, have a greater body resistance, require a difficult high aspect ratio etching operation, or face void problems in a deposition operation. Since the interval between the first conductive via 201A and the second conductive via 201B is too small, the height H1 of the first conductive via 201A greater than 20nm or the height H2 less than 30nm faces the problem of dielectric breakdown. In some cases, the height H1 greater than 20nm faces the problem of increased body resistance. For example, voids may appear during the deposition operation, the etching operation becomes more difficult and / or the total body resistance becomes larger due to the higher aspect ratio. The height H1 of the first conductive via 201A less than 8nm faces the problem of dielectric breakdown or reliability. For example, a coupling effect may occur between the first metal line 202A and the underlying gate structure, which may affect the electrical signal. Although in FIG. 4A to FIG. 4B In the example shown, the first conductive via 201A and the second conductive via 201B are in different cross sections, but it will be understood by those skilled in the art that the present disclosure is not limited thereto. In some alternative embodiments, the first conductive via 201A and the second conductive via 201B are partially or completely aligned and are therefore shown in one cross section. In some embodiments, the lateral distance between the first conductive via 201A and the second conductive via 201B is in the range of about 6nm to about 10nm. When the lateral distance is less than 6nm, dielectric breakdown problems may occur in some cases. A lateral distance greater than 10nm violates some design rules for reducing device size.

[0048] The third metal line 212 extending along the secondary direction SD is above the first metal line 202A and the second metal line 202B and is perpendicular to the first metal line 202A and the second metal line 202B. The third conductive via 203 is electrically connected between the third metal line 212 and the top surface of the first metal line 202A (or in some alternative embodiments, the top surface of the second metal line 202B). In some embodiments, the portion of the first insulating layer 207 that intersects the first metal line 202A and the second metal line 202B is penetrated by the second conductive via 201B and the third conductive via 203. The thickness T3 of the third metal line 212 is in the range of about 20nm to about 30nm. A thickness T3 less than 20nm faces reliability issues, and a thickness T3 greater than 30nm violates some design rules intended to reduce device size. The distance H3 between the top surface of the second metal line 202B and the bottom surface of the third metal line 212 is in the range of about 10nm to about 30nm. In the case where the height H3 is greater than 30 nm or in some cases, it is difficult to form the third conductive via 203, the third conductive via 203 has a greater body resistance or faces void problems during deposition operations. A height H3 less than 10 nm faces reliability issues such as dielectric breakdown.

[0049] The second insulating layer 217 is above the third metal line 212. The second group of metal lines 222 extending along the main direction are disposed in the second insulating layer 217 and are separated from the third metal line 212. In some embodiments, the second group of metal lines 222 also includes multiple horizontal metal lines configured similarly to the first metal line 202A and the second metal line 202B, for example, a fourth metal line 222A at the third level and a fifth metal line 222B at the fourth level above the third layer. The third conductive via 213 is connected between the third metal line 212 and the fifth metal line 222B, and the fourth conductive via 221 is connected between the fourth metal line 222A and the third metal line 212. In some alternative embodiments, the second group of metal lines 222 includes multiple metal lines at one level.

[0050] In some embodiments, a protective layer 231 is provided to line the sidewalls of the first metal line 202A, the second metal line 202B, the fourth metal line 222A, and / or the fifth metal line 222B. The protective layer 231 includes an insulating material, such as a high-k material, silicon nitride, a nitride-based material, or a type of metal oxide with a high resistivity. The protective layer 231 is used as a barrier layer to separate the conductive portion of the above-mentioned metal line from the adjacent conductive vias (e.g., the second conductive via 201B, the third conductive via 203, and / or the third conductive via 213), thereby alleviating the problem of electrical short circuit. In some embodiments, the thickness T4 of the protective layer 231 is in the range of about 3nm to about 7nm, or in the range of about one-third of the thickness of the metal line, so that the protective layer 231 can effectively alleviate the problem of electrical short circuit. When the thickness T4 of the protective layer 231 is thicker than the aforementioned value, the protective layer 231 may undesirably reduce the space for forming adjacent conductive components and / or increase the total resistance of the semiconductor device 200. In some embodiments, the top surface of the protection layer 231 is located below the coverage of the vertical projection area of ​​the second metal line.

[0051] Reference Figure 5A and Figure 5B , Figure 5A is a cross-sectional view of a semiconductor structure. Figure 5B is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure. FIG. 5A to FIG. 5B The semiconductor structure 200' shown in FIG. FIG. 4A to FIG. 4B The semiconductor structure 200 shown in FIG. 2 is different in that the protective layer 231 is in direct physical contact with the second conductive via 201B, the third conductive via 203 and / or the third conductive via 213. Specifically, due to the overlapping displacement problem of the conductive vias, the reduction of the landing area of ​​the advanced technology node and / or other limitations on the precision of the manufacturing process, the position of the conductive via may be offset, so that the landing area overlaps with the adjacent metal line. Thus, the protective layer 231 separates the conductive via from the conductive portion of the metal line. In some embodiments, at least a portion of the sidewall of the protective layer 231 is in direct contact with the second conductive via 201B, the third conductive via 203 and / or the third conductive via 213. The top surface of the protective layer 231 is in direct contact with the second conductive via 201B, the third conductive via 203 and / or the third conductive via 213. In some embodiments, the thickness T4 of the protection layer 231 is in a range from about 3 nm to about 7 nm or is about one-third of the thickness of the metal line, so that the protection layer 231 can effectively alleviate the problem of electrical short circuit (for example, the top surface of the first metal line 202A is not directly in contact with the second conductive via 201B). When the thickness T4 of the protection layer 231 is greater than the aforementioned value, the protection layer 231 may undesirably reduce the space for forming adjacent conductive features and / or increase the overall resistance of the semiconductor device 200'.

[0052] refer to Figure 6 , Figure 6 A flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure is shown. The method 1000 for manufacturing a semiconductor device includes: providing a substrate (operation 1001, for example, see Fig. 7A ), forming a first insulating material over the substrate (operation 1004, see Fig. 7A ), forming a first conductive via in the first insulating material (operation 1007, see for example Fig. 7A ), forming a first insulating material over the first conductive via (operation 1013, see for example Figure 7B ), forming a first recess above the first conductive via in the first insulating material (operation 1018, see, for example Figure 7C ), forming a second insulating material lining the sidewalls of the first recess (operation 1024, see for example FIG. 7D to FIG. 7E ), forming a first metal line in the first groove (operation 1029, see e.g. Figure 7F ), forming a second conductive via, the height of the second conductive via being greater than the height of the first conductive via (operation 1034, see for example Figure 7G ), forming a second metal line over the top surface of the second conductive line (operation 1039, see for example Fig.7I ), forming a third metal line over the second metal line (operation 1044, see Figure 7J ).

[0053] A person of ordinary skill in the art will appreciate that although in this example, each of the first conductive via 201A and the second conductive via 201B (and so on) is 7A to 7J Although shown in cross-sectional views, the scope of the present disclosure also includes embodiments in which one or more of the aforementioned elements are arranged in different positions, which are shown in different cross-sections.

[0054] refer to Fig. 7A , Fig. 7A is a cross-sectional view of a semiconductor structure during an intermediate stage of manufacturing operations according to some embodiments of the present disclosure. A substrate 299 is provided, wherein the material and configuration of the substrate 299 are similar to FIG. 4A to FIG. 4B . A first insulating layer 207 is formed over the substrate 299. One or more first conductive vias 201A are formed over the substrate 299 and in the first insulating layer 207. In some embodiments, a planarization operation, such as a chemical mechanical planarization (CMP) operation, is performed from the top surface of the first insulating layer 207 to remove excess material of the first conductive vias 201A. After the planarization operation, the height H1 of the first conductive vias 201A is in a range from about 30 nm to about 40 nm. As previously discussed in FIG. 4A to FIG. 4B As discussed in , in some cases, a height H1 greater than 20 nm faces the problem of increased bulk resistance. A height H1 of the first conductive via 201A less than 8 nm faces dielectric reliability issues, such as breakdown issues.

[0055] Reference Figure 7B , Figure 7B is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A layer of a first insulating layer 207 is also disposed above the top surface of the first conductive via 201A. The thickness TH1 of the first insulating layer 207 after deposition is greater than the height H1. Figure 7C , Figure 7C 2 is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A first recess RA1 along the main direction PD is formed above each first conductive via 201A and in the first insulating layer 207 (e.g., by patterning and / or etching), and at least a portion of the top surface of the conductive via 201A is exposed.

[0056] refer to Fig.7D , Fig.7D 2 is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. An insulating material 231M is blanket deposited over the exposed top surface of the first conductive via 201A, the sidewalls of the first recess RA1, and the top surface of the first insulating layer 207. In some embodiments, the insulating material 231M includes a high-k material, silicon nitride, a nitride-based material, or a type of metal oxide with high resistivity, etc.

[0057] refer to Fig. 7E , Fig. 7E 2 is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. An etching operation 231E, such as anisotropic dry etching, is performed to remove a portion of the insulating material 231M above the top surface of the first conductive via 201A and a portion of the insulating material 231M above the top surface of the first insulating layer 207. A portion of the top surface of the first conductive via 201A is exposed. In some embodiments, at least a portion of the insulating material 231M remains above the sidewalls of the first recess RA1, which is FIG. 7F to FIG. 7J In some embodiments, the thickness T4 of the protective layer 231 is in the range of about 3 nm to about 7 nm, or is subsequently Figure 7FWhen the thickness T4 of the protective layer 231 is greater than the aforementioned value, the protective layer 231 may undesirably reduce the space for forming adjacent conductive features and / or increase the overall resistance of the semiconductor device 200'. When the thickness T4 of the protective layer 231 is less than the aforementioned value, the protective layer 231 may not effectively mitigate the problem of electrical short circuits.

[0058] Reference Figure 7F , Figure 7F 2 is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A first metal line 202A extending along the main direction PD is formed in the first groove RA1, whereby the protective layer 231 lines the sidewalls of the first metal line 202A. In some embodiments, the material of the first metal line 202A includes ruthenium (Ru), aluminum (Al), copper (Cu), tungsten (W), or other conductive materials. In some embodiments, a planarization operation such as a CMP operation is performed to remove excess material of the first metal line 202A.

[0059] refer to Figure 7G , Figure 7G is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A layer of a first insulating layer 207 is further disposed above the top surface of the first metal line 202A, and one or more second conductive vias 201B are formed in the first insulating layer 207. The presence of the protective layer 231 allows the second conductive vias 201B to not be in direct contact with the conductive portion of the first metal line 202A during the manufacturing operation. In some embodiments, a planarization operation such as a CMP operation is performed to remove excess material of the second conductive via 201B. When the top surface of the second conductive via 201B is above the top surface of the first metal line 202A, the planarization operation stops, so that after the planarization operation, the height H2 of the second conductive via 201B is greater than the height H1 (e.g., FIG. 7A to FIG. 7B ), for example, height H2 is in the range of about 30 nm to about 40 nm. (Evidence of the criticality of height H2 was previously reported in FIG. 4A to FIG. 4B (discussed in ) In some embodiments, the bottom surface of the second conductive via 201B is flush with the bottom surface of the first conductive via 201A. In some embodiments, as Figure 4A and Figure 4B As discussed in , the second conductive via 201B is between the protection layer 231 lining two adjacent first metal lines 202A. In some alternative embodiments, such as Figure 5A and Figure 5BAs discussed in , due to the overlap shift problem or precision limitation, some second conductive vias 201B are in direct contact with the sidewalls of the protection layer 231. In some embodiments, the second conductive vias 201B are in direct contact with the top surface of the protection layer 231.

[0060] refer to Figure 7H , Figure 7H is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A layer of a first insulating layer 207 is further disposed over the top surface of the second conductive via 201B, and a second recess RA2 is further formed over the second conductive via 201B along the main direction PD, such as by patterning and / or etching. Similar to FIG. 7C to FIG. 7E According to the operation discussed in the above, a protection layer 231 lining the sidewalls of the second recess RA2 is formed.

[0061] refer to Fig.7I , Fig.7I 2 is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A second metal line 202B extending along the main direction PD is formed in each second recess RA2. In some embodiments, the material of the second metal line 202B includes ruthenium (Ru), aluminum (Al), copper (Cu), tungsten (W), or other conductive materials. In some embodiments, a planarization operation such as a CMP operation is performed to remove excess material of the second metal line 202B.

[0062] refer to Figure 7J , Figure 7J 2 is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A layer of a first insulating layer 207 is further disposed over a top surface of the second metal line 202B. A third conductive via 203 is formed over a top surface of the first metal line 202A and / or a top surface of the second metal line 202B. In some embodiments, a planarization operation such as a CMP operation is performed to remove excess material of the third conductive via 203. Figure 4A and Figure 4B As discussed in , the third conductive via 203 is between the protection layer 231 lining two adjacent second metal lines 202B. In some alternative embodiments, such as Figure 5A and Figure 5B As discussed in , due to the overlap shift problem or precision limitation, some of the third conductive vias 203 are in direct contact with the sidewalls of the protection layer 231. In some embodiments, the third conductive vias 203 are in direct contact with a portion of the protection layer 231. A third metal line 212 extending along the secondary direction SD is formed above the third conductive via 203. Similar operations may be repeated in the metal layer above the third metal line 212, such as FIG. 4A to FIG. 5B The embodiment shown.

[0063] refer to Fig. 8A and Figure 8B , according to some embodiments of the present disclosure, Fig. 8A is along Figure 3 A cross-sectional view of the semiconductor structure along line AA′ in FIG. Figure 8B is along Figure 3 Cross-sectional view of the semiconductor structure along line BB′ in FIG. Fig. 8A and Figure 8B The semiconductor structure 300 shown is similar to Figure 4A and Figure 4B The semiconductor structure 200 shown in FIG. Fig. 8A and Figure 8B ) and the protective layer 231 (as shown FIG. 4A to FIG. 4B The difference between the protective layer 231' and the third conductive via 203 is that the protective layer 231' also includes a top portion, which covers at least a portion of the top surface of the metal line (such as the first metal line 202A, the second metal line 202B, the fourth metal line 222A and / or the fifth metal line 222B). The protective layer 231' further improves the protection of the top surface of the metal line to prevent undesired direct contact with adjacent conductive vias. In some embodiments, the thickness T5 of the top of the protective layer 231' is similar to the thickness T4 of the side wall of the protective layer 231', taking into account the compromise between total resistance and electrical short circuit. In some embodiments, the third conductive via 203 penetrates the top of the protective layer 231' and is connected to the top surface of the conductive portion of the first metal line 202A and / or the top surface of the second metal line 202B.

[0064] refer to Fig. 9A and Fig. 9B , according to some embodiments of the present disclosure, Fig. 9A is a cross-sectional view of a semiconductor structure. Fig. 9B It is a cross-sectional view of a semiconductor structure. FIG. 9A to FIG. 9B The semiconductor structure 300′ shown in FIG. FIG. 8A to FIG. 8B The semiconductor structure 300 shown. The difference is that the protective layer 231 is in direct physical contact with the second conductive via 201B, the third conductive via 203 and / or the third conductive via 213. Specifically, due to the overlapping displacement problem of the conductive vias, the landing area of ​​the conductive layer is reduced. Due to the advanced technology nodes and / or other limitations on the precision of the manufacturing process, the position of the conductive via is offset, so that its landing area overlaps with the adjacent metal line. As a result, the protective layer 231' separates the conductive via from the conductive portion of the metal line. In some embodiments, at least a portion of the sidewall of the protective layer 231' is in direct contact with the second conductive via 201B, the third conductive via 203 and / or the third conductive via 213. The top surface of the protective layer 231' is in direct contact with the second conductive via 201B, the third conductive via 203 and / or the third conductive via 213.

[0065] refer to Fig.10 , Fig.10 A flow chart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure is shown. The method 2000 for manufacturing a semiconductor device includes providing a substrate (operation 2001, for example, see Fig.11A ), forming a first insulating material over the substrate (operation 2004, see for example Fig.11A ), forming a first conductive via in the first insulating via (operation 2007, see for example Fig.11A ), forming a first insulating material over the first conductive via (operation 2013, see for example Fig. 11B ), a first recess is formed above the first conductive via in the first insulating material (operation 2018, see for example Fig. 11C ), forming a second insulating material lining the sidewalls of the first recess (operation 2024, see for example FIG. 11D to FIG. 11E ), forming a first metal line in the first groove (operation 2029, see for example Fig.11F ), removing a portion of the first metal line (operation 2031, see for example Fig.11G ), forming a second insulating material on the first metal line (operation 2033, see Fig.11H ), forming a second conductive via with a height greater than that of the first conductive via (operation 2034, see for example Figure 11K ), forming a second metal line over the top surface of the second conductive line (operation 2039, see for example Fig.11O ), and forming a third metal line over the second metal line (operation 2044, see for example Figure 11S ).

[0066] A person of ordinary skill in the art will appreciate that although in this example, each of the first conductive via 201A and the second conductive via 201B (and so on) is FIG. 11A to FIG. 11S Although shown in cross-sectional views, the scope of the present disclosure also includes embodiments in which one or more of the aforementioned elements are arranged in different positions, which are shown in different cross-sections.

[0067] Reference Fig.11A , Fig.11A is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A substrate 299 is provided, wherein the material of the substrate 299 is similar to FIG. 4A to FIG. 4BA first insulating layer 207 is formed over the substrate 299. One or more first conductive vias 201A are formed over the substrate 299 and in the first insulating layer 207. In some embodiments, a planarization operation, such as a chemical mechanical planarization (CMP) operation, is performed to remove excess material of the first conductive vias 201A from the top surface of the first insulating layer 207. After the planarization operation, in some embodiments, the height H1 of the first conductive vias 201A is in a range of about 30 nm to about 40 nm. Evidence of the criticality of the height H1 is previously discussed in FIG. 4A to FIG. 4B discussed in.

[0068] refer to Fig. 11B , Fig. 11B is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A layer of a first insulating layer 207 is also disposed above the top surface of the first conductive via 201A. The thickness TH1 of the first insulating layer 207 after deposition is greater than the height H1. Fig. 11C , Fig. 11C 2 is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A first recess RB1 along the main direction PD is formed above each first conductive via 201A and in the first insulating layer 207 (such as by patterning and / or etching) and exposes at least a portion of the top surface of the conductive via 201A.

[0069] refer to Fig.11D , Fig.11D 2 is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. An insulating material 231M' is blanket deposited over the exposed top surface of the first conductive via 201A, the sidewalls of the first recess RB1, and the top surface of the first insulating layer 207. In some embodiments, the insulating material 231M' includes a high-k material, silicon nitride, a nitride-based material, or a type of metal oxide with high resistivity, etc.

[0070] refer to Fig.11E , Fig.11E is a cross-sectional view of a semiconductor structure during an intermediate stage of manufacturing operations according to some embodiments of the present disclosure. Fig. 7E In the operation of performing an etching operation 231E, such as anisotropic dry etching, to remove a portion of the insulating material 231M' above the top surface of the first conductive via 201A and a portion of the insulating material 231M' above the top surface of the first insulating layer 207. A portion of the top surface of the first conductive via 201A is exposed. In some embodiments, at least a portion of the insulating material 231M' remains above the sidewalls of the first recess RB1. FIG. 11F to FIG. 11S It is referred to as protection layer 231'.

[0071] refer to Fig.11F , Fig.11F 2 is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A first metal line 202A extending along the main direction PD is formed in a first groove RB1, whereby a protective layer 231' lines the sidewalls of the first metal line 202A. In some embodiments, the first metal line 202A includes ruthenium (Ru), tungsten (W), aluminum (Al), etc. In some embodiments, a planarization operation such as a CMP operation is performed to remove excess material of the first metal line 202A.

[0072] refer to Fig.11G , Fig.11G 2 is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A portion of the first metal line 202A is removed from the top by an etch-back operation to form a second groove RB2 along the main direction PD. Fig.11F As discussed in , the etch-back operation is easier for materials such as ruthenium (Ru), tungsten (W), and aluminum (Al) than for some other types of conductive materials.

[0073] refer to Fig.11H , Fig.11H 2 is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. An additional layer of insulating material 231M' is blanket deposited to line the second recess RB2 and over the first metal line 202A and the first insulating layer 207. In some embodiments, the top surface of the insulating material 231M' is non-uniform after the blanket deposition.

[0074] Reference Image Fig.11I , Fig.11I is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. In some embodiments, a planarization operation such as a CMP operation is performed to remove excess material of the insulating material 231M'.

[0075] refer to Figures 11J to 11K , Fig.11J is a cross-sectional view of a semiconductor structure during an intermediate stage of manufacturing operations. Figure 11Kis a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A layer of a first insulating layer 207 is further disposed on a top surface of the first metal line 202A, and one or more second conductive vias 201B are formed in the first insulating layer 207. The presence of the protective layer 231' allows the second conductive vias 201B to not be in direct contact with the conductive portion of the first metal line 202A during the manufacturing operation. In some embodiments, a planarization operation such as a CMP operation is performed to remove excess material of the second conductive via 201B. When the top surface of the second conductive via 201B is above the top surface of the first metal line 202A, the planarization operation is stopped, so that after the planarization operation, the height H2 of the second conductive via 201B is greater than the height H1 (e.g., Fig.11A and Fig. 11B ), for example, height H2 is in the range of about 30 nm to about 40 nm. (Evidence of the criticality of height H2 was previously reported in FIG. 4A to FIG. 4B In some embodiments, such as Fig. 8A and Figure 8B As discussed in , the second conductive via 201B is between the protection layer 231' lining two adjacent first metal lines 202A. In some alternative embodiments, such as Fig. 9A and Fig. 9B As discussed in , due to the overlap shift problem or precision limitation, some second conductive vias 201B directly contact the sidewalls of the protection layer 231 '. In some embodiments, the second conductive vias 201B directly contact portions of the top surface and the sidewalls of the protection layer 231 '.

[0076] refer to Fig.11L , Fig.11L is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. An additional layer of the first insulating layer is formed over the second conductive vias 201B, and a third recess RB3 is formed over each second conductive via 201B.

[0077] refer to Fig.11M , Fig.11M is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. Insulating material 231M′ is blanket deposited over the exposed top surface of second conductive via 201B, the sidewalls of third recess RB3 , and the top surface of first insulating layer 207 .

[0078] refer to Fig.11N , Fig.11N is a cross-sectional view of a semiconductor structure during an intermediate stage of manufacturing operations according to some embodiments of the present disclosure. Fig. 7E and Fig.11EIn the operation of performing an etching operation 231E, such as anisotropic dry etching, to remove a portion of the insulating material 231M' above the top surface of the first conductive via 201A and a portion of the insulating material 231M' above the top surface of the first insulating layer 207. At least a portion of the insulating material 231M' remains above the sidewall of the third recess RB3.

[0079] refer to Fig.11O , Fig.11O is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A second metal line 202B extending along the main direction PD is formed in the third groove RB3, so that the protection layer 231' lines the sidewalls of the second metal line 202B. In some embodiments, the second metal line 202B includes ruthenium (Ru), tungsten (W), aluminum (Al), etc. In some embodiments, a planarization operation such as a CMP operation is performed to remove excess material of the second metal line 202B.

[0080] refer to Figure 11P , Figure 11P is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A portion of the first metal line 202A is removed from the top by an etch-back operation to form a fourth recess RB4.

[0081] refer to Figure 11Q , Figure 11Q is a cross-sectional view of a semiconductor structure during an intermediate stage of fabrication operations according to some embodiments of the present disclosure. An additional layer 231M′ of insulating material is blanket deposited to line the fourth recess RB4 and over the second metal line 202B and the first insulating layer 207 .

[0082] refer to Figure 11R , Figure 11R is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. In some embodiments, a planarization operation such as a CMP operation is performed to remove excess material of the insulating material 231M'.

[0083] Reference Figure 11S , Figure 11S 2 is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A layer of a first insulating layer 207 is further disposed over a top surface of the second metal line 202B. A third conductive via 203 may be formed over a top surface of the first metal line 202A and / or a top surface of the second metal line 202B. In some embodiments, a planarization operation such as a CMP operation is performed to remove excess material of the third conductive via 203. In some embodiments, as Fig. 8A and Figure 8BAs discussed, the third conductive via 203 is between the protection layer 231' lining two adjacent second metal lines 202B. Fig. 9A and Fig. 9B As discussed in , due to the overlap shift problem or precision limitation, some third conductive vias 203 are in direct contact with the top surface and sidewalls of the protection layer 231 ′. A third metal line 212 extending along the secondary direction SD is formed above the third conductive via 203. In some embodiments, similar operations are repeated in the metal layer above the third metal line 212, such as FIG. 8A to FIG. 9B The embodiment shown.

[0084] refer to Fig. 12A and Fig. 12B , according to some embodiments of the present disclosure, Fig. 12A is along Figure 3 A cross-sectional view of the semiconductor structure along line AA' in FIG. Fig. 12B is along Figure 3 A cross-sectional view of the semiconductor structure taken along line BB' in FIG. Fig. 12A and Fig. 12B The semiconductor structure 400 shown is similar to Figure 4A and Figure 4B The semiconductor structure 200 (and Figure 5A and Figure 5B The difference lies in the relative position and connection between the first metal line 202A and the second metal line 202B (also applicable to the fourth metal line 222A and the fifth metal line 222B). FIG. 4A to FIG. 4B In the illustrated embodiment, the bottom surface of each second metal line 202B is not directly connected and physically connected to the top surface of the first metal line 202A through a conductive path such as a metal via. FIG. 12A to FIG. 12B In the illustrated embodiment, at least one of the second metal lines 202B has a bottom surface connected to the top surface of the first metal line 202A through the auxiliary conductive via 204. In some embodiments, one of the second metal lines 202B is electrically connected to a conductive region 299E having a first type of conductivity (such as p-type), and the other second metal line 202B is electrically connected to a conductive region 299E having a second type of conductivity (such as n-type). In this way, one of the second metal lines 202B is connected to a power supply voltage and the other of the second metal lines 202B is connected to a ground voltage. The semiconductor structure 400 can be used in the technical field of high-power semiconductor devices, where power consumption is an issue and therefore, in some cases, factors related to reducing the overall resistance are more dominant. Each first metal line 202A is wider than the second metal line 202B. In some embodiments, in order to reserve a landing area for the auxiliary conductive via 204, the width W1 of the first metal line 202A along the secondary direction SD is wider than the second metal line 202B. Figure 4A and Figure 4B The embodiment shown is wide. For example, the width W1 is sufficient to form a via landing space for the auxiliary conductive via 204. In other words, the vertical overlap between the second metal line 202B and the first metal line 202A should accommodate the width of the auxiliary conductive via 204. As previously described, the relative position / size trade-offs of the first metal line 202A and the second metal line 202B with respect to the total resistance (related to the width W1 of the first metal line 202A) and the parasitic capacitance (related to (1) the vertical distance between the first metal line 202A and the second metal line 202B and (2) the total vertical overlap area of ​​the first metal line 202A and the second metal line 202B) can be adjusted and tuned according to the design rules of different types of devices with different applications.

[0085] The present disclosure provides a semiconductor structure with a staggered via structure, which utilizes metal lines arranged in the same metal layer (i.e., in the same layer of the insulating layer) at two or more different height levels, and metal lines at a higher level partially overlapping the metal lines at the lower level, so that the overall device / unit size can be more compact and the device density can be increased. For example, Figures 1A to 2B As shown, even in advanced technology nodes, the total number of metal lines in one cell area is increased.

[0086] The present disclosure further provides methods and configurations that help achieve device size minimization while mitigating electrical short circuit issues by utilizing a protective layer 231 / 231'. The protective layer 231 / 231' acts as an electrical barrier between the conductive portion of the metal line and a nearby conductive via on the side, so that even if the landing area of ​​the conductive via overlaps the metal line due to overlay shift or similar precision issues, the conductive via is spaced apart from the nearby metal line, which increases the tolerance of the conductive via's landing area accuracy in advanced technology nodes (particularly in BEOL processes).

[0087] Specifically, in FIG. 4A to FIG. 7B In the first type of embodiment shown, the protection layer 231 is used to protect the sidewalls and / or peripheral portions of the top surface of the metal line. A method for forming the protection layer 231 using anisotropic etching compatible with the staggered via structure is also provided. FIG. 8A to FIG. 11S In the second type of embodiment shown, a protective layer 231' is used to protect the sidewalls and top surface of the metal line. A method of forming the protective layer 231' by further using an etch-back operation is provided, wherein among various types of conductive materials, ruthenium (Ru), aluminum (Al), and tungsten (W) are suitable for this technology. FIG. 12A to FIG. 12BIn the third type of embodiment shown, auxiliary vias 204 are used to connect metal lines disposed in the same metal layer but at two or more different height levels, and the width of the metal lines at the lower level is increased. This configuration helps to further minimize the overall device resistance and reduce power consumption.

[0088] The aforementioned techniques also allow adjustment of the size of each metal line, the relative position of each metal line at different levels, the degree of overlap between metal lines at different levels, the thickness of the protective layer, etc., to adjust the total resistance and parasitic capacitance (or their compromise) to comply with design rules tailored for different types of devices with specified specific functions.

[0089] Some embodiments of the present disclosure provide a semiconductor structure including: a substrate; a first metal line located above the substrate and extending along a first direction; a protective layer lining the sidewalls of the first metal line; a second metal line located on the first metal line and extending along the first direction; and a third metal line located above the second metal line and extending along a second direction perpendicular to the first direction.

[0090] In the above semiconductor structure, it also includes a first conductive via connected to the bottom of the second metal line, wherein the first conductive via is in direct contact with the protection layer.

[0091] In the above semiconductor structure, it also includes a second conductive via connected to the bottom surface of the first metal line, wherein a height of the first conductive via is greater than a height of the second conductive via.

[0092] In the above semiconductor structure, the first conductive via covers at least a portion of a top surface of the protection layer.

[0093] In the above semiconductor structure, in a top view, the protection layer overlaps with the second metal line.

[0094] In the above semiconductor structure, the protection layer includes an electrically insulating material.

[0095] In the above semiconductor structure, a vertical interval between a bottom surface of the second metal line and a top surface of the first metal line is in a range of 6 nm to 15 nm.

[0096] In the above semiconductor structure, a third conductive via connected to the top surface of the first metal line is further included, wherein a portion of the third conductive via is located above the top surface of the second metal line.

[0097] Some embodiments of the present disclosure provide a semiconductor structure including: a substrate; a first insulating layer located above the substrate; a plurality of first metal wires located at a first level of the first insulating layer, wherein each of the plurality of first metal wires extends along a first direction; and a plurality of second metal wires, wherein each of the plurality of second metal wires extends along the first direction and is located at a second level of the first insulating layer above the first level, a first metal wire among the plurality of first metal wires and a second metal wire among the plurality of second metal wires are arranged in a staggered manner, a first portion of the first insulating layer is located between a bottom surface of each of the plurality of second metal wires and a top surface of each of the plurality of first metal wires, and a height of the first portion is in the range of 6nm to 15nm.

[0098] In the above interconnect structure, it also includes a first conductive via that traverses the first portion of the first insulating layer, wherein the first conductive via connects a bottom surface of a second metal line of the plurality of second metal lines to the substrate.

[0099] The above interconnect structure further includes a third metal line located above the plurality of second metal lines, wherein the third metal line extends along a second direction perpendicular to the first direction, and the first insulating layer is located below the third metal line.

[0100] In the above interconnection structure, a second conductive via is further included, and the second conductive via connects the top surface of the first metal line and the bottom surface of the third metal line among the plurality of first metal lines.

[0101] In the above interconnect structure, a portion of a second metal line among the plurality of second metal lines overlaps a first metal line among the plurality of first metal lines in a vertical direction.

[0102] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, the method comprising: depositing a first insulating material above a substrate, wherein the substrate includes an active area; etching the first insulating material to define a first groove extending along a first direction at a first level of the first insulating material; depositing a second insulating material to line the sidewalls of the first groove; and depositing a first metal line in the first groove.

[0103] In the above method, the further comprising: forming a second metal line extending along the first direction and located at a second level above the first level in the first insulating material, wherein the second metal line is offset relative to the first metal line.

[0104] In the above method, it also includes forming a first conductive via in the first insulating material.

[0105] In the above method, depositing a second insulating material lining the sidewalls of the first groove includes depositing a second insulating material over a top surface of the first metal line, wherein the second insulating material is different from the first insulating material.

[0106] In the above method, the method further includes depositing a third metal line over the second metal line, wherein the third metal line extends along a second direction substantially perpendicular to the first direction.

[0107] In the above method, it also includes: before depositing the third metal line at a third level above the second level of the first insulating material, depositing the first insulating material over the second metal line.

[0108] In the above method, forming the second metal line includes: etching the first insulating material to define a second groove located at a second level in the first insulating material and extending along the first direction; and depositing a conductive material in the second groove.

[0109] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

[0110] Moreover, the scope of the present application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods and steps described in the specification. As will be readily understood by those skilled in the art from the disclosure of the present invention, processes, machines, manufactures, material compositions, means, methods or steps that currently exist or will be developed in the future and perform substantially the same functions can achieve substantially the same results as the corresponding embodiments described herein according to the present invention. Therefore, the present application is intended to include such processes, machines, manufactures, material compositions, means, methods or steps within their scope.

Claims

1. A semiconductor structure comprising: substrate; A first metal line, located above the substrate and extending along a first direction; a protective layer lining the sidewall of the first metal line; a second metal line, located on the first metal line and extending along the first direction; a first conductive via connected to a bottom of the second metal line, wherein the protection layer is located between the first metal line and the first conductive via; as well as The third metal line is located above the second metal line and extends along a second direction perpendicular to the first direction.

2. The semiconductor structure according to claim 1, wherein: The first conductive via is in direct contact with the protection layer.

3. The semiconductor structure of claim 2, further comprising a second conductive via connected to a bottom surface of the first metal line, wherein: The height of the first conductive via is greater than the height of the second conductive via.

4. The semiconductor structure according to claim 2, wherein: The first conductive via covers at least a portion of a top surface of the protection layer.

5. The semiconductor structure according to claim 1, wherein: In a top view, the protection layer overlaps the second metal line.

6. The semiconductor structure according to claim 1, wherein: The protective layer includes an electrically insulating material.

7. The semiconductor structure according to claim 1, wherein: A vertical spacing between a bottom surface of the second metal line and a top surface of the first metal line is in a range of 6 nm to 15 nm.

8. The semiconductor structure of claim 1, further comprising a third conductive via connected to a top surface of the first metal line, wherein A portion of the third conductive via is located above a top surface of the second metal line.

9. An interconnect structure comprising: substrate; A first insulating layer, located above the substrate; a plurality of first metal lines located at a first level of the first insulating layer, wherein each of the plurality of first metal lines extends along a first direction; a protective layer lining a sidewall of one of the plurality of first metal lines; a plurality of second metal lines, wherein each of the plurality of second metal lines extends in a first direction and is located at a second level of the first insulating layer above the first level, first metal lines of the plurality of first metal lines and second metal lines of the plurality of second metal lines are arranged in a staggered manner, a first portion of the first insulating layer is located between a bottom surface of each of the plurality of second metal lines and a top surface of each of the plurality of first metal lines, and a height of the first portion is in a range of 6 nm to 15 nm; and A first conductive via is connected to a bottom of one of the plurality of second metal lines, wherein the protection layer is located between the one of the plurality of first metal lines and the first conductive via.

10. The interconnect structure according to claim 9, wherein: The first conductive via traverses the first portion of the first insulating layer, wherein the first conductive via connects a bottom surface of a second metal line of the plurality of second metal lines to the substrate.

11. The interconnect structure according to claim 9, further comprising a third metal line located above the plurality of second metal lines, wherein The third metal line extends along a second direction perpendicular to the first direction, and the first insulating layer is located under the third metal line. 12 . The interconnect structure of claim 11 , further comprising a second conductive via connecting a top surface of a first metal line of the plurality of first metal lines and a bottom surface of the third metal line.

13. The interconnect structure according to claim 9, wherein: Portions of second metal lines among the plurality of second metal lines overlap with first metal lines among the plurality of first metal lines in a vertical direction.

14. A method of forming a semiconductor structure, comprising: depositing a first insulating material over a substrate, wherein the substrate includes an active region; etching the first insulating material to define a first groove extending along a first direction at a first level of the first insulating material; depositing a second insulating material lining the sidewalls of the first recess; depositing a first metal line in the first groove; and A first conductive via is formed in the first insulating material, wherein the second insulating material is located between the first metal line and the first conductive via.

15. The method according to claim 14, further comprising: A second metal line is formed extending in the first direction and located at a second level above the first level in the first insulating material, wherein the second metal line is offset relative to the first metal line.

16. The method according to claim 14, wherein: The first conductive via is in direct contact with the second insulating material.

17. The method according to claim 14, wherein: Depositing the second insulating material lining the sidewalls of the first groove includes depositing the second insulating material over a top surface of the first metal line, wherein the second insulating material is different from the first insulating material.

18. The method according to claim 15, further comprising depositing a third metal line over the second metal line, wherein The third metal line extends in a second direction substantially perpendicular to the first direction.

19. The method according to claim 18, further comprising: The first insulating material is deposited over the second metal line before depositing the third metal line at a third level above the second level of the first insulating material.

20. The method according to claim 15, wherein: Forming the second metal line includes: etching the first insulating material to define a second groove located at a second level in the first insulating material and extending along a first direction; and A conductive material is deposited in the second groove.

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