Static random access memory and manufacturing method thereof

Abstract

The present invention discloses a static random access memory and a method for manufacturing the static random access memory, wherein the method for manufacturing the static random access memory is to first form a gate structure on a substrate, then form an epitaxial layer next to the gate structure, form a first interlayer dielectric layer surrounding the gate structure, convert the gate structure into a metal gate, form a contact hole to expose the epitaxial layer, form a barrier layer in the contact hole, form a metal layer on the barrier layer, and then flatten the metal layer and the barrier layer to form a contact plug, wherein the bottom of the barrier layer includes a titanium-rich portion and the top of the barrier layer includes a nitrogen-rich portion.

Description

Technical Field

[0001] The present invention relates to a static random access memory (SRAM), and in particular to a SRAM having a contact plug with a gradient concentration barrier layer. Background Art

[0002] An embedded static random access memory (embedded SRAM) includes a logic circuit and a static random access memory connected to the logic circuit. The static random access memory itself is a volatile memory cell, that is, when the power supplied to the static random access memory disappears, the stored data will be erased at the same time. The way in which static random access memory stores data is to use the conductive state of the transistor in the memory cell. The design of static random access memory is based on mutually coupled transistors. There is no problem of capacitor discharge, and it does not need to be continuously charged to keep the data from being lost. In other words, there is no need to update the memory. This is different from the way that dynamic random access memory (DRAM), which is also a volatile memory, uses the charged state of the capacitor to store data. The access speed of static random access memory is quite fast, so it is used as cache memory in computer systems.

[0003] However, as the manufacturing process line width and exposure pitch are reduced, it is difficult to use the existing structure to expose the desired pattern in the current SRAM device manufacturing. Therefore, how to improve the existing SRAM device structure to enhance the quality of exposure is an important issue today. Summary of the invention

[0004] An embodiment of the present invention discloses a method for manufacturing a static random access memory, wherein a gate structure is first formed on a substrate, an epitaxial layer is formed next to the gate structure, a first interlayer dielectric layer is formed to surround the gate structure, the gate structure is converted into a metal gate, a contact hole is formed to expose the epitaxial layer, a barrier layer is formed in the contact hole, a metal layer is formed on the barrier layer, and the metal layer and the barrier layer are planarized to form a contact plug, wherein the bottom of the barrier layer includes a titanium-rich portion and the top of the barrier layer includes a nitrogen-rich portion.

[0005] Another embodiment of the present invention discloses a static random access memory, which mainly includes a gate structure arranged on a substrate, an epitaxial layer arranged next to the gate structure, a first contact plug arranged on the epitaxial layer, a second contact plug arranged on the gate structure, a first interlayer dielectric layer surrounding the first contact plug, the second contact plug and the gate structure, a third contact plug arranged on the first contact plug, a fourth contact plug arranged on the second contact plug and a second interlayer dielectric layer surrounding the third contact plug and the fourth contact plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A layout diagram of a static random access memory according to a preferred embodiment of the present invention;

[0007] Figure 2 A circuit diagram of a group of six-transistor static random access memory (6T-SRAM) storage cells in the static random access memory of the present invention;

[0008] Figures 3 to 6 Schematic diagram of a method for manufacturing a 6T-SRAM memory cell according to an embodiment of the present invention.

[0009] Main component symbols

[0010] PL1: First pull-up transistor

[0011] PL2: Second pull-up transistor

[0012] PD1: First pull-down transistor

[0013] PD2: Second pull-down transistor

[0014] PG1: first access transistor

[0015] PG2: Second access transistor

[0016] WL: Character Line

[0017] BL: Bit Line

[0018] Vcc: voltage source

[0019] Vss: voltage source

[0020] 10: Six-transistor static random access memory

[0021] 24: Storage Node

[0022] 26: Storage Node

[0023] 28: Series circuit

[0024] 30: Series circuit

[0025] 52: Base

[0026] 54: Fin structure

[0027] 56: Shallow Trench Isolation

[0028] 58: Gate structure

[0029] 60: Gate structure

[0030] 62: Gate dielectric layer

[0031] 64: Gate material layer

[0032] 66: Hard mask

[0033] 68: Gap wall

[0034] 70: Source / drain region

[0035] 72: Epitaxial layer

[0036] 74: Contact hole etching stop layer

[0037] 76: Interlayer dielectric layer

[0038] 78: Dielectric layer

[0039] 80: High dielectric constant dielectric layer

[0040] 82: Work function metal layer

[0041] 84: Low impedance metal layer

[0042] 86:Metal Gate

[0043] 88: Hard mask

[0044] 90: Contact plug

[0045] 92: First barrier layer

[0046] 94: Second barrier layer

[0047] 96:Metal silicide

[0048] 98:Metal layer

[0049] 100: First floor

[0050] 102: Second floor

[0051] 104: Stop layer

[0052] 106: interlayer dielectric layer

[0053] 108: Contact plug

[0054] 110: Contact plug

[0055] 112: Intermetallic dielectric layer

[0056] 114:Metal interconnect DETAILED DESCRIPTION

[0057] In order to enable a person of ordinary skill in the art to which the present invention belongs to further understand the present invention, the preferred embodiments of the present invention are listed below, and the components of the present invention and the effects to be achieved are described in detail in conjunction with the attached drawings. For the convenience of explanation, the drawings of the present invention are only for illustration to make it easier to understand the present invention, and the detailed proportions can be adjusted according to the design requirements. The upper and lower relationships of the relative elements in the figures described in the text should be understood by those in the art to refer to the relative positions of the objects, so they can be flipped to present the same components, which should all belong to the scope disclosed in this specification, and will be described here first.

[0058] Please refer to Figure 1 and Figure 2 , Figure 1 is a layout diagram of a static random access memory according to a preferred embodiment of the present invention, Figure 2 The circuit diagram of a group of six-transistor SRAM (6T-SRAM) storage cells in the SRAM of the present invention is shown in FIG. Figure 1 and Figure 2 As shown, the SRAM of the present invention preferably comprises at least one group of SRAM cells, wherein each SRAM cell comprises a six-transistor SRAM cell (6T-SRAM) 10 .

[0059] In the present embodiment, each 6T-SRAM memory cell 10 preferably comprises a first pull-up transistor PL1, a second pull-up transistor PL2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first access transistor PG1 and a second access transistor PG2 to form a flip-flop, wherein the first pull-up transistor PL1 and the second pull-up transistor PL2, the first pull-down transistor PD1 and the second pull-down transistor PD2 form a latch circuit, so that data can be latched at the storage node 24 or 26. In addition, the first pull-up transistor PL1 and the second pull-up transistor PL2 are used as active loads, and they can also be replaced by general resistors as pull-up elements, in which case it is a four-transistor SRAM (4T-SRAM). In addition, in the present embodiment, a source region of each of the first pull-up transistor PL1 and the second pull-up transistor PL2 is electrically connected to a voltage source Vcc, and a source region of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 is electrically connected to a voltage source Vss.

[0060] Generally speaking, the first pull-up transistor PL1 and the second pull-up transistor PL2 of the 6T-SRAM memory cell 10 are composed of P-type metal oxide semiconductor (PMOS) transistors, while the first pull-down transistor PD1, the second pull-down transistor PD2 and the first access transistor PG1, the second access transistor PG2 are composed of N-type metal oxide semiconductor (NMOS) transistors. The first pull-up transistor PL1 and the first pull-down transistor PD1 together form an inverter, and the two ends of the series circuit 28 formed by the two are respectively coupled to a voltage source Vcc and a voltage source Vss; similarly, the second pull-up transistor PL2 and the second pull-down transistor PD2 form another inverter, and the two ends of the series circuit 30 formed by the two are also respectively coupled to the voltage source Vcc and the voltage source Vss.

[0061] In addition, the gates of the second pull-down transistor PD2 and the second pull-up transistor PL2, and the drains of the first pull-down transistor PD1, the first pull-up transistor PL1, and the first access transistor PG1 are electrically connected to the storage node 24. Similarly, the gates of the first pull-down transistor PD1 and the first pull-up transistor PL1, and the drains of the second pull-down transistor PD2, the second pull-up transistor PL2, and the second access transistor PG2 are electrically connected to the storage node 26. The gates of the first access transistor PG1 and the second access transistor PG2 are coupled to the word line WL, and the sources of the first access transistor PG1 and the second access transistor PG2 are coupled to the corresponding bit line BL.

[0062] Please refer to Figures 3 to 6 , Figures 3 to 6 FIG. 1 is a schematic diagram of a method for manufacturing a 6T-SRAM storage cell 10 according to an embodiment of the present invention. Figure 3 As shown, a substrate 52 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. The substrate 52 has at least one fin structure 54 and an insulating layer (not shown), wherein the bottom of the fin structure 54 is covered by an insulating layer, such as silicon oxide, to form a shallow trench isolation 56. It should be noted that although this embodiment takes the manufacture of a fin structure field effect transistor as an example, it is not limited to this. The present invention can also be applied to a general planar field effect transistor, and this embodiment also falls within the scope of the present invention.

[0063] According to a preferred embodiment of the present invention, the fin structure 54 is preferably obtained by sidewall image transfer (SIT) technology, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. Subsequently, the patterned sacrificial layer is removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0064] In addition, the formation method of the fin structure 54 may include first forming a patterned mask (not shown) on the substrate 52, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 52 to form the fin structure 54. In addition, the formation method of the fin structure 54 may also include first forming a patterned hard mask layer (not shown) on the substrate 52, and using an epitaxial process to grow a semiconductor layer such as silicon germanium on the substrate 52 exposed from the patterned hard mask layer, and this semiconductor layer can serve as the corresponding fin structure 54. These embodiments of forming the fin structure 54 are all within the scope of the present invention.

[0065] Then, a gate structure 58, 60 or a dummy gate may be formed on the substrate 52. In the present embodiment, the gate structures 58, 60 are preferably formed by sequentially forming a gate dielectric layer 62, a gate material layer 64 and a selective hard mask 66 on the substrate 52, and performing a pattern transfer process using a patterned photoresist (not shown) as a mask, removing a portion of the hard mask 66, a portion of the gate material layer 64 and a portion of the gate dielectric layer 62 by a single etching or successive etching steps, and then stripping the patterned photoresist to form at least one dummy gate or gate structure 58, 60 consisting of the patterned gate dielectric layer 62, the patterned gate material layer 64 and the patterned hard mask 66 on the fin structure 54. In the present embodiment, the gate dielectric layer 62 may include silicon oxide and the gate material layer 64 may include polysilicon, but is not limited thereto.

[0066] Then, at least one spacer 68 is formed on the sidewalls of each gate structure 58, 60, and a source / drain region 70 and an epitaxial layer 72 are formed in the fin structure 54 and / or the substrate 52 on both sides of the spacer 68. In the present embodiment, the spacer 68 may be a single spacer or a composite spacer, for example, it may include an offset spacer (not shown) and a main spacer (not shown), and the spacer 68 may be selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide, but is not limited thereto. The source / drain region 70 and the epitaxial layer 72 may include different dopants or different materials according to the conductivity type of the transistor to be prepared. For example, the source / drain region 70 may include P-type dopants or N-type dopants, and the epitaxial layer 72 may include silicon germanium, silicon carbide or silicon phosphide.

[0067] Then, a contact etch stop layer (CESL) 74 made of silicon nitride may be selectively formed on the substrate 52 and covers the gate structures 58 and 60, and an interlayer dielectric layer 76 is formed on the contact etch stop layer 74. Then, a planarization process is performed, such as using chemical mechanical polishing (CMP) to remove a portion of the interlayer dielectric layer 76 and a portion of the contact etch stop layer 74 and expose the hard mask 66, so that the upper surface of the hard mask 66 is flush with the upper surface of the interlayer dielectric layer 76.

[0068] A metal gate replacement process is then performed to convert the gate structures 58 and 60 into metal gates. Figure 4 As shown, a selective dry etching or wet etching process may be performed first, for example, using an etching solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the hard mask 66, the gate material layer 64 and the gate dielectric layer 62 in the gate structures 58 and 60 to form a groove in the interlayer dielectric layer 76 (not shown).

[0069] Thereafter, a dielectric layer 78, a high dielectric constant dielectric layer 80, a selective bottom barrier metal (BBM), a work function metal layer 82 and a low resistance metal layer 84 are sequentially formed in each groove, and then a planarization process is performed, such as using CMP to remove part of the low resistance metal layer 84, part of the work function metal layer 82 and part of the high dielectric constant dielectric layer 80 to form a metal gate 86.

[0070] In the present embodiment, the high-k dielectric layer 80 comprises a dielectric material having a dielectric constant greater than 4, for example, selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (strontium bismuth tantalum oxide), and strontium tantalum oxide (strontium bismuth tantalum oxide). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x The bottom metal barrier layer may be selected from the group consisting of titanium nitride (TiN) and tantalum nitride (TaN), but is not limited thereto.

[0071] The work function metal layer 82 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 82 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl) or TiAlC (titanium aluminum carbide), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 82 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 82 and the low resistance metal layer 84, wherein the barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low resistance metal layer 84 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., or a combination thereof.

[0072] Thereafter, a portion of the high-k dielectric layer 80, a portion of the bottom metal barrier layer 82, and a portion of the low-resistance metal layer 84 may be selectively removed to form a groove (not shown), and then a hard mask 88 is filled into the groove and made flush with the top of the interlayer dielectric layer 76, wherein the hard mask 88 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0073] Subsequently, a contact plug manufacturing process may be performed to form a contact plug 90 to electrically connect the source / drain region 70 and the gate structure 60. In the present embodiment, the contact plug 90 may be formed by first removing a portion of the interlayer dielectric layer 76 on both sides of the gate structure 60 and a portion of the contact hole etch stop layer 74 and a portion or even all of the hard mask 88 directly above the gate structure 60 to form a contact hole (not shown), wherein the contact holes on both sides of the gate structure 60 preferably expose the epitaxial layer 72 and the contact hole directly above the gate structure 60 exposes the metal gate 86.

[0074] Then, a first barrier layer 92 and a second barrier layer 94 are sequentially deposited in each contact hole, wherein the first barrier layer 92 and the second barrier layer 94 are preferably conformally formed on the surface of the substrate 52 and the inner sidewall of the contact hole. In the present embodiment, the first barrier layer 92 is preferably selected from the group consisting of titanium, cobalt, nickel and platinum, and is preferably titanium, and the second barrier layer 94 preferably includes metal compounds such as titanium nitride and tantalum nitride.

[0075] After the first barrier layer 92 and the second barrier layer 94 are continuously deposited, a first heat treatment process and a second heat treatment process are sequentially performed to form a metal silicide 96 on the surface of the epitaxial layer 72. In the present embodiment, the first heat treatment process includes a soak anneal process, the temperature of which is preferably between 500°C and 600°C, and preferably 550°C, and the treatment time is preferably between 10 seconds and 60 seconds, and preferably 30 seconds. The second heat treatment process includes a spike anneal process, the temperature of which is preferably between 600°C and 950°C, and preferably 600°C, and the treatment time is preferably between 100 milliseconds and 5 seconds, and preferably 5 seconds.

[0076] After two heat treatment processes, a metal layer 98 is formed and fills the contact hole. In the present embodiment, the metal layer 98 preferably comprises tungsten, but is not limited thereto. Finally, a planarization process is performed, such as using a CMP process to partially remove the third metal layer 98, a portion of the second metal layer 94, and a portion of the first metal layer 92, and even a portion of the interlayer dielectric layer 76 can be removed according to the process requirements to form a contact plug 90 to electrically connect the epitaxial layer 30 and the gate structure 60.

[0077] It is worth noting that the second barrier layer 94 formed in this embodiment preferably comprises titanium nitride, and the second barrier layer 94 is preferably formed by alternately performing a deposition process and a treatment process to form the second barrier layer 94 having a gradient titanium nitride concentration. Figure 5 , Figure 5 A schematic diagram of a method for forming a second barrier layer according to an embodiment of the present invention is disclosed. Figure 5 As shown, the steps of forming the second barrier layer 94 mainly include first performing a first deposition process to form a first layer 100 in each contact hole, performing a first treatment process on the first layer 100, performing a second deposition process to form a second layer 102 on the first layer 100, and then performing a second treatment process on the second layer 102, wherein the first deposition process and the second deposition process both include the deposition of titanium nitride, and the first treatment process and the second treatment process both include the introduction of hydrogen and / or nitrogen, but the time for the second treatment process to introduce nitrogen is preferably greater than the time for the first treatment process to introduce nitrogen.

[0078] In other words, by extending the time of introducing nitrogen in the second processing step, the present invention preferably makes the nitrogen concentration of the first layer 100 in the second barrier layer 94 lower than the nitrogen concentration of the second layer 102 and the titanium concentration of the second layer 102 lower than the titanium concentration of the first layer 100. Alternatively, from another perspective, the second barrier layer 94 close to the substrate 52 has a higher titanium concentration and a lower nitrogen concentration, while the second barrier layer 94 far from the substrate 52 has a lower titanium concentration and a higher nitrogen concentration. The portion close to the substrate 52 with a higher titanium concentration can promote the formation of the metal silicide 96, while the portion far from the substrate 52 or close to the metal layer 98 can be used as a metal barrier. In addition, since the higher nitrogen concentration close to the substrate 52 may cause the barrier layer and the metal layer 98 to have poor adhesion on the sidewall of the contact hole, resulting in metal loss and affecting the device performance, the present invention preferably adjusts the concentration of nitrogen atoms in the second barrier layer 94 by the above means to improve this problem. In addition, although the present embodiment takes two deposition processes and two treatment processes as an example, the number of deposition processes and treatment processes and the number of titanium nitride layers formed to form the second barrier layer 94 can be adjusted according to the process requirements and are not limited thereto.

[0079] Then Figure 6 As shown, a stop layer 104 and another interlayer dielectric layer 106 are sequentially formed on the interlayer dielectric layer 76, and one or more photolithography and etching processes are performed to remove part of the interlayer dielectric layer 106, part of the stop layer 104, and the hard mask 88 directly above the gate structure 58 to form contact holes (not shown). Then, a conductive material is filled into each contact hole and a planarization process such as CMP is used to form metal interconnects or contact plugs 108 and 110 to connect the contact plugs 90 below, wherein the contact plugs 108 are preferably simultaneously connected to or directly contact the gate structure 58 and the contact plugs 90 between the gate structures 58 and 60, and the contact plugs 110 contact the contact plugs 90 directly above the lower gate structure 60. Then, an intermetallic dielectric layer 112 is formed on the interlayer dielectric layer 106, and one or more photolithography and etching processes are performed to remove part of the intermetallic dielectric layer 112, part of the interlayer dielectric layer 106 and part of the stop layer 104 to form a contact hole. Then, a conductive material is filled in the contact hole and a planarization process such as CMP is performed to form a metal interconnect 114 or a contact plug 90 next to the contact gate structure 60.

[0080] In this embodiment, the stop layer 104 can be selected from the group consisting of nitrogen doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As the contact plug 90 formed above, each metal interconnect 114 or contact plug 108, 110 disposed in the interlayer dielectric layer 106 and the intermetallic dielectric layer 112 can be embedded in the interlayer dielectric layer 106 and / or the intermetallic dielectric layer 112 according to a single damascene process or a dual damascene process. For example, each contact plug 108, 110 and metal interconnect 114 may further include a barrier layer and a metal layer, wherein the barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN), and the metal layer may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since the single-damascene or dual-damascene manufacturing process is a well-known technology in the art, it will not be further described here. At this point, the manufacturing of the semiconductor device of one embodiment of the present invention is completed.

[0081] In summary, the present invention mainly forms a titanium nitride barrier layer with a gradient concentration by alternately performing multiple depositions and multiple treatments during the contact plug manufacturing process of the SRAM device, wherein the bottom of the barrier layer includes a titanium-rich portion and the top of the barrier layer includes a nitrogen-rich portion. According to the above-mentioned embodiment, the portion with a higher titanium concentration close to the substrate can promote the formation of metal silicide, while the portion away from the substrate or close to, for example, the metal layer 98 can be used as a metal barrier. Since the higher nitrogen concentration close to the substrate 52 in the current manufacturing process may cause the barrier layer and the metal layer 98 to have poor adhesion on the sidewall of the contact hole, resulting in metal loss and affecting the device performance, the present invention preferably adjusts the concentration of nitrogen atoms in the second barrier layer 94 through the above-mentioned means to improve this problem.

[0082] In addition, another embodiment of the present invention preferably separates the contact plug (or M0PY contact plug) that originally penetrates the two interlayer dielectric layers 76 and 106 and connects the gate structure 60 into two parts, wherein the top of the contact plug 90 located in the lower interlayer dielectric layer 76 and directly above the gate structure 60 is preferably aligned with the top of the contact plug 90 connected to the source / drain region 70 and the epitaxial layer 72 on both sides, while the top of the contact plug 110 located in the upper interlayer dielectric layer 106 and directly above the gate structure 60 is aligned with the contact plug 108 connected to the lower contact plug 90 and the gate structure 58. By separating the M0PY contact plug into two upper and lower sections, the present invention can significantly reduce the height of the connection between the contact plugs and the chance of short circuit between devices when the manufacturing process line width and exposure pitch are reduced.

[0083] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a static random access memory, characterized in that: Include: forming a gate structure on the substrate; forming an epitaxial layer beside the gate structure; forming a first interlayer dielectric layer surrounding the gate structure; converting the gate structure into a metal gate; forming a first contact hole to expose the epitaxial layer; and A first barrier layer is formed in the first contact hole, wherein the bottom of the first barrier layer includes a titanium-rich portion and the top of the first barrier layer includes a nitrogen-rich portion, and the step of forming the first barrier layer further includes: Performing a first deposition process to form a first layer in the first contact hole; Performing a first processing step on the first layer; Performing a second deposition process to form a second layer on the first layer; as well as Performing a second processing step on the second layer, The first deposition process and the second deposition process both include the deposition of titanium nitride, the first treatment process and the second treatment process both include the introduction of hydrogen and / or nitrogen, and the time for the second treatment process to introduce nitrogen is longer than the time for the first treatment process to introduce nitrogen, the nitrogen concentration of the first layer is lower than the nitrogen concentration of the second layer, and the titanium concentration of the second layer is lower than the titanium concentration of the first layer.

2. The method according to claim 1, further comprising: Forming the first contact hole to expose the epitaxial layer and the second contact hole to expose the metal gate; forming the first barrier layer in the first contact hole and the second contact hole; forming a metal layer on the first barrier layer; planarizing the metal layer and the first barrier layer to form a first contact plug and a second contact plug; forming a second interlayer dielectric layer on the first interlayer dielectric layer; as well as A third contact plug is formed on the first contact plug and a fourth contact plug is formed on the second contact plug.

3. The method of claim 2, further comprising performing an annealing process to form metal silicide before forming the metal layer. 4 . The method of claim 1 , further comprising forming a second barrier layer in the first contact hole before forming the first barrier layer.

5. The method of claim 4, wherein the first barrier layer comprises titanium nitride and the second barrier layer comprises titanium.

6. A static random access memory, characterized in that: Include: A gate structure is disposed on the substrate; An epitaxial layer is disposed next to the gate structure; A first contact plug is disposed on the epitaxial layer; A second contact plug is disposed on the gate structure; A first interlayer dielectric layer surrounds the first contact plug, the second contact plug and the gate structure; A third contact plug is disposed on the first contact plug; a fourth contact plug disposed on the second contact plug; as well as A second interlayer dielectric layer surrounds the third contact plug and the fourth contact plug, Each of the first contact plug and the second contact plug comprises: First barrier layer; A second barrier layer is disposed on the first barrier layer; as well as a metal layer disposed on the second barrier layer, The bottom of the second barrier layer includes a titanium-rich portion and the top of the second barrier layer includes a nitrogen-rich portion, the titanium-rich portion directly contacts the nitrogen-rich portion, and the nitrogen-rich portion at the top of the second barrier layer directly contacts the metal layer. 7 . The static random access memory as claimed in claim 6 , wherein a top portion of the first contact plug is flush with a top portion of the second contact plug. 8 . The static random access memory as claimed in claim 6 , wherein a top portion of the third contact plug is aligned with a top portion of the fourth contact plug.

9. The static random access memory as claimed in claim 6, further comprising a metal silicide disposed between the epitaxial layer and the first contact plug.

10. The static random access memory of claim 6, wherein the first barrier layer comprises titanium and the second barrier layer comprises titanium nitride.

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