A circuit for detecting data correlation

Abstract

The present application discloses a circuit for detecting data correlation, including: a serial-to-parallel conversion module, receiving a serial data signal and a reference data signal, and converting the serial data signal into a parallel data signal according to the reference data signal and a sampling clock; a voltage detection module, receiving the parallel data signal, and converting the parallel data signal into an analog voltage detection signal; a correlation output module, suitable for comparing the voltage detection signal with a first threshold voltage and a second threshold voltage to determine the correlation between the serial data signal and the reference data signal. By determining the correlation of data in an analog comparison manner, a resistor and a comparator are used to replace the accumulator and the numerical comparator in the existing digital correlator, which greatly simplifies the calculation part circuit of the correlation detection, is conducive to simplifying the circuit structure, reducing the complexity of the circuit, and reducing the cost of correlation detection.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more particularly to a circuit for detecting data correlation. Background Art

[0002] In digital communication systems, it is very important to ensure frame synchronization between the data streams on the sending and receiving sides. How to quickly and effectively determine the starting position of the data stream frame and obtain frame synchronization is a key part directly related to the communication speed and quality in the modern communication field.

[0003] Generally, a relatively simple and recognized frame synchronization method is to insert a feature code at a specific position in a frame as part of the frame structure during the data transmission process on the sending side, and then the receiving side detects frame synchronization by continuously searching for the feature code in the received data stream. The prior art usually uses a correlator or a matched filter to detect the peak value of the correlation value to continuously search for the feature code in the received data stream. The position corresponding to the peak value of the correlation value is the position of the detected feature code. Once the feature code is determined, the starting position of the frame is determined, thereby obtaining frame synchronization.

[0004] Figure 1 The figure shows a schematic diagram of the structure of a digital correlator in the prior art. The digital correlator mainly plays the role of digital matched filtering in communication signal processing. It can perform correlation processing on a specific code sequence, thereby completing signal decoding and recovering the transmitted information. Therefore, it is widely used in the fields of frame synchronization detection, error correction and pattern matching.

[0005] like Figure 1 As shown, the digital correlator 100 includes an input sequence shift register 110, a reference sequence shift register 120, a correlation operation array 130, and a correlation summation network 140. The input sequence shift register 110 is used to receive the input data stream DATAIN under the drive of the sampling clock CLK, the reference sequence shift register 120 is used to receive the reference data stream REF, and the correlation operation array 130 is used to perform a correlation operation on the input data stream DATAIN and the reference data stream REF. Each time the input sequence shift register 110 updates a bit of data, the correlation operation array 130 performs a correlation operation, and then sends the correlation operation result to the correlation summation network 140, which calculates the correlation value. The correlation value output by the correlation summation network 140 is compared with a detection threshold, and a correlation peak signal DETECTION is generated according to the comparison result.

[0006] The input sequence shift register 110 includes a plurality of cascaded D flip-flops 101, each of which includes a data input terminal, a clock terminal, a first output terminal, and a second output terminal. The clock terminal of the plurality of D flip-flops 101 is used to receive a sampling clock CLK, the data input terminal of the first-stage D flip-flop 101 is connected to the input data stream DATAIN, the data input terminals of the D flip-flops 101 of each stage except the first-stage D flip-flop 101 are connected to the first output terminal of the previous-stage D flip-flop 101 to receive the output of the previous-stage D flip-flop 101, and each stage of the D flip-flop 101 is used to output the corresponding data bit of the input data stream DATAIN under the driving of the sampling clock CLK.

[0007] The correlation operation array 130 includes a plurality of XNOR gates, each of which is used to perform an XOR logic operation on each data bit of the input data stream DATAIN located at the corresponding data bit of the reference data stream REF, and then count the number of “1” and “0” in the correlation operation array 130 .

[0008] The correlation summation network 140 includes an AND gate AND, a NOR gate NOR, and an OR gate OR. The input end of the AND gate AND is connected to the output ends of multiple XNOR gates XNOR in the correlation operation array 130. The AND gate AND is used to detect positive polarity correlation peaks, and outputs positive polarity correlation peak signals SIG1 according to the number of "1" and "0" in the correlation operation array 130. The input end of the NOR gate NOR is connected to the output ends of multiple XNOR gates XNOR in the correlation operation array 130. The NOR gate NOR is used to detect negative polarity correlation peaks, and outputs negative polarity correlation peak signals SIG0 according to the number of "1" and "0" in the correlation operation array 130. The input end of the OR gate OR is connected to the output ends of the AND gate AND and the NOR gate NOR, respectively, and the output end of the OR gate OR is used to output correlation peak signals DETECTION. Among them, the correlation peak signal DETECTION represents that the current input data stream DATAIN is correlated with the reference data stream REF, the positive polarity correlation peak signal SIG1 represents that the current input data stream DATAIN is positively correlated with the reference data stream REF, and the negative polarity correlation peak signal SIG0 represents that the current input data stream DATAIN is negatively correlated with the reference data stream REF.

[0009] In the digital correlator 100 of the prior art, it is necessary to perform an XOR operation on the input data stream and the reference data stream, and to accumulate the operation results, so it is necessary to use a shift register, an accumulator, a numerical comparator and an XOR operator in the circuit. The circuit structure is complex, which increases the circuit area and is not suitable for some fields that need to control costs. Summary of the invention

[0010] In view of this, an object of the present invention is to provide a circuit for detecting data correlation, which can simplify the circuit structure, reduce the complexity of the circuit, and reduce the cost of correlation detection.

[0011] According to an embodiment of the present invention, a circuit for detecting data correlation is provided, comprising: a serial-to-parallel conversion module, receiving a serial data signal and a reference data signal, and converting the serial data signal into a parallel data signal according to the reference data signal and a sampling clock; a voltage detection module, receiving the parallel data signal, and converting the parallel data signal into an analog voltage detection signal; a correlation output module, adapted to compare the voltage detection signal with a first threshold voltage and a second threshold voltage to determine the correlation between the serial data signal and the reference data signal, wherein the correlation output module is adapted to generate a first indication signal and a second indication signal according to the comparison result, the first indication signal indicating whether the serial data signal is correlated with the reference data signal, and the second indication signal indicating whether the serial data signal is positively correlated or negatively correlated with the reference data signal.

[0012] Preferably, the related output module includes: a first operational amplifier, whose inverting input terminal receives the first threshold voltage, whose non-inverting input terminal receives the voltage detection signal, and whose output terminal is used to provide a first comparison signal; a second operational amplifier, whose non-inverting input terminal receives the second threshold voltage, whose inverting input terminal receives the voltage detection signal, and whose output terminal is used to provide a second comparison signal; a first transistor, whose control terminal is connected to the output terminal of the first operational amplifier, whose first terminal is connected to the power supply voltage via a pull-up resistor, and whose second terminal is grounded; a second transistor, whose control terminal is connected to the output terminal of the second operational amplifier, whose first terminal is connected to the first terminal of the first transistor, and whose second terminal is grounded, wherein the intermediate node between the first transistor and the second transistor is used to output the first indication signal, and the intermediate node between the first transistor and the first operational amplifier is used to output the second indication signal.

[0013] Preferably, the relevant output module also includes first to third resistors connected in series between the power supply voltage and ground, wherein the intermediate node between the first resistor and the second resistor is suitable for providing the first threshold voltage, and the intermediate node between the second resistor and the third resistor is suitable for providing the second threshold voltage.

[0014] Preferably, the second resistor is an adjustable resistor, and the detection threshold of data correlation detection can be adjusted by adjusting the resistance value of the second resistor.

[0015] Preferably, the serial-to-parallel conversion module includes: a plurality of cascaded trigger units, each level of the trigger unit being suitable for processing the received data according to the sampling clock to generate first output data and second output data; a plurality of switching units arranged corresponding to the plurality of trigger units, each of the switching units being used to output one of the first output data and the second output data as a valid data bit of the parallel data signal according to the reference data signal.

[0016] Preferably, the voltage detection module includes a plurality of detection resistors arranged corresponding to the plurality of switching units, wherein the first ends of the plurality of detection resistors are respectively connected to the output ends of the corresponding switching units, and the second ends of the plurality of detection resistors are connected to each other to provide the voltage detection signal.

[0017] Preferably, each level of the trigger unit includes a data input terminal, a clock terminal, a first output terminal and a second output terminal, wherein the clock terminal of each level of the trigger unit is used to receive the sampling clock, the first output terminal is used to output the first output data, and the second output terminal is used to output the second output data. The data input terminal of the first-level trigger unit is used to receive the serial data signal, and the data input terminal of each level of the trigger unit other than the first-level trigger unit is connected to the first output terminal of the trigger unit of the previous level to receive the first output data of the trigger unit of the previous level.

[0018] Preferably, each level of the trigger unit further includes: a first current source, a third transistor and a fourth transistor connected sequentially between the power supply voltage and the ground, the control end of the third transistor being connected to the data input end, and the control end of the fourth transistor being connected to the clock end; a second current source and a fifth transistor connected sequentially between the power supply voltage and the ground, the control end of the fifth transistor being connected to the data input end; a third current source and a sixth transistor connected sequentially between the power supply voltage and the first end of the fourth transistor, the control end of the sixth transistor being connected to the first end of the fifth transistor; a fourth current source, a seventh transistor and an eighth transistor connected sequentially between the power supply voltage and the ground, the control end of the seventh transistor being connected to the first output end, the first end of the seventh transistor being connected to the second output end, and the control end of the eighth transistor being connected to the first end of the third transistor; a fifth current source, a ninth transistor and a tenth transistor connected sequentially between the power supply voltage and the ground, the control end of the ninth transistor being connected to the second output end, the first end of the ninth transistor being connected to the first output end, and the control end of the tenth transistor being connected to the first end of the sixth transistor.

[0019] Preferably, the first output data is the same as the data received by the data input terminal, and the second output data is opposite to the data received by the data input terminal.

[0020] Preferably, the switching unit is selected from a single-pole double-throw switch, and each data bit of the reference data signal is provided to a control end of a corresponding single-pole double-throw switch.

[0021] The circuit for detecting data correlation in the embodiment of the present invention includes a serial-to-parallel conversion module, a voltage detection module and a correlation output module. The voltage detection module converts the parallel data signal into an analog voltage detection signal, and then the correlation output module compares the voltage detection signal with a first threshold voltage and a second threshold voltage, and determines the correlation between the serial data signal and the reference data signal according to the comparison result. By determining the correlation of data in an analog comparison manner, a resistor and a comparator are used to replace the accumulator and the numerical comparator in the existing digital correlator, which greatly simplifies the calculation part circuit of the correlation detection, helps to simplify the circuit structure, reduce the complexity of the circuit, and reduce the cost of correlation detection.

[0022] In a further embodiment, the circuit for detecting data correlation uses 8 transistors and 5 current sources to implement sampling and holding of serial data to obtain parallel data. Compared with the existing method of using a shift register and then performing an XOR operation, the circuit of the embodiment of the present invention omits circuits such as the input data shift register, the reference data shift register and the XOR operator, which is beneficial to further simplify the circuit structure and reduce the circuit area of ​​the correlator.

[0023] In a further embodiment, the circuit for detecting data correlation adjusts the voltage values ​​of the first threshold voltage and the second threshold voltage through an adjustable resistor, so as to achieve the purpose of adjusting the detection threshold. There is no need to set a special comparison set value register in the circuit, which can not only further simplify the circuit structure, but also increase the applicability of multi-bit serial data correlation detection. It can be applied to intermittent short sequence data acquisition and application fields that are not particularly strict with sequence acquisition. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0025] Figure 1 A schematic diagram of the structure of a digital correlator in the prior art is shown;

[0026] Figure 2 A schematic diagram showing the structure of a circuit for detecting data correlation according to a first embodiment of the present invention;

[0027] Figure 3 A schematic structural diagram of a trigger unit according to a second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0028] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0029] Many specific details of the present invention are described below, such as component structures, materials, dimensions, processing techniques and technologies, in order to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0030] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuit, a programmable circuit, a state machine circuit and / or an element that can store instructions executed by a programmable circuit. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0031] It should be pointed out that in binary data transmission, high-level signal "1" and low-level signal "0" are relative concepts.

[0032] Figure 2 FIG. 2 is a schematic diagram showing a circuit for detecting data correlation according to a first embodiment of the present invention. Figure 2 As shown, the circuit 200 includes a serial-to-parallel conversion module 210 , a voltage detection module 220 and a related output module 230 .

[0033] The serial-to-parallel conversion module 210 is used to receive the serial data signal DATAIN, the sampling clock CLK and the reference data signal REF, and convert the serial data signal DATAIN into a parallel data signal according to the reference data signal REF and the sampling clock CLK. In the data transmission system, the data on the transmitting side is sent byte by byte to form a bit stream arranged in a serial order. Each byte is a "0" or "1" of a fixed but unimportant length. The serial-to-parallel conversion module 210 samples the serial data signal DATAIN synchronously with the sampling clock CLK, and generates a plurality of output signals, which are provided in parallel to the voltage detection module 220, and each output signal corresponds to a valid bit data of the parallel data signal.

[0034] The voltage detection module 220 receives the parallel data signal and converts the parallel data signal into an analog voltage detection signal Vs.

[0035] The correlation output module 230 receives the voltage detection signal Vs, and compares the voltage detection signal Vs with the first threshold voltage Vu and the second threshold voltage Vd to determine the correlation between the serial data signal DATAIN and the reference data signal REF. The correlation output module 230 generates a first indication signal LOST and a second indication signal SIG according to the comparison result, wherein the first indication signal LOST indicates whether the serial data signal DATAIN is correlated with the reference data signal REF, and the second indication signal SIG indicates whether the serial data signal DATAIN is positively correlated with the reference data signal REF or negatively correlated.

[0036] When the first indication signal LOST is a low level signal “0”, it indicates that the serial data signal DATAIN is related to the reference data signal REF; when the first indication signal LOST is a high level signal “1”, it indicates that the serial data signal DATAIN is not related to the reference data signal REF.

[0037] Under the premise that the first indication signal LOST is a low-level signal "0", when the second indication signal SIG is a low-level signal "0", it represents that the serial data signal DATAIN is positively correlated with the reference data signal REF, that is, the serial data signal DATAIN is the same as the reference data signal REF; when the second indication signal SIG is a high-level signal "1", it represents that the serial data signal DATAIN is opposite to the reference data signal REF, that is, the serial data signal DATAIN is the inverse of the reference data signal REF.

[0038] Further, the serial-to-parallel conversion module 210 includes a plurality of cascaded trigger units 201 and a plurality of switching units 202 corresponding to the plurality of trigger units 201. For the convenience of description, Figure 2 4 trigger units 201 and switching units 202 are used as examples for explanation. Each trigger unit 201 includes a data input terminal D, a clock terminal Clk, a first output terminal Q+ and a second output terminal Q-. The clock terminals Clk of the multiple trigger units 201 are connected to the sampling clock CLK, the data input terminal D of the first-stage trigger unit is used to receive the serial data signal DATAIN, and the data input terminals D of the trigger units of each stage other than the first-stage trigger unit are connected to the first output terminal Q+ of the trigger unit of the previous stage. Each stage of the trigger unit 201 is suitable for processing the received data according to the sampling clock CLK to generate the first output data and the second output data at the first output terminal Q+ and the second output terminal Q-, respectively.

[0039] The multiple switching units 202 are used to obtain multiple output signals S1-S4 according to the outputs of the multiple trigger units 201 and the reference data signal REF. Further, the reference data signal REF is a multi-bit binary number, and each of the switching units 202 is used to output one of the first output data and the second output data as a valid bit data of the parallel data signal according to the data bit corresponding to the reference data signal REF. Taking the first switching unit as an example, when the first data bit of the reference data signal REF is a high-level signal "1", the first switching unit outputs the second output data as the output signal S1; when the first data bit of the reference data signal REF is a low-level signal "0", the first switching unit outputs the first output data as the output signal S1. Furthermore, the multiple switching units 202 are implemented by a single-pole double-throw switch, and the control end of the single-pole double-throw switch is controlled by a data bit of the reference data signal REF.

[0040] Furthermore, the voltage detection module 220 includes a plurality of detection resistors R (only the detection resistors R1-R4 are shown in the figure) arranged corresponding to the plurality of switching units 202, the first ends of the plurality of detection resistors R are respectively connected to the output ends of the corresponding switching units 202, and the second ends of the plurality of detection resistors R are connected to each other to provide a voltage detection signal Vs.

[0041] Further, the relevant output module 230 includes an operational amplifier OPA1, an operational amplifier OPA2, a transistor M1, a transistor M2 and a pull-up resistor Rpull. The inverting input terminal of the operational amplifier OPA1 receives a first threshold voltage Vu, the non-inverting input terminal receives a voltage detection signal Vs, and the output terminal is used to provide a first comparison signal. The non-inverting input terminal of the operational amplifier OPA2 receives a second threshold voltage Vd, the inverting input terminal receives the voltage detection signal Vs, and the output terminal is used to provide a second comparison signal. The control terminal of the transistor M1 is connected to the output terminal of the operational amplifier OPA1, the first terminal is connected to the power supply voltage VCC via the pull-up resistor Rpull, and the second terminal is grounded. The control terminal of the transistor M2 is connected to the output terminal of the operational amplifier OPA2, the first terminal is connected to the first terminal of the transistor M1, and the second terminal is grounded. Among them, the intermediate node of the transistor M1 and the transistor M2 is used to output the first indication signal LOST, and the intermediate node of the transistor M1 and the operational amplifier OPA1 is used to output the second indication signal SIG.

[0042] Furthermore, the relevant output module 230 also includes a resistor Ru, a resistor Rv and a resistor Rd connected in series between the power supply voltage VCC and the ground. Among them, the middle node of the resistor Ru and the resistor Rv is suitable for providing the first threshold voltage Vu, and the middle node of the resistor Rv and the resistor Rd is suitable for providing the second threshold voltage Vd. Further, the first threshold voltage Vu is always greater than the second threshold voltage Vd. The transistor M1 and the transistor M2 compare the first comparison signal with the second comparison signal, and the comparison result of the two is pulled up by the pull-up resistor Rpull to generate the first indication signal LOST.

[0043] Among them, when the voltage detection signal Vs is less than the second threshold voltage Vd, the first indication signal LOST is a low level signal "0", and the second indication signal SIG is a low level signal "0"; when the voltage detection signal Vs is greater than the second threshold voltage Vd, and the voltage detection signal Vs is less than the first threshold voltage Vu, the first indication signal LOST is a high level signal "1", and the second indication signal SIG is a low level signal "0"; when the voltage detection signal Vs is greater than the first threshold voltage Vu, the first indication signal LOST is a low level signal "0", and the second indication signal SIG is a high level signal "1".

[0044] It can be seen that the first threshold voltage Vu and the second threshold voltage Vd constitute the detection threshold of the correlation detection. When the voltage detection signal Vs is higher or lower than the detection threshold, it is considered that the serial data signal DATAIN is correlated with the reference data signal REF; when the voltage detection signal Vs is within the detection threshold, it is considered that the serial data signal DATAIN is not correlated with the reference data signal REF. Therefore, the height of the detection threshold determines the false alarm probability and the missed alarm probability of the correlation detection (false alarm means that when the serial data signal DATAIN is not correlated with the reference data signal REF, the correlator believes that the serial data signal DATAIN is correlated with the reference data signal REF at this time; missed alarm means that when the serial data signal DATAIN is correlated with the reference data signal REF, the correlator mistakenly believes that the serial data signal DATAIN is not correlated with the reference data signal REF at this time).

[0045] Furthermore, the resistor Rv is an adjustable resistor, and the first threshold voltage Vu and the second threshold voltage Vd can be adjusted by adjusting the resistance value of the resistor Rv, thereby achieving the purpose of adjusting the detection threshold of the correlation detection and increasing or reducing the number of data bits allowed to be erroneous.

[0046] Figure 3 FIG. 2 is a schematic diagram showing the structure of a trigger unit according to a second embodiment of the present invention. Figure 3As shown, the trigger unit 201 includes current sources I1-I5 and transistors M3-M10. Among them, the current source I1, the transistor M3 and the transistor M4 are connected between the power supply voltage VCC and the ground in sequence, the control end of the transistor M3 is connected to the data input end D, and the control end of the transistor M4 is connected to the clock end Clk. The current source I2 and the transistor M5 are connected between the power supply voltage VCC and the ground in sequence, and the control end of the transistor M5 is connected to the data input end D. The current source I3 and the transistor M6 are connected between the power supply voltage VCC and the first end of the transistor M4 in sequence, and the control end of the transistor M6 is connected to the first end of the transistor M5. The current source I4, the transistor M7 and the transistor M8 are connected between the power supply voltage VCC and the ground in sequence, the control end of the transistor M7 is connected to the first output end Q+, the first end of the transistor M7 is connected to the second output end Q-, and the control end of the transistor M8 is connected to the first end of the transistor M3. The current source I5, the transistor M9 and the transistor M10 are connected between the power supply voltage VCC and the ground in sequence, the first end of the transistor M9 is connected to the first output end Q+, the control end of the transistor M9 is connected to the second output end Q-, and the control end of the transistor M10 is connected to the first end of the transistor M6.

[0047] The data input port D is a bit input port of serial data, the clock terminal Clk is an input port of a local sampling clock, the transistor M4 receives the local sampling clock, the transistors M7-M10 are used to output and maintain the states of the first output port Q+ and the second output port Q- according to the states of the transistors M8 and M10, and the transistors M3, M5 and M6 are used to generate the input states of the transistors M8 and M10 under the control of the transistor M4. Through the synchronization of the local sampling clock, the transistors M3-M10 generate the first output data and the second output data at the first output port Q+ and the second output port Q- according to the data of the data input port D, wherein the first output data is the same as the data of the data input port D, and the second output data is opposite to the data of the data input port D.

[0048] In the present application, transistors M1-M10 are implemented, for example, by N-type MOSFET (N-Metal-Oxide-Semiconductor Field-Effect Transistor), and the first end, the second end and the control end of the N-type MOSFET are the drain, the source and the gate, respectively.

[0049] In summary, the circuit for detecting data correlation in the embodiment of the present invention includes a serial-to-parallel conversion module, a voltage detection module and a correlation output module. The voltage detection module converts the parallel data signal into an analog voltage detection signal, and then the correlation output module compares the voltage detection signal with the first threshold voltage and the second threshold voltage, and determines the correlation between the serial data signal and the reference data signal according to the comparison result. By determining the correlation of data in an analog comparison manner, resistors and comparators are used to replace the accumulators and numerical comparators in the existing digital correlator, which greatly simplifies the calculation part circuit of the correlation detection, helps to simplify the circuit structure, reduce the complexity of the circuit, and reduce the cost of correlation detection.

[0050] In a further embodiment, the circuit for detecting data correlation uses 8 transistors and 5 current sources to implement sampling and holding of serial data to obtain parallel data. Compared with the existing method of using a shift register and then performing an XOR operation, the circuit of the embodiment of the present invention omits circuits such as the input data shift register, the reference data shift register and the XOR operator, which is beneficial to further simplify the circuit structure and reduce the circuit area of ​​the correlator.

[0051] In a further embodiment, the circuit for detecting data correlation adjusts the voltage values ​​of the first threshold voltage and the second threshold voltage through an adjustable resistor, so as to achieve the purpose of adjusting the detection threshold. There is no need to set a special comparison set value register in the circuit, which can not only further simplify the circuit structure, but also increase the applicability of multi-bit serial data correlation detection. It can be applied to intermittent short sequence data acquisition and application fields that are not particularly strict with sequence acquisition.

[0052] It should be noted that although in this article, the device is described as a certain N-channel or P-channel device, or a certain N-type or P-type doped region, it can be understood by those skilled in the art that complementary devices can also be realized according to the present invention. It can be understood by those skilled in the art that the conductivity type refers to the mechanism by which the conduction occurs, such as conduction by holes or electrons, so the conductivity type does not involve the doping concentration but the doping type, such as P-type or N-type. It can be understood by those skilled in the art that the words "during", "when" and "when..." used in this article in connection with the operation of the circuit are not strict terms indicating the action that occurs immediately when the start-up action begins, but there may be some small but reasonable one or more delays between it and the reaction action initiated by the start-up action, such as various transmission delays, etc. The words "approximately" or "substantially" used in this article mean that the element value has a parameter that is expected to be close to the declared value or position. However, as is well known in the art, there are always slight deviations that make it difficult for the value or position to be strictly the declared value. It has been well established in the art that a deviation of at least ten percent (10%) (or at least twenty percent (20%) for semiconductor doping concentrations) is a reasonable deviation from the exact ideal goal described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive logic or negative logic is used.

[0053] In addition, it is also necessary to explain that the relational terms such as first and second, etc. in this article are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0054] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A circuit for detecting data correlation, characterized in that: include: A serial-to-parallel conversion module receives a serial data signal and a reference data signal, and converts the serial data signal into a parallel data signal according to the reference data signal and a sampling clock; A voltage detection module receives the parallel data signal and converts the parallel data signal into an analog voltage detection signal; a correlation output module, adapted to compare the voltage detection signal with a first threshold voltage and a second threshold voltage to determine the correlation between the serial data signal and the reference data signal, The correlation output module is adapted to generate a first indication signal and a second indication signal according to the comparison result, wherein the first indication signal indicates whether the serial data signal is correlated with the reference data signal, and the second indication signal indicates whether the serial data signal is positively correlated with the reference data signal or negatively correlated. Wherein, the relevant output module includes: A first operational amplifier, an inverting input terminal receiving the first threshold voltage, and a non-inverting input terminal receiving the voltage detection signal; a second operational amplifier, wherein a non-inverting input terminal receives the second threshold voltage, and an inverting input terminal receives the voltage detection signal; a first transistor, having a control end connected to the output end of the first operational amplifier, a first end connected to a power supply voltage via a pull-up resistor, and a second end connected to ground; a second transistor, a control end connected to the output end of the second operational amplifier, a first end connected to the first end of the first transistor, and a second end grounded, The intermediate node between the first transistor and the second transistor is used to output the first indication signal, and the intermediate node between the first transistor and the first operational amplifier is used to output the second indication signal.

2. The circuit for detecting data correlation according to claim 1, characterized in that: The relevant output module also includes first to third resistors connected in series between the power supply voltage and ground, The middle node between the first resistor and the second resistor is suitable for providing the first threshold voltage, and the middle node between the second resistor and the third resistor is suitable for providing the second threshold voltage.

3. The circuit for detecting data correlation according to claim 2, characterized in that: The second resistor is an adjustable resistor, and the detection threshold of data correlation detection can be adjusted by adjusting the resistance value of the second resistor.

4. The circuit for detecting data correlation according to claim 1, characterized in that: The serial-to-parallel conversion module comprises: A plurality of trigger units connected in cascade, each trigger unit being adapted to process received data according to the sampling clock to generate first output data and second output data; A plurality of switching units are arranged corresponding to the plurality of trigger units, each of the switching units being used to output one of the first output data and the second output data as a valid data bit of the parallel data signal according to the reference data signal.

5. The circuit for detecting data correlation according to claim 4, characterized in that: The voltage detection module includes a plurality of detection resistors arranged corresponding to the plurality of switching units. The first ends of the plurality of detection resistors are respectively connected to the output ends of the corresponding switching units, and the second ends of the plurality of detection resistors are connected to each other to provide the voltage detection signal.

6. The circuit for detecting data correlation according to claim 4, characterized in that: Each level of the trigger unit includes a data input terminal, a clock terminal, a first output terminal and a second output terminal. Wherein, the clock end of the trigger unit of each stage is used to receive the sampling clock, the first output end is used to output the first output data, and the second output end is used to output the second output data. The data input end of the first-stage trigger unit is used to receive the serial data signal, and the data input ends of the trigger units of each stage other than the first-stage trigger unit are connected to the first output end of the previous-stage trigger unit to receive the first output data of the previous-stage trigger unit.

7. The circuit for detecting data correlation according to claim 6, characterized in that: Each level of the trigger unit also includes: A first current source, a third transistor and a fourth transistor connected in sequence between a power supply voltage and a ground, wherein a control terminal of the third transistor is connected to the data input terminal, and a control terminal of the fourth transistor is connected to the clock terminal; a second current source and a fifth transistor connected in sequence between the power supply voltage and ground, wherein a control terminal of the fifth transistor is connected to the data input terminal; a third current source and a sixth transistor connected in sequence between the power supply voltage and the first end of the fourth transistor, wherein the control end of the sixth transistor is connected to the first end of the fifth transistor; a fourth current source, a seventh transistor and an eighth transistor connected in sequence between the power supply voltage and ground, the control end of the seventh transistor being connected to the first output end, the first end of the seventh transistor being connected to the second output end, and the control end of the eighth transistor being connected to the first end of the third transistor; A fifth current source, a ninth transistor and a tenth transistor are sequentially connected between the power supply voltage and ground, the control end of the ninth transistor is connected to the second output end, the first end of the ninth transistor is connected to the first output end, and the control end of the tenth transistor is connected to the first end of the sixth transistor.

8. The circuit for detecting data correlation according to claim 7, characterized in that: The first output data is the same as the data received by the data input terminal, and the second output data is opposite to the data received by the data input terminal.

9. The circuit for detecting data correlation according to claim 4, characterized in that: The switching unit is selected from a single-pole double-throw switch, and each data bit of the reference data signal is provided to a control end of a corresponding single-pole double-throw switch.

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