Processor elements for quantum information processors

Abstract

A processor element is described herein. The processor element includes a silicon layer. The processor element further includes one or more conductive electrodes. The processor element further includes a dielectric material having a non-uniform thickness, the dielectric material being disposed at least between the silicon layer and the one or more conductive electrodes. In use, when a bias potential is applied to one or more of the conductive electrodes, the positioning of the one or more conductive electrodes and the non-uniform thickness of the dielectric material together define an electric field distribution to induce quantum dots at an interface between the silicon layer and the dielectric layer. Methods are also described herein.

Description

Technical Field

[0001] The present disclosure relates to processor elements for quantum information processing. In particular, the present application relates to processor elements that use confined regions (such as quantum dots) to store charge carriers used as qubits and that can be manufactured using complementary metal oxide semiconductor manufacturing processes. Background Art

[0002] The invention described herein is based at least in part on quantum mechanics, quantum information and quantum computing. For interested readers, the basic principles are described in detail in "Quantum Computation and Quantum Information" by Michael A Nielsen and Isac L Chuang. Specifically, this reference contains the characteristics of qubits and the basis of quantum measurement on a complementary basis, and provides an introduction to quantum error correction and fault-tolerant quantum computing. This reference also makes the reader familiar with the symbols conventionally used in the field of quantum physics.

[0003] A quantum computer is a device that processes quantum information, which is a generalization of the classical information processed by classical computers, such as discrete classical bits, i.e., 0s and 1s. For at least some processing, quantum computers have the potential to be much more powerful than classical computers because many operations can be performed more efficiently.

[0004] In computers that process quantum bits (otherwise known as "qubits"), each qubit can be placed in one of two states. However, due to the nature of qubits, they can also be placed in a superposition of these two states. If each qubit of a computer is placed in a superposition of the appropriate states, the overall superposition of states in the computer is in the ratio of 2 m , where m is the number of qubits. By placing the computer in this superposition of states, quantum algorithms can be used to solve various problems faster. This can be seen as arising from the fact that the qubit does not go through each possible state sequentially, but is in all possible combinations of states simultaneously. While a qubit can be thought of as a classical 0, a classical 1, or a superposition of these two states, a qubit can be thought of as a superposition of 0, 1, …, d-1, or any d states.

[0005] Universal quantum computers promise to speed up processing times for several operations, such as factoring large numbers, search algorithms, and quantum simulations, but progress has been hampered by the high precision required to control quantum states, and the difficulty of scaling up quantum computers to be able to process large numbers of quantum bits, or qubits.

[0006] The present disclosure provides processor devices, architectures, and apparatus that can alleviate some of the above-mentioned problems. Summary of the invention

[0007] As mentioned above, there is a long-sought hope of building a universal quantum computer, but many obstacles exist in the way of creating a universal quantum computer. Specifically, a major obstacle to the development of quantum computers is decoherence - the unintended interaction of quantum states with the outside world resulting in the loss of quantum information. Quantum error correction can be used to protect quantum information from errors due to decoherence and other noise sources. In fact, a logical qubit can be constructed from multiple physical qubits, so that the logical qubit can be processed more precisely than any individual physical qubit.

[0008] The second major obstacle to building a quantum computer is scalability. Although there are several competing architectures for implementing qubits (such as ion trap architectures and superconducting qubit architectures, etc.), it is difficult to build a device that can maintain more than a few qubits. Many of the most promising approaches for large-scale general quantum computing rely on quantum error correction, where an ideal logical qubit can be simulated by using multiple (noisy) physical qubits, provided that the error is below a fault tolerance threshold. Such methods require an architecture that can be scaled up to very large numbers of qubits. It will prove difficult to realize large-scale quantum computers with any architecture that cannot be sufficiently scaled up to operate reliably with a large number of physical qubits.

[0009] The inventors have recognised that if quantum computing architectures can be fabricated using complementary metal oxide semiconductor (CMOS) processes, there is the potential that such architectures can be scaled up to include many physical qubits.

[0010] The elements / architectures / designs described herein can form basic building blocks for spin qubit quantum processors that can be manufactured using existing CMOS technology (e.g., 40nm CMOS processes). Such processes typically limit the materials, certain dimensions, and manufacturing methods used to produce devices, but their highly developed and well-controlled properties mean that complex devices can be produced at relatively low cost on a very large scale with very high yields and high uniformity. However, due to process limitations, many creative steps are required to produce appropriate spin qubit building blocks using this technology. Although the principle of CMOS compatibility is often assumed (e.g., due to the materials used), the reality is that the scale of the device or other complexities in patterning make them incompatible with standard CMOS processes. For example, small feature sizes and spacings mean that some designs can only be made using electron beam lithography. It is extremely challenging to pattern metal regions with only nanometers between different regions using standard CMOS manufacturing processes. In addition, when trying to fit many quantum processor elements into a small space, many difficulties are involved in the interface with the control electronics. In formulating the architecture described herein, the inventors have "broken" many standard design rules of the CMOS manufacturing process.

[0011] Localized spins in semiconductors can be used to encode elementary bits of quantum information. Silicon (Si) quantum dots (QDs) are promising candidates for realizing spin qubits. Metal regions (such as gates) that help define the quantum dot structure can be implemented by patterning a metal layer on a dielectric layer of substantially uniform thickness to separate the metal from the silicon semiconductor region. Quantum dots are conventionally defined by the electrostatic potential of a combination of several such gates. This creates problems such as how to obtain signals to many gates by spreading metal connections from small metal gate regions to electrode regions for interfacing with classical control electronics. The more quantum dot regions there are in a processor, the greater the difficulty this presents, and therefore, scalable arrays of tens of thousands of quantum dots required to make quantum computers remain a significant challenge, and the examples described help alleviate this problem.

[0012] According to aspects of the invention, a processor element is provided herein. The processor element includes a silicon layer. The processor element further includes one or more conductive electrodes. The processor element further includes a dielectric material having a non-uniform thickness, the dielectric material being disposed at least between the silicon layer and the one or more conductive electrodes. In use, when a bias potential is applied to one or more of the conductive electrodes, the positioning of the one or more conductive electrodes and the non-uniform thickness of the dielectric material together define an electric field distribution to induce quantum dots at the interface between the silicon layer and the dielectric layer.

[0013] Advantageously, the processor elements described herein enable the definition of gates and tunnel barriers between them without the need for precise patterning of metal or doped polysilicon layers. Instead, the electrostatic field distribution required to confine electrons to a region (e.g., a quantum dot) can be provided by depositing a top gate, such as polysilicon, on top of a dielectric layer of varying (non-uniform) thickness. Thus, the processor elements described herein are easier to manufacture than other designs, although many conventional design rules for CMOS manufacturing are broken in this process.

[0014] Throughout this specification, reference is made to directional terms such as "above" and "below," or "upper" and "lower," etc. Reference to such terms is purely indicative of the relative positions of features of the embodiments disclosed herein. For example, if it is mentioned that an electrode is located above a dielectric layer and a silicon layer is located below the dielectric layer, it is understood that the electrode and the silicon layer are formed on opposite sides of the dielectric layer. That is, directional terms (such as those described herein) do not refer to directions relative to an observer's viewpoint, but should be considered relative terms in all respects.

[0015] In addition, in the following, Cartesian axes have been used to define the relative orientation and positioning of components. Specifically, the x-axis and y-axis are used to describe the horizontal plane coordinate system, and the z-axis is used to describe the "vertical" direction. The skilled person will understand that the use of such axes is only for illustrative purposes and helps the reader understand the structure of the several processor elements described herein. The axes do not limit the scope of the present invention in any way.

[0016] The thickness of the dielectric material can vary between a maximum thickness and a minimum thickness. The minimum thickness can be less than half of the maximum thickness and greater than 1 nm. The maximum thickness can be considered as the "thick oxide thickness" in the CMOS process, and the minimum thickness can be considered as the "thin oxide thickness" in the CMOS process. Thick oxides in CMOS processes are illustratively used to provide isolation between electrodes and contacts and other conductive features, thereby providing a very high level of isolation. Thin oxides in CMOS processes are illustratively used to separate gate electrodes from silicon substrates, allowing electric fields to penetrate the silicon substrate and can have a thickness between 1 nm-10 nm. Changing from thin oxide to thick oxide within a short lateral distance (e.g., <40 nm) is conventionally hindered, thereby breaking the CMOS "design rules" because the thick oxide will not be fully formed and therefore will not provide good isolation. However, for the purposes of the present disclosure, the thick oxide region is only used to reduce the electric field penetrating the silicon substrate, so the design rule can be violated and a region of "intermediate" thickness oxide is formed, in which the thick oxide is defined.

[0017] The silicon layer may have a non-uniform thickness. For example, the silicon layer may be etched so that trenches / channels in the silicon layer may be filled with a dielectric material such that the dielectric material has a non-uniform thickness.

[0018] One or more of the conductive electrodes may have a non-uniform thickness. For example, one or more of the conductive electrodes may be shaped such that a groove in the electrode may be filled with a dielectric material.

[0019] The processor may further include a source electrode. The processor element may further include a drain electrode. The one or more conductive electrodes may include one or more gate electrodes. The induced quantum dots may provide a single electron transistor (SET) island. Thus, the processor element may include a single electron transistor.

[0020] The processor element may include a source electrode and / or a drain electrode, and the quantum dot may be separated from the source and / or the drain by a quantum tunneling barrier.

[0021] Quantum dots can be used to confine electrons or holes for use as qubits. In this way, CMOS processor elements can be used as processors of quantum information.

[0022] The one or more conductive electrodes may include at least a second electrode. In use, when a bias potential is applied to the second conductive electrode, the positioning of the one or more conductive electrodes and the non-uniform thickness of the dielectric material may together define an electric field distribution to induce a second quantum dot at a second interface between the silicon layer and the dielectric layer.

[0023] The distance between the conductive electrode and the second conductive electrode may be between 10 nm and 140 nm. For example, the distance may be between 30 nm and 60 nm. For example, the distance may be between 40 nm and 50 nm.

[0024] The interface and the second interface may be distinct contact points between the silicon layer and the dielectric material. The interface and the second interface may be located on the same continuous plane between the dielectric and the silicon layer. The term "second interface" is intended only to refer to a second region defined by the second electrode at which charged particles may be confined.

[0025] The quantum dot and the second quantum dot may be separated by a quantum tunneling barrier. In this way, control of the first quantum dot can be used to manipulate or read out the spin state of the electron confined in the second quantum dot (or vice versa). The first quantum dot or the second quantum dot may be a SET island.

[0026] The second quantum dot can be used to define an electron or a hole that acts as a qubit.

[0027] One or more electrodes may include doped polysilicon electrodes.

[0028] The processor elements can be manufactured using a complementary metal oxide silicon manufacturing process.

[0029] According to an aspect of the present invention, a processor element is provided. The processor element includes a silicon layer. The processor element includes two or more conductive electrodes. The processor element further includes a dielectric material having a non-uniform thickness, the dielectric material being disposed at least between the silicon layer and the two or more conductive electrodes. In use, when a bias potential is applied to each of the two or more conductive electrodes, the positioning of the conductive electrodes and the non-uniform thickness of the dielectric material together define an electric field distribution to induce a first quantum dot at an interface between the silicon layer and the dielectric layer and induce a second quantum dot at a second interface between the silicon layer and the dielectric layer. The first quantum dot serves as an island of a single electron transistor, and the second quantum dot serves to confine charge carriers used as qubits.

[0030] According to an aspect of the invention there is provided a quantum information processor comprising a plurality of processor elements as described herein.

[0031] According to aspects of the invention, there is provided a method of manufacturing a processor element as described herein. The method comprises providing a silicon layer. The method further comprises depositing a dielectric layer on the silicon layer at least at contact points for conductive electrodes, the dielectric layer being formed of a dielectric material. The method further comprises depositing one or more conductive electrodes at the contact points on the dielectric layer. The method further comprises further depositing a dielectric material to fill a void beneath the one or more conductive electrodes. Such a manufacturing method does not require precise patterning of the metal or doped polysilicon layer.

[0032] According to aspects of the present invention, there is provided a method of manufacturing a processor element as described herein. The method includes providing a silicon layer having a fin. The method also includes etching a groove in the fin of the silicon layer. The method further includes depositing a dielectric material on the silicon layer to fill the etched groove. The method further includes depositing one or more conductive electrodes on the dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0034] Figure 1A is a cross-sectional plan view of a processor element;

[0035] Figure 1B yes Figure 1A a first cross-sectional side view of a processor element;

[0036] Figure 1C yes Figure 1A a second cross-sectional side view of a processor element;

[0037] Figure 2A is a cross-sectional plan view of a processor element;

[0038] Figure 2B yes Figure 2A a first cross-sectional side view of a processor element;

[0039] Figure 2C yes Figure 2A a second cross-sectional side view of a processor element;

[0040] Figure 3A A FIN field effect transistor (FET) nanowire is shown from a first angle;

[0041] Figure 3B The FINFET nanowire is shown from a second angle;

[0042] Figure 3C The FINFET nanowire is shown from a third angle;

[0043] Figure 4A Demonstrated FINFET nanowires with etched non-uniform thickness silicon fins;

[0044] Figure 4B Shown Figure 4A A FINFET nanowire in which the etched space is filled with a dielectric material;

[0045] Figure 4C Shows include Figure 4B processor elements comprising FINFET nanowires and conductor layers; and

[0046] Figure 5 A block diagram of a controller for operating one or more processor elements as described herein is shown.

[0047] Like reference numerals refer to like parts throughout the specification and drawings. DETAILED DESCRIPTION

[0048] Although various embodiments are described below, the present invention is not limited to these embodiments and variations of these embodiments may well fall within the scope of the present invention, which is limited only by the appended claims.

[0049] Figure 1A-Figure 1C A processor element 100 according to an example is depicted. Figure 1A 1 shows a cross-sectional view of the processor element 100 in the xy plane at a first height along the z-axis. That is, FIG. 1 illustrates the processor element 100 as viewed from above (plan view) at a first height within the processor element 100. Specifically, the plan view is at Figure 1B At the height shown by line A in . Figure 1B It is shown that generally along the direction B ( Figure 1A ) is a cross-sectional view of the processor element 100 as viewed in FIG.

[0050] Figure 1B The source and drain electrodes are not Figure 1A Shown in. Figure 1C Showing generally along direction C( Figure 1A A second cross-sectional view of the processor element 100 as viewed in FIG. 1 is shown in FIG. 1 . The features shown in dashed lines (e.g., Figure 1B and 1C Example features 104A and 104B) in FIG. 1 are shown for illustrative purposes only but are obscured from view.

[0051] Figure 1A-Figure 1C The processor element 100 may be implemented as a qubit control element for a quantum computer comprising a plurality of these processor elements. Figure 1A-Figure 1C In the processor element 100 , charge carriers such as electrons can be confined to a small region of semiconductor (ie, in a quantum dot), where they can be brought into a single electronic state or a few electronic states. Figure 1A-Figure 1C The processor element 100 provides two quantum dots, one quantum dot used as an island for a single electron transistor (SET) and one quantum dot used to confine charge carriers used as a spin qubit.

[0052] See also Figure 1A-Figure 1C , the processor element 100 includes a silicon layer 106. The silicon layer may be isotropically enriched. In this example, an isotropically enriched silicon layer 106 is used. 28 Four. 28 The Si may be an epitaxial layer grown on a conventional silicon substrate.

[0053] The processor element 100 further comprises a metal source electrode 112A and a metal drain electrode 112B, each connected to a corresponding metal via 108A, 108B. Under the source electrode 112A there is an ohmic region 107A. Under the drain electrode 112B there is an ohmic region 107B. The source / drain regions may be formed by standard CMOS technology.

[0054] The processor element further includes two conductive polysilicon electrodes 105A and 105B, each coupled to metal wiring through dedicated vias 104A, 104B for fanning out to external voltage connections. In this example, the polysilicon gate electrodes 105A and 105B are separated from each other by a distance of approximately 40 nm (at the points where those electrodes contact the marked thin dielectric regions 102C and 102D, respectively).

[0055] As in Figure 1A-Figure 1CAs can be seen in FIG. 1 , the processor element 100 further includes thin dielectric material regions, specifically, a first thin dielectric material region 102A, a second thin dielectric material region 102B, a third thin dielectric material region 102C, and a fourth thin dielectric material region 102D. In this example, the dielectric material includes silicon dioxide (SiO 2 ). In addition to the thin dielectric material regions 102A-102D, the processor element also includes one or more thicker regions 101 composed of dielectric material, so that the dielectric material in the processor element has a non-uniform thickness. The "thick" dielectric material in this example also includes SiO 2 , but in embodiments may be different from the dielectric material used at locations 102A-102D. That is, the dielectric material used in thick region 101 may be the same as dielectric material 102A-102D and applied at the same density and at the same stage during fabrication as thin dielectric regions 102A-102D— Figure 1A-Figure 1C The shading and markings are for indicative purposes only. During fabrication, thin dielectric regions and thick dielectric regions may be deposited simultaneously. That is, a non-uniform dielectric layer may be deposited before providing the electrodes with conductive material. As an alternative example, thin oxide regions may be formed first, and then thick oxide regions may be grown by deposition through a mask. As another alternative example, thick oxide regions may be grown first, and then the thick oxide regions are masked and selectively etched back to the silicon layer; a thin oxide may then be grown on top.

[0056] In this manner, the processor element 100 includes dielectric material 101, 102A-102D such that the dielectric material is disposed at least between the silicon layer 106 and the polysilicon electrodes 105A, 105B and has a varying thickness between the silicon layer 106 and the polysilicon electrodes 105A, 105B. In this example, the thickness of the dielectric material at the "thin" locations 102A-102D is approximately 5 nm, but may be as high as approximately 10 nm. The thickness of the dielectric material varies between a maximum thickness and a minimum thickness, wherein the minimum thickness is less than half of the maximum thickness and greater than 1 nm.

[0057] The first conductive electrode 105A and the second conductive electrode 105B respectively cover the thin dielectric material regions 102A-102D and the thick dielectric material region 101. The metal vias 104A and 104B may be used to maintain the conductive electrodes at an appropriate bias potential during operation of the processor element 100.

[0058] In the region between the silicon layer 106 and the first conductive electrode 105A, the dielectric material has a non-uniform thickness. Specifically, there is a first thick dielectric material region (at Figure 1B60 nm at its peak height "h"), and similarly, there is a second thick dielectric material region (at about 100 nm) laterally separating the third thin dielectric material region 102C and the second thin dielectric material region 102B. Figure 1B 60 nm at its peak height "h" in the electrode). That is, the dielectric material and the conductive material used for the electrode are shaped to form a non-uniform electrostatic potential at the interface between the dielectric material and the silicon layer in use. The first thin dielectric material region 102A and the third dielectric material region 102C are separated by a distance of about 40 nm. The second thin dielectric material region 102B and the third dielectric material region 102C are separated by a distance of about 40 nm.

[0059] Technicians will understand that Figure 1B The peak height "h" in may be up to about 150 nm. A skilled person will recognize that the spacing between the first thin dielectric material region 102A / second region 102B and the third thin dielectric material region 102C may be between 10 nm and 140 nm.

[0060] By applying an electric potential to metal via 104A, a region in which charge carriers are induced is formed in silicon layer 106 at the interface between silicon layer 106 and silicon dioxide 102A, 102B, and 102C.

[0061] In use, a bias potential may be applied to the first conductive electrode 105A through the first metal via 104. The bias potential may be between -5V and +5V, depending on the oxide thickness that controls the allowable range (to breakdown voltage) and the useful range (threshold voltage). Applying a bias potential to the first conductive electrode 105A generates an electric field within the processor element. The dielectric material located between the conductive electrode 105A and the silicon layer 106 reduces the effect of the electric field at the silicon-dielectric boundary. The region where the thick dielectric is located at the silicon-dielectric boundary between the conductive electrode and the silicon layer 106 will have a reduced electric field effect relative to the region where only the thin dielectric material is located at the boundary between the conductive electrode and the silicon layer 106. Thus, the non-uniform thickness of the dielectric material between the silicon layer 106 and the first polysilicon electrode 105A forms a non-uniform electrostatic potential at the interface of the dielectric material and the silicon. The electric field at the first boundary region may be large enough to induce an inversion layer at the boundary. However, due to the thick dielectric region located between the silicon layer 106 and the first conductive electrode 105A (as described above), the electric field at the interface between the silicon and the dielectric at the region of the induced charge carriers and the quantum dots 110 is greatly reduced. This results in a region where the electric field at the boundary is insufficient to induce an inversion layer, and thus the dielectric region between the quantum dots 110 and the source / drain electrodes acts as a tunneling barrier. The charge carriers in the inversion layer of the first region 109 must tunnel through the tunneling barrier in order to reach the induced quantum dots 110. Si / SiO 2The region 110 at the interface is a region where electrons or holes can be isolated. If a sufficiently positive potential is applied to the far end of the metal via 104A, the electrons will be isolated in the region 110; and if a sufficiently negative potential is applied to the far end of the via 104A, the holes will be isolated in the region 110. In an example, the potential applied to the via 104A can be sufficient to isolate a single electron in the quantum dot region 110, with a quantum tunneling barrier between the quantum dot 110 and the source electrode 112A and the drain electrode 112B. In this way, a single electron transistor (SET) is formed.

[0062] The single electron transistor accordingly includes a SET island 110 formed between tunneling junctions connected to the source electrode and the drain electrode in the silicon layer 106, and tunneling between the SET islands 110 is controlled by a potential applied to the gate electrode 105A. Through tunneling, electrons can be added to / subtracted from the SET island 110, charging it negatively or positively.

[0063] The presence of excess electrons at the SET island 110 affects the electrostatic energy of the system, which depends on the charge energy of the SET:

[0064]

[0065] Where Q 岛 is the charge on the island given by ne, where n is the number of excess electrons and e is the charge of an electron, and C is the total capacitance of the SET island 110. The total capacitance of the SET island 110 includes the intrinsic capacitance of the tunneling junctions to the source and drain electrodes and the gate capacitance controlled by electrode 105A.

[0066] The electrostatic energy of SET is roughly given by:

[0067]

[0068] Among them, n 栅极 is the amount of basic gate charge. The electrostatic energy of the SET determines whether tunneling through the junction is prohibited or allowed at a given potential difference between the source and drain electrodes. This is the Coulomb blockade effect. The drain-source voltage determines the energy of the electron before the junction - when the voltage is above the Coulomb blockade, the electron will overcome the blockade and tunneling will occur. The height of the blockade can be determined by the number of excess electrons on the SET island 110 and the gate charge.

[0069] The coupling between the SET island and the source / drain is set via the potential bias applied to the conductive electrode 105A and the proximity of the third thin dielectric material region 102C to the first thin dielectric material region 102A and the second thin dielectric material region 102B. The potential bias applied to the first conductive electrode 105A tunes the electrochemical potential of the point region so that one or more electrons are confined at the SET island 110. Typically, the SET island can confine between 10 and 100 electrons.

[0070] Figure 1C Depicts a cross section of the processor element in the yz plane (along Figure 1A ). A fourth thin dielectric material region 102D is located between the silicon layer 106 and the second conductive electrode 105B. The dielectric material between the silicon layer 106 and the first conductive electrode 105A and the second conductive electrode 105B may have a non-uniform thickness, such that the thickness of the dielectric material (between the first conductive electrode or the second conductive electrode and the silicon layer) varies with the y coordinate. The first conductive electrode 105A and the second conductive electrode 105B are laterally separated by a thick dielectric material region, where the thickness may again vary with the y coordinate between the first conductive electrode and the second conductive electrode. In this example, the first conductive electrode and the second conductive electrode are separated by a distance of 40 nm, although the skilled person will appreciate that any suitable distance is sufficient, such as between 10 nm and 140 nm. The second quantum dot 111 may be defined at the boundary between the silicon layer 106 and the fourth thin dielectric material region 102D.

[0071] A potential bias may be applied to the second conductive electrode 105B through the second metal via 104B. Applying a potential bias to the first conductive electrode 105A and the second conductive electrode 105B, combined with a thick region of dielectric material that laterally separates the first conductive electrode 105A and the second conductive electrode 105B, creates a tunneling barrier between the quantum dot 110 (SET island 110) and the second quantum dot 111. The potential bias of the conductive electrodes may be tuned so that charge carriers may tunnel from the SET island 110 to the second quantum dot 111 through the tunneling barrier. The potential bias may be tuned so that the electric field confines a single electron to the second quantum dot 111, so that the electron may be used as a qubit. Due to the proximity of the qubits in the SET island 110 and the quantum dot 111, they may be capacitively coupled.

[0072] Thus, the processor element 100 includes a SET having a first quantum dot (acting as a SET island 110), and a second quantum dot 111 located on the proximal side, which is used to confine electrons used as spin qubits. The SET island 110 can be manipulated to read out the qubits stored in the quantum dot 111. The occupancy of the two quantum dots 110 and 111 is controlled by the voltage applied to the vias 104A and 104B, and can be tuned so that a relatively small number N of electrons is confined to the quantum dots. In a simple scenario, when the occupancy N is an odd number, each quantum dot 110, 111 carries a spin of S=1 / 2, and when the occupancy N is an even number, each quantum dot 110, 111 carries a spin of S=0. Tunneling between the SET island 110 and the quantum dot 111 depends on the Pauli spin-blockade mechanism. Specifically, when the spins in the SET island 110 and the quantum dot 111 are the same, tunneling between the two regions is prohibited according to the Pauli exclusion principle. On the other hand, if the spins in the SET island 110 and the quantum dot 111 are different, tunneling can be achieved. The difference in current flow between the source electrode and the drain electrode enables the user to distinguish between the two states. Specifically, the total capacitance at the SET island 110 depends on the state of the spin qubit maintained in the second quantum dot 111, and accordingly, the state of the spin qubit in the second quantum dot 111 can be determined by analyzing the drain-source voltage required to overcome the electrostatic energy of the SET.

[0073] The quantum dots 110, 111 are defined by the electrostatic potential of the combination of electrodes 105A and 105B and the non-uniform thickness of the dielectric material, respectively.

[0074] The processor element 100 may be formed by any suitable manufacturing process, such as a 40 nm CMOS process, etc. For example, a silicon layer 106 may be provided. A thick oxide layer 101 may be disposed on the silicon layer 106, and the thick oxide layer 101 may be etched to provide spaces for conductive vias and electrodes, the conductive vias being separated from the silicon layer 106 by the remaining thin oxide layers 102A-102D. The conductive vias and electrodes may be inserted into the spaces formed in the thick oxide layer.

[0075] Figure 2A-2C A processor element 200 according to another example of the present disclosure is shown from several vantage points. Figure 2A 2 shows a cross-sectional view of the processor element 200 in the xy plane at a first height along the z-axis. That is, Figure 2A A first height within the processor element 200 is shown (specifically, as Figure 2B 2 is a cross-section of the processor element 200 as viewed from above (plan view) at a height indicated by line D in FIG. Figure 2BIt is shown that substantially along the direction E( Figure 2A A cross-sectional view of a processor element as viewed in FIG. Figure 2C It is shown that substantially along the direction F( Figure 2A ) is a cross-sectional view of the processor element 200 as viewed in FIG. Figure 2B The source and drain electrodes are not Figure 2A Shown in.

[0076] See also Figure 2A-2C , the processor element includes a silicon layer 207, one or more conductive electrodes 205A-205D, and a thin dielectric material region 202. In addition to the thin dielectric material region 202, there is also a thick dielectric material region 201, so that the dielectric material in the processor element has a non-uniform thickness. The dielectric material 201 is at least disposed between the silicon layer 207 and the one or more conductive electrodes 205A-205D.

[0077] Due to the use of patterned polysilicon boundaries at the transition between thin oxide regions and thick oxide regions, Figure 2A-2C The processor element shown in advantageously induces (in use) a better defined quantum dot region.

[0078] Figure 2A A first conductive electrode 205A, a second conductive electrode 205B, a third conductive electrode 205C, and a fourth conductive electrode 205D are depicted in addition to the thin dielectric material 202 and thick dielectric material 201 regions. The thin dielectric material region 202 is surrounded by the thick dielectric material region 201, wherein the thickness of the thick dielectric material 201 is not necessarily uniform. The dielectric material has a non-uniform thickness in the z-direction (i.e., outside the plane of the page). The thin dielectric material region may be referred to as a gate layer or gate region of dielectric material. The thin dielectric material region and the thick dielectric material region may be composed of the same dielectric material, and the dielectric material may be silicon oxide. The thin dielectric material region may be formed within the processor element by etching the thick dielectric material region. The first conductive electrode, the second conductive electrode, the third conductive electrode, and the fourth conductive electrode at least partially cover the thin dielectric material region and the thick dielectric material region. The conductive electrodes may be formed of polysilicon.

[0079] A first end of the first metal via 204A is connected to the first conductive electrode 205A, and a second end of the first metal via 204A is connected to the metal crossbar 206. Similarly, a first end of the second metal via 204B is connected to the second conductive electrode 205B, and a second end of the second metal via 204B is connected to the metal crossbar 206. A third metal via 204C is connected to the third conductive electrode 205C, and a fourth metal via 204D is connected to the fourth conductive electrode 205D. The metal vias may be used to maintain the conductive electrodes at a bias potential during operation of the processor element. Since the first metal via 204A and the second metal via 204B are connected to the same metal crossbar 206, both are maintained at the same potential. The third metal via 204C and the fourth metal via 204D may be independently maintained at the same potential bias or at different potential biases.

[0080] Figure 2B Depicts a cross section of a processor element in the xz plane (along Figure 2A The dashed line E). Figure 2B Further depicted are a metal source electrode 212A and a metal drain electrode 212B within the silicon layer, with ohmic regions 208A and 208B formed below the electrodes in the silicon layer. The source electrode 212A and the drain electrode 212B are connected to a fifth metal via 209A and a sixth metal via 209B, respectively.

[0081] The first conductive electrode 205A, the second conductive electrode 205B, and the fourth conductive electrode 205D are separated from the silicon layer 207 by thin dielectric material regions 202 and laterally separated from each other in the x-direction by thick dielectric material regions. The dielectric material has a non-uniform thickness in the z-direction, alternating between thin dielectric material 202 and sufficiently thick dielectric material regions to separate the conductive electrodes. The conductive electrodes are separated by a distance of 100nm-150nm (within the thickness range of the thick oxide layer).

[0082] The boundary between the thin dielectric material region 202 and the silicon layer 207 in the region near the first conductive electrode 205A and the second conductive electrode 205B can be considered as a first boundary region 210. The boundary between the thin dielectric material region 202 and the silicon layer 207 adjacent to the fourth conductive electrode 205D can be considered as a second boundary region or quantum dot 211.

[0083] When used, bias potentials may be applied to the first conductive electrode 205A, the second conductive electrode 205B, and the fourth conductive electrode 205D through the first metal via 204A, the second metal via 204B, and the fourth metal via 204D, respectively, wherein the first metal via 204A and the second metal via 204B are connected to the same metal crossbar 206. The skilled person will appreciate that the first metal via 204A and the second metal via 204B do not need to be connected to the same metal crossbar 206. Figure 1A-Figure 1C As in the example of , the bias potential can be between -5V and +5V.

[0084] A bias potential is applied to the conductive electrode to generate an electric field within the processor element. The dielectric material located between the conductive electrode and the silicon layer 207 can be used to reduce the effect of the electric field at the silicon-dielectric boundary. The area of ​​the silicon-dielectric boundary where the thick dielectric is located between the conductive electrode and the silicon layer 207 will have a reduced electric field effect relative to the area where only the thin dielectric material is located at the boundary between the conductive electrode and the silicon layer 207. In this way, an induced charge carrier region 210 can be formed in the silicon layer 207 near the source and drain electrodes. The Si / SiO2 layer below the electrode 205D 2 interface, can induce quantum dots 211.

[0085] As and about Figure 1A-Figure 1C As described in the example, Figure 2A-2C The processor element 200 includes a SET. Specifically, the quantum dot 211 acts as a SET island between the source electrode 212A and the drain electrode 212B. Advantageously, the processor 200 allows the size of the SET island 211 to be controlled by the electrode 205D independently of the potential applied to the electrodes 205A and 205B.

[0086] Figure 2C A cross section of the processor element 200 in the yz plane (along Figure 2A 205C and the fourth conductive electrode 205D. The dielectric material between the silicon layer 207 and the third conductive electrode 205C and the fourth conductive electrode 205D may have a non-uniform thickness, such that the thickness of the dielectric material (between the third conductive electrode or the fourth conductive electrode and the silicon layer) varies with the y coordinate. The third conductive electrode 205C and the fourth conductive electrode 205D are laterally spaced by the thick dielectric material region in the y direction by about 40 nm (but optionally between 10 nm and 140 nm). The second quantum dot 215 may be induced at the interface between the silicon layer 207 and the thin dielectric material region 202 at a location close to the quantum dot 211.

[0087] A potential bias may be applied to the third conductive electrode 205C through the third metal via 204C. The potential bias applied to the first conductive electrode, the second conductive electrode, and the fourth conductive electrode, combined with the thick dielectric material region that laterally separates the third conductive electrode 205C and the fourth conductive electrode 205D, creates a tunneling barrier between the first quantum dot 211 (or SET island 211) and the second quantum dot 215. The potential bias of the conductive electrodes may be tuned so that charge carriers may tunnel from the SET island 211 to the second quantum dot 215 through the tunneling barrier. The potential bias may be tuned so that the electric field confines a single electron to the third boundary region 215 so that the second quantum dot may store electrons used as spin qubits.

[0088] SET Island 211 and Figure 2C The SET shown in FIG. 2 can be used as a readout device for measuring the quantum state of a qubit in a quantum dot 215 by measuring the coupling (e.g., capacitive coupling) between the SET island 211 and the qubit of the quantum dot 215, as described above with respect to Figure 1A-Figure 1C As described.

[0089] Figure 3A-3B A fin field effect transistor (FINFET) nanowire is depicted. A FINFET is a type of non-planar or "3D" transistor used in the design of modern processors. Figure 3A Depicts the nanowire as viewed in the xy plane, Figure 3B Depicts the nanowire as viewed in the xz plane, Figure 3C Depicted is a nanowire as viewed in the yz plane. A FINFET nanowire includes a silicon layer 301 on which a ridge 302 (or 'fin') is located. The nanowire may be formed of silicon. A 'fin' here may be considered a FINFET formed in etched bulk silicon, while a 'nanowire' may be considered a silicon fin or wire etched in SOI technology.

[0090] Figure 3A-3C The FINFET nanowires can be used as a starting point for producing processor components. Figure 4A-4C Another example of a processor element formed using FINFET nanowires is depicted. Figure 4A Describes how Figure 3A-3C A nanowire is depicted in which a first trench or channel 303A and a second trench or channel 303B have been etched by removing material from the fin of the nanowire. Etching in this example means that the silicon layer 301 has a non-uniform thickness.

[0091] Figure 4B Describes Figure 4BAn etched fin is shown, wherein at least the first and second trenches are filled with a dielectric material 304, such as silicon oxide, etc. The structure includes an etched silicon fin on which there is a non-uniform dielectric material layer 304 that is thicker in areas due to the trenches etched into the fin.

[0092] Figure 4C A single electron transistor (SET) is depicted formed by depositing a material layer on a dielectric material 304 to form a conductive electrode 305. The conductive electrode 305 may be formed of polysilicon. A first boundary region 306, a second boundary region 307, and a third boundary region 308 may be defined at the interface between the silicon fin and the thin dielectric material region 304. As described above with respect to Figure 1A-Figure 1C and Figure 2A-2C In the depicted embodiment, the positioning of the non-uniform dielectric layer and electrode 305 defines a non-uniform electrostatic potential at the interface between the dielectric material 304 and the silicon layer 301. In this manner, the confinement region 307 may define a SET island.

[0093] A bias potential may be applied to the conductive electrode 305 so that an electric field is generated within the SET. The electric field at the boundary layer between the dielectric layer 304 and the fin will be strongest at the boundary between the thin dielectric material region and the fin (i.e., the first boundary region, the second boundary region, and the third boundary region). The dielectric material is used to reduce the electric field at the boundary between the silicon fins and within the silicon fins. Therefore, the electric field in the first boundary region, the second boundary region, and the third boundary region may be strong enough to induce an inversion layer at the boundary. However, in the region of the boundary between the first boundary region 306 and the second boundary region 307 and between the second boundary region 307 and the third boundary region 308 (i.e., the region near the thick dielectric material region), the electric field will not be strong enough to induce an inversion layer. The lack of an inversion layer in this region creates a tunneling barrier for the charge carriers in the inversion layer, so that the charge in the first boundary region 306 must tunnel in order to reach the second boundary region 307 (similarly, the charge carriers must tunnel between the second boundary region and the third boundary region).

[0094] The potential bias of the conductive electrode can be tuned so that charge carriers can tunnel through the tunneling barrier from the first boundary region 306 to the second boundary region 307. The potential bias can be tuned so that the electric field confines a single electron to the second boundary region 307. The second boundary region can thus be used to define a SET island, or to store charge carriers for use as a spin qubit.

[0095] Figure 5is a block diagram of a (classical) controller / computing device 500 for operating a quantum processor that includes one or more processor elements, such as processor elements 100 and 200 described above. For example, computing device 500 may include a computing device. Computing device 500 may be distributed across multiple connected devices. As will be appreciated by those skilled in the art, the computing device 500 may be used. Figure 5 Other architectures shown in .

[0096] Referring to the drawings, the controller / computing device 500 includes one or more (classical) processors 510, one or more memories 520, a plurality of optional user interfaces (such as a visual display 530 and a virtual or physical keyboard 540, etc.), a communication module 550, and an optional port 560 and an optional power supply 570. Each of the components 510, 520, 530, 540, 550, 560, and 570 is interconnected using a different bus. The classic processor 510 can process instructions for execution within the computing device 500, including instructions stored in the memory 520 received via the communication module 550 or via the port 560.

[0097] The memory 520 is used to store data within the computing device 500. One or more memories 520 may include volatile memory units. One or more memories may include one or more non-volatile memory units. One or more memories 520 may also be another form of computer-readable medium, such as a magnetic disk or optical disk. One or more memories 520 may provide mass storage for the computing device 500. Instructions for executing the methods described herein may be stored in one or more memories 520.

[0098] The device 500 includes a plurality of user interfaces including visualization means, such as a visual display 530 , and virtual or dedicated user input devices, such as a keyboard 540 .

[0099] The communication module 550 is adapted to send and receive communications between the processor 510 and a remote system. For example, the communication module 550 may be adapted to send and receive communications via a communication network such as the Internet.

[0100] Port 560 is adapted to receive, for example, non-transitory computer-readable media containing instructions to be processed by processor 510 .

[0101] The processor 510 is configured to receive data, access the memory 520 , and act according to instructions received from the memory 520 or a computer-readable storage medium connected to the port 560 , from the communication module 550 , or from the user input device 540 .

[0102] Reference Figure 1A-Figure 1C of the processor element 100 (although this also applies to Figure 2A-2C processor element 200), Figure 5 The classical processor 510 is configured to apply a bias potential to the distal end of the conductive via 104A of the processor element 100 so as to induce the quantum dots 110 at the interface between the dielectric layer 102C and the silicon layer 106 .

[0103] Processor 510 is further configured to apply a bias potential to the distal end of conductive via 104B of processor element 100 to induce a second quantum dot 111 at a second interface between dielectric layer 102D and silicon layer 106 for confining one or more electrons or holes in the silicon layer.

[0104] The processor 510 may be further configured to apply a voltage between the source electrode and the drain electrode of the processor element 100. As described above, the drain-source voltage may be used to read out the logic state of any spin qubit stored in the second quantum dot 111. The processor 510 may be further configured to manipulate the logic state of the qubit confined within the second quantum dot 111 by manipulating the state of the electrons or holes confined in the SET island 110.

[0105] Variations of the described embodiments are envisioned. For example, the features of all disclosed embodiments may be combined in any manner.

[0106] In many of the examples of processor elements provided above, both a SET and a second quantum dot are provided. The skilled person will recognize that the techniques and designs described herein can be used to produce a SET alone, or a quantum dot alone.

[0107] An array of such processor elements may be formed. For example, a processor may include an array of such processor elements.

[0108] Although silicon dioxide has been mentioned above, those skilled in the art will recognize that any suitable dielectric material may be used, such as hafnium oxide.

[0109] The first quantum dot and the second quantum dot may be separated by between 10 nm and 140 nm. Typical quantum dot sizes may be between 1 nm and 100 nm (ie, small enough to have a single electron therein, and spacing between energy levels large enough that thermal occupancy of higher energy levels is unlikely).

[0110] It will be understood that the different methods as described herein or at least aspects thereof can be implemented by a computer program. The computer program may include a computer code arranged to instruct a computer to cause the execution of the functions of one or more of the different methods described above, such as controlling the manufacturing method described herein. The computer program and / or code for executing such methods may be provided to a device on a computer-readable medium or a computer program product, such as a computer, etc. The computer-readable medium may be, for example, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, or a propagation medium for data transmission, such as for downloading code via the Internet. Alternatively, the computer-readable medium may take the form of a physical computer-readable medium, such as a semiconductor or solid-state boot, a magnetic tape, a removable disk, a random access memory (RAM), a read-only memory (ROM), a hard disk and an optical disk (such as a CD-ROM, CD-R / W or DVD, etc.), etc.

[0111] Devices such as computers can be configured according to such code to perform one or more processes according to the different methods discussed herein. Such devices can take the form of data processing systems. Such data processing systems can be distributed systems. For example, such data processing systems can be distributed across a network.

[0112] The above embodiments are described by way of example only, and the described embodiments are to be considered in all respects only as illustrative and not restrictive. It should be appreciated that variations can be made to the described embodiments without departing from the scope of the present invention.

Claims

1. A processor element, the processor element include: Silicon layer; a first conductive electrode; a second conductive electrode; source electrode; Drain electrode; as well as a dielectric material, the dielectric material comprising a first thin dielectric material region, a second thin dielectric material region, a third thin dielectric material region, a fourth thin dielectric material region, and one or more thick dielectric material regions, such that the dielectric material has a non-uniform thickness in a region between the silicon layer and the first and second conductive electrodes, the dielectric material being disposed at least between the silicon layer and the first and second conductive electrodes; wherein the first conductive electrode covers the first thin dielectric material region, the second thin dielectric material region, the third thin dielectric material region and the thick dielectric material region, wherein the first thick dielectric material region laterally separates the first thin dielectric material region and the third thin dielectric material region, and the second thick dielectric material region laterally separates the third thin dielectric material region and the second thin dielectric material region; wherein the second conductive electrode covers the fourth thin dielectric material region and the thick dielectric material region, wherein the third thick dielectric material region laterally separates the first conductive electrode and the second conductive electrode; wherein the processor element is configured such that when a bias potential is applied to the first conductive electrode, the positioning of the first conductive electrode and the non-uniform thickness of the dielectric material together define an electric field distribution to induce one or more charge carriers at each of the first thin dielectric material region, the second thin dielectric material region, and the third thin dielectric material region at an interface between the silicon layer and the dielectric material; wherein the one or more charge carriers induced at the interface of the silicon layer and the third thin dielectric material region are quantum dots, wherein the quantum dots are separated from the source electrode and / or the drain electrode by a quantum tunneling barrier, and wherein the induced quantum dots provide single electron transistor (SET) islands; wherein the processor element is configured such that when a bias potential is applied to the second conductive electrode, the positioning of the second conductive electrode and the non-uniform thickness of the dielectric material together define an electric field distribution to induce a second quantum dot at an interface of the silicon layer and the fourth thin dielectric material region; Wherein, applying a bias potential to the first conductive electrode and the second conductive electrode, combined with a thick dielectric material region laterally separating the first conductive electrode and the second conductive electrode, results in a quantum tunneling barrier between the quantum dot and the second quantum dot.

2. The processor element according to claim 1, in, The thickness of the dielectric material varies between a maximum thickness and a minimum thickness, wherein the minimum thickness is less than half of the maximum thickness and greater than 1 nm.

3. The processor element according to claim 1, in, The quantum dots are used to define electrons or holes that function as qubits.

4. The processor element according to claim 1, in, The first conductive electrode and the second conductive electrode include gate electrodes.

5. The processor element according to claim 1, in, The second quantum dot is used to define an electron or a hole used as a quantum bit.

6. The processor element according to claim 1, in, The first conductive electrode and the second conductive electrode include doped polysilicon electrodes.

7. A processor element, the processor element include: Silicon layer; a silicon fin covering the silicon layer, wherein the fin comprises a first trench or channel and a second trench or channel, so that the silicon layer has a non-uniform thickness; conductive electrodes; and a dielectric material covering the silicon layer and filling at least the first trench or channel and the second trench or channel, so that the dielectric material has a non-uniform thickness in a region between the silicon layer and the conductive electrode, the dielectric material being disposed at least between the silicon layer and the conductive electrode; wherein the dielectric material comprises a plurality of thin dielectric material regions and one or more thicker dielectric material regions, wherein a first boundary region, a second boundary region, and a third boundary region are defined at interfaces between the silicon fin and the thin dielectric material regions; wherein the processor element is configured such that when a bias potential is applied to the conductive electrode, the positioning of the conductive electrode and the non-uniform thickness of the dielectric material together define an electric field distribution to induce one or more charge carriers at each of the first boundary region, the second boundary region, and the third boundary region; wherein a tunneling barrier exists between the first boundary region and the second boundary region, and a tunneling barrier exists between the second boundary region and the third boundary region, so that charge carriers can tunnel from the first boundary region through the tunneling barrier to the second boundary region; Wherein, the second boundary region defines a single electron transistor (SET) island.

8. The processor element according to claim 7, in, The thickness of the dielectric material varies between a maximum thickness and a minimum thickness, wherein the minimum thickness is less than half of the maximum thickness and greater than 1 nm.

9. A quantum information processor comprising a plurality of processor elements according to claim 1 or claim 7.

10. A method of manufacturing a processor element according to claim 1, said method include: providing a silicon layer; depositing a source electrode on the silicon layer; depositing a drain electrode on the silicon layer; depositing a dielectric layer on the silicon layer, wherein the dielectric layer includes a first thin dielectric material region, a second thin dielectric material region, a third thin dielectric material region, a fourth thin dielectric material region, and one or more thick dielectric material regions such that the dielectric layer has a non-uniform thickness; and Depositing a first conductive electrode and a second conductive electrode covering the dielectric layer so that the dielectric layer has a non-uniform thickness in a region between the silicon layer and the first conductive electrode and the second conductive electrode; wherein the first conductive electrode is deposited to cover the first thin dielectric material region, the second thin dielectric material region, the third thin dielectric material region, and the thick dielectric material region, wherein the first thick dielectric material region laterally separates the first thin dielectric material region and the third thin dielectric material region, and the second thick dielectric material region laterally separates the third thin dielectric material region and the second thin dielectric material region; wherein the second conductive electrode is deposited to cover the fourth thin dielectric material region and the thick dielectric material region, wherein the third thick dielectric material region laterally separates the first conductive electrode and the second conductive electrode; wherein the processor element is configured such that when a bias potential is applied to the first conductive electrode, the positioning of the first conductive electrode and the non-uniform thickness of the dielectric layer together define an electric field distribution to induce one or more charge carriers at each of the first thin dielectric material region, the second thin dielectric material region, and the third thin dielectric material region at an interface between the silicon layer and the dielectric layer; wherein the one or more charge carriers induced at the interface of the silicon layer and the third thin dielectric material region are quantum dots, wherein the quantum dots are separated from the source electrode and / or the drain electrode by a quantum tunneling barrier, and wherein the induced quantum dots provide single electron transistor (SET) islands; wherein the processor element is configured such that when a bias potential is applied to the second conductive electrode, the positioning of the second conductive electrode and the non-uniform thickness of the dielectric material together define an electric field distribution to induce a second quantum dot at an interface of the silicon layer and the fourth thin dielectric material region; Wherein, applying a bias potential to the first conductive electrode and the second conductive electrode, combined with a thick dielectric material region laterally separating the first conductive electrode and the second conductive electrode, results in a quantum tunneling barrier between the quantum dot and the second quantum dot.

11. The method of manufacturing a processor element according to claim 10, in, The method is a complementary metal oxide silicon manufacturing process.

12. A method of manufacturing a processor element according to claim 7, said method include: providing a silicon layer having fins; etching a first trench and a second trench in the fin of the silicon layer so that the silicon layer has a non-uniform thickness; depositing a dielectric material on the silicon layer to fill the etched trenches, such that the dielectric material has a non-uniform thickness; and depositing a conductive electrode on the dielectric material; wherein the dielectric material comprises a plurality of thin dielectric material regions and one or more thicker dielectric material regions, wherein a first boundary region, a second boundary region, and a third boundary region are defined at interfaces between the silicon fin and the thin dielectric material regions; wherein the processor element is configured such that when a bias potential is applied to the conductive electrode, the positioning of the conductive electrode and the non-uniform thickness of the dielectric material together define an electric field distribution to induce one or more charge carriers at each of the first boundary region, the second boundary region, and the third boundary region; wherein a tunneling barrier exists between the first boundary region and the second boundary region, and a tunneling barrier exists between the second boundary region and the third boundary region, so that charge carriers can tunnel from the first boundary region through the tunneling barrier to the second boundary region; Wherein, the second boundary region defines a single electron transistor (SET) island.

13. The method of manufacturing a processor element according to claim 12, in, The method is a complementary metal oxide silicon manufacturing process.

Images