Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: etching the sidewall of the initial first mask layer, reducing the size of the initial first mask layer along the extension direction of the initial fin structure, and forming a first mask layer; forming an initial isolation layer covering the first mask layer, wherein the initial isolation layer exposes the top surface of the first mask layer; after forming the initial isolation layer, removing the first mask layer; after removing the first mask layer, etching the initial fin structure using the initial isolation layer as a mask. By controlling the process parameters for etching the initial first mask layer, the width of the formed first mask layer can be made small enough, the accuracy is high, and the process difficulty is effectively reduced, thereby making the size of the formed opening small enough, which is conducive to improving the performance of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] FinFET transistor architecture is the main force in today's semiconductor industry. However, with the continuous miniaturization of devices, when the channel length is small to a certain value, the FinFET structure cannot provide sufficient electrostatic control and sufficient drive current. Therefore, the Nanosheet structure, namely the gate-all-around technology (GAA), is introduced. Compared with the FinFET, the GAA feature of the Nanosheet provides excellent channel control capabilities. At the same time, the excellent distribution of the channel in three dimensions optimizes the effective drive current per unit area.

[0003] As the journey towards smaller track heights continues, further reductions in cell height will require smaller spacing between NMOS and PMOS devices within a standard cell. However, for FinFETs and nanosheets, the process limits the spacing between these NMOS and PMOS devices. To expand the scalability of these devices, an innovative architecture is proposed, called a forksheet device. Forksheets can be considered a natural extension of nanosheets. Compared to nanosheets, the channel of forksheets is controlled by a forked gate structure, which is achieved by introducing a "dielectric wall" between NMOS and PMOS devices before gate patterning. The wall physically isolates the NMOS gate trench from the PMOS gate trench, thereby significantly reducing the spacing between NMOS and PMOS, making forksheets have better area and performance scalability.

[0004] However, the performance of fork-shaped nanosheets needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: forming an initial first mask layer on the surface of an initial fin structure, the initial fin structure including several sacrificial layers overlapping along the normal direction of the top surface of the initial fin structure, and a channel layer located between adjacent sacrificial layers; etching the sidewalls of the initial first mask layer to reduce the size of the initial first mask layer along the extension direction of the initial fin structure to form a first mask layer; forming an initial isolation layer covering the first mask layer, the initial isolation layer exposing the top surface of the first mask layer; after forming the initial isolation layer, removing the first mask layer; after removing the first mask layer, etching the initial fin structure using the initial isolation layer as a mask.

[0007] Optionally, along the extension direction of the initial fin structure, the width of the first mask layer ranges from 3 nanometers to 30 nanometers.

[0008] Optionally, the method for etching the side wall of the initial first mask layer includes: forming a second mask layer on the top surface of the initial first mask layer, the initial first mask layer and the second mask layer have different materials; etching the initial first mask layer to form the first mask layer; after forming the first mask layer, removing the second mask layer.

[0009] Optionally, the method for forming the initial fin structure and the initial first mask layer and the second mask layer includes: forming a fin material film on a substrate, the fin material film including several layers of sacrificial material films overlapping along the normal direction of the substrate, and a channel material film located between adjacent sacrificial material films; forming a first mask material film on the surface of the fin material film; forming a second mask material film on the surface of the first mask material film, the first mask material film and the second mask material film being made of different materials; forming a patterned layer on the surface of the second mask material film, the patterned layer covering a portion of the second mask material film; using the patterned layer as a mask, etching the second mask material film, the first mask material film and the fin material film until the substrate surface is exposed, thereby forming the initial fin structure, the initial first mask layer and the second mask layer on the substrate.

[0010] Optionally, the process of etching the initial first mask layer is a wet etching process, and the process parameters of the wet etching include: the etching solution used includes dilute phosphoric acid, and the temperature ranges from 50 degrees Celsius to 90 degrees Celsius.

[0011] Optionally, the process of removing the second mask layer includes: a dry etching process and a wet etching process, or a combination of the two.

[0012] Optionally, the process of removing the first mask layer includes: a dry etching process and a wet etching process, or a combination of the two.

[0013] Optionally, the material of the initial first mask layer includes: silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

[0014] Optionally, a material of the second mask layer includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

[0015] Optionally, the thickness of the initial first mask layer ranges from 5 nanometers to 100 nanometers.

[0016] Optionally, the thickness of the second mask layer ranges from 5 nanometers to 100 nanometers.

[0017] Optionally, the method further includes: etching the initial fin structure until the substrate surface is exposed to form a fin structure and an opening in the fin structure; and forming an isolation structure in the opening.

[0018] Optionally, the material of the isolation structure includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

[0019] Optionally, the material of the initial isolation layer is different from the material of the first mask layer; the material of the initial isolation layer includes: silicon oxide, silicon nitride, silicon carbide, silicon boron nitride, silicon carbon nitride or silicon oxynitride.

[0020] Optionally, the method for forming the initial isolation layer includes: forming an initial isolation layer film on a substrate covering the top surface and side wall surfaces of the initial fin structure and the top surface and side wall surfaces of the first mask layer; and flattening the initial isolation layer film until the surface of the first mask layer is exposed to form the initial isolation layer.

[0021] Optionally, the method further includes: after forming the isolation structure, etching the initial isolation layer to form an isolation layer, wherein the isolation layer covers a portion of the sidewall surface of the fin structure.

[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0023] In the method for forming a semiconductor structure provided by the technical solution of the present invention, by controlling the process parameters for etching the sidewalls of the initial first mask layer, the width of the formed first mask layer can be made small enough, the accuracy is high, and it is helpful to reduce the process difficulty. Then, the initial isolation layer is used as a mask to perform self-aligned etching of the initial fin structure. Since the size and position of the first mask layer define the size and position of the opening in the fin structure, the width of the first mask layer is small, so that the size of the formed opening is small enough, which is helpful to improve the performance of the formed semiconductor structure.

[0024] Furthermore, since the materials of the initial first mask layer and the second mask layer are different, and the second mask layer is located on the top surface of the initial first mask layer, during the process of etching the initial first mask layer, the second mask layer can protect the top surface of the initial first mask layer, thereby reducing the width of the initial first mask layer to form the first mask layer. This does not require a high-resolution photolithography process, and effectively reduces the process difficulty.

[0025] Furthermore, when the process of etching the initial first mask layer is a wet etching process, the wet etching process makes the width of the formed first mask layer within a smaller range and makes the edge roughness of the first mask layer smaller. Since the size and position of the first mask layer define the size and position of the opening in the fin structure, the edge roughness of the first mask layer is smaller, which is conducive to improving the accuracy of pattern transfer, so that the morphology of the formed opening is better, thereby helping to improve the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 3 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0027] Figures 4 to 13 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0028] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0029] First, the reasons why the performance of the existing semiconductor structure is poor are described in detail with reference to the accompanying drawings. Figures 1 to 3 The present invention is a structural schematic diagram of each step of a method for forming a conventional semiconductor structure.

[0030] Please refer to Figure 1 , providing a substrate 100 having an initial fin structure thereon, the initial fin structure comprising a plurality of sacrificial layers 101 overlapping along a normal direction of the substrate 100 , and a channel layer 102 located between adjacent sacrificial layers 101 .

[0031] Please refer to Figure 2 , a patterned layer 110 is formed on the surface of the initial fin structure, and a first opening 120 is provided in the patterned layer 110, and the first opening 120 exposes a portion of the surface of the initial fin structure; using the patterned layer 110 as a mask, the initial fin structure is etched until the surface of the substrate 100 is exposed, thereby forming a fin structure 130 and a second opening 140 located in the fin structure 130.

[0032] Please refer to Figure 3 , an isolation structure 150 is formed in the second opening 140 .

[0033] In the above method, the patterned layer 110 is used as a mask for etching the initial fin structure, thereby forming a fin structure 130 and a second opening 140 located in the fin structure 130, and then forming an isolation structure 150 in the second opening 140, so that the isolation structure 150 electrically isolates the fin structures 130 located on both sides of the isolation structure 150.

[0034] However, as the density of components in integrated circuits increases, the sizes of various devices are getting smaller and smaller, and the size of the isolation structure 150 located in the fin structure 130 is required to be small enough. Since the position and size of the isolation structure 150 are determined by the position and size of the first opening 120 in the patterned layer 110, forming a first opening 120 with a smaller size exceeds the limit of the existing photolithography process, resulting in the inability to form a first opening 120 with a good morphology, or even the inability to form a first opening 120 with a small enough size.

[0035] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: etching the sidewall of the initial first mask layer, reducing the size of the initial first mask layer along the extension direction of the initial fin structure, and forming a first mask layer. By controlling the process parameters of etching the initial first mask layer, the width of the formed first mask layer can be made small enough, the accuracy is high, and the process difficulty is effectively reduced, thereby making the size of the formed opening small enough, which is beneficial to improving the performance of the formed semiconductor structure.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 4 to 13 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0038] Please refer to Figure 4 , providing a substrate 200.

[0039] The material of the substrate 200 includes silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also include silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials, such as III-V group compounds such as gallium arsenide.

[0040] In this embodiment, the material of the substrate 200 is silicon.

[0041] Next, an initial fin structure and an initial first mask layer located on the surface of the initial fin structure are formed on the substrate 200 . The initial fin structure includes several sacrificial layers overlapping along the normal direction of the top surface of the initial fin structure and a channel layer located between adjacent sacrificial layers.

[0042] In this embodiment, the method for forming the semiconductor structure further includes: forming a second mask layer on the top surface of the initial first mask layer, and the initial first mask layer and the second mask layer are made of different materials.

[0043] For the specific process of forming the initial fin structure, the initial first mask layer and the second mask layer, please refer to Figures 5 to 6 .

[0044] Please refer to Figure 5 , a fin material film is formed on the substrate 200, wherein the fin material film includes a plurality of sacrificial material films 202 overlapping along the normal direction of the substrate 200, and a channel material film 201 located between adjacent sacrificial material films 202; a first mask material film 210 is formed on the surface of the fin material film; a second mask material film 220 is formed on the surface of the first mask material film 210, and the first mask material film 210 and the second mask material film 220 are made of different materials.

[0045] The first mask material film 210 provides material for subsequently forming a first mask layer.

[0046] The second mask material film 220 provides material for subsequently forming a second mask layer.

[0047] The material of the first mask material film 210 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

[0048] In this embodiment, the material of the first mask material film 210 is silicon nitride.

[0049] The material of the second mask material film 220 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

[0050] In this embodiment, the material of the second mask material film 220 is silicon oxide.

[0051] Please refer to Figure 6, a patterned layer 230 is formed on the surface of the second mask material film 220, and the patterned layer 230 covers a portion of the surface of the second mask material film 220; using the patterned layer 230 as a mask, the second mask material film 220, the first mask material film 210 and the fin material film are etched until the surface of the substrate 200 is exposed, and the initial fin structure 205, the initial first mask layer 211 and the second mask layer 221 are formed on the substrate 200.

[0052] Specifically, the initial fin structure 205 includes a plurality of sacrificial layers 204 overlapping along a normal direction of a top surface of the initial fin structure 205 , and a channel layer 203 located between adjacent sacrificial layers 204 .

[0053] The second mask layer 221 is used to protect the top surface of the initial first mask layer 211 during the subsequent etching of the initial first mask layer 211, and only etches the side wall surface of the initial first mask layer 211, thereby reducing the width of the initial first mask layer 211 along the extension direction of the initial fin structure 205.

[0054] The initial first mask layer 211 is formed by etching the first mask material film 210 . In the present embodiment, the material of the initial first mask layer 211 is silicon nitride.

[0055] The second mask layer 221 is formed by etching the second mask material film 220 . In the present embodiment, the material of the second mask layer 221 is silicon oxide.

[0056] The thickness of the initial first mask layer 211 ranges from 5 nanometers to 100 nanometers.

[0057] The thickness of the second mask layer 221 ranges from 5 nanometers to 100 nanometers.

[0058] After forming the initial fin structure 205 , the initial first mask layer 211 and the second mask layer 221 , the method for forming a semiconductor structure further includes: removing the patterned layer 230 .

[0059] Please refer to Figure 7 , etching the sidewall of the initial first mask layer 211 to reduce the size of the initial first mask layer 211 along the extension direction of the initial fin structure 205 , and forming a first mask layer 212 .

[0060] Along the extension direction of the initial fin structure 205 , the width of the first mask layer 212 ranges from 3 nanometers to 30 nanometers.

[0061] The size of the first mask layer 212 determines the size of the isolation structure formed subsequently.

[0062] The significance of selecting the width range is that: if the width is less than 3 nanometers, the width of the subsequently formed bit isolation structure is small, and the isolation structure cannot play an effective physical isolation role between the fin structures located on both sides of the isolation structure; if the width is greater than 30 nanometers, the width of the subsequently formed isolation structure is too large, and the volume occupied by the isolation structure is too large, resulting in the volume of the fin structure being too small, which is not conducive to the electrical performance of the formed semiconductor structure.

[0063] In the process of etching the sidewall of the initial first mask layer 211 , the etching rate of the initial first mask layer 211 is greater than the etching rate of the second mask layer 221 .

[0064] Since the materials of the initial first mask layer 211 and the second mask layer 221 are different, and the second mask layer 221 is located on the top surface of the initial first mask layer 211, during the etching process of the initial first mask layer 211, the second mask layer 221 can protect the top surface of the initial first mask layer 211, thereby reducing the width of the initial first mask layer 211 and forming the first mask layer 212. This does not require a high-resolution photolithography process, thereby effectively reducing the process difficulty.

[0065] The process of etching the initial first mask layer 211 is a wet etching process, and the process parameters of the wet etching include: the etching solution used includes dilute phosphoric acid, and the temperature ranges from 50 degrees Celsius to 90 degrees Celsius.

[0066] When the process of etching the initial first mask layer 211 is a wet etching process, the wet etching process makes the width of the formed first mask layer 212 within a smaller range and makes the edge roughness of the first mask layer 212 smaller. Since the size and position of the first mask layer 212 define the size and position of the opening formed in the fin structure subsequently, the edge roughness of the first mask layer 212 is smaller, which is conducive to improving the accuracy of pattern transfer, so that the morphology of the formed opening is better, thereby helping to improve the performance of the formed semiconductor structure.

[0067] By controlling the process parameters for etching the sidewalls of the initial first mask layer 211, the width of the formed first mask layer 212 can be made small enough, with high precision, and it is helpful to reduce the difficulty of the process. Then, the initial isolation layer is used as a mask to perform self-aligned etching of the initial fin structure. Since the size and position of the first mask layer 212 define the size and position of the opening in the fin structure, the width of the first mask layer 212 is small, so that the size of the formed opening is small enough, which is helpful to improve the performance of the formed semiconductor structure.

[0068] Please refer to Figure 8 After forming the first mask layer 212 , the second mask layer 221 is removed.

[0069] Specifically, after the second mask layer 221 is removed, the top surface of the first mask layer 212 is exposed.

[0070] In the process of removing the second mask layer 221 , the etching rate of the second mask layer 221 is greater than the etching rate of the first mask layer 212 .

[0071] The process of removing the second mask layer 221 includes: a dry etching process and a wet etching process, or a combination of the two.

[0072] Please refer to Fig. 9 , an initial isolation layer 240 covering the first mask layer 212 is formed on the substrate 200 , the initial isolation layer 240 exposes the top surface of the first mask layer 212 , and the material of the initial isolation layer 240 is different from that of the first mask layer 212 .

[0073] The initial isolation layer 240 is used as a mask for subsequent etching of the initial fin structure 205 .

[0074] The material of the initial isolation layer 240 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

[0075] In this embodiment, the material of the initial isolation layer 240 is silicon oxide.

[0076] The method for forming the initial isolation layer 240 includes: forming an initial isolation layer film (not shown in the figure) on the substrate 200 to cover the top surface and side wall surfaces of the initial fin structure 205 and the top surface and side wall surfaces of the first mask layer 212; and planarizing the initial isolation layer film until the surface of the first mask layer 212 is exposed to form the initial isolation layer 240.

[0077] Please refer to Fig.10 After forming the initial isolation layer 240 , the first mask layer 212 is removed.

[0078] Specifically, after the first mask layer 212 is removed, the top surface of the initial fin structure 205 is exposed.

[0079] Since the material of the initial isolation layer 240 is different from that of the first mask layer 212, it is helpful to select a suitable etching process to ensure that the initial isolation layer 240 will not be damaged by etching while removing the first mask layer 212, thereby not increasing the size of the opening formed subsequently.

[0080] The etching rate of the first mask layer 212 in the process of removing the first mask layer 212 is greater than the etching rate of the initial isolation layer 240, so that in the process of removing the first mask layer 212, no etching damage will be caused to the initial isolation layer 240. In the subsequent process of etching the initial fin structure 205 using the initial isolation layer 240 as a mask, the size and position of the first mask layer 212 accurately determine the size and position of the opening subsequently formed in the fin structure.

[0081] The process of removing the first mask layer 212 includes: a dry etching process and a wet etching process, or a combination of the two.

[0082] Please refer to Fig.11 After removing the first mask layer 212 , the initial fin structure 205 is etched using the initial isolation layer 240 as a mask until the surface of the substrate 200 is exposed, thereby forming a fin structure 206 and an opening 250 in the fin structure.

[0083] In the process step of self-aligning and etching the initial fin structure 205 using the initial isolation layer 240 as a mask, since the size and position of the first mask layer 212 define the size and position of the opening 250 in the fin structure 206, the width of the first mask layer 212 is small and the precision is high, so that the size of the formed opening 250 is small enough, which is beneficial to improving the performance of the formed semiconductor structure.

[0084] Please refer to Fig.12 After forming the fin structure 206 and the opening 250 in the fin structure 206 , an isolation structure 260 is formed in the opening 250 .

[0085] The material of the isolation structure 260 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide, or silicon nitride oxide.

[0086] The method for forming the isolation structure 260 includes: forming an isolation material film (not shown in the figure) in the opening 250 and on the surface of the initial isolation layer 240, and the isolation material film fills the opening 250; flattening the isolation material film until the surface of the initial isolation layer 240 is exposed, and forming the isolation structure 260 in the opening 250.

[0087] The formation process of the isolation material film includes: a fluid chemical vapor deposition process. The isolation material film formed by the fluid chemical vapor deposition process can be better filled in the opening 250 with a relatively large depth and width, and the formed isolation material film has high density and good quality, so that the quality of the formed isolation structure is better, so that the isolation structure 260 can fully play a role of physical isolation, and the performance of the formed semiconductor structure is better.

[0088] Please refer to Fig.13 After forming the isolation structure 260 , the initial isolation layer 240 is etched to form an isolation layer 241 , and the isolation layer 241 covers a portion of the sidewall surface of the fin structure 206 .

[0089] The isolation layer 240 is used to achieve electrical isolation between different devices.

[0090] The isolation layer 241 is formed by etching the initial isolation layer 240 . Accordingly, in this embodiment, the material of the isolation layer 241 is silicon oxide.

[0091] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: forming an initial first mask layer on the surface of the initial fin structure, wherein the initial fin structure includes a plurality of sacrificial layers overlapping along a normal direction of a top surface of the initial fin structure, and a channel layer located between adjacent sacrificial layers; Etching the sidewall of the initial first mask layer to reduce the size of the initial first mask layer along the extension direction of the initial fin structure to form a first mask layer; forming an initial isolation layer covering the first mask layer, wherein the initial isolation layer exposes a top surface of the first mask layer; After forming the initial isolation layer, removing the first mask layer; After removing the first mask layer, the initial fin structure is etched using the initial isolation layer as a mask until the substrate surface is exposed to form a fin structure and an opening in the fin structure; forming an isolation structure in the opening; The size and position of the first mask layer define the size and position of the opening in the fin structure; Among them, the method for etching the side wall of the initial first mask layer includes: forming a second mask layer on the top surface of the initial first mask layer, and the materials of the initial first mask layer and the second mask layer are different; etching the initial first mask layer to form the first mask layer; after forming the first mask layer, removing the second mask layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: Along the extension direction of the initial fin structure, the width of the first mask layer ranges from 3 nanometers to 30 nanometers.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the initial fin structure and the initial first mask layer and the second mask layer includes: forming a fin material film on a substrate, the fin material film including several layers of sacrificial material films overlapping along the normal direction of the substrate, and a channel material film located between adjacent sacrificial material films; forming a first mask material film on the surface of the fin material film; forming a second mask material film on the surface of the first mask material film, the first mask material film and the second mask material film being made of different materials; forming a patterned layer on the surface of the second mask material film, the patterned layer covering a portion of the second mask material film; using the patterned layer as a mask, etching the second mask material film, the first mask material film and the fin material film until the substrate surface is exposed, thereby forming the initial fin structure, the initial first mask layer and the second mask layer on the substrate.

4. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching the initial first mask layer is a wet etching process, and the process parameters of the wet etching include: the etching solution used includes dilute phosphoric acid, and the temperature ranges from 50 degrees Celsius to 90 degrees Celsius.

5. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the second mask layer includes: a dry etching process and a wet etching process, or a combination of the two.

6. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the first mask layer includes: a dry etching process and a wet etching process, or a combination of the two.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the initial first mask layer includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

8. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second mask layer includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

9. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the initial first mask layer ranges from 5 nanometers to 100 nanometers.

10. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the second mask layer ranges from 5 nanometers to 100 nanometers.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the isolation structure includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride or silicon oxynitride.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the initial isolation layer is different from that of the first mask layer; the material of the initial isolation layer includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

13. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the initial isolation layer includes: forming an initial isolation layer film on a substrate to cover the top surface and side wall surfaces of the initial fin structure and the top surface and side wall surfaces of the first mask layer; and planarizing the initial isolation layer film until the surface of the first mask layer is exposed to form the initial isolation layer.

14. The method for forming a semiconductor structure according to claim 11, wherein: Also includes: After forming the isolation structure, the initial isolation layer is etched to form an isolation layer, and the isolation layer covers a portion of the sidewall surface of the fin structure.

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