System and method for training artificial neural networks

Abstract

A computing device includes one or more processors, a first random access memory (RAM) including a magnetic random access memory (MRAM), a second random access memory of a type different from the MRAM, and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data on which an artificial neural network (ANN) is trained and trains the ANN by using the first RAM including the MRAM, executing a first set of training iterations to train the ANN using the first data, and after executing the first set of training iterations, executing a second set of training iterations using the second RAM of a type different from the MRAM to train the ANN using the first data. The computing device stores values ​​of the trained ANN. The trained ANN is configured to classify second data based on the stored values.

Description

Technical Field

[0001] The present invention relates generally to the field of memory applications, including but not limited to the use of magnetic memory to train artificial neural networks. Background Art

[0002] Modern artificial neural networks (ANNs) are trained on large amounts of data to optimize their internal parameters—for example, their weights and biases—before they can be deployed. The optimization process (i.e., training) involves a large number of iterations (i.e., epochs) through the training data. Training requires a large amount of energy usage due to the large amount of data transfer (of training data) to or from the chip and energy leakage from on-chip memory. A related problem is the large footprint of SRAM, which limits the available on-chip memory, thereby increasing the need for data transfer. Summary of the invention

[0003] In order to reduce the cost of the training process, some embodiments of the present disclosure use, at least in part, error-prone memories to train ANNs. Error-prone memories require less energy than error-free memories and have the potential to occupy less on-chip area. Generally, using error-prone memories for part of the ANN training process does not affect the efficiency of the training process, and can actually provide a beneficial degree of randomness for the initial "high entropy" phase of the ANN training process (e.g., searching the ANN parameter space). Such ANNs include, but are not limited to, fully connected networks (FNNs) and convolutional neural networks (CNNs).

[0004] (A1) To this end, in some implementations, a method performed at a computing device is provided. The computing device includes one or more processors, a first random access memory (RAM) including a magnetic random access memory (MRAM), a second random access memory of a type different from the MRAM, and a non-transitory computer-readable storage medium storing instructions executed by the one or more processors. In some embodiments, the non-transitory computer-readable storage medium includes instructions for performing the method. The method includes receiving first data on which an artificial neural network (ANN) is trained. The method includes training the ANN by: using a first RAM including the MRAM, executing a first training iteration set to train the ANN using the first data; and after executing the first training iteration set, using a second RAM of a type different from the MRAM, executing a second training iteration set to train the ANN using the first data. The method further includes storing values ​​of the trained ANN, wherein the trained ANN is configured to classify the second data based on the stored values.

[0005] (A2) In some implementations of (A1), each of the first set of training iterations includes reading values ​​of a weight set of the ANN from a first RAM including an MRAM; using one or more processors, performing a set of arithmetic operations to update the values ​​of the weight set of the ANN; and writing the updated weight set of the ANN to the first RAM including the MRAM.

[0006] (A3) In some implementations of (A2), each of the first set of training iterations includes reading values ​​of a bias set of the ANN from a first RAM including MRAM; using one or more processors, performing a set of arithmetic operations to update the values ​​of the bias set of the ANN; and writing the updated bias set of the ANN to the first RAM including MRAM.

[0007] (A4) In some implementations of (A3), each of the second set of training iterations includes: reading values ​​of a weight set and / or a bias set of the ANN from a second RAM of a type different from the MRAM; using one or more processors, performing a set of arithmetic operations to update the values ​​of the weight set and / or the bias set of the ANN; and writing the updated weight set and / or bias set of the ANN to a second RAM of a type different from the MRAM.

[0008] (A5) In some embodiments of any one of (A3)-(A4), each of the second set of training iterations includes: reading values ​​of an activation set of the ANN from a second RAM of a type different from the MRAM; using one or more processors, performing a set of arithmetic operations to update the values ​​of the activation set of the ANN; and writing the updated activation set of the ANN to a second RAM of a type different from the MRAM.

[0009] (A6) In some implementations of any of (A1)-(A5), the first RAM comprising the MRAM is on the same chip as the one or more processors.

[0010] (A7) In some implementations of any of (A1)-(A6), during the first set of training iterations, the first RAM operates as an error-prone memory.

[0011] (A8) In some implementations of any one of (A1)-(A7), the stored values ​​of the trained ANN include stored weights; the method further includes: during a first set of training iterations, performing error detection, the error detection including detecting errors in corresponding weights stored in a first RAM; and replacing the values ​​stored in the corresponding weights with zero values ​​before using the corresponding weights.

[0012] (A9) In some implementations of any one of (A7)-(A8), a bit error rate of the first RAM is below a threshold for convergence of the first training iteration set.

[0013] (A10) In some implementations of (A9), the convergence threshold is greater than: 10 -3 , 10 -5 , or 10 -7 .

[0014] (A11) In some implementations of any one of (A9)-(A10), the bit error rate is greater than: 10 -4 , 10 -6 , or 10 -8 .

[0015] (A12) In some implementations of any one of (A1)-(A11), the second RAM includes static RAM (SRAM).

[0016] (A13) In some implementations of any of (A1)-(A12), the first set of training iterations includes more than 20%, 40%, 60%, 80%, or 95% of the total number of training iterations used to train the ANN.

[0017] (A14) In some implementations of any one of (A1)-(A13), the method further includes, after training the ANN: receiving second data; and assigning scores to the second data using the stored values ​​of the trained ANN.

[0018] In some implementations, an electronic system is provided. The electronic system includes one or more processors; a first random access memory (RAM) including a magnetic random access memory (MRAM); a second random access memory of a type different from the MRAM; and a non-transitory computer-readable storage medium storing instructions executable by the one or more processors. The instructions include instructions for performing the following operations: training an artificial neural network (ANN) using first data by performing a first training iteration set using the first RAM including the MRAM; training the ANN using the first data by performing a second training iteration set using the second RAM including the type different from the MRAM; and storing values ​​of the trained ANN, wherein the trained ANN is configured to classify second data based on the stored values.

[0019] In some implementations, an electronic system includes a chip.

[0020] In some implementations, the electronic system is configured to perform any one of the methods (A1)-(A14) above.

[0021] (B1) In addition, in some implementations, a method is performed at a computing device, the computing device including one or more processors, a magnetic random access memory (MRAM), and a non-transitory computer-readable storage medium storing instructions. In some embodiments, the non-transitory computer-readable storage medium includes instructions for performing the method. The method includes receiving first data on which an artificial neural network (ANN) is trained. The method further includes using the MRAM to train the ANN by performing a first training iteration set on the first data. Each of the first iteration set includes writing the value of the weight set of the ANN to the MRAM using a first write parameter corresponding to a first write error rate. Training the ANN further includes performing a second training iteration set on the first data after performing the first iteration set. Each of the second iteration set includes writing the value of the weight set of the ANN to the MRAM using a second write parameter corresponding to a second write error rate. The second write error rate is lower than the first write error rate. The method further includes storing the values ​​of the trained ANN, wherein the trained ANN is configured to classify the second data based on the stored values.

[0022] (B2) In some implementations of (B1), each of the first iteration sets includes values ​​written to a bias set and an activation set of the ANN; and each of the second iteration sets includes values ​​written to a bias set and an activation set of the ANN.

[0023] (B3) In some implementations of any of (B1)-(B2), the first write parameter includes a first write pulse duration; and the second write parameter includes a second write pulse duration that is longer than the first write pulse duration.

[0024] (B4) In some implementations of any one of (B1)-(B3), the first write parameter includes a first write current; and the second write parameter includes a second write current greater than the first write current.

[0025] (B5) In some implementations of any one of (B1)-(B4), writing the values ​​of the weight set of the ANN to the MRAM using write parameters corresponding to a first write error rate includes writing the values ​​without using an error correction code; and writing the values ​​of the weight set of the ANN to the MRAM using second write parameters corresponding to a second write error rate includes writing the values ​​using an error correction code.

[0026] (B6) In some implementations of any one of (B1)-(B5), each of the first training iteration sets includes: reading the value of the weight set of the ANN from the MRAM; using one or more processors, performing a set of arithmetic operations to update the value of the weight set of the ANN, wherein the value of the weight set of the ANN written to the MRAM for that iteration is the updated weight set.

[0027] (B7) In some implementations of (B6), each of the second training iteration sets includes: reading the value of the weight set of the ANN from the MRAM; using one or more processors, performing a set of arithmetic operations to update the value of the weight set of the ANN, wherein the value of the weight set of the ANN written to the MRAM for that iteration is the updated weight set.

[0028] (B8) In some implementations of any of (B1)-(B7), the MRAM is on the same chip as the one or more processors.

[0029] (B9) In some implementations of any one of (B1)-(B8), the method further includes: during a first set of training iterations, performing error detection, the error detection comprising detecting errors in corresponding weights stored in the MRAM; and replacing values ​​stored in the corresponding weights with zero values ​​before using the corresponding weights.

[0030] (B10) In some implementations of any one of (B1)-(B9), the first written parameter corresponds to a bit error rate that is below a threshold of convergence of the first set of training iterations.

[0031] (B11) In some implementations of (B10), the converged bit error rate threshold is greater than: 10 -3 , 10 -5 , or 10 -7 .

[0032] (B12) In some implementations of any one of (B1)-(B11), the first write error rate is greater than: 10 -4 , 10 -6 , or 10 -8 .

[0033] (B13) In some implementations of any of (B1)-(B12), the first set of training iterations includes more than 20%, 40%, 60%, 80%, or 95% of the total number of training iterations used to train the ANN.

[0034] (B14) In some implementations of any one of (B1)-(B13), each of the first iteration sets includes reading the value of the weight set of the ANN into the MRAM using a first read parameter corresponding to a first read error rate; and each of the second iteration sets includes reading the value of the weight set of the ANN into the MRAM using a second read parameter corresponding to a second read error rate, wherein the second read error rate is lower than the first read error rate.

[0035] (B15) In some implementations of (B14), the first read parameter includes a first read pulse duration; and the second read parameter includes a second read pulse duration that is longer than the first read pulse duration.

[0036] (B16) In some implementations of any one of (B1)-(B15), the first read parameter includes a first read current; and the second read parameter includes a second read current greater than the first read current.

[0037] (B17) In some implementations of any one of (B1)-(B16), the method further includes, after training the ANN: receiving second data; and assigning scores to the second data using the stored values ​​of the trained ANN.

[0038] In some implementations, a system is provided, the system having one or more processors; a magnetic random access memory (MRAM); a write circuit configured to write data to the MRAM; and a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores instructions for execution by the one or more processors, including instructions for receiving first data on which an artificial neural network (ANN) is trained. The instructions further include instructions for training the ANN by performing a first training iteration set on the first data using the MRAM. Each of the first iteration sets includes using the write circuit to write a value of a weight set of the ANN to the MRAM using a first write parameter corresponding to a first write error rate. The instructions include instructions for performing a second training iteration set on the first data after performing the first iteration set. Each of the second iteration sets includes using the write circuit to write a value of a weight set of the ANN to the MRAM using a second write parameter corresponding to a second write error rate. The second write error rate is lower than the first write error rate. The instructions further include instructions for storing the values ​​of the trained ANN. The trained ANN is configured to classify the second data based on the stored values.

[0039] In some implementations, an electronic system includes a chip.

[0040] In some implementations, the electronic system is configured to perform any one of methods (B1)-(B17) above.

[0041] Although ANN is used as a specific example of a training process that can benefit from the methods and apparatus described herein, it should be noted that any resource-intensive optimization process (e.g., statistical process) can also benefit from the methods and apparatus described herein. Therefore, some embodiments of the present disclosure are not only applicable to ANN, but also to any kind of optimization (e.g., statistical) process. Some embodiments of the present disclosure are applicable to machine learning processes. Such machine learning processes may include supervised learning (e.g., classification, regression), clustering (e.g., latent Dirichlet allocation), dimensionality reduction, structured prediction, anomaly detection, and reinforcement learning. Therefore, training a machine learning process can include training a model for any of the above applications.

[0042] For example, in some embodiments, a method performed at a computing device is provided. The computing device includes one or more processors, a first random access memory (RAM) including a magnetic random access memory (MRAM), a second random access memory of a type different from the MRAM, and a non-transitory computer-readable storage medium storing instructions executed by the one or more processors. The method includes receiving first data on which a machine learning process is trained. The method includes training the machine learning process by: using a first RAM including the MRAM, executing a first training set of iterations to train the machine learning process using the first data; and after executing the first training set of iterations, using a second RAM of a type different from the MRAM, executing a second training set of iterations to train the machine learning process using the first data. The method further includes storing values ​​of the machine learning process based on the training. The values ​​of the machine learning process are used to reconfigure the machine (e.g., to cause the machine to operate differently than before the values ​​were reconfigured).

[0043] As another example, in some implementations, a method is provided for execution at a computing device that includes one or more processors, a magnetic random access memory (MRAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The instructions include instructions for receiving first data on which a machine learning process is trained. The instructions further include instructions for training the machine learning process using the MRAM by executing a first training set of iterations on the first data. Each of the first set of iterations includes writing a value of the machine learning process to the MRAM using a first write parameter corresponding to a first write error rate. Training the machine learning process further includes executing a second set of training iterations on the first data after executing the first set of iterations. Each of the second set of iterations includes writing a value of the machine learning process to the MRAM using a second write parameter corresponding to a second write error rate. The second write error rate is lower than the first write error rate. The instructions further include instructions for storing the value of the machine learning process. The value of the machine learning process is used to reconfigure the machine (e.g., to cause the machine to operate differently than before the value was reconfigured).

[0044] Therefore, methods for training optimization processes (e.g., machine learning processes, ANN training, etc.) are provided for devices and systems, improving the effectiveness, efficiency, and user satisfaction of these systems and devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] For a better understanding of the various described implementations, reference should be made to the following description of the implementations in conjunction with the following drawings, wherein like reference numerals refer to corresponding parts throughout the drawings.

[0046] Figure 1 A schematic diagram illustrating a chip structure according to some implementations.

[0047] Figure 2 A schematic diagram illustrating a chip structure according to some implementations.

[0048] Figure 3A Illustrated is a graph of a loss function according to some implementations.

[0049] Figure 3B Illustrated is a graph of training loss for multiple iterations according to some implementations.

[0050] Figure 4A-4B A method for training an artificial neural network according to some implementations is illustrated.

[0051] Figures 5A-5C A method for training an artificial neural network according to some implementations is illustrated.

[0052] Figure 6is a block diagram of a computer system for training an artificial neural network, according to some embodiments.

[0053] Like reference numerals refer to corresponding parts throughout the several views of the drawings. DETAILED DESCRIPTION

[0054] Reference will now be made in detail to implementations, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a comprehensive understanding of each described implementation. However, it will be apparent to one of ordinary skill in the art that each described implementation may be practiced without these specific details. In other cases, well-known methods, processes, components, circuits, and networks are not described in detail in order to unnecessarily obscure aspects of the embodiments.

[0055] A fully connected artificial neural network can be mathematically represented as follows:

[0056] A1=f1(W1X+b1) (1a)

[0057] A i =f i (W i A i-1 +b i ) (1b)

[0058] O=f n (W n A n-1 +b n ) (1c)

[0059] In the above equations (1a)-(1c), A i Indicates activation, W i represents the weight, b i The variable X represents the input data. The parameter n represents the number of layers in the neural network. The last layer O activated is called the output. During training, the output is compared with the known results to determine the loss function. The function f i is the activation function, usually a simple nonlinear function such as ReLU: f(x) = max(0,x).

[0060] The ANN training process aims to optimize certain network parameters (e.g., weights and biases) through an iterative process. The total number of parameters is usually more than 10 6 And can reach 10 9 Finding the global minimum in such a multidimensional space is a huge challenge. In some implementations, the process begins by initializing the network parameters with random values. Throughout the iterations, the network parameters are adjusted to reduce the value by 10 xdimensional landscape of the error measure (e.g., ideally to find the global minimum of the error measure). The starting point is usually far from the minimum, and there is a risk that the iterative process may get stuck in a local minimum. Therefore, it is often beneficial to start the iterative process with a high entropy search, where each early iteration adjusts the network parameters with large steps to get a rough idea of ​​the error landscape. Towards the end of the process, when the network is close to the desired solution, small careful steps are taken to find the minimum.

[0061] Therefore, for most of the training process, high accuracy is not necessary. Instead, a certain degree of randomness can help to better explore the error landscape. Furthermore, if high accuracy comes at the expense of on-chip area and energy, it may be better to use hardware that places less emphasis on accuracy but focuses on energy cost, area, and / or speed.

[0062] Therefore, according to some embodiments, the ANN training process is divided into two parts: a first set of iterations and a second set of iterations. For the first set of iterations, some implementations replace the high-accuracy memory in the ANN training process with an error-prone memory. As long as the errors are not too frequent to prevent convergence during the first set of iterations of training, the damage to efficiency is small and is usually worthwhile in terms of energy cost, chip area, and speed. This is especially true when the errors are detectable and can be constrained.

[0063] The first set of iterations may include most of the iterations (e.g., epochs) from the beginning of training to almost the end (e.g., until the last 10 epochs). During these iterations, an error-prone energy-efficient memory is used, such as an MRAM or a combination of an MRAM and a small SRAM buffer. During this first phase, when data is stored in or loaded from an external memory, errors may occur at a certain rate that is not too high (e.g., 0.01%-50%). In some embodiments, when an erroneous number is detected, the erroneous number is replaced with a zero value, or the value of the erroneous number is constrained so as not to overwhelm the rest of the data. The resulting information contains a small number of constrained errors, such as 0.01%-50% erroneous zeros. Despite these errors, training of the ANN continues as usual.

[0064] For the last iterations (e.g., the last 10 epochs), an error-free memory is used. This can be SRAM, or it can be MRAM with an error correction algorithm, a combination of the last two, or some other type of memory. This error-free memory enables the process to lead to a minimum (e.g., a global minimum or at least a local minimum) of the loss function that tracks the network parameters.

[0065] It should also be noted that, depending on the read / write time (e.g., the duration of the electrical pulses used to read / write the MRAM), the MRAM can be used as an error-prone memory or a substantially error-free memory. Thus, when the MRAM is used for at least the first portion of the ANN training process, the MRAM can be operated with faster read / write times (e.g., compared to error-free MRAM) because the error rates associated with the short read / write times do not affect the results.

[0066] Furthermore, in some implementations, MRAM is used for all iterations to train the ANN, but the read and / or write speeds are reduced during the final stages of the computation. This makes read and write operations less error-prone near the minimum.

[0067] Figure 1 A schematic diagram of an electronic system including a chip 102 is illustrated. The system includes a first type of RAM (e.g., an error-prone MRAM) and a second type of RAM (e.g., an error-free RAM, which may include one or more external (e.g., off-chip) devices, such as a RAM chip 100). For example, the RAM chip 100 includes DRAM or another form of memory (e.g., which is different from magnetic RAM). In some implementations, the chip 102 includes a RAM interface 104 (e.g., a DDR3 interface) that facilitates communication between the chip 102 and the external RAM chip 100. The chip 102 includes an SRAM buffer / cache 108 for buffering data used by a processor 112 during an ANN training process. For example, the SRAM buffer / cache 108 buffers data stored off-chip (e.g., in the external RAM 100) and / or data stored in the MRAM 110 (e.g., an error-prone memory). For example, during a first set of iterations of the ANN training process, data used to train the ANN is stored in the MRAM 110 (e.g., all data required to perform the first set of iterations of the ANN training process is stored in the MRAM 110). Data is cached from MRAM 110 as needed by SRAM buffer / cache 108, making it available to processor 112 (e.g., an arithmetic logic unit (ALU)), which performs the calculations required to train the ANN. In some implementations, the data includes values ​​of the ANN, such as weights, activations, and biases. In some implementations, the data includes intermediate values ​​(e.g., during training of the ANN).

[0068] During a second set of iterations of the ANN training process, data used to train the ANN is stored in RAM chip 100. The data is bussed on and off chip 102 via RAM interface 104. Data is cached from RAM chip 100 as needed by SRAM buffer / cache 108 so that it is available to processor 112. In some implementations, the second set of iterations produces final values ​​for the ANN parameters (e.g., values ​​for weights and biases after the ANN has been fully trained), which are exported to a host computer via host interface 106.

[0069] In some implementations, processing unit 112 executes instructions for training the ANN (e.g., instructions for executing process 400). In some implementations, instructions executable by one or more processor units 112 are stored in a non-transitory computer-readable storage medium. In some implementations, the instructions are stored on chip 102. In some implementations, the instructions are stored off-chip (e.g., stored in RAM chip 100). In some implementations, chip 102 includes two different types of memory, including MRAM 110 and a second type of memory different from MRAM. For example, although RAM chip 100 is shown as being separated from chip 102, it should be understood that in some implementations, data stored on RAM chip 100 is stored on chip 102.

[0070] Although not shown, in some embodiments, a first RAM (e.g., MRAM 110) of a first iteration set and a second RAM different from the first RAM of a second iteration set reside on chip 102. In some embodiments, one or more processors (e.g., processor unit 112) reside on chip. In some embodiments, a non-transitory computer-readable storage medium storing instructions for training the ANN resides on chip 102. In some embodiments, when chip 102 is powered on, instructions are loaded (e.g., written) to the non-transitory computer-readable storage medium (e.g., from a host computer). In some embodiments, the non-transitory computer-readable storage medium includes a portion of the first RAM or the second RAM. In some embodiments, as described below, after training the ANN, chip 102 is used to classify untrained second data. After receiving the second data, an off-chip memory (e.g., RAM chip 100) stores some or all of the second data.

[0071] Figure 2 A schematic diagram of a computing device (eg, chip 202) is shown. Figure 1 Unlike a system in which a first set of ANN training iterations is executed using a first RAM and a second set of ANN training iterations is executed using a second RAM different from the first RAM, Figure 2A computing device is illustrated in which both a first set of ANN training iterations and a second set of ANN training iterations are executed by the same RAM, such as MRAM 210. However, during the first set of ANN training iterations, the first RAM operates in an error-prone mode, while during the second set of ANN training iterations, the first RAM operates in an error-free mode.

[0072] To this end, in some implementations, the chip 202 includes a host interface 206 (e.g., a PCIe interface), an SRAM buffer / cache 208, an MRAM 210, and a processor unit 212. In some implementations, the MRAM 210 is communicatively coupled to a write circuit 214 for writing data (e.g., ANN weights calculated during a training iteration of the ANN) to the MRAM and a read circuit 216 for reading data (e.g., the value of the ANN weights) from the MRAM. In some embodiments, the write circuit includes a word line and a bit line (e.g., a conductor) and a set of corresponding transistors (e.g., for activating the word line and the bit line). In some embodiments, the write circuit includes or is coupled to a memory storing a first write parameter and a second write parameter. In some embodiments, the read circuit is configured to modify a read parameter for reading a value from the MRAM. In some embodiments, the write circuit is configured to modify a write parameter for writing a value to the MRAM.

[0073] It should be noted that in some embodiments, chip 102 also includes similar write circuits and read circuits, but for simplicity, these features are not shown in FIG. Figure 1 Not shown in FIG.

[0074] In some implementations, chip 202 includes a non-transitory computer-readable storage medium storing instructions for receiving first data on which an artificial neural network (ANN) is trained. The instructions further include instructions for training the ANN by performing a first training iteration set on the first data using MRAM 210. Each iteration in the first iteration set includes writing a value of a weight set of the ANN to the MRAM using a first write parameter corresponding to a first write error rate using a write circuit. The instructions include instructions for performing a second training iteration set on the first data after executing the first iteration set. Each iteration in the second iteration set includes writing a value of a weight set of the ANN to the MRAM using a second write parameter corresponding to a second write error rate using a write circuit. The second write error rate is lower than the first write error rate. The instructions further include instructions for storing the values ​​of the trained ANN. The trained ANN is configured to classify the second data based on the stored values.

[0075] Thus, chip 202 trains the ANN using MRAM (e.g., for all iterations) and reads / writes parameters during a first set of iterations so as to train the ANN with a high read / write error rate, and reads / writes the parameters during a second set of iterations using a lower read / write error rate than that of the first set of iterations.

[0076] In some implementations, chip 202 includes a Figure 1 Any or all modules of chip 102 are described.

[0077] Figure 3A A graph of a loss function 300 for an ANN is illustrated. The loss function 300 is shown for conceptual purposes, namely to illustrate the fact that the initial part of the ANN training process does not require high precision memory. For this reason, the graph of the loss function 300 is simplified to show the error as a function of a single parameter. However, it should be noted that the total number of parameters is typically more than 10 6 And can reach 10 9 .

[0078] As shown, there are two sets of iterations, with the first set of iterations (e.g., represented by dashed lines) being performed on an error-prone memory (e.g., MRAM). The first set of training iterations begins at iteration 302. As the process gets closer to identifying a minimum of the loss function 300, a second set of iterations 304 (e.g., represented by solid lines, performed after the first set of iterations is performed) is performed on an error-free memory (such as SRAM, DRAM, or MRAM with error correction). In some embodiments, the first set of training iterations includes more than 20%, 40%, 60%, 80%, or 95% of the total number of training iterations used to train the ANN. Thus, most of the training of the ANN is performed on dense, fast, energy-efficient memory (e.g., MRAM), even though the memory is less accurate. As shown, when the training iterations converge to a minimum of the loss function 300, the second set of training iterations 304 is executed. As the training iterations are executed, the weights, biases, and / or activation sets are updated.

[0079] Figure 3B 306) and the training loss for the second set of iterations (e.g., the training loss represented by the solid line 308). Figure 3BAs shown, the errors from the first set of iterations (e.g., performed using MRAM) are not too large, and the ANN can still be trained (e.g., to compute and store weights to be applied to untrained data). As explained above, the first set of iterations is performed on MRAM (e.g., or a combination of MRAM and SRAM), while the second set of iterations is performed on SRAM (e.g., or a combination of SRAM and DRAM). During the first set of iterations, when data is stored in or loaded from memory (e.g., external memory), errors may occur at a certain rate that is not too high (e.g., 0.01%-50%). Error detection and masking can then be performed so that when an erroneous number is detected, it is replaced (e.g., masked) with a zero value, or the value of the erroneous number is constrained so as not to overwhelm the rest of the data. The resulting information contains a small number of constrained errors, such as 0.01%-50% erroneous zeros. Despite these errors, training continues as usual.

[0080] Figure 4A-4B A method 400 for training an artificial neural network according to an implementation of the present invention is illustrated. Figure 1 Method 400 is performed (402) at a computing device ) shown in FIG. 1 , the computing device including one or more processors (e.g., processor unit 112), a first random access memory (RAM) including a magnetic random access memory (MRAM) (e.g., MRAM 110), a second random access memory of a different type than the MRAM (e.g., RAM chip 100), and a non-transitory computer-readable storage medium having instructions for execution by the one or more processors.

[0081] In some implementations, the first RAM including the MRAM is on the same chip as the one or more processors (404) (e.g., as shown in FIG. Figure 1 ). For example, MRAM allows for an increase in on-chip memory data, thereby reducing the need for data movement on and off the chip. Data movement requires a lot of energy, so as described herein, using MRAM in method 400 is more efficient than conventional ANN training methods using conventional types of memory. In some implementations, a second RAM of a type different from MRAM is on the same chip as a first RAM including MRAM. In some implementations, the first RAM including MRAM is on a first chip including one or more first processors, and the second RAM different from MRAM is on one or more second chips (e.g., RAM chip 100) different from the first chip and including one or more second processors different from the one or more first processors.

[0082] In some implementations, the second RAM includes (406) static RAM (SRAM). In some implementations, the second RAM includes dynamic RAM (DRAM). In some embodiments, the second RAM includes high bandwidth memory (HBM).

[0083] The method 400 includes receiving (408) first data on which to train an artificial neural network (ANN). In some embodiments, the first data is stored in a database (e.g., stored on-chip or off-chip). In some implementations, the first data is received in response to an instruction from a host (e.g., via the host interface 106).

[0084] The method further includes training (410) the ANN by performing (412) a first training iteration set (e.g., epoch) using the first RAM including the MRAM to train the ANN using the first data. In some implementations, the first training iteration set includes (at least) the first half of the total number of training iterations. In some implementations, the first training iteration set includes all training iterations except the last N iterations, where N is an integer. For example, the first training iteration set includes all training iterations except the last 10 iterations (e.g., N=10).

[0085] In some implementations, each of the first training iteration sets includes (414) reading values ​​of a set of weights of the ANN from a first RAM including MRAM, and performing a set of arithmetic operations using one or more processors to update the values ​​of the set of weights of the ANN. The computing device writes the updated set of weights of the ANN to the first RAM including MRAM. In some implementations, the values ​​of the updated set of weights written to the first RAM include intermediate values ​​(e.g., not final values ​​to be applied to untrained data). For example, the updated values ​​written during the first training iteration set are intermediate values ​​because the final values ​​are determined after executing the second training iteration set. In some implementations, each of the first training iteration sets includes (416) reading values ​​of a set of biases (and / or activations) of the ANN from the first RAM including MRAM, and performing a set of arithmetic operations using one or more processors to update the values ​​of the set of biases (and / or activations) of the ANN. The computing device writes the updated set of biases (and / or activations) of the ANN to the first RAM including MRAM.

[0086] In some embodiments, the MRAM includes a magnetic tunnel junction (MTJ). In some embodiments, the MRAM includes a spin transfer torque (STT) memory. Data stored in the MRAM is encoded by using the relative orientation of two or more magnetic layers (e.g., a free layer and a reference data) in a bit. The value of the bit (e.g., the value of the data stored in the bit) can be determined based on the resistance of the bit, because the resistance of the bit changes based on the relative orientation of the magnetizations due to the magnetoresistive effect (e.g., an antiparallel arrangement of the respective magnetizations of the free layer and the fixed layer has a different resistance than a parallel arrangement of the free layer and the fixed layer).

[0087] In some embodiments, an MRAM bit is written by applying a current pulse (e.g., a write pulse having an amplitude and a time length) to the MRAM bit to switch the bit under the action of the spin transfer torque. The MRAM bit is read by applying a smaller pulse (e.g., a read pulse having a smaller amplitude and / or a shorter time length) to the bit to determine its resistance. For some MRAMs (e.g., MTJ), there are upper and lower limits on the pulse amplitude and length. For example, when reading the bit, the voltage (and thus the current) of the read pulse should be high enough and applied long enough to allow the MTJ state to be determined (e.g., to allow the resistance of the bit to be determined by the sense amplifier), but the voltage should not be too high, or the read pulse should not be too long so that the data is disturbed (e.g., by the action of the STT). When writing the bit, the voltage should be high enough and applied long enough so that the information is correctly and reliably written, but it should not be too high or too long so that the write pulse oppresses or destroys the MTJ.

[0088] Therefore, in various situations, when reading and writing data to MRAM, there are the following types of errors:

[0089] (a1) Write error: When the write pulse voltage amplitude is not high enough (or the write pulse is not long enough) to write data into the MRAM, a write error occurs. Depending on the characteristics of the voltage pulse and the MRAM, the probability of correct writing can be determined.

[0090] (a2) Breakdown Error: A breakdown error occurs when the write voltage amplitude used for writing is too high (or the write pulse is too long) so that the MRAM bit is damaged due to the breakdown of the tunnel oxide barrier.

[0091] (b) Retention error: A retention error occurs when the MRAM does not retain (eg, loses) data that has been written thereto. Depending on the characteristics of the MRAM and the idle time, the probability that the data is correctly retained can be determined.

[0092] (c1) Read Errors: Read errors occur when the applied voltage amplitude is not high enough (or the read pulse is not long enough) to detect the resistance state of the MRAM bit. These errors are caused by the sense amplifier rather than the MRAM.

[0093] (c2) Read disturb errors: A read disturb error occurs when the read voltage is too high (or the read pulse is too long) so that it disturbs the state of the MRAM bit (e.g., effectively writes the MRAM bit) when attempting to read the MRAM bit. The read disturb probability can be calculated from the read pulse and the MRAM characteristics. In some embodiments, read errors are preferred over read disturb errors. Thus, the read operations described herein are performed using read parameters that limit the number of read disturb errors (e.g., the read voltage and / or pulse length is below the corresponding threshold for causing read disturb errors, even at the expense of a greater number of read errors). A conventional way to mitigate the above error types is to use error correction codes (ECC). Error correction codes are expensive, not only in terms of memory capacity, but also because ECC slows down the process of reading the memory. In contrast, in some implementations of the present method, during the first training iteration set, the first RAM is operated (418) as an error-prone memory. For example, the computing device does not perform error correction (or performs minimal error correction) on the MRAM during the first training iteration set.

[0094] In some implementations, the stored values ​​of the trained ANN include stored weights, and the method further includes: during a first set of training iterations, performing (420) error detection, the error detection including detecting errors in corresponding weights (or activations or biases) stored in a first RAM. The value of the weight may be incorrect (e.g., erroneous) because (I) the value of the stored weight is erroneous (e.g., a write error, a retention error, or a read disturbance error); or (II) the value of the stored weight is correct but is read incorrectly. In some embodiments, when an error in the corresponding weight is detected, a zero value is used instead for the iteration (e.g., the iteration begins with an attempt to read the weight set, an error is detected in the weight, and the error is replaced with a zero value to perform the calculation of the iteration). In addition, in some cases (e.g., when the value of the stored weight is erroneous), the computing device replaces the value stored in the corresponding weight with a zero value before using the corresponding weight (e.g., in a forward or backward propagation). In some embodiments, the method includes determining whether the erroneous value is read correctly (e.g., determining whether the value is incorrectly stored or incorrectly read). In some embodiments, replacing the value stored in the corresponding weight with a zero value is performed based on determining that the erroneous value was correctly read.

[0095] In some cases, detecting and masking errors with zero values ​​significantly relaxes the convergence requirements (e.g., the first set of training iterations can tolerate much higher error rates and still converge). In addition to the stored weights, errors may also occur with respect to the stored biases, activations, and possibly other network parameters. The above discussion of errors is generally applicable to any network parameter.

[0096] In some implementations, the first RAM has (422) a bit error rate below a threshold for convergence of the first set of training iterations. For example, in some implementations, the bit error rate can be configured for the first RAM. For example, in some embodiments, the bit error rate of the MRAM depends on the write pulse duration and / or the write pulse length, and the write pulse duration and / or the write pulse length are selected (e.g., from a calibration curve) to operate the first RAM with a bit error rate below the threshold for convergence during the first set of training operations.

[0097] In some implementations, the convergence threshold is greater than (424): 10 -3 , 10 -5 , 10 -7 (e.g., in terms of bit error rate). In some embodiments, the method is performed without error detection and concealment, and the threshold for convergence is greater than 10 -2 , 10 -3 , 10 -4 In some implementations, the bit error rate is greater than (426): 10 -4 , 10 -6 , 10 -8 .

[0098] In some implementations, the first set of training iterations includes (428) more than 20%, 40%, 60%, 80%, or 95% of the total number of training iterations used to train the ANN.

[0099] The method includes, after executing the first training iteration set, executing (430) a second training iteration set to train the ANN using the first data using a second RAM of a type different from the MRAM. In some implementations, the second training iteration set includes all remaining iterations not included in the first training iteration set. For example, the total training iterations used to train the ANN include the first training iteration set and the second training iteration set.

[0100] In some implementations, each of the second training iteration sets includes (432) reading values ​​of a weight set and / or a bias set of the ANN from a second RAM of a type different from the MRAM (e.g., intermediate values ​​stored during the first training iteration set), and performing a set of arithmetic operations using one or more processors to update the values ​​of the weight set and / or bias set of the ANN. Each of the second training iteration sets further includes writing the updated weight set and / or bias set of the ANN to the second RAM of a type different from the MRAM. In some implementations, the values ​​of the updated weight set and / or bias set written during the second training iteration set include intermediate values. In some implementations, at the end of the second training iteration set (e.g., during a final training iteration), the values ​​of the updated weight set and / or bias (and / or activation) set of the ANN include final values, wherein the final values ​​are stored so that the computing device can apply the final stored values ​​to the received second data (e.g., unclassified second data) to classify the second data. In some implementations, the intermediate stored values ​​are stored in MRAM (e.g., on-chip), and the final stored values ​​are stored in non-volatile off-chip memory. In some implementations, all immediately stored values ​​are stored in MRAM (e.g., available from MRAM), and no data needs to be transferred on-chip and / or off-chip buses. In some implementations, only a sub-portion of the intermediate stored values ​​is stored in MRAM.

[0101] The method further includes storing (434) values ​​(e.g., weights and / or biases) of the trained ANN, wherein the trained ANN is configured to classify the second data based on the stored values ​​(e.g., classify the second data by assigning a classification score).

[0102] In some implementations, after training the ANN, the computing device receives (436) second data (e.g., untrained data); and assigns a score to the second data using the stored values ​​of the trained ANN. In some implementations, after assigning a score (e.g., classifying) the second data using the stored (final) values ​​of the trained ANN, the computing device provides the assigned score to the host device (e.g., via host interface 106).

[0103] In some implementations, an electronic system (eg, Figure 1The electronic system includes one or more processors, a first random access memory (RAM) including a magnetic random access memory (MRAM), a second random access memory of a type different from the MRAM, and a non-transitory computer-readable storage medium storing instructions executable by the one or more processors. The instructions include instructions for performing a first training set of iterations using the first RAM including the MRAM to train an artificial neural network (ANN) using first data, performing a second training set of iterations using the second RAM including the type different from the MRAM to train the ANN using the first data, and storing values ​​of the trained ANN. The trained ANN is configured to classify the second data based on the stored values.

[0104] In some implementations, the electronic system includes a chip (e.g., chip 102). In some embodiments, a first RAM (e.g., MRAM 110) and a second RAM (e.g., at least a portion of the second RAM stored in SRAM buffer / cache 108) reside on chip 102. In some embodiments, one or more processors (e.g., processor unit 112) reside on the chip. In some embodiments, one or more processors include an arithmetic logic unit (ALU). In some embodiments, a non-transitory computer-readable storage medium resides on the chip. In some embodiments, when the chip is powered on, the non-transitory computer-readable storage medium is loaded (e.g., written) with instructions. In some embodiments, the non-transitory computer-readable storage medium includes a portion of the first RAM or the second RAM. In some embodiments, the electronic system includes an off-chip memory (e.g., DRAM, HBM, RAM chip 100) that maintains some or all of the first data during the first training iteration set and / or the second training iteration set (e.g., during the first iteration set and the second iteration set, the first data bus is transferred to the chip and off the chip as needed). Likewise, in some embodiments, after receiving the second data, the off-chip memory stores some or all of the second data (e.g., when assigning a score to the second data). In some embodiments, the off-chip memory (e.g., non-volatile memory) stores instructions when the chip is powered off. In some embodiments, the chip includes a buffer (e.g., SRAM buffer / cache 108) communicatively coupled to the off-chip memory. In some embodiments, the buffer includes a portion of the first RAM or the second RAM. In some implementations, the electronic system is configured to perform any of the operations of method 400.

[0105] Figure 5A-5B A method 500 for training an artificial neural network is illustrated. The method 500 is performed on a computing device (e.g., Figure 2The method of executing (502) at a chip 202 shown in FIG. 20 is a computing device including one or more processors, a magnetic random access memory (MRAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. In some implementations, the MRAM is on the same chip as the one or more processors (504).

[0106] The method includes receiving (506) first data on which an artificial neural network (ANN) is trained. Using the MRAM, the computing device trains (508) the ANN by executing a first set of training iterations on the first data. Each of the first set of iterations includes writing values ​​of a weight set of the ANN to the MRAM using a first write parameter corresponding to a first write error rate. The method 400 ( Figure 4A-4B ) discusses various types of errors. For the sake of brevity, these details are not repeated here. The error rates described herein may refer to specific error rates (e.g., error rates for specific types of errors) or net error rates (e.g., rates based on a combination of errors because (I) the stored value for a weight is erroneous (e.g., a write error, a retention error, or a read disturb error); and (II) the stored value for a weight is correct but it is read incorrectly), according to various embodiments.

[0107] In some implementations, each of the first set of training iterations includes (510) reading values ​​of a set of weights of the ANN from the MRAM and performing a set of arithmetic operations using one or more processors to update the values ​​of the set of weights of the ANN. The values ​​of the set of weights of the ANN written to the MRAM for that iteration are the updated set of weights.

[0108] In some implementations, during the first training iteration set, the computing device performs (512) error detection, which includes detecting errors in corresponding weights (or activations or biases) stored in the MRAM and replacing the values ​​stored for the corresponding weights with zero values ​​before using the corresponding weights (e.g., in forward or backward propagation). In some cases, detecting and masking errors with zero values ​​significantly relaxes the requirements for convergence (e.g., the first training iteration set can tolerate a much higher bit error rate and still converge).

[0109] In some implementations, the first write parameter corresponds (514) to a bit error rate that is below a threshold for convergence of the first set of training iterations (e.g., during a read process, errors are generated at a bit error rate that is below the threshold for convergence). In some embodiments, the bit error rate can be configured for the first RAM. For example, in some embodiments, the bit error rate of the MRAM depends on a write pulse duration and / or a write pulse length, and the write pulse duration and / or the write pulse length are selected (e.g., from a calibration curve) to operate the first RAM at a bit error rate that is below the threshold for convergence during the first set of training operations.

[0110] In some implementations, the convergence threshold is greater than (516): 10 -3 , 10 -5 , or 10 -7 (516). In some embodiments, the method is performed without error detection and masking, and the threshold for convergence is greater than 10 -2 , 10 -3 or 10 -4 .

[0111] In some implementations, the first write error rate is greater than (518): 10 -4 , 10 -6 , or 10 -8 .

[0112] In some implementations, the first set of training iterations includes (520) more than 20%, 40%, 60%, 80%, or 95% of the total number of training iterations used to train the ANN.

[0113] After executing the first set of iterations, the computing device executes (522) a second set of training iterations on the first data. Each of the second set of iterations includes writing values ​​of the weight set of the ANN to the MRAM using second write parameters corresponding to a second write error rate (e.g., generating errors at a bit error rate below a converged threshold during a read process). The second write error rate is lower than the first write error rate.

[0114] In some embodiments, the write error rate gradually decreases. To this end, in some embodiments, there are more than two iteration sets, including a third iteration set. Each of the third iteration sets includes writing the value of the weight set of the ANN to the MRAM using a third write parameter corresponding to the third write error rate. The third write error rate is lower than the first write error rate and the second error rate. In some embodiments, each iteration set includes a single iteration. In some embodiments, each iteration set includes multiple iterations.

[0115] In some implementations, each of the first iteration sets includes (524) writing values ​​of a bias set and an activation set of the ANN, and each of the second iteration sets includes writing values ​​of a bias set and an activation set of the ANN.

[0116] In some implementations, the first write parameter includes (526) a first write pulse duration, and the second write parameter includes a second write pulse duration that is longer than the first write pulse duration.

[0117] In some implementations, the first write parameter includes (528) a first write current and the second write parameter includes a second write current greater than the first write current.

[0118] In some implementations, writing the values ​​of the weight set of the ANN to the MRAM using write parameters corresponding to a first write error rate includes (530) writing the values ​​without using an error correction code, and writing the values ​​of the weight set of the ANN to the MRAM using second write parameters corresponding to a second write error rate includes writing the values ​​using an error correction code. In some embodiments, the first iteration set includes error detection and masking, as described above, but does not include error correction.

[0119] In some implementations, each of the second set of training iterations includes (532) reading a value of a set of weights of the ANN from the MRAM and performing a set of arithmetic operations using one or more processors to update the value of the set of weights of the ANN. The value of the set of weights of the ANN written to the MRAM for that iteration is the updated set of weights.

[0120] In some implementations, each of the first iteration sets includes (534) reading values ​​of the weight set of the ANN to the MRAM using first read parameters corresponding to a first read error rate, and each of the second iteration sets includes reading values ​​of the weight set of the ANN to the MRAM using second read parameters corresponding to a second read error rate. The second read error rate is lower than the first read error rate.

[0121] In some embodiments using a third set of iterations, each of the third set of iterations includes reading values ​​of a set of weights of the ANN into the MRAM using third read parameters corresponding to a third read error rate. The third read error rate is lower than the first read error rate and the second read error rate (e.g., the read error rate decreases as training progresses).

[0122] In some implementations, the first read parameter includes (536) a first read pulse duration, and the second read parameter includes a second read pulse duration that is longer than the first read pulse duration.

[0123] In some implementations, the first read parameter includes (538) a first read current and the second read parameter includes a second read current greater than the first read current.

[0124] The computing device stores (540) the values ​​of the trained ANN. The trained ANN is configured to classify second data (eg, untrained data) based on the stored values.

[0125] In some implementations, after training the ANN, the computing device receives ( 542 ) second data and assigns scores to the second data using the stored values ​​of the trained ANN.

[0126] In some implementations, an electronic system is provided. The system includes one or more processors, a magnetic random access memory (MRAM), a write circuit configured to write data to the MRAM, and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. In some embodiments, the write circuit includes a word line and a bit line (e.g., a conductor) and a corresponding set of transistors (e.g., for activating the word line and the bit line). In some embodiments, the write circuit includes or is coupled to a memory storing a first write parameter and a second write parameter. The stored instructions include instructions for receiving first data on which an artificial neural network (ANN) is trained. The instructions further include instructions for using the MRAM to train the ANN by performing a first training iteration set on the first data. Each of the first iteration sets includes using the write circuit to write a value of a weight set of the ANN to the MRAM using a first write parameter corresponding to a first write error rate. The instructions include instructions for performing a second training iteration set on the first data after executing the first iteration set. Each of the second iteration sets includes using the write circuit to write a value of a weight set of the ANN to the MRAM using a second write parameter corresponding to a second write error rate. The second write error rate is lower than the first write error rate. The instructions further include instructions for storing the values ​​of the trained ANN. The trained ANN is configured to classify the second data based on the stored values.

[0127] In some implementations, the electronic system includes a chip (e.g., chip 202). In some embodiments, the MRAM resides on the chip. In some embodiments, one or more processors reside on the chip. In some embodiments, the one or more processors include an arithmetic logic unit (ALU). In some embodiments, a non-transitory computer-readable storage medium resides on the chip. In some embodiments, when the chip is powered on, the non-transitory computer-readable storage medium is loaded (e.g., written) with instructions. In some embodiments, the non-transitory computer-readable storage medium includes a portion of the MRAM. In some embodiments, the electronic system includes an off-chip memory (e.g., DRAM, HBM) that maintains some or all of the first data during the first training iteration set and / or the second training iteration set (e.g., during the first iteration set and the second iteration set, the first data bus is transferred to the chip and off the chip as needed). Similarly, in some embodiments, after receiving the second data, the off-chip memory stores some or all of the second data (e.g., when assigning a score to the second data). In some embodiments, when the chip is powered off, the off-chip memory (e.g., non-volatile memory) stores instructions. In some embodiments, the chip includes a buffer communicatively coupled to the off-chip memory. In some embodiments, the buffer includes a portion of the MRAM. In some embodiments, the buffer includes a type of memory other than MRAM (eg, SRAM).

[0128] In some implementations, the electronic system is configured to perform any of the operations described with reference to method 500 .

[0129] Figure 6 6 is a block diagram of a computer system 630 for training an artificial neural network according to some embodiments. Computer system 630 generally includes one or more processors (sometimes referred to as CPUs) 602 for executing programs or instructions; memory 610; one or more communication interfaces 606; and one or more communication buses 605 for interconnecting these components. In some embodiments, processor 602 includes reference Figure 1-2 The chip 102 / 202 shown and described. The computer system 630 optionally includes a user interface 609 coupled to other components of the computer system 630 via one or more communication buses 605, the user interface 609 including a display device 611 and one or more input devices 613 (e.g., one or more of a keyboard, a mouse, a touch screen, a keypad, etc.). The one or more communication buses 605 may include circuits (sometimes referred to as a chipset) that interconnect system components and control communications between system components.

[0130] Computer system 630 uses communication interface 606 to transmit information to external systems and receive communications from external systems, such as external database 652 (e.g., which may store ANN training data or data classified by a trained ANN). The connection between computer system 630 and external database 652 may include a communication network, such as the Internet or a public or private wireless network.

[0131] The memory 610 includes high-speed random access memory, such as DRAM, SRAM, DDRRAM or other random access solid-state memory devices, and may include non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices or other non-volatile solid-state storage devices. The memory 610 optionally includes one or more storage devices placed away from the CPU 602. The memory 610 or the non-volatile memory device in the memory 610 includes a computer-readable storage medium. In some embodiments, the memory 610 or the computer-readable storage medium of the memory 610 stores the following programs, modules and data structures or subsets thereof:

[0132] Operating system 612, which includes processes for handling various basic system services and for performing hardware-related tasks;

[0133] A communications module 614 that operates in conjunction with the communications interface 606 to handle communications between the computer 130 and external systems;

[0134] A user interface module 616 for receiving information from one or more input devices 613 of the user interface database 609 and communicating the information to a user of the computer system 630 via one or more displays or output devices 611;

[0135] ANN training module 618 for training an artificial neural network (e.g., causing the system to perform any ANN training method described herein);

[0136] • ANN training data 620 (eg, a set of inputs and labels indicating correct classifications) used to train the artificial neural network.

[0137] Each of the operating system 612 and the modules and applications identified above corresponds to an instruction set for performing the above functions. The instruction set can be executed by one or more processors 602 of the computer system 630. The modules, applications or programs (i.e., instruction sets) identified above need not be implemented as separate software programs, processes or modules, and therefore in various embodiments, various subsets of these modules can be combined or otherwise rearranged. In some embodiments, the memory 610 stores a subset of the modules and data structures identified above. In addition, the memory 610 optionally stores additional modules and data structures not described above.

[0138] Figure 6 It is intended more as a functional description of various features that may be present in computer system 630 than as a schematic diagram of the architecture of the embodiments described herein. In practice, and as recognized by one of ordinary skill in the art, items shown separately may be combined and some items may be separated. For example, Figure 6 Some items shown separately in the figure can be combined into a single module or component, and a single item can be implemented using two or more modules or components. The actual number of modules and components and how features are distributed between them will vary depending on the implementation.

[0139] Additionally, in some embodiments, some or all of the above functions may be implemented using hardware circuits (e.g., field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), "systems on a chip" including processors and memory, etc.). To this end, in some embodiments, CPU 602 includes dedicated hardware for performing these and other tasks.

[0140] Although some of the various figures show multiple logical stages in a particular order, stages that are not dependent on order may be reordered, and other stages may be combined or decomposed. Although some reordering or other groupings are specifically mentioned, others will be apparent to one of ordinary skill in the art, and thus the ordering and groupings presented herein are not an exhaustive list of alternatives. Furthermore, it should be appreciated that the stages may be implemented in hardware, firmware, software, or any combination thereof.

[0141] It should also be understood that, although in some cases, the terms first, second, etc. are used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the various described implementations, a first electronic device can be referred to as a second electronic device, and similarly, a second electronic device can be referred to as a first electronic device. Both the first electronic device and the second electronic device are electronic devices, but they are not electronic devices of the same type.

[0142] The terms used in the description of the various described embodiments described herein are only for the purpose of describing a specific implementation, and are not intended to be limiting. As used in the description of each described implementation and the appended claims, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly states otherwise. It should also be understood that the terms "and / or" used herein refer to and encompass any and all possible combinations of one or more of the items listed in question. It will be further understood that the terms "include" and / or "comprise" when used in this specification specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0143] As used herein, the term "if" is alternatively interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting" or "according to determining", depending on the context. Similarly, the phrases "if determining" or "if [the condition or event] is detected" are alternatively interpreted to mean "upon determining" or "in response to determining" or "upon detecting [the condition or event]" or "in response to detecting [the condition or event]" or "according to detecting [the condition or event]".

[0144] For purposes of explanation, the foregoing description has been described with reference to specific implementations. However, the above illustrative discussion is not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. In light of the above teachings, many modifications and variations are possible. Implementations are selected to best explain the principles underlying the claims and their practical application, thereby enabling others skilled in the art to best use implementations with various modifications suitable for the specific use contemplated.

Claims

1. A method for training an artificial neural network, comprising: A set of operations is performed at a computing device including one or more processors, a first random access memory (RAM) including a magnetic random access memory (MRAM), a second random access memory of a type other than the MRAM, and a non-transitory computer-readable storage medium storing instructions executed by the one or more processors, the set of operations comprising: receiving first data on which to train an artificial neural network (ANN); pass: performing a first set of training iterations to train the ANN using the first data using a first RAM including the MRAM, wherein the first RAM operates as an error-prone memory; and After performing the first set of training iterations, performing a second set of training iterations to train the ANN using the first data using a second RAM of a type different from the MRAM, to train the ANN; and storing values ​​of the trained ANN, wherein the trained ANN is configured to classify second data based on the stored values, wherein the stored values ​​of the trained ANN include stored weights; The method further comprises: During the first set of training iterations, performing error detection, the error detection comprising detecting errors in corresponding weights stored in the first RAM; Prior to using the corresponding weight, the value stored in the corresponding weight is replaced with a zero value.

2. The method of claim 1, wherein: Each of the first training iteration sets includes: reading values ​​of a set of weights of the ANN from the first RAM including the MRAM; using the one or more processors, performing a set of arithmetic operations to update the values ​​of the set of weights of the ANN; and The updated set of weights of the ANN is written to the first RAM including the MRAM.

3. The method of claim 2, wherein: Each of the first training iteration sets includes: reading a value of a bias set of the ANN from the first RAM including the MRAM; using the one or more processors, performing a set of arithmetic operations to update the values ​​of the set of biases of the ANN; and The updated set of biases of the ANN is written to the first RAM including the MRAM.

4. The method of claim 3, wherein: Each of the second training iteration sets includes: reading the values ​​of the set of weights and / or the set of biases of the ANN from the second RAM of a type different from MRAM; using the one or more processors, performing the set of arithmetic operations to update the values ​​of the set of weights and / or the set of biases of the ANN; and The updated set of weights and / or biases of the ANN is written to the second RAM of a type different from the MRAM.

5. The method according to any one of claims 3 to 4, wherein: Each of the second training iteration sets includes: reading the value of the activation set of the ANN from the second RAM of a type different from the MRAM; using the one or more processors, performing the set of arithmetic operations to update the values ​​of the activation set of the ANN; and The updated activation set of the ANN is written to the second RAM of a type different from the MRAM.

6. The method of claim 1, wherein: The first RAM including the MRAM is on a same chip as the one or more processors.

7. The method of claim 1, wherein: The first RAM has a bit error rate below a threshold of convergence for the first set of training iterations.

8. The method of claim 7, wherein: The convergence threshold is greater than: 10 -3 .

9. The method of claim 7, wherein: The convergence threshold is greater than: 10 -5 .

10. The method of claim 7, wherein: The convergence threshold is greater than: 10 -7 .

11. The method of claim 7, wherein: The bit error rate is greater than: 10 -4 .

12. The method of claim 7, wherein: The bit error rate is greater than: 10 -6 .

13. The method of claim 7, wherein: The bit error rate is greater than: 10 -8 .

14. The method of claim 1, wherein: The second RAM includes a static RAM (SRAM).

15. The method of claim 1, wherein: The first set of training iterations includes more than 20% of the total number of training iterations used to train the ANN.

16. The method of claim 1, wherein: The first set of training iterations includes more than 40% of the total number of training iterations used to train the ANN.

17. The method of claim 1, wherein: The first set of training iterations includes more than 60% of the total number of training iterations used to train the ANN.

18. The method of claim 1, wherein: The first set of training iterations includes more than 80% of the total number of training iterations used to train the ANN.

19. The method of claim 1, wherein: The first set of training iterations includes more than 95% of the total number of training iterations used to train the ANN.

20. The method of claim 1, further comprising, after training the ANN: receiving second data; and Using the stored values ​​of the trained ANN, a score is assigned to the second data.

21. An electronic system for training an artificial neural network, comprising: one or more processors; a first random access memory (RAM) comprising a magnetic random access memory (MRAM); a second random access memory of a type other than MRAM; A non-transitory computer-readable storage medium storing instructions executable by the one or more processors, the instructions comprising instructions for: training an artificial neural network (ANN) using first data by performing a first set of training iterations using a first RAM including the MRAM, wherein the first RAM operates as an error-prone memory; training the ANN using the first data by performing a second set of training iterations using a second RAM comprising a type different from the MRAM; as well as storing values ​​of the trained ANN, wherein the trained ANN is configured to classify second data based on the stored values, wherein the stored values ​​of the trained ANN include stored weights; The instructions also include instructions for: During the first set of training iterations, performing error detection, the error detection comprising detecting errors in corresponding weights stored in the first RAM; Prior to using the corresponding weight, the value stored in the corresponding weight is replaced with a zero value.

22. An electronic system for training an artificial neural network, comprising: one or more processors; a first random access memory (RAM) comprising a magnetic random access memory (MRAM); a second random access memory of a type other than MRAM; A non-transitory computer-readable storage medium storing instructions executable by the one or more processors, the instructions comprising instructions for performing the method of any one of claims 1-20.

23. A non-transitory computer-readable storage medium storing one or more programs executable by an electronic device, the electronic device comprising one or more processors, a first random access memory (RAM) comprising a magnetic random access memory (MRAM), and a second random access memory of a type other than the MRAM, the one or more programs comprising instructions for performing the method of any one of claims 1-20.

24. A method for training an artificial neural network, comprising: A set of operations is performed at a computing device including one or more processors, a magnetic random access memory (MRAM), and a non-transitory computer-readable storage medium storing instructions executed by the one or more processors, the set of operations comprising: receiving first data on which to train an artificial neural network (ANN); Using the MRAM, by: performing a first set of training iterations on the first data, wherein each of the first set of training iterations includes writing values ​​of a set of weights of the ANN to the MRAM using first write parameters corresponding to a first write error rate; and After performing the first set of training iterations, performing a second set of training iterations on the first data, wherein each of the second set of training iterations includes writing values ​​of the set of weights of the ANN to the MRAM using second write parameters corresponding to a second write error rate, wherein the second write error rate is lower than the first write error rate, To train the ANN; storing values ​​of the trained ANN, wherein the trained ANN is configured to classify second data based on the stored values, The method further comprises: During the first set of training iterations, performing error detection, the error detection comprising detecting errors in corresponding weights stored in the MRAM; Prior to using the corresponding weight, the value stored for the corresponding weight is replaced with a zero value.

25. The method of claim 24, wherein: Each of the first training iteration sets includes values ​​written to a bias set and an activation set of the ANN; and Each of the second training iteration sets includes values ​​of the bias set and the activation set written to the ANN.

26. The method of claim 24, wherein: The first write parameter comprises a first write pulse duration; and The second write parameters include a second write pulse duration that is longer than the first write pulse duration.

27. The method of claim 24, wherein: The first writing parameter includes a first writing current; and The second write parameter includes a second write current greater than the first write current.

28. The method of claim 24, wherein: Writing the values ​​of the set of weights of the ANN to the MRAM using write parameters corresponding to the first write error rate includes writing the values ​​without using an error correction code; as well as Writing the values ​​of the set of weights of the ANN to the MRAM using second write parameters corresponding to the second write error rate includes writing the values ​​using an error correction code.

29. The method of claim 24, wherein: Each of the first training iteration sets includes: reading the value of the set of weights of the ANN from the MRAM; performing, using the one or more processors, a set of arithmetic operations to update the values ​​of the set of weights of the ANN, Wherein, the value of the weight set of the ANN written to the MRAM for the first training iteration set is the updated weight set.

30. The method of claim 29, wherein: Each of the second training iteration sets includes: reading the value of the set of weights of the ANN from the MRAM; performing, using the one or more processors, the set of arithmetic operations to update the values ​​of the set of weights of the ANN, Wherein, the value of the weight set of the ANN written to the MRAM for the second training iteration set is the updated weight set.

31. The method of claim 24, wherein: The MRAM is on the same chip as the one or more processors.

32. The method of claim 24, wherein: The first written parameter corresponds to a bit error rate that is below a threshold for convergence of the first set of training iterations.

33. The method of claim 32, wherein: The convergence threshold is greater than: 10 -3 .

34. The method of claim 32, wherein: The convergence threshold is greater than: 10 -5 .

35. The method of claim 32, wherein: The convergence threshold is greater than: 10 -7 .

36. The method of claim 24, wherein: The first write error rate is greater than: 10 -4 .

37. The method of claim 24, wherein: The first write error rate is greater than: 10 -6 .

38. The method of claim 24, wherein: The first write error rate is greater than: 10 -8 .

39. The method of claim 24, wherein: The first set of training iterations includes more than 20% of the total number of training iterations used to train the ANN.

40. The method of claim 24, wherein: The first set of training iterations includes more than 40% of the total number of training iterations used to train the ANN.

41. The method of claim 24, wherein: The first set of training iterations includes more than 60% of the total number of training iterations used to train the ANN.

42. The method of claim 24, wherein: The first set of training iterations includes more than 80% of the total number of training iterations used to train the ANN.

43. The method of claim 24, wherein: The first set of training iterations includes more than 95% of the total number of training iterations used to train the ANN.

44. The method of claim 24, wherein: Each of the first set of training iterations includes reading values ​​of the set of weights of the ANN into the MRAM using first read parameters corresponding to a first read error rate; as well as Each of the second set of training iterations includes reading values ​​of the set of weights of the ANN into the MRAM using second read parameters corresponding to a second read error rate, wherein the second read error rate is lower than the first read error rate.

45. The method of claim 44, wherein: The first read parameter includes a first read pulse duration; as well as The second read parameters include a second read pulse duration that is longer than the first read pulse duration.

46. ​​The method of claim 36, wherein: The first read parameter includes a first read current; and The second read parameter includes a second read current greater than the first read current.

47. The method of claim 24, further comprising, after training the ANN: receiving second data; and Using the stored values ​​of the trained ANN, a score is assigned to the second data.

48. A system for training an artificial neural network, comprising: one or more processors; Magnetic random access memory (MRAM); a write circuit configured to write data into the MRAM; as well as A non-transitory computer-readable storage medium storing instructions for execution by the one or more processors, the instructions comprising instructions for: receiving first data on which to train an artificial neural network (ANN); Using the MRAM, by: performing a first set of training iterations on the first data, wherein each of the first set of training iterations includes using the write circuit to write values ​​of a weight set of the ANN to the MRAM using first write parameters corresponding to a first write error rate; and After performing the first set of training iterations, performing a second set of training iterations on the first data, wherein each of the second set of training iterations includes using the write circuit to write values ​​of the weight set of the ANN to the MRAM using second write parameters corresponding to a second write error rate, wherein the second write error rate is lower than the first write error rate, To train the ANN; storing values ​​of the trained ANN, wherein the trained ANN is configured to classify second data based on the stored values, The instructions also include instructions for: During the first set of training iterations, performing error detection, the error detection comprising detecting errors in corresponding weights stored in the first RAM; Prior to using the corresponding weight, the value stored in the corresponding weight is replaced with a zero value.

49. A system for training an artificial neural network, comprising: one or more processors; Magnetic random access memory (MRAM); a write circuit configured to write data into the MRAM; as well as A non-transitory computer-readable storage medium storing instructions for execution by the one or more processors, the instructions comprising instructions for performing the method of any of claims 24-47.

50. A non-transitory computer-readable storage medium storing one or more programs executed by a system having one or more processors, a magnetic random access memory (MRAM), and a write circuit configured to write data to the MRAM, the one or more programs comprising instructions for performing the method of any of claims 24-47.

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