A chip verification method and device

Abstract

An embodiment of the present application discloses a chip verification method. When verifying a chip, verification cases corresponding to a first verification method are obtained to verify a first feature of the chip using the verification cases, and a first coverage rate is obtained. When it is impossible to determine whether the first feature of the chip is verified based on the first coverage rate, the first feature of the chip is verified using a second verification method. The verification result of the first feature is determined using the second coverage rate. That is, in the embodiment of the present application, by fusing the first coverage rate and the second coverage rate, when it is impossible to determine whether the first feature is verified by the first coverage rate, the second coverage rate can be used for verification, thereby accelerating the verification convergence speed and reducing the verification time.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a chip verification method and device. Background Art

[0002] In recent years, the integration of chips has been getting higher and higher. At each stage of chip design, different verification methods and a variety of verification tools need to cooperate with each other to solve different verification problems, which brings many difficulties and challenges to the chip verification work. According to statistics, simulation verification occupies more than half of the R & D workload.

[0003] The verification method driven by coverage can quantify the verification progress and ensure the completeness of verification. Generally, specific coverage targets will be specified in the verification plan, and it can be determined whether the verification meets the requirements through coverage verification. Coverage is a means to measure the integrity of testing and a measure of the effectiveness of testing. Test coverage is an evaluation of the completeness of testing, which is represented by the coverage of test requirements and test cases or the coverage of the executed code. However, the existing coverage verification methods have a slow convergence speed, resulting in a long verification time and affecting the verification speed. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a chip verification method and device to accelerate the convergence speed of chip verification and improve verification efficiency.

[0005] To achieve the above object, the technical solutions provided by the embodiments of the present application are as follows:

[0006] In the first aspect of the embodiments of the present application, a chip verification method is provided, characterized in that the method includes:

[0007] Verify the first feature of the chip using a first verification method to obtain a first coverage rate;

[0008] When it is impossible to determine whether the first feature of the chip is verified according to the first coverage rate, verify the first feature of the chip using a second verification method to obtain a second coverage rate;

[0009] Determine the verification result of the first feature according to the second coverage rate.

[0010] In a specific implementation, the first coverage rate is a functional coverage rate, the second coverage rate is an assertion coverage rate, and the first feature is the functional feature of the chip.

[0011] In a specific implementation, the first coverage rate is an assertion coverage rate, the second coverage rate is a functional coverage rate, and the first feature is the value or state of the interface signal of the chip.

[0012] In a specific implementation, the database of the first coverage rate and the database of the second coverage rate are the same database.

[0013] In a specific implementation, when it is impossible to determine whether the first feature of the chip is verified according to the first coverage rate, the second verification method is used to verify the first feature of the chip, and obtaining the second coverage rate includes:

[0014] Integrate the database corresponding to the first verification method and the database corresponding to the second verification method to obtain verification cases;

[0015] Use the verification cases to verify the chip to obtain the second coverage rate.

[0016] In the second aspect of the embodiments of the present application, a chip verification device is provided. The device includes:

[0017] A first acquisition unit, configured to use a first verification method to verify the first feature of the chip and obtain the first coverage rate;

[0018] A second acquisition unit, configured to use a second verification method to verify the first feature of the chip and obtain the first coverage rate when it is impossible to determine whether the first feature of the chip is verified according to the first coverage rate;

[0019] A determination unit, configured to determine the verification result of the first feature according to the second coverage rate.

[0020] In the third aspect of the embodiments of the present application, a chip verification system is provided. The system includes: a first coverage rate collector, a second coverage rate collector, and a coverage rate fuser;

[0021] The first coverage rate collector is configured to collect the first coverage rate;

[0022] The second coverage rate collector is configured to collect the second coverage rate;

[0023] The coverage rate fuser is configured to fuse the first coverage rate collected by the first coverage rate collector and the first coverage rate collected by the second coverage rate collector.

[0024] In a specific implementation, the system further includes: a use case generator;

[0025] The use case generator is configured to generate verification cases according to the fusion result of the coverage rate fuser.

[0026] In the fourth aspect of the embodiments of the present application, an electronic device is provided, including: a processor, a memory;

[0027] The memory is used to store computer-readable instructions or computer programs;

[0028] The processor is used to read the computer-readable instructions or the computer program, so that the device implements the chip verification method described in the first aspect.

[0029] In the fifth aspect of the embodiments of the present application, a computer-readable storage medium is provided, including instructions or a computer program, which when running on a computer, causes the computer to execute the chip verification method described in the first aspect.

[0030] Thus, the embodiments of the present application have the following beneficial effects:

[0031] In the embodiments of the present application, when verifying a chip, a verification case corresponding to the first verification method is obtained to verify the first feature of the chip using the verification case, and a first coverage rate is obtained. When it is impossible to determine whether the first feature of the chip is verified according to the first coverage rate, the first feature of the chip is verified using the second verification method. The verification result of the first feature is determined using the second coverage rate. That is, in the embodiments of the present application, by fusing the first coverage rate and the second coverage rate, when it is impossible to determine whether the first feature is verified using the first coverage rate, the second coverage rate can be used for verification, thereby accelerating the verification convergence speed and reducing the verification time. Description of the Drawings

[0032] Figure 1 It is a schematic diagram of a traditional coverage verification scenario;

[0033] Figure 2 It is a flowchart of a chip verification method provided by the embodiments of the present application;

[0034] Figure 3 It is a structural diagram of a chip verification device provided by the embodiments of the present application;

[0035] Figure 4 It is a structural diagram of a chip verification system provided by the embodiments of the present application. Detailed Embodiments

[0036] To make the above objects, features, and advantages of the present application more obvious and understandable, the embodiments of the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0037] Coverage is a general term for measuring the completeness of design verification. As tests gradually cover various reasonable scenarios, the simulation process will slowly outline the design situation. The coverage tool collects information during the simulation process, and then performs subsequent processing and obtains a coverage report. Use this report to find blind spots outside of coverage, and then modify existing tests or create new tests to fill these blind spots. This process can be iterated until you are satisfied with the coverage.

[0038] The traditional verification method is directed testing, which adds specific stimuli to the design. After the simulation is completed, the result files and waveforms are manually checked to ensure that the simulation results are consistent with the expected results. The disadvantage of this method is that it is difficult to achieve the expected coverage. In contrast to directed testing, random testing is a controlled random stimulus that increases the probability of errors being detected by constraining the random sequence within a reasonable range. In addition, compared with directed testing, random testing greatly improves the convergence speed of verification coverage.

[0039] At present, chip verification coverage is mainly divided into three types: functional coverage, assertion coverage, and code coverage. Functional coverage is mainly used to measure whether the various functions implemented by the design are executed according to the expected behavior, that is, whether they meet the functional point requirements of the design specification, and to detect whether the test stimulus covers the functional points listed in the test plan. Assertion coverage is generally used to measure the verification progress of timing-related test cases. It is used to declaratively code one or more design signals in logic or timing at one time or over a period of time. Code coverage is a measure of whether the entire design test is thorough, describing the proportion and degree of source code tested in the program.

[0040] Different from the commonly used random constraint verification method, the coverage-driven random verification is that the coverage collector merges the collected coverage with the existing coverage database in each test, and feeds the merged coverage database back to the next random constraint. This can further narrow the random constraint domain, bias it to generate a random constraint sequence, and cover the function points that were not tested in the previous verification. For example Figure 1 As shown, the function coverage collector merges the collected function coverage with the existing function coverage database in each test, and feeds the merged coverage database back to the next constraint to cover the function points that have not been tested before, and continuously improve the function coverage of the test. Similarly, the verification of assertion coverage is also improved in the same way.

[0041] From the above, we can see that the functional coverage and assertion coverage are two parallel lines collected separately without interfering with each other. The disadvantage of this working mode is that when encountering functional points that are difficult to cover, it will reduce the convergence speed of verification coverage.

[0042] Based on this, the embodiments of the present application provide a chip verification method, which uses a coverage cross-fusion method to accelerate the convergence of chip verification coverage. Specifically, when verifying the first feature of multiple chips using the first coverage method, the first coverage rate is obtained to determine whether the first feature is verified according to the first coverage rate. When it is impossible to determine that the first feature of the chip cannot be verified based on the first coverage rate, the second coverage method is used to verify the first feature of the chip, and the second coverage rate is obtained, and then the verification result of the first feature is determined according to the second coverage rate.

[0043] To facilitate the understanding of the solution provided by the embodiments of the present application, the following will be described with reference to the accompanying drawings.

[0044] See Figure 2 , which is a flowchart of a chip verification method provided by an embodiment of the present application. As Figure 2 shown, the method may include:

[0045] S201: Verify the first feature of the chip using the first verification method to obtain the first coverage rate.

[0046] In this embodiment, the first verification method in the coverage verification method is used to verify the first feature of the chip to obtain the first coverage rate. Specifically, corresponding verification cases are generated according to the first verification method, and the chip is tested using the verification cases to obtain the first coverage rate.

[0047] S202: When it is impossible to determine whether the first feature of the chip is verified based on the first coverage rate, use the second verification method to verify the first feature of the chip to obtain the second coverage rate.

[0048] After obtaining the first coverage rate, it is determined whether the first feature of the chip is covered and verified according to the first coverage rate. If it is impossible to determine whether the first feature of the chip is covered and verified through the first coverage rate, the second verification method is used to verify the first feature of the chip to obtain the second coverage rate. Specifically, the database corresponding to the first verification method and the database corresponding to the second verification method are integrated to obtain verification cases, and the chip is verified using the verification cases to obtain the second coverage rate. Among them, the verification cases are used to verify the first feature of the chip. Among them, the database corresponding to the first verification method and the database corresponding to the second verification method may be the same database, that is, the first coverage rate database and the second coverage rate database collected are merged.

[0049] Among them, the first verification method can be one of functional coverage verification or assertion coverage verification, and the second verification method is the other of functional coverage verification or assertion coverage verification. That is, the first coverage rate is the functional coverage rate, the second coverage rate is the assertion coverage rate, the first feature is the functional feature of the chip, or the first coverage rate is the assertion coverage rate, the second coverage rate is the functional coverage rate, and the first feature is the value or state of the interface signal of the chip.

[0050] S203: Determine the verification result of the first feature according to the second coverage rate.

[0051] After obtaining the second coverage rate, determine the verification result of the first feature according to the second coverage rate. That is, when it is impossible to determine whether the first feature of the chip is verified through the first coverage rate, the second coverage rate is used to determine the verification result of the first feature. For example, in the case where the assertion coverage rate is integrated into the functional coverage rate, during simulation, when verifying functional points such as multiple writes and reads of registers and deadlocks of state machines, assertion verification is inserted, and the error location can be reported immediately when an abnormal situation occurs. In normal situations, passing the assertion can also determine the coverage of the corresponding functional points.

[0052] It can be seen that when verifying a chip, obtain the test cases corresponding to the first verification method to verify the first feature of the chip using the test cases, and obtain the first coverage rate. When it is impossible to determine whether the first feature of the chip is verified according to the first coverage rate, use the second verification method to verify the first feature of the chip. Use the second coverage rate to determine the verification result of the first feature. That is, in the embodiment of the present application, by fusing the first coverage rate and the second coverage rate, when the first coverage rate cannot determine whether the first feature is verified, the second coverage rate can be used for verification, thereby accelerating the verification convergence speed and reducing the verification time.

[0053] Based on the above method embodiments, an embodiment of the present application provides a chip verification device, which will be described below with reference to the accompanying drawings.

[0054] See Figure 3 , this figure is a structural diagram of a chip verification device provided by an embodiment of the present application. As Figure 3 shown, the device 300 may include: a first acquisition unit 301, a second acquisition unit 302, and a determination unit 303.

[0055] Among them, the first acquisition unit 301 is used to verify the first feature of the chip using the first verification method and obtain the first coverage rate. Among them, for the specific implementation of the first acquisition unit 301, reference can be made to the relevant description of S201, and details are not described herein again in this embodiment.

[0056] A second acquisition unit 302, configured to, when it is impossible to determine whether the first feature of the chip is verified according to the first coverage rate, verify the first feature of the chip by using a second verification method, and obtain the first coverage rate. For the specific implementation of the second acquisition unit 302, reference may be made to the related description of S202, which will not be elaborated herein in this embodiment.

[0057] A determination unit 303, configured to determine a verification result of the first feature according to the second coverage rate. For the specific implementation of the determination unit 303, reference may be made to the related description of S203, which will not be elaborated herein in this embodiment.

[0058] In a specific implementation manner, the first coverage rate is a functional coverage rate, the second coverage rate is an assertion coverage rate, and the first feature is a functional feature of the chip.

[0059] In a specific implementation manner, the first coverage rate is an assertion coverage rate, the second coverage rate is a functional coverage rate, and the first feature is a value or state of an interface signal of the chip.

[0060] In a specific implementation manner, the database of the first coverage rate and the database of the second coverage rate are the same database.

[0061] In a specific implementation manner, the second acquisition unit 302 is specifically configured to integrate the database corresponding to the first verification method and the database corresponding to the second verification method to obtain verification cases; verify the chip by using the verification cases to obtain the second coverage rate.

[0062] It should be noted that for the implementation of each unit in this embodiment, reference may be made to the related description in the above method embodiment, which will not be elaborated herein in this embodiment.

[0063] In addition, an embodiment of the present application provides a chip verification system, which will be described below with reference to the accompanying drawings.

[0064] See Figure 4 , this figure is a chip verification system provided by an embodiment of the present application. As Figure 4 shown, the system 400 may include: a first coverage rate collector 401, a second coverage rate collector 402, and a coverage rate integrator 403.

[0065] Among them, the first coverage rate collector 401 is configured to collect the first coverage rate. That is, when verifying the chip by using the first verification method, the first coverage rate is collected.

[0066] The second coverage rate collector 402 is configured to collect the second coverage rate. That is, when verifying the chip by using the second verification method, the second coverage rate is collected.

[0067] The coverage combiner 403 is configured to combine the first coverage rate collected by the first coverage collector 401 and the first coverage rate collected by the second coverage collector 402.

[0068] In a specific implementation, the system further includes: a use case generator 404;

[0069] The use case generator 404 is configured to generate verification use cases according to the combination result of the coverage combiner 403.

[0070] In addition, an embodiment of the present application further provides an electronic device, which includes: a processor and a memory;

[0071] The memory is configured to store computer-readable instructions or a computer program;

[0072] The processor is configured to read the computer-readable instructions or the computer program to enable the device to implement the chip verification method described above.

[0073] An embodiment of the present application provides a computer-readable storage medium, including instructions or a computer program, which when running on a computer, enables the computer to execute the chip verification method described above.

[0074] An embodiment of the present application provides a computer program product, which when running on a processor, implements the chip verification method described above.

[0075] It should be noted that the embodiments in this specification are described in a progressive manner, and the key points of each embodiment are the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the systems or devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the description of the method part.

[0076] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally means that the associated objects before and after are in an "or" relationship. "At least one (item) of the following" or its similar expressions refer to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0077] It should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0078] The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0079] The above description of the disclosed embodiments enables those skilled in the art to implement or use this application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip verification method, characterized in that, The method includes: Verifying the first feature of the chip using a first verification method to obtain a first coverage rate; When it is impossible to determine whether the first feature of the chip is verified based on the first coverage rate, verifying the first feature of the chip using a second verification method to obtain a second coverage rate; the database of the first coverage rate and the database of the second coverage rate are the same database; Determining the verification result of the first feature according to the second coverage rate; Wherein, when it is impossible to determine whether the first feature of the chip is verified based on the first coverage rate, verifying the first feature of the chip using a second verification method to obtain a second coverage rate, includes: Integrating the database corresponding to the first verification method and the database corresponding to the second verification method to obtain verification cases; Verifying the chip using the verification cases to obtain a second coverage rate.

2. The method according to claim 1, wherein The first coverage rate is a functional coverage rate, the second coverage rate is an assertion coverage rate, and the first feature is the functional feature of the chip.

3. The method according to claim 1, wherein The first coverage rate is an assertion coverage rate, the second coverage rate is a functional coverage rate, and the first feature is the value or state of the interface signal of the chip.

4. A chip verification device, characterized in that, The device includes: A first acquisition unit, configured to verify the first feature of the chip using a first verification method to obtain a first coverage rate; A second acquisition unit, configured to, when it is impossible to determine whether the first feature of the chip is verified based on the first coverage rate, verify the first feature of the chip using a second verification method to obtain a second coverage rate, including integrating the database corresponding to the first verification method and the database corresponding to the second verification method to obtain verification cases; verifying the chip using the verification cases to obtain a second coverage rate; the database of the first coverage rate and the database of the second coverage rate are the same database; A determination unit, configured to determine the verification result of the first feature according to the second coverage rate.

5. An electronic device, characterized in that, Includes: a processor, a memory; The memory is configured to store computer-readable instructions or a computer program; The processor is configured to read the computer-readable instructions or the computer program so that the device implements the chip verification method according to any one of claims 1-3.

6. A computer-readable storage medium, including instructions or a computer program, when running on a computer, causes the computer to execute the chip verification method according to any one of the above claims 1-3.

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