Neuron core control method and device, processing chip

Abstract

The embodiment of the present invention provides a neuron core control method and device, and a processing chip, which relate to the field of control technology. The neuron core control method includes: mapping multiple layers of a pulse neural network to the neuron core of a processing chip respectively; for each neuron core, setting the local delay parameter of the neuron core based on the number of layers of the pulse neural network to which the neuron core is mapped; the local delay parameter of each neuron core increases in sequence based on the number of layers of the mapped pulse neural network; for each neuron core, the neuron core controls the start of processing of the received input pulse signal according to the acquired control signal, the global synchronization signal and the local delay parameter of the neuron core. In the present invention, when controlling the start-up sequence of the neuron cores in the processing chip, the start-up sequence of the neuron cores mapping different layers of the pulse neural network is controlled by setting the local delay parameter for each neuron core, and the regularity and scalability are good.

Description

Technical Field

[0001] The present invention relates to the field of control technology, and in particular to a neuron core control method and device, and a processing chip. Background Art

[0002] Research on deep neural networks (DNNs) has made rapid progress in recent years and has been initially applied. However, deep neural network algorithms usually consume a lot of computing power, which also leads to greater power consumption. For example, the classic deep convolutional network (CNN) model AlexNet requires at least 720 million multiplication operations, and generally consumes about 10 watts to 100 watts of power.

[0003] In order to improve classification accuracy, the structure of deep neural networks has become more and more complex. Currently, there are deep neural networks with more than 1,000 layers. Even at the edge, deep neural networks generally require about 50 layers. Due to the limitations of chip computing power and storage resources, when hardware acceleration of complex deep neural networks is performed, due to the limitations of chip computing resources and storage resources, it is rare to map the entire deep neural network to the chip at one time. At present, a streamlined operation method is generally used. For example, the first layer is mapped to the chip, the chip performs operations, and the weights of the second layer are prepared at the same time. After the chip finishes calculating the first layer, it performs the second layer operation. And so on, until all layers are calculated.

[0004] In recent years, the spiking neural network (SNN) has attracted the attention of academia and industry for its low power consumption and characteristics that are closer to the human brain. In a spiking neural network, the axon is the unit that receives pulses, and the neuron is the unit that sends pulses. A neuron is connected to multiple axons through dendrites, and the connection point between the dendrite and the axon is called a synapse. After the axon receives a pulse, all dendrites that have synaptic connections with this axon will receive the pulse, which in turn affects the neurons downstream of the dendrite. The neuron adds the pulses from multiple axons and accumulates them with the previous membrane voltage. If the value exceeds the threshold, it sends a pulse downstream. The pulse propagates in the spiking neural network with a 1-bit pulse. The activation frequency of the pulse is relatively low, and only addition and subtraction operations are required, without multiplication operations. The computing power consumption and power consumption are lower than those of the deep neural network. Therefore, the deep neural network can be converted into a spiking neural network by spiking, so as to fully utilize the low power consumption advantage of the spiking neural network.

[0005] After mapping the various layers of the pulse neural network in the neuron core of the chip, the startup order of each neuron core needs to be controlled. Figure 1This is a schematic diagram of the startup of a neuron core in an existing control chip. The chip includes a synchronous controller 100 and a 3×3 array of neuron cores 200. The synchronous controller 100 sets a corresponding startup signal for each neuron core and sends each startup signal to the corresponding neuron core. Each neuron core performs an operation when it detects that the received startup signal is at a high level, thereby realizing the control of the startup sequence of each neuron core 200.

[0006] However, in the existing neuron core startup control process, when the synchronization controller 100 controls the startup sequence of each neuron core 200, it is necessary to set each neuron core 200 to have a startup signal connected to the synchronization controller 100. This startup signal has no regularity in the physical implementation of the chip, which destroys the regularity of the neuron core array; when the array is large, the wiring around the synchronization controller 100 is easily blocked, resulting in signal transmission failure. In addition, it is not suitable for the use scenario where the neural network obtained by deep neural network pulsing needs to be mapped to multiple chips. Summary of the invention

[0007] The purpose of the present invention is to provide a neuron core control method and device, and a processing chip. When controlling the startup sequence of neuron cores in the processing chip, the startup sequence of neuron cores mapping different layers of the pulse neural network is controlled by setting local delay parameters for each neuron core. The method has good regularity and scalability, and at the same time avoids signal failure problems that occur when multiple neuron cores are controlled separately by a controller alone. The method is suitable for scenarios where pulse neural networks are mapped to multiple chips.

[0008] To achieve the above-mentioned purpose, the present invention provides a neuron core control method, comprising: mapping multiple layers of a pulse neural network to the neuron cores of a processing chip respectively; for each neuron core, setting the local delay parameter of the neuron core based on the number of layers of the pulse neural network to which the neuron core is mapped; the local delay parameters of each neuron core increase in sequence based on the number of layers of the mapped pulse neural network; for each neuron core, the neuron core controls the start of processing of the received input pulse signal according to the acquired control signal, the global synchronization signal and the local delay parameter of the neuron core.

[0009] The present invention also provides a processing chip, which includes a controller and multiple neuron cores; the controller is respectively connected to each neuron core; the controller is used to map multiple layers of the pulse neural network to each neuron core respectively; the controller is also used to set the local delay parameter of the neuron core for each neuron core based on the number of layers of the pulse neural network to which the neuron core is mapped; the local delay parameter of each neuron core increases in sequence based on the number of layers of the mapped pulse neural network; the neuron core is used to control the start of processing of the received input pulse signal according to the acquired control signal, the global synchronization signal and the local delay parameter of the neuron core.

[0010] The present invention also provides a neuron core control device, including: the above-mentioned processing chip.

[0011] In an embodiment of the present invention, after the neuron cores in the processing chip are mapped with a pulse neural network, the local delay parameters of each neuron core are set based on the number of layers of the pulse neural network to which each neuron core is mapped, and then each neuron core obtains a control signal and a global synchronization signal, and then each neuron core can control the start-up of the input pulse signal based on the control signal, the global synchronization signal and its own local delay parameters; thereby, when controlling the start-up sequence of the neuron cores in the processing chip, the start-up sequence of the neuron cores mapping different layers of the pulse neural network is controlled by setting local delay parameters for each neuron core, which has good regularity and scalability, and at the same time avoids signal failure problems that occur when multiple neuron cores are controlled separately by simply using a controller; and it is suitable for scenarios where the pulse neural network is mapped to multiple chips.

[0012] In one embodiment, the global synchronization signal is a periodic signal, and the control signal includes a high level that lasts for a preset number of cycles; for each neuron core, the neuron core controls the start of processing of the received input pulse signal based on the acquired control signal, the global synchronization signal and the local delay parameter of the neuron core, including: for each neuron core, when the neuron core detects that the control signal is a high level at the current edge of the global synchronization signal and detects that the control signal is a low level at the previous edge of the global synchronization signal, the processing of the received input pulse signal is started after a target number of cycles of the global synchronization signal, and the target number is the local delay parameter of the neuron core.

[0013] In one embodiment, the global synchronization signal is a periodic signal, and the control signal includes a high level that lasts for a preset number of cycles; for each neuron core, the neuron core controls the start of processing of the received input pulse signal based on the acquired control signal, the global synchronization signal, and the local delay parameter of the neuron core, including: for each neuron core, when the neuron core detects that the control signal is a high level, the neuron core performs edge detection on the global synchronization signal, and starts processing the received input pulse signal when the number of edges of the detected global synchronization signal is equal to the local delay parameter of the neuron core.

[0014] In one embodiment, edge detection is performed on a global synchronization signal, and when the number of edges of the detected global synchronization signal is equal to a local delay parameter of the neuron core, control is performed to start processing of a received input pulse signal, including: detecting a rising edge of the global synchronization signal, and when the number of rising edges of the detected global synchronization signal is equal to a local delay parameter of the neuron core, control is performed to start processing of the received input pulse signal.

[0015] In one embodiment, the difference between the local delay parameter of the first neuron core and the local delay parameter of the second neuron core is 1, the first neuron core is a neuron core mapping the Mth layer of the pulse neural network, the second neuron core is a neuron core mapping the M+1th layer of the pulse neural network, and M is an integer greater than or equal to 1.

[0016] In one embodiment, each neuron core includes: a first register; a controller is used to set the local delay parameters of the neuron core for each neuron core based on the number of layers of the pulse neural network to which the neuron core is mapped, and store the local delay parameters of the neuron core in the first register of the neuron core.

[0017] In one embodiment, each neuron core further includes: a second register; and the controller is used to store the control signal in the second register of each neuron core. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of a processing chip for neuron core synchronization in the prior art;

[0019] Figure 2 is a specific flow chart of the neuron core control method according to the first embodiment of the present invention;

[0020] Figures 3 to 5 is a schematic diagram of a processing chip according to a first embodiment of the present invention;

[0021] Figure 6 is a specific flow chart of the neuron core control method according to the second embodiment of the present invention;

[0022] Figure 7 is a timing diagram of neuron core control according to the second embodiment of the present invention;

[0023] Figure 8 is a specific flow chart of the neuron core control method according to the third embodiment of the present invention;

[0024] Fig. 9 is a timing diagram of neuron core control according to the third embodiment of the present invention;

[0025] Fig.10 is a schematic diagram of a processing chip according to a fourth embodiment of the present invention;

[0026] Fig.11 is a schematic diagram of a neuron core in a processing chip according to a fourth embodiment of the present invention;

[0027] Fig.12 is a schematic diagram of a neuron core in a processing chip according to a fifth embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following will be described in detail with reference to the accompanying drawings to provide a clearer understanding of the purpose, features and advantages of the present invention. It should be understood that the embodiments shown in the accompanying drawings are not intended to limit the scope of the present invention, but are only intended to illustrate the essential spirit of the technical solution of the present invention.

[0029] In the following description, certain specific details are set forth for the purpose of illustrating various disclosed embodiments to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the relevant art will recognize that the embodiments may be practiced without one or more of these specific details. In other cases, well-known devices, structures, and techniques associated with the present application may not be shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0030] Unless the context requires otherwise, throughout the specification and claims, the word "comprise" and variations such as "include" and "have" should be construed in an open, inclusive sense, ie, should be interpreted as "including, but not limited to."

[0031] References throughout the specification to "one embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any manner in one or more embodiments.

[0032] As used in this specification and the appended claims, the singular forms "a", "an", and "" include plural referents unless the context clearly dictates otherwise. It should be noted that the term "or" is generally employed in its sense including "or / and" unless the context clearly dictates otherwise.

[0033] In the following description, in order to clearly show the structure and working mode of the present invention, many directional words will be used for description, but the words "front", "back", "left", "right", "outside", "inside", "outward", "inward", "up", "down", etc. should be understood as convenient terms and should not be understood as restrictive terms.

[0034] The first embodiment of the present invention relates to a neuron core control method, which is applied to a processing chip. After the multiple neuron cores in the processing chip are respectively mapped to the layers of the pulse neural network, the processing chip can use the neuron core control method to control the startup order of each neuron core, and each neuron core starts processing the input pulse signal. If a single processing chip cannot map all layers of the pulse neural network, all layers of the pulse neural network can be mapped by multiple processing chips. Among them, the pulse neural network can also be obtained by pulsing a deep neural network.

[0035] The specific process of the neuron core control method of this embodiment is as follows Figure 2 shown.

[0036] Step 101, mapping multiple layers of the pulse neural network to the neuron cores of the processing chip respectively.

[0037] Specifically, the processing chip includes multiple neuron cores, the spiking neural network includes Y layers, Y is an integer greater than 1, and the Y layers of the spiking neural network can be represented as: layer(1), layer(2), ..., layer(Y), and layer(M) represents the Mth layer of the Y layers of the spiking neural network, 1<M≤Y; according to the layer order of the spiking neural network, the multiple layers of the spiking network are sequentially mapped to the neuron cores of the processing chip. For example, please refer to Figure 3 The processing chip includes 9 neuron cores, namely neuron core 1 to neuron core 9, and the 9 neuron cores form a 3x3 neuron core array; the pulse neural network includes three layers, namely the first layer layer(1), the second layer layer(2) and the third layer layer(3). Mapping one layer of the pulse neural network requires three neuron cores. The first layer layer(1) of the pulse neural network can be mapped to neuron core 1 to neuron core 3, the second layer layer(2) of the pulse neural network can be mapped to neuron core 4 to neuron core 6, and the third layer layer(3) of the pulse neural network can be mapped to neuron core 7 to neuron core 9.

[0038] Step 102, for each neuron core, a local delay parameter of the neuron core is set based on the number of layers of the spiking neural network to which the neuron core is mapped; the local delay parameter of each neuron core increases sequentially based on the number of layers of the spiking neural network to which the neuron core is mapped.

[0039] Specifically, for each neuron core mapped to the pulse neural network, it is necessary to set the local delay parameters of each neuron core; taking any neuron core as an example, after the neuron core is mapped to a layer of the pulse neural network, the local delay parameters of the neuron core are set based on the number of layers of the neural network to which it is mapped, and the local delay parameters of the neuron cores mapped to the same layer are equal; the local delay parameters of each neuron core increase in sequence based on the number of layers of the mapped pulse neural network.

[0040] by Figure 3 Taking the processing chip in as an example, after each neuron core is mapped to the pulse neural network, the local delay parameters of each neuron core are set, and the local delay parameters of the neuron cores mapped to the same layer are equal. The local delay parameters of each neuron core are positively correlated with the number of layers of the neural network to which they are mapped, that is, the local delay parameters of neuron core 1, neuron core 2 and neuron core 3 mapped to the first layer layer (1) of the pulse neural network are equal, denoted as A1; the local delay parameters of neuron core 4, neuron core 5 and neuron core 6 mapped to the second layer layer (2) of the pulse neural network are equal, denoted as A2; the local delay parameters of neuron core 7, neuron core 8 and neuron core 9 mapped to the third layer layer (3) of the pulse neural network are equal, denoted as A3; and A1<A2<A3. Among them, the difference between A1, A2 and A3 can be set to be equal or unequal.

[0041] Step 103: For each neuron core, the neuron core controls and starts processing the received input pulse signal according to the acquired control signal, the global synchronization signal and the local delay parameter of the neuron core.

[0042] Specifically, the processing chip can achieve pipeline synchronization between neuron cores through control signals and local delay parameters. Taking any neuron core mapped with a pulse neural network as an example, the neuron core can obtain control signals and global synchronization signals. The global synchronization signal is used to set the periodic signal of the neuron core in the processing chip, which is obtained by clock division; the neuron core uses the global synchronization signal as the working frequency, determines its own startup cycle through the control signal and the corresponding local delay parameter, and can process the received input pulse signal after startup. Among them, each neuron core can obtain a control signal, which can come from the controller inside the processing chip, or from the register inside each neuron core, or from the control module outside the chip; each neuron core will also obtain a global synchronization signal, which can also come from the controller or control module inside the processing chip, or from an external control module connected to the processing chip.

[0043] For an example, see Figure 4 , the processing chip includes 9 neuron cores, namely neuron core 2 to neuron core 9, and the 9 neuron cores form a 3x3 neuron core array. For neuron cores 1 to 3, the control signal en and the global synchronization signal ref_sync they obtain are from the controller 20 inside the processing chip, neuron core 4 obtains the control signal en and the global synchronization signal ref_sync from neuron core 1, neuron core 7 obtains the control signal en and the global synchronization signal ref_sync from neuron core 4, and the way in which neuron cores 5, 6, 8, and 9 obtain the control signal en and the global synchronization signal ref_sync is similar to that of neuron cores 4 and 7, which will not be repeated here; therefore, there is no need for the controller to distribute the control signal en and the global synchronization signal ref_sync to each neuron core, which reduces the input signal of the neuron core and reduces the signal connection between the controller and the neuron core. Among them, when the control signal en is transmitted between two adjacent neuron cores, there can be a small delay, which is much smaller than one cycle of the global synchronization signal ref_sync.

[0044] It should be noted that when a single processing chip cannot map all layers of the spiking neural network, and multiple processing chips jointly map all layers of the spiking neural network, each processing chip can still use the neuron core control method in this embodiment to complete the data processing process. There is no need to set up a control signal transmission connection between adjacent processing chips, but a pulse signal connection needs to be set up. Each processing chip uses the number of layers of the mapped spiking neural network to set the startup order of each neuron core. For example, please refer to Figure 5, both the processing chip A and the processing chip B include 9 neuron cores, namely neuron core 1 to neuron core 9, and the 9 neuron cores form a 3x3 neuron core array; the spiking neural network includes five layers, namely the first layer layer(1), the second layer layer(2) and the third layer layer(3), and three neuron cores are required to map one layer of the spiking neural network. Therefore, the first layer layer(1) of the spiking neural network can be mapped to neuron cores 1 to 3 of the processing chip A, the second layer layer(2) of the spiking neural network can be mapped to neuron cores 4 to 6 of the processing chip A, the third layer layer(3) of the spiking neural network can be mapped to neuron cores 7 to 9 of the processing chip A, the fourth layer layer(4) of the spiking neural network can be mapped to neuron cores 1 to 3 of the processing chip B, and the fifth layer layer(5) of the spiking neural network can be mapped to neuron cores 4 to 6 of the processing chip A. The processing chip A and the processing chip B set the local delay parameters of each neuron core based on the number of layers of the spiking neural network to which each neuron core is mapped, and the local delay parameters of the neuron cores mapped to the same layer are equal. In processing chip A, the local delay parameters of neuron core 1, neuron core 2 and neuron core 3 are equal, denoted as A11; the local delay parameters of neuron core 4, neuron core 5 and neuron core 6 are equal, denoted as A12; the local delay parameters of neuron core 7, neuron core 8 and neuron core 9 are equal, denoted as A13; in processing chip B, the local delay parameters of neuron core 1, neuron core 2 and neuron core 3 are equal, denoted as A14; the local delay parameters of neuron core 4, neuron core 5 and neuron core 6 are equal, denoted as A15; and A11<A12<A13<A14<A15. The neuron cores in processing chip A and processing chip B can receive the same control signal and global synchronization signal, so that the neuron cores in processing chip A and processing chip B start working in the order of the layers of the mapped pulse neural network.

[0045] In this embodiment, the input pulse signal of each neuron core can be a pulse signal of multiple pulse cycles obtained by encoding the audio and video signal, or an output pulse signal of a neuron core in the same processing chip or another processing chip. Specifically, for each neuron core of the first layer layer (1) mapped with the pulse network, its input pulse signal is a pulse signal of multiple pulse cycles obtained by encoding the audio and video signal; for each neuron core of the Mth layer layer (M) mapped with the pulse neural network, its input pulse signal is the output pulse signal of the M-1th layer layer (M-1) of the pulse neural network in each pulse cycle. In addition, in the i-th pulse cycle per(i), for the M-th layer layer(M) of the pulse neural network, the membrane voltage of the M-th layer layer(M) is calculated as follows: the product of the current input pulse signal and the weight of the M-th layer layer(M) is calculated, and then the sum of the product and the membrane voltage of the M-th layer layer(M) in the i-1-th pulse cycle per(i-1) is calculated. The sum is the membrane voltage of the M-th layer layer(M) in the i-th pulse cycle per(i). Then, the membrane voltage of the M-th layer layer(M) in the i-th pulse cycle per(i) is compared with a preset membrane voltage threshold. When the membrane voltage of the M-th layer layer(M) in the i-th pulse cycle per(i) is greater than or equal to the membrane voltage threshold, the output pulse signal of the M-th layer layer(M) in the i-th pulse cycle per(i) is 1; when the membrane voltage of the M-th layer layer(M) in the i-th pulse cycle per(i) is less than the membrane voltage threshold, the output pulse signal of the M-th layer layer(M) in the i-th pulse cycle per(i) is 0. Here, i is an integer greater than 1.

[0046] The present embodiment provides a neuron core control method. After the neuron cores in the processing chip are mapped with a pulse neural network, the local delay parameters of each neuron core are set based on the number of layers of the pulse neural network to which each neuron core is mapped. Subsequently, each neuron core obtains a control signal and a global synchronization signal. Then, each neuron core can control the start-up of the input pulse signal based on the control signal, the global synchronization signal and its own local delay parameters. Therefore, when controlling the start-up sequence of the neuron cores in the processing chip, the start-up sequence of the neuron cores mapped to different layers of the pulse neural network is controlled by setting local delay parameters for each neuron core, which has good regularity and scalability, and avoids signal failure problems that occur when multiple neuron cores are controlled separately by simply using a controller. The method is suitable for scenarios where the pulse neural network is mapped to multiple chips.

[0047] The second embodiment of the present invention relates to a neuron core control method. Compared with the first embodiment, this embodiment provides a specific implementation method for each neuron core, in which the neuron core controls and starts processing the received input pulse signal according to the acquired control signal, the global synchronization signal and the local delay parameter of the neuron core. The global synchronization signal is a periodic signal used to set the operation of the neuron core in the processing chip, and the control signal includes a high level that lasts for a preset number of cycles.

[0048] The specific process of the neuron core control method of this embodiment is as follows: Figure 6 shown.

[0049] Step 201, mapping multiple layers of the spiking neural network to the neuron cores of the processing chip respectively, is substantially the same as step 101 of the first embodiment and will not be described in detail here.

[0050] Step 202, for each neuron core, a local delay parameter of the neuron core is set based on the number of layers of the spiking neural network to which the neuron core is mapped; the local delay parameter of each neuron core increases sequentially based on the number of layers of the spiking neural network to which the neuron core is mapped.

[0051] In one example, the difference between the local delay parameter of the first neuron core and the local delay parameter of the second neuron core is set to 1, the first neuron core is the neuron core mapping the Mth layer of the spiking neural network, the second neuron core is the neuron core mapping the M+1th layer of the spiking neural network, and M is an integer greater than or equal to 1; that is, the difference between the local delay parameters of the neuron cores mapping two adjacent layers of the spiking neural network is 1. Figure 3 Taking the processing chip as an example, the first layer layer (1) of the pulse neural network is mapped to neuron cores 1 to 3, the second layer layer (2) of the pulse neural network is mapped to neuron cores 4 to 6, and the third layer layer (3) of the pulse neural network is mapped to neuron cores 7 to 9. The local delay parameters of neuron cores 1, 2 and 3 are equal, denoted as i; the local delay parameters of neuron cores 4, 5 and 6 are equal, denoted as i+1; the local delay parameters of neuron cores 7, 8 and 9 are equal, denoted as i+2. Among them, i can be any integer greater than or equal to 0. Exemplarily, i=1, that is, the local delay parameter of the neuron core that maps the first layer of the pulse neural network is set to 1.

[0052] Step 203, for each neuron core, when the neuron core detects that the control signal is at a high level at the current edge of the global synchronization signal and detects that the control signal is at a low level at the previous edge of the global synchronization signal, it starts processing the received input pulse signal after a target number of cycles of the global synchronization signal, and the target number is the local delay parameter of the neuron core.

[0053] Specifically, taking any neuron core mapped to the first layer layer(1) of the pulse neural network as an example, i represents the local delay parameter of the neuron core mapped to the first layer layer(1) of the pulse neural network. The neuron core can obtain the control signal and the global synchronization signal, and detect the control signal while performing edge detection on the global synchronization signal. If the control signal is detected to be at a high level at the current edge of the global synchronization signal and the control signal is detected to be at a low level at the previous edge of the global synchronization signal, the timing starts. When the timing reaches the cycle of i global synchronization signals, the neuron core starts processing the received input pulse signal.

[0054] Please refer to Figure 7 The processing chip maps three layers of the pulse neural network, namely the first layer layer(1), the second layer layer(2) and the third layer layer(3). core1 represents the neuron core mapped to the first layer layer(1) of the pulse neural network, core2 represents the neuron core mapped to the second layer layer(2) of the pulse neural network, and core3 represents the neuron core mapped to the third layer layer(3) of the pulse neural network. The local delay parameter latency_cout of core1 is 0, the local delay parameter latency_cout of core2 is 1, and the local delay parameter latency_cout of core3 is 2. The control signal en has a high level that lasts for 5 cycles. Among them, all the neuron cores in the processing chip can complete the configuration of local delay parameters within the same cycle of the global synchronization signal ref_sync, and then core1 to core3 respectively execute step 203. At the first rising edge and the second rising edge of the global synchronization signal ref_sync, en is both low level, and at the third rising edge of the global synchronization signal ref_sync, en is high level. At this time, core1 immediately starts to process the received input pulse signal; core2 starts timing, and when the timing reaches 1 cycle of the global synchronization signal ref_sync, core2 immediately starts to process the received input pulse signal; core3 also starts timing, and when the timing reaches 2 cycles of the global synchronization signal ref_sync, core3 immediately starts to process the received input pulse signal.

[0055] It should be noted that the present embodiment and subsequent embodiments only schematically provide the preset number of cycles for which the control signal continues at a high level, and do not impose any limitation on the size of the preset number of cycles for which the control signal continues at a high level. The setting method for the preset number of cycles for which the control signal continues at a high level can be any of the following: Method 1, setting the preset number of cycles for which the control signal continues at a high level equal to the number of pulse cycles of the pulse signal obtained by encoding the audio and video signal, the control signal changes from a high level to a low level after continuing for the preset number of cycles, each neuron core detects that the control signal is at a low level at the current edge of the global synchronization signal, and when the control signal is at a high level at the previous edge of the global synchronization signal, each neuron core stops processing the received input pulse signal after a target number of cycles of the global synchronization signal, and the target number is the local delay parameter of the neuron core; wherein, if it is necessary to continuously process the audio and video signal of frame A, the pulse period of the pulse signal obtained after encoding each frame of the audio and video signal is B, then the preset number of cycles for which the signal continues at a high level can be set to A*B. Method 2: Set the preset number of cycles of the control signal maintaining a high level to any value greater than 0, set a register in the processing chip or set a register in each neuron core, and configure the operation duration in the register. Each neuron core can read the operation duration in the register, so that it can control the stop of processing the received input pulse signal after the operation duration ends.

[0056] The third embodiment of the present invention relates to a neuron core control method. Compared with the first embodiment, this embodiment provides another specific implementation method for each neuron core, in which the neuron core controls and starts processing the received input pulse signal according to the acquired control signal, the global synchronization signal and the local delay parameter of the neuron core. The global synchronization signal is a periodic signal used to set the operation of the neuron core in the processing chip, and the control signal includes a high level that lasts for a preset number of cycles.

[0057] The specific process of the neuron core control method of this embodiment is as follows: Figure 8 shown.

[0058] Step 301, mapping multiple layers of the spiking neural network to the neuron cores of the processing chip respectively, which is substantially the same as step 101 of the first embodiment and will not be described in detail here.

[0059] Step 302, for each neuron core, a local delay parameter of the neuron core is set based on the number of layers of the spiking neural network to which the neuron core is mapped; the local delay parameter of each neuron core increases sequentially based on the number of layers of the spiking neural network to which the neuron core is mapped.

[0060] In one example, the difference between the local delay parameter of the first neuron core and the local delay parameter of the second neuron core is set to 1, the first neuron core is the neuron core mapping the Mth layer of the spiking neural network, the second neuron core is the neuron core mapping the M+1th layer of the spiking neural network, and M is an integer greater than or equal to 1; that is, the difference between the local delay parameters of the neuron cores mapping two adjacent layers of the spiking neural network is 1. Figure 3 Taking the processing chip as an example, the first layer layer (1) of the pulse neural network is mapped to neuron cores 1 to 3, the second layer layer (2) of the pulse neural network is mapped to neuron cores 4 to 6, and the third layer layer (3) of the pulse neural network is mapped to neuron cores 7 to 9. The local delay parameters of neuron cores 1, 2 and 3 are equal, denoted as i; the local delay parameters of neuron cores 4, 5 and 6 are equal, denoted as i+1; the local delay parameters of neuron cores 7, 8 and 9 are equal, denoted as i+2. Among them, i can be any integer greater than or equal to 0. Exemplarily, i=1, that is, the local delay parameter of the neuron core that maps the first layer of the pulse neural network is set to 1.

[0061] Step 303, for each neuron core, when the neuron core detects that the control signal is at a high level, the neuron core performs edge detection on the global synchronization signal, and when the number of edges of the detected global synchronization signal is equal to the local delay parameter of the neuron core, starts processing the received input pulse signal.

[0062] Specifically, for each neuron core, when the neuron core detects that the control signal is at a high level, it detects the rising edge of the global synchronization signal, and when the number of rising edges of the detected global synchronization signal is equal to the local delay parameter of the neuron core, it starts processing the received input pulse signal.

[0063] Taking any neuron core mapped with the first layer layer (1) of the pulse neural network as an example, i represents the local delay parameter of the neuron core mapped with the first layer layer (1) of the pulse neural network. After the neuron core obtains the control signal and the global synchronization signal, it continuously detects the high level of the control signal. If the control signal is detected to be at a high level, it starts to detect the rising edge of the global synchronization signal and counts the number of rising edges of the detected global synchronization signal. When the number of rising edges of the detected global synchronization signal is equal to i, the neuron core starts processing the received input pulse signal. Wherein, i is an integer greater than or equal to 1.

[0064] Please refer to Fig. 9The processing chip maps three layers of the pulse neural network, namely the first layer layer(1), the second layer layer(2) and the third layer layer(3). core1 represents the neuron core mapped to the first layer layer(1) of the pulse neural network, core2 represents the neuron core mapped to the second layer layer(2) of the pulse neural network, and core3 represents the neuron core mapped to the third layer layer(3) of the pulse neural network. The local delay parameter latency_cout of core1 is 1, the local delay parameter latency_cout of core2 is 2, and the local delay parameter latency_cout of core3 is 3. The control signal en has a high level that lasts for 5 cycles. Among them, all the neuron cores in the processing chip can complete the configuration of local delay parameters within the same cycle of the global synchronization signal ref_sync, and then core1 to core3 respectively execute step 303, perform a high-level detection on the control signal en, and when it is detected that en is at a high level, the rising edge of the global synchronization signal ref_sync is detected. When core1 detects the first rising edge of the global synchronization signal ref_sync, it immediately starts to process the received input pulse signal; when core2 detects the second rising edge of the global synchronization signal ref_sync, it immediately starts to process the received input pulse signal; when core3 detects the third rising edge of the global synchronization signal ref_sync, it immediately starts to process the received input pulse signal.

[0065] It should be noted that, in this embodiment, the setting method of the preset number of cycles of the control signal being continuously at a high level can refer to the relevant content in the second embodiment, and will not be repeated here.

[0066] The fourth embodiment of the present invention relates to a processing chip, which is used in the neuron core control method in any one of the first to third embodiments, that is, after the multiple neuron cores in the processing chip are respectively mapped to the layers of the pulse neural network, the processing chip can use the neuron core control method to control the startup sequence of each neuron core, and each neuron core starts processing the input pulse signal. If a single processing chip cannot map all layers of the pulse neural network, all layers of the pulse neural network can be mapped by multiple processing chips. Among them, the pulse neural network can also be obtained by pulsing the deep neural network.

[0067] Please refer to Fig.10 The processing chip 10 includes a controller 101 and a plurality of neuron cores 102 (nine are taken as an example in the figure), and the controller 101 is connected to each neuron core 102 respectively.

[0068] The controller 101 is used to map the multiple layers of the pulse neural network to each neuron core 102 respectively.

[0069] The controller 101 is also used to set the local delay parameter of each neuron core 102 based on the number of layers of the pulse neural network to which the neuron core 102 is mapped; the local delay parameter of each neuron core 102 increases sequentially based on the number of layers of the mapped pulse neural network.

[0070] The neuron core 102 is used to control and start processing of the received input pulse signal according to the acquired control signal, the global synchronization signal and the local delay parameter of the neuron core 102 .

[0071] For example, please refer to Fig.11 Each neuron core 102 includes: an operation unit 1021, a first cache 1022, a second cache 1023, and a third cache 1024.

[0072] The operation unit 1021 is used to use the layer of the mapped pulse neural network to operate on the received input pulse signal.

[0073] The first cache 1022 is used to cache input pulse signals, the second cache 1023 is used to cache layer weights of the pulse neural network, and the third cache 1024 is used to cache the membrane voltage calculated by the operation unit 1021.

[0074] The fifth embodiment of the present invention relates to a processing chip. The main difference between this embodiment and the fourth embodiment is that: Fig.12 , each neuron core 102 also includes: a first register 1025 and a second register 1026.

[0075] The controller 101 is used to set the local delay parameters of each neuron core 102 based on the number of layers of the pulse neural network to which the neuron core 102 is mapped, and store the local delay parameters of the neuron core 102 in the first register 1025 of the neuron core. That is, each neuron core 102 is provided with a first register 1025 for storing the corresponding local delay parameters, and the local delay parameters of all neuron cores 102 in the processing chip 10 need to be configured within the same cycle of the global synchronization signal ref_sync.

[0076] The controller 101 is used to store the control signal in the second register 1026 of each neuron core 102. That is, each neuron core 102 is provided with a second register 1026 for storing the control signal, and the neuron core 102 can read the control signal from the second register 1026. The local delay parameters and control signals of all neuron cores 102 in the processing chip 10 need to be configured within the same cycle of the global synchronization signal ref_sync. Before the cycle of the global synchronization signal ref_sync, the second registers 1026 of the neuron cores 102 mapped with the pulse neural network are all configured to be 0, and during the cycle of the global synchronization signal ref_sync, the second registers 1026 of the neuron cores 102 mapped with the pulse neural network are all configured to be 1; each neuron core 102 reads the control signal in the second register 1026 as 1 (i.e., the control signal is at a high level) at the current edge of the global synchronization signal, and detects the control signal in the second register 1026 as 0 (i.e., the control signal is at a low level) at the previous edge of the global synchronization signal, and each neuron core 102 starts after the corresponding local delay parameter and the cycle of the global synchronization signal, and processes the input pulse signal.

[0077] The sixth embodiment of the present invention relates to a neuron core control device, such as an electronic device such as a laptop computer, a desktop host, a tablet computer, etc. The neuron core control device includes the processing chip in the third or fourth embodiment.

[0078] Preferred embodiments of the present invention have been described above in detail, but it should be understood that aspects of the embodiments can be modified, if necessary, to employ aspects, features and concepts of the various patents, applications and publications to provide further embodiments.

[0079] These and other changes can be made to the embodiments in light of the above detailed description.In general, in the claims, the terms used should not be considered limited to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which these claims are entitled.

Claims

1. A neuron nucleus control method, characterized in that: include: Mapping multiple layers of the spiking neural network to the neuron cores of the processing chip; For each of the neuron cores, a local delay parameter of the neuron core is set based on the number of layers of the spiking neural network to which the neuron core is mapped; the local delay parameters of each of the neuron cores are sequentially increased based on the number of layers of the spiking neural network to which the neuron core is mapped; For each of the neuron cores, the neuron core controls and starts processing the received input pulse signal according to the acquired control signal, the global synchronization signal and the local delay parameters of the neuron core, wherein the global synchronization signal is a periodic signal, and the control signal includes a high level that lasts for a preset number of cycles, and the local delay parameters of the neuron cores mapped to the same layer are equal.

2. The neuron nucleus control method according to claim 1, characterized in that: For each of the neuron cores, the neuron core controls and starts processing of the received input pulse signal according to the acquired control signal, the global synchronization signal and the local delay parameter of the neuron core, including: For each of the neuron cores, when the neuron core detects that the control signal is at a high level at the current edge of the global synchronization signal and detects that the control signal is at a low level at the previous edge of the global synchronization signal, the neuron core starts processing the received input pulse signal after a target number of cycles of the global synchronization signal, where the target number is a local delay parameter of the neuron core.

3. The neuron nucleus control method according to claim 1, characterized in that: For each of the neuron cores, the neuron core controls and starts processing of the received input pulse signal according to the acquired control signal, the global synchronization signal and the local delay parameter of the neuron core, including: For each of the neuron cores, when the neuron core detects that the control signal is at a high level, it performs edge detection on the global synchronization signal, and when the number of edges of the detected global synchronization signal is equal to the local delay parameter of the neuron core, it starts processing the received input pulse signal.

4. The neuron nucleus control method according to claim 3, characterized in that: Performing edge detection on the global synchronization signal, and when the number of edges of the detected global synchronization signal is equal to the local delay parameter of the neuron core, controlling to start processing of the received input pulse signal, including: The rising edge of the global synchronization signal is detected, and when the number of the detected rising edges of the global synchronization signal is equal to the local delay parameter of the neuron core, the processing of the received input pulse signal is started.

5. The neuron nucleus control method according to claim 1, characterized in that: The difference between the local delay parameter of the first neuron nucleus and the local delay parameter of the second neuron nucleus is 1, the first neuron nucleus is the neuron nucleus mapping the Mth layer of the pulse neural network, the second neuron nucleus is the neuron nucleus mapping the M+1th layer of the pulse neural network, and M is an integer greater than or equal to 1.

6. A processing chip, characterized in that: The processing chip includes a controller and a plurality of neuron cores; the controller is respectively connected to each of the neuron cores; The controller is used to map multiple layers of the spiking neural network to each of the neuron nuclei respectively; The controller is also used to set a local delay parameter of each neuron core based on the number of layers of the spiking neural network to which the neuron core is mapped; the local delay parameters of each neuron core are sequentially increased based on the number of layers of the spiking neural network to which the neuron core is mapped; The neuron core is used to control the start of processing of the received input pulse signal according to the acquired control signal, the global synchronization signal and the local delay parameter of the neuron core; wherein the global synchronization signal is a periodic signal, the control signal includes a high level that lasts for a preset number of cycles, and the local delay parameters of the neuron cores mapped to the same layer are equal.

7. The processing chip according to claim 6, characterized in that: Each of the neuron cores comprises: a first register; The controller is used to set the local delay parameter of each neuron core based on the number of layers of the pulse neural network to which the neuron core is mapped, and store the local delay parameter of the neuron core in the first register of the neuron core.

8. The processing chip according to claim 6, characterized in that: Each of the neuron cores also includes: a second register; The controller is used to store the control signal in the second register of each neuron core.

9. A neuron core control device, characterized in that: include: The processing chip according to any one of claims 6 to 8.

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