Combined VCSEL chip

Abstract

The present application relates to a combined VCSEL chip, which includes a first VCSEL chip and a second VCSEL chip. The first VCSEL chip and the second VCSEL chip are arranged back to back so that the laser emission direction of the first VCSEL chip is opposite to the laser emission direction of the second VCSEL chip. The first VCSEL chip and the second VCSEL chip share a negative conductive layer. In this way, the combined VCSEL chip integrates different types of VCSEL chips at the structural level, taking advantage of the advantages of different types of VCSEL chips and having a relatively small thickness.

Description

Technical Field

[0001] The present application relates to the field of VCSEL, and in particular to a combined VCSEL chip. Background Art

[0002] With the development of VCSEL (Vertical-Cavity Surface-Emitting Laser) technology, VCSEL chips suitable for different application scenarios have gradually emerged on the market, such as TOF VCSEL chips and structured light VCSEL chips.

[0003] Different types of chips have different characteristics. Specifically, existing structured light chips have the advantages of high transmittance and low energy consumption, but they are easily affected by the external environment and are only suitable for short-distance application scenarios. Moreover, they cannot work normally under low environmental conditions; existing TOF VCSEL chips have advantages such as being less affected by the environment, but their measurement accuracy is poor and their power consumption is high. In particular, high-power TOF VCSEL chips will generate a lot of heat during operation. Without sufficient heat dissipation, the performance of the chip will be affected in many ways.

[0004] In actual applications, there are cases where terminal devices use multiple VCSEL chips at the same time. For example, different models of VCSEL chips are placed on different sides of a smartphone to serve as the front VCSEL chip of the front camera module and the rear VCSEL chip of the rear camera module.

[0005] Accordingly, how to combine the advantages of different types of VCSEL chips and solve the respective defects of different types of VCSEL chips has become a very important technical issue. Summary of the Invention

[0006] The main advantage of the present application is to provide a combined VCSEL chip, wherein the combined VCSEL chip integrates VCSEL chips of different models at the structural level, takes advantage of VCSEL chips of different models, and has a relatively small thickness.

[0007] Another advantage of the present application is to provide a combined VCSEL chip, wherein the combined VCSEL chip has an integrated and compact one-piece structure.

[0008] Another advantage of the present application is that it provides a combined VCSEL chip, wherein the combined chip can selectively start different types of chips based on the needs of different application scenarios to improve its application scenario compatibility.

[0009] Another advantage of the present application is that it provides a combined VCSEL chip, wherein each VCSEL chip in the combined VCSEL chip can be illuminated in a zoned manner through the configuration of a negative conductive layer, thereby solving the heat dissipation problem of its high-power chip.

[0010] In order to achieve at least one of the above technical advantages, a combined VCSEL chip is provided, comprising:

[0011] A first VCSEL chip, wherein the first VCSEL chip includes a plurality of first VCSEL units arranged in a first array; and

[0012] a second VCSEL chip, wherein the second VCSEL chip includes a plurality of second VCSEL units arranged in a second array, wherein the first VCSEL chip and the second VCSEL chip are arranged back to back so that the laser emission direction of the first VCSEL chip is opposite to the laser emission direction of the second VCSEL chip, wherein the first VCSEL chip and the second VCSEL chip share a negative conductive layer.

[0013] In the combined VCSEL chip according to the present application, the cathode conductive layer includes a first electrically conductive pattern and a second electrically conductive pattern, wherein the first electrically conductive pattern is electrically connected to a first subset of the plurality of first VCSEL units and electrically connected to a third subset of the plurality of second VCSEL units; and the second electrically conductive pattern is electrically connected to a second subset of the plurality of first VCSEL units and electrically connected to a fourth subset of the plurality of second VCSEL units.

[0014] In the combined VCSEL chip according to the present application, the first subset and the second subset do not have the same first VCSEL unit, and the third subset and the fourth subset do not have the same second VCSEL unit.

[0015] In the combined VCSEL chip according to the present application, the first subset includes all the first VCSEL units in the second subset, and the third subset includes all the second VCSEL units in the fourth subset.

[0016] In the combined VCSEL chip according to the present application, the cathode conductive layer further includes a third electrical conductive pattern, and the third electrical conductive pattern is electrically connected to the fifth subset of the plurality of first VCSEL units and the seventh subset of the plurality of second VCSEL units.

[0017] In the combined VCSEL chip according to the present application, each first VCSEL unit includes, from bottom to top, a substrate, an N-type doped DBR, an active region, a confinement layer having openings, a P-type doped DBR, an ohmic contact layer, and a positive conductive layer. The first VCSEL chip has an isolation trench formed between every two first VCSEL units. Each isolation trench extends upward from the substrate, passes through the substrate and the N-type doped DBR, and reaches the bottom of the positive conductive layer, thereby electrically isolating the first VCSEL units in the first VCSEL chip from each other.

[0018] In the combined VCSEL chip according to the present application, each second VCSEL unit includes, from bottom to top, a substrate, an N-type doped DBR, an active region, a confinement layer having openings, a P-type doped DBR, an ohmic contact layer, and a positive conductive layer. The second VCSEL chip has an isolation trench formed between each two second VCSEL units. Each isolation trench extends upward from the substrate, passes through the substrate and the N-type doped DBR, and reaches the bottom of the positive conductive layer, thereby electrically isolating the second VCSEL units in the second VCSEL chip from each other.

[0019] In the combined VCSEL chip according to the present application, each first VCSEL unit includes, from bottom to top, a substrate, an N-type doped DBR, an active region, a confinement layer having openings, a P-type doped DBR, an ohmic contact layer, and a positive conductive layer. The first VCSEL chip further includes an isolation dielectric formed by doping between every two first VCSEL units. The isolation dielectric extends between the substrates and the N-type doped DBRs of the first VCSEL units, thereby electrically isolating the first VCSEL units in the first VCSEL chip from each other.

[0020] In the combined VCSEL chip according to the present application, each second VCSEL unit includes, from bottom to top, a substrate, an N-type doped DBR, an active region, a confinement layer with openings, a P-type doped DBR, an ohmic contact layer, and a positive conductive layer. The second VCSEL chip further includes an isolation dielectric formed by doping between every two second VCSEL units. The isolation dielectric extends between the substrate and the N-type doped DBR of the second VCSEL unit, thereby electrically isolating the second VCSEL units in the second VCSEL chip from each other.

[0021] In the combined VCSEL chip according to the present application, the first VCSEL chip and the second VCSEL chip are VCSEL chips of the same type and have different powers.

[0022] In the combined VCSEL chip according to the present application, the oxidation apertures of the first VCSEL unit and the second VCSEL unit range from 1 nm to 100 um, preferably from 7.5 um to 50 um.

[0023] In the combined VCSEL chip according to the present application, the first VCSEL chip and the second VCSEL chip are selected from a TOF VCSEL chip and a speckle structured light VCSEL.

[0024] In the combined VCSEL chip according to the present application, the first VCSEL chip and the second VCSEL chip are different types of VCSEL chips, wherein the first VCSEL chip is selected from a TOF VCSEL chip and a structured light VCSEL chip, and the second VCSEL chip is selected from a TOF VCSEL chip and a structured light VCSEL chip.

[0025] Further advantages and strengths of the present application will be fully apparent through understanding of the following description and accompanying drawings.

[0026] These and other advantages, features and strengths of the present application are fully apparent from the following detailed description, drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The figure shows a schematic diagram of applying two VCSEL chips to terminal equipment.

[0028] Figure 2 Another schematic diagram of applying two VCSEL chips to a terminal device is shown.

[0029] Figure 3 FIG2 shows a cross-sectional schematic diagram of a combined VCSEL chip according to an embodiment of the present application.

[0030] Figure 4 FIG2 shows a schematic diagram of each VCSEL unit in the combined VCSEL chip according to an embodiment of the present application.

[0031] Figure 5 FIG2 shows a top view of the combined VCSEL chip according to an embodiment of the present application.

[0032] Figure 6 The figure shows a bottom view of the combined VCSEL chip according to an embodiment of the present application.

[0033] Figure 7 FIG2 shows a cross-sectional schematic diagram of a combined VCSEL chip according to another embodiment of the present application.

[0034] Figure 8 FIG2 shows a top view of the combined VCSEL chip according to another embodiment of the present application.

[0035] Figure 9 FIG2 shows a bottom view of the combined VCSEL chip according to another embodiment of the present application.

[0036] Figure 10 FIG2 is a cross-sectional schematic diagram of a modified implementation of the combined VCSEL chip according to another embodiment of the present application. DETAILED DESCRIPTION

[0037] The following description is intended to disclose the present application and enable those skilled in the art to implement the present application. The preferred embodiments described below are for illustrative purposes only, and those skilled in the art may readily conceive of other obvious variations. The basic principles of the present application defined in the following description may be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present application.

[0038] Those skilled in the art should understand that, in the disclosure of this application, the terms "longitudinal", "transverse", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like to indicate orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms should not be understood as limiting this application.

[0039] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the elements may be multiple, and the term "one" should not be understood as a limitation on the quantity.

[0040] Application Overview

[0041] As mentioned above, in actual applications, terminal devices have already adopted multiple VCSEL chip types. For example, in smartphones, different types of VCSEL chips are placed on different sides of the smartphone, serving as the front-facing VCSEL chip for the front camera module and the rear-facing VCSEL chip for the rear camera module. Therefore, how to combine the advantages of different VCSEL chip types and address their respective shortcomings has become a very important technical issue.

[0042] There are two types of existing VCSEL chip combinations: "front-to-back light emission" and "same-side light emission". Front-to-back light emission refers to placing two VCSEL chips back to back so that the laser emission directions of the two are opposite. Figure 1 and Figure 2 shown. Figure 1 The figure shows a schematic diagram of applying two VCSEL chips to terminal equipment. Figure 1 As shown, in this solution, the two VCSEL chips are placed in an offset and back-to-back manner. Although this solution can integrate the advantages of the two VCSEL chips to a certain extent, the solution occupies too large an area, that is, it occupies a large volume of the terminal device, which does not conform to the current development trend of miniaturization and thinning of terminal devices. Figure 2 The figure shows another schematic diagram of applying two VCSEL chips to terminal equipment. Figure 2 As shown, in this solution, the two VCSEL chips are aligned and arranged back to back. Although this solution can integrate the advantages of two VCSEL chips to a certain extent, the thickness of this solution is relatively large, that is, the volume occupied by the terminal device is still relatively large, which does not conform to the current development trend of miniaturization and thinning of terminal devices.

[0043] Correspondingly, "light emitting from the same side" means setting the light-emitting surfaces of the two VCSEL chips on the same plane. Obviously, this solution occupies a large area and still does not conform to the current development trend of miniaturization and thinning of terminal equipment.

[0044] Moreover, looking at the existing "light emitting from the same side" and "light emitting from the front and back" technical solutions, it can be found that: in the existing combined VCSEL chip application solution, there is no structural connection between the various VCSEL chips. That is, in the existing combined VCSEL chip application solution, the various VCSEL chips are only placed in different positions of the terminal device, but they essentially still work and are controlled separately.

[0045] In addition, as the power of VCSEL chips increases, the heat dissipation problem of VCSEL chips becomes more serious, that is, the thermal sensitivity problem becomes more serious. The current solution to the thermal sensitivity characteristics is mainly to change the thermal sensitivity characteristics of the VCSEL chip itself by adjusting the underlying design of the VCSEL chip. However, due to the unique properties of the semiconductor itself, this thermal sensitivity is difficult to fundamentally optimize or eliminate. That is, this solution can only improve the thermal sensitivity characteristics within a certain range.

[0046] In response to the above technical problems, the basic idea of ​​this application is to realize the integration of multiple VCSEL chips at the structural level, so that the final combined VCSEL chip has the advantages of different models of VCSEL chips and has a relatively small thickness.

[0047] Based on this, the present application provides a combined VCSEL chip, comprising a first VCSEL chip including a plurality of first VCSEL units arranged in a first array; and a second VCSEL chip including a plurality of second VCSEL units arranged in a second array, wherein the first VCSEL chip and the second VCSEL chip are arranged back to back so that the laser emission direction of the first VCSEL chip is opposite to the laser emission direction of the second VCSEL chip, and wherein the first VCSEL chip and the second VCSEL chip share a negative conductive layer. In this way, the combined VCSEL chip integrates different types of VCSEL chips at the structural level, taking advantage of the advantages of different types of VCSEL chips and having a relatively small thickness.

[0048] After introducing the basic principles of the present application, various non-limiting embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0049] Example 1

[0050] The inventors of this application have studied the structural consistency of chips of different models and proposed a technical solution for integrating different chip models at the structural level, so that the combined chip has the multiple advantages of different types of VCSEL chips. Moreover, through structural optimization, the combined chip has a compact structure, especially a relatively small thickness, which meets the current trend of thinning terminal devices. Here, in the embodiments of this application, different chip models include chips of the same type but different parameters and chips of different models. Among them, chips of the same type but different parameters include, for example, TOF VCSEL chips with different power and speckle structured light chips with different power; chips of different models include, for example, TOF VCSEL chips and speckle structured light chips.

[0051] The following takes the combination chip integrating the first VCSEL chip and the second VCSEL chip as an example to illustrate the combination chip of the embodiment of the present application, wherein the first VCSEL chip and the second VCSEL chip are chips of different models.

[0052] Figure 3 FIG2 shows a schematic diagram of a combined VCSEL chip according to an embodiment of the present application, as shown in FIG2. Figure 3As shown, the combined chip includes a first VCSEL chip 10 and a second VCSEL chip 20. The first VCSEL chip 10 and the second VCSEL chip 20 are arranged back to back, so that the laser emission direction of the first VCSEL chip 10 is opposite to the laser emission direction of the second VCSEL chip 20. The first VCSEL chip 10 includes a plurality of first VCSEL units 11 arranged in a first array, and the second VCSEL chip 20 includes a plurality of second VCSEL units 21 arranged in a second array. Specifically, the first VCSEL chip 10 and the second VCSEL chip 20 share a negative conductive layer 30. In this way, VCSEL chips of different models are integrated at the structural level.

[0053] It should be noted that in the implementation of the present application, the first VCSEL chip 10 and the second VCSEL chip 20 are front-emitting VCSEL chips, that is, the light-emitting surfaces of the first VCSEL chip 10 and the second VCSEL chip 20 are formed on the front, and the negative conductive layer 30 forms the back of the VCSEL chips 10 and 20.

[0054] In order to illustrate the light emitting principle of the first VCSEL chip 10 and the second VCSEL chip 20 , the structures of the first VCSEL unit 11 and the second VCSEL unit 21 are described. Figure 4 FIG. 1 shows a schematic diagram of each VCSEL unit in the combined VCSEL chip according to an embodiment of the present application, as shown in FIG. Figure 4 As shown, the first and second VCSEL units 11 and 21 (the first VCSEL unit 11 and the second VCSEL unit are structurally identical) comprise, from bottom to top, a negative electrode 09, a substrate 01, a buffer layer 02, an N-type doped DBR 03, an active region 04, a confinement layer 05, a P-type doped DBR 06, an ohmic contact layer 07, and a positive electrode 08. The active region 04 is sandwiched between the P-type doped DBR 06 and the N-type doped DBR 03 to form a resonant cavity. It should be understood that the negative electrodes of the VCSEL units are interconnected to form the negative conductive layer 30 of the first VCSEL chip 10 and the negative conductive layer 30 of the second VCSEL chip 20; and the positive electrodes of the VCSEL units are interconnected to form the positive conductive layer 40 of the first VCSEL chip 10 and the positive conductive layer 40 of the second VCSEL chip 20.

[0055] During operation, the VCSEL unit can achieve laser excitation only if the following two conditions are met: (1) Particle population inversion process: When there is a population inversion in the active region 04, so that the gain provided by the laser medium is sufficient to exceed the loss, when current is injected through the negative electrode 09 and the positive electrode 08, the light intensity will continue to increase, and when the electrons at the bottom of the high-energy conduction band transition to the low-energy band, as the light of a specific wavelength is reflected back and forth between the P-type doped DBR 06 and the N-type doped DBR 03, the amplification process is repeated continuously, and a laser is formed; (2) Resonant cavity: composed of the P-type doped DBR 06, the N-type doped DBR 03 and the gain medium, it is one of the main conditions for generating lasers. The main function of the resonant cavity is to form multiple light energy feedbacks when the light generated in the active region 04 is reflected back and forth between the P-type doped DBR 06 and the N-type doped DBR 03, providing a cavity in which the stimulated radiation is fed back and forth to form laser oscillation. After being turned on, the laser light projected by the VCSEL unit will generate a set of interference fringes in space.

[0056] It is worth mentioning that in the embodiments of the present application, the selection of materials for each layer of the VCSEL units 11, 21 is not limited to the present application. For example, the substrate 01 may include but is not limited to a silicon substrate, a sapphire substrate, and a potassium arsenide substrate; the materials of the P-type doped DBR 06 and the N-type doped DBR 03 include but are not limited to: InGaAsP / InP, AlGaInAs / AlInAs, AlGaAsSb / AlAsSb, GaAs / AlGaAs, Si / MgO, and Si / Al2O3, etc.

[0057] It should be understood that, in a normal structural configuration, the first VCSEL chip 10 and the second VCSEL chip 20 each have their own cathode conductive layer 30. However, in the embodiment of the present application, because the first VCSEL chip 10 and the second VCSEL chip 20 are arranged back to back, that is, the cathode conductive layer 30 of the first VCSEL chip 10 and the cathode conductive layer 30 of the second VCSEL chip 20 are overlapped, the cathode conductive layer 30 of the first VCSEL chip 10 and the second VCSEL chip 20 can be integrated and shared at the structural level. In other words, in the embodiment of the present application, the combined VCSEL chip only includes a common cathode conductive layer 30. It should be understood that, in this manner, the thickness of the combined chip can be reduced. Moreover, because the first VCSEL chip 10 and the second VCSEL chip 20 are overlapped in the combined chip, the horizontal area occupied by the combined chip is also relatively small. In other words, the horizontal and thickness dimensions of the combined chip can be optimized compared to existing technical solutions.

[0058] Figure 5 FIG2 shows a top view of the combined VCSEL chip according to an embodiment of the present application. Figure 6 FIG2 shows a bottom view of the combined VCSEL chip according to an embodiment of the present application. Figure 5 As shown, in this example, the first VCSEL chip 10 is implemented as a TOF VCSEL chip, and the plurality of first VCSEL units 11 included therein are arranged in a regular array; Figure 6 As shown, in this example, the second VCSEL chip 20 is implemented as a structured light VCSEL chip, and the plurality of second VCSEL units 21 included therein are arranged in an array in a specific coding manner. That is, in this example, the first VCSEL chip 10 and the second VCSEL chip 20 are of different types. Therefore, the combined chip can selectively activate the first VCSEL chip 10 and / or the second VCSEL chip 20 based on the requirements of different application scenarios. For example, in an application scenario requiring higher measurement accuracy, the second VCSEL chip 20 can be activated and the first VCSEL chip 10 can be disabled. When measuring at a long distance, the first VCSEL chip 10 can be activated and the second VCSEL chip 20 can be disabled.

[0059] It is worth mentioning that, in this example, the first VCSEL chip 10 and the second VCSEL chip 20 may also be implemented as VCSEL chips of the same type but with different parameters (eg, different powers), which is not limited by the present application.

[0060] During the preparation process, the epitaxial structures of the first VCSEL chip 10 and the second VCSEL chip 20 (the epitaxial structure includes the substrate 01, the buffer layer 02, the N-type doped DBR 03, the active region 04, the confinement layer 05, the P ... 06 and ohmic contact layer 07); then, the epitaxial structure is processed by photolithography or other etching processes to form a mesa structure of the first VCSEL chip 10 and the second VCSEL chip 20; then, a positive conductive layer 40 is formed on the mesa structure by an evaporation process to obtain the first VCSEL chip 10 and the second VCSEL chip 20 without the negative conductive layer 30; then, the first VCSEL chip 10 and the second VCSEL chip 20 without the negative conductive layer 30 are arranged back to back, and then, the negative conductive layer 30 is formed between the first VCSEL chip 10 and the second VCSEL chip 20 without the negative conductive layer 30 by a metal growth process, so as to integrate the first VCSEL chip 10 and the second VCSEL chip 20 at the structural level through the negative conductive layer 30.

[0061] It is worth mentioning that those skilled in the art should be aware that in the field of VCSEL, there are also VCSEL chips with back-light emission (i.e., the light-emitting surface is formed on the back side of the VCSEL chip). Accordingly, based on the inventive concept of the present application, the first VCSEL chip 10 and the second VCSEL chip 20 with back-light emission can be similarly arranged back to back, so that the laser emission direction of the first VCSEL chip 10 is opposite to the laser emission direction of the second VCSEL chip 20. In addition, at the structural level, the first VCSEL chip 10 and the second VCSEL chip 20 share the positive conductive layer 40, that is, the first VCSEL chip 10 and the second VCSEL chip 20 are structurally integrated by sharing the positive conductive layer 40.

[0062] In summary, the combined VCSEL chip according to the embodiment of the present application is explained, which integrates different types of VCSEL chips at the structural level, has the advantages of different types of VCSEL chips, and has a relatively small thickness.

[0063] Example 2

[0064] like Figure 7As shown, a combined VCSEL chip based on another embodiment of the present application is illustrated, wherein the combined VCSEL chip illustrated in Example 2 is further optimized at the structural level compared to Example 1 to solve the technical problem of heat dissipation of high-power VCSEL chips.

[0065] like Figure 7 As shown, in the embodiment of the present application, the first VCSEL chip 10 and the second VCSEL chip 20 still share the negative conductive layer 30 at the structural level. In order to solve the problem of heat dissipation, a "partitioned lighting" electrical connection solution is adopted. Specifically, Figures 7 to 9 As shown, in the embodiment of the present application, the negative conductive layer 30 includes a first electrically conductive pattern 31 and a second electrically conductive pattern 32, wherein the first electrically conductive pattern 31 is electrically connected to a first subset of the plurality of first VCSEL units 11 and electrically connected to a third subset of the plurality of second VCSEL units 21; and the second electrically conductive pattern 32 is electrically connected to a second subset of the plurality of first VCSEL units 11 and electrically connected to a fourth subset of the plurality of second VCSEL units 21.

[0066] In particular, there are two relationships between the first subset and the second subset, and between the third subset and the fourth subset: the first subset and the second subset do not have the same first VCSEL unit 11, and the third subset and the fourth subset do not have the same second VCSEL unit 21; or the first subset includes all the first VCSEL units 11 in the second subset, and the third subset includes all the second VCSEL units 21 in the fourth subset. In other words, either there is no intersection between the first subset and the second subset, and there is no intersection between the third subset and the fourth subset, or the first subset completely includes the second subset, and the third subset completely includes the fourth subset.

[0067] Of course, in other examples of the present application, the negative conductive layer 30 may further include more electrical conductive patterns to divide the first VCSEL chip 10 and the second VCSEL chip 20 into more areas. For example, the negative conductive layer 30 may further include a third electrical conductive pattern 33, and the third electrical conductive pattern 33 is electrically connected to the fifth subset of the plurality of first VCSEL units 11 and the seventh subset of the plurality of second VCSEL units 21.

[0068] It should be understood that the negative conductive layer 30 can divide the first VCSEL chip 10 and the second VCSEL chip 20 into different areas, that is, the first VCSEL chip 10 and the second VCSEL chip 20 can be lit in different areas, so that the combined VCSEL chip can selectively adjust the number of actually working VCSEL units of the first VCSEL chip 10 and the second VCSEL chip 20 based on the needs of actual application scenarios, so as to reduce power consumption and solve the problem of heat dissipation.

[0069] It should be understood that since the negative conductive layer 30 is formed on the back side of the first VCSEL chip 10 and the second VCSEL chip 20, no matter how complex the wiring and direction structure of the negative conductive layer 30 are, it will not affect the normal light emission of the first VCSEL chip 10 and the second VCSEL chip 20.

[0070] Furthermore, in order to achieve the technical purpose of “divided lighting”, the first VCSEL units 11 in the first VCSEL chip 10 and the second VCSEL units 21 in the second VCSEL chip 20 should be electrically isolated from each other. Figure 7 As shown, in this example, the first VCSEL chip 10 has an isolation trench 100 formed between every two first VCSEL units 11. Each isolation trench 100 extends upward from the substrate 01, penetrates the substrate 01 and the N-type doped DBR 03, and reaches the bottom of the positive conductive layer 40, so that the first VCSEL units 11 in the first VCSEL chip 10 are electrically isolated from each other. Correspondingly, the second VCSEL chip 20 has an isolation trench 100 formed between every two second VCSEL units 21. Each isolation trench 100 extends upward from the substrate 01, penetrates the substrate 01 and the N-type doped DBR 03, and reaches the bottom of the positive conductive layer 40, so that the second VCSEL units 21 in the second VCSEL chip 20 are electrically isolated from each other.

[0071] During the preparation process, the combined chip can be prepared by the following preparation process, which first includes preparing the first VCSEL chip 10 and the second VCSEL chip 20 without the negative conductive layer 30. The process includes: first, forming an epitaxial structure, which includes, from bottom to top, a substrate 01, an N-type doped DBR 03, an active region 04, a confinement layer 05, and a P-type doped DBR. 06 and the ohmic contact layer 07; remember, a plurality of mesa structures are formed on the epitaxial structure by an etching process, each of the mesa structures includes the active area 04, the confinement layer 05, the P-type doped DBR 06 and the ohmic contact layer 07 from bottom to top, wherein the ohmic contact layer 07 includes a top electrical contact area formed on its upper surface; then, the confinement layer 05 of each mesa structure is oxidized by an oxidation process so that the confinement layer 05 has an opening with a specific aperture; then, a dielectric insulating layer is deposited on the mesa structure, wherein the dielectric insulating layer covers the upper surface of the substrate, the bottom area of ​​the mesa structure, and other areas of the ohmic contact layer 07 except the top electrical contact area; then, a positive conductive layer 40 is formed on the upper surface of the ohmic contact layer 07; then, the substrate 01 and the N-type doped DBR are etched 03 to form an isolation trench 100 between every two of the mesa structures, so as to separate and form a plurality of VCSEL units through the isolation trench 100, wherein the isolation trench 100 extends upward from the substrate 01 and penetrates the substrate 01 and the N-type doped DBR 03 and reaches the bottom of the positive conductive layer 40.

[0072] After forming the first VCSEL chip 10 and the second VCSEL chip 20 without the negative conductive layer 30 , the negative conductive layer 30 is further formed between the first VCSEL chip 10 and the second VCSEL chip 20 , so as to integrate the first VCSEL chip 10 and the second VCSEL chip 20 at the structural level through the negative conductive layer 30 .

[0073] Of course, in other examples of the present application, electrical isolation between the multiple first VCSEL units 11 in the first VCSEL chip 10 and between the multiple second VCSEL units 21 in the second VCSEL chip 20 can also be achieved in other ways. Figure 10 FIG2 shows a cross-sectional view of a modified embodiment of the combined VCSEL chip according to another embodiment of the present application. Figure 10As shown, in this variant embodiment, the first VCSEL chip 10 further includes an isolation dielectric doped between every two first VCSEL units 11. The isolation dielectric extends between the substrate of the first VCSEL unit 11 and the N-type doped DBR, thereby electrically isolating the first VCSEL units 11 in the first VCSEL chip 10. The second VCSEL chip 20 further includes an isolation dielectric doped between every two second VCSEL units 21. The isolation dielectric 100A extends between the substrate of the second VCSEL unit 21 and the N-type doped DBR, thereby electrically isolating the second VCSEL units 21 in the second VCSEL chip 20. In particular, the isolation dielectric 100A is doped by any one or a combination of high-energy implants selected from H, He, C, O, and N, with an energy level of MeV and a dose of 10 11-15 .

[0074] During the preparation process, the combined chip can be prepared by the following preparation process, which first includes preparing the first VCSEL chip 10 and the second VCSEL chip 20 without the negative conductive layer 30. The process includes: first forming an epitaxial structure, which includes, from bottom to top, a substrate 01, an N-type doped DBR 03, an active area 04, a confinement layer 05, and a P-type doped DBR. 06 and ohmic contact layer 07; then, a plurality of mesa structures are formed on the epitaxial structure by an etching process, each of the mesa structures including the active area 04, the confinement layer 05, the P-type doped DBR 06 and the ohmic contact layer 07 from bottom to top, wherein the ohmic contact layer 07 includes a top electrical contact area formed on its upper surface; then, the confinement layer 05 of each mesa structure is oxidized by an oxidation process so that the confinement layer 05 has an opening with a specific aperture; then, an isolation dielectric 100A is injected between each two of the mesa structures, wherein the isolation dielectric 100A is doped and formed between the substrate 01 and the N-type doped DBR 03; then, a dielectric insulating layer is deposited on the mesa structure, wherein the dielectric insulating layer covers the upper surface of the substrate 01, the bottom area of ​​the mesa structure, and other areas of the ohmic contact layer 07 except the top electrical contact area; then, a positive conductive layer 40 is formed on the upper surface of the ohmic contact layer 07, wherein the positive conductive layer 40 is electrically connected to the top electrical contact areas of all the mesa structures.

[0075] After forming the first VCSEL chip 10 and the second VCSEL chip 20 without the negative conductive layer 30 , the negative conductive layer 30 is further formed between the first VCSEL chip 10 and the second VCSEL chip 20 , so as to integrate the first VCSEL chip 10 and the second VCSEL chip 20 at the structural level through the negative conductive layer 30 .

[0076] Moreover, in an embodiment of the present application, the first VCSEL chip 10 and the second VCSEL chip 20 are also chips of different models, including chips of the same type but different parameters and chips of different models. For example, the first VCSEL chip 10 and the second VCSEL chip 20 are VCSEL chips of the same type and have different powers, or the first VCSEL chip 10 is a TOF VCSEL chip, and the second VCSEL chip 20 is a structured light VCSEL chip.

[0077] In summary, the combined VCSEL chip according to the embodiment of the present application is explained, which integrates VCSEL chips of different models at the structural level, has the advantages of VCSEL chips of different models, and has a relatively small thickness.

[0078] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, and effects mentioned in this application are merely illustrative and not restrictive, and it should not be assumed that these advantages, strengths, and effects are required of each embodiment of this application. In addition, the specific details disclosed above are merely illustrative and facilitating understanding, and are not restrictive. The above details do not limit this application to necessarily being implemented using the above specific details.

[0079] The block diagrams of the devices, devices, equipment, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, devices, equipment, and systems can be connected, arranged, or configured in any manner. Words such as "include," "comprise," "have," and the like are open-ended words, meaning "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or" and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0080] It should also be noted that in the apparatus, device, and method of the present application, each component or each step can be decomposed and / or recombined, and such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0081] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0082] The above description has been given for the purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A combined VCSEL chip, characterized in that: include: A first VCSEL chip, wherein the first VCSEL chip includes a plurality of first VCSEL units arranged in a first array; as well as a second VCSEL chip, the second VCSEL chip comprising a plurality of second VCSEL units arranged in a second array, wherein the first VCSEL chip and the second VCSEL chip are arranged back to back so that a laser emission direction of the first VCSEL chip is opposite to a laser emission direction of the second VCSEL chip, and wherein the first VCSEL chip and the second VCSEL chip share a cathode conductive layer; The first VCSEL chip and the second VCSEL chip are VCSEL chips of the same type but have different powers, or the first VCSEL chip and the second VCSEL chip are VCSEL chips of different types.

2. The combined VCSEL chip according to claim 1, wherein: The cathode conductive layer includes a first electrically conductive pattern and a second electrically conductive pattern, wherein the first electrically conductive pattern is electrically connected to a first subset of the plurality of first VCSEL units and is electrically connected to a third subset of the plurality of second VCSEL units; And, the second electrical conduction pattern is electrically connected to a second subset of the plurality of first VCSEL units and is electrically connected to a fourth subset of the plurality of second VCSEL units.

3. The combined VCSEL chip according to claim 2, wherein: The first subset and the second subset do not have the first VCSEL unit in common, and the third subset and the fourth subset do not have the second VCSEL unit in common.

4. The combined VCSEL chip according to claim 2, wherein: The first subset includes all the first VCSEL units in the second subset, and the third subset includes all the second VCSEL units in the fourth subset.

5. The combined VCSEL chip according to claim 3 or 4, wherein: The cathode conductive layer further includes a third electrical conductive pattern, wherein the third electrical conductive pattern is electrically connected to a fifth subset of the plurality of first VCSEL units and is electrically connected to a seventh subset of the plurality of second VCSEL units.

6. The combined VCSEL chip according to claim 1, wherein: Each of the first VCSEL units includes, from bottom to top, a substrate, an N-type doped DBR, an active region, a confinement layer having openings, a P-type doped DBR, an ohmic contact layer, and an anode conductive layer. The first VCSEL chip has an isolation trench formed between every two of the first VCSEL units. Each of the isolation trenches extends upward from the substrate, passes through the substrate and the N-type doped DBR, and reaches the bottom of the anode conductive layer, so that the first VCSEL units in the first VCSEL chip are electrically isolated from each other.

7. The combined VCSEL chip according to claim 1, wherein: Each of the second VCSEL units includes, from bottom to top, a substrate, an N-type doped DBR, an active region, a confinement layer having openings, a P-type doped DBR, an ohmic contact layer, and an anode conductive layer. The second VCSEL chip has an isolation trench formed between each two of the second VCSEL units. Each of the isolation trenches extends upward from the substrate, passes through the substrate and the N-type doped DBR, and reaches the bottom of the anode conductive layer, so that the second VCSEL units in the second VCSEL chip are electrically isolated from each other.

8. The combined VCSEL chip according to claim 1, wherein: Each of the first VCSEL units includes, from bottom to top, a substrate, an N-type doped DBR, an active region, a confinement layer having openings, a P-type doped DBR, an ohmic contact layer, and a positive conductive layer. The first VCSEL chip further includes an isolation dielectric formed between every two of the first VCSEL units by doping. The isolation dielectric extends between the substrate and the N-type doped DBR of the first VCSEL unit, so as to electrically isolate the first VCSEL units in the first VCSEL chip from each other.

9. The combined VCSEL chip according to claim 1, wherein: Each of the second VCSEL units includes, from bottom to top, a substrate, an N-type doped DBR, an active region, a confinement layer having openings, a P-type doped DBR, an ohmic contact layer, and a positive conductive layer. The second VCSEL chip further includes an isolation dielectric formed between every two second VCSEL units by doping. The isolation dielectric extends between the substrate and the N-type doped DBR of the second VCSEL unit, so as to electrically isolate the second VCSEL units in the second VCSEL chip from each other.

10. The combined VCSEL chip according to claim 1, wherein: When the first VCSEL chip and the second VCSEL chip are of the same type and have different powers, the first VCSEL chip and the second VCSEL chip are selected from a TOF VCSEL chip, a coded structured light VCSEL chip, and a speckle structured light VCSEL chip.

11. The combined VCSEL chip according to claim 1, wherein: When the first VCSEL chip and the second VCSEL chip are different types of VCSEL chips, the first VCSEL chip is selected from a TOF VCSEL chip, a coded structured light VCSEL chip, and a speckle structured light VCSEL chip, and the second VCSEL chip is selected from a TOF VCSEL chip, a coded structured light VCSEL chip, and a speckle structured light VCSEL chip.

Images