Voltage amplifier, method of amplifying input voltage and system thereof

Abstract

Disclosed herein are a voltage amplifier, a method of amplifying an input voltage, and a system thereof, related to systems and methods of amplifying an input voltage based on a series of charge pumpings. In an aspect, a first charge is stored in a first capacitor according to an input voltage to obtain a second voltage. In an aspect, the second voltage is amplified according to the first charge stored in the first capacitor to obtain a third voltage. In an aspect, a second charge is stored in a second capacitor according to the third voltage. In an aspect, the third voltage is amplified according to the second charge stored in the second capacitor to obtain a fourth voltage.

Description

TECHNICAL FIELD

[0001] The present disclosure provides a voltage amplifier, a method of amplifying an input voltage, and a system thereof. BACKGROUND

[0002] Many electronic components can include a voltage amplifier for processing a small signal. The voltage amplifier can amplify a voltage of an input signal to obtain an amplified signal, which has a voltage greater than that of the input signal. By obtaining the amplified signal, additional processing can be performed, e.g., analog processing or digital processing can be performed on the amplified signal having a greater voltage. SUMMARY

[0003] The present disclosure provides a voltage amplifier, comprising: a first capacitor, a second capacitor, a differential amplifier, a first set of switches, a second set of switches, a third set of switches, and a fourth set of switches. The first capacitor comprises a first electrode and a second electrode. The second capacitor comprises a third electrode and a fourth electrode. The differential amplifier comprises a first input port, a second input port, and an output port, wherein the second input port of the differential amplifier is coupled to the output port of the differential amplifier. The first set of switches is configured to selectively couple the first electrode of the first capacitor to i) the output port of the differential amplifier or ii) a reference metal rail. The second set of switches is configured to selectively couple the second electrode of the first capacitor to i) the output port of the differential amplifier or ii) the first input port of the differential amplifier. The third set of switches is configured to selectively couple the third electrode of the second capacitor to i) the output port of the differential amplifier or ii) the reference metal rail. The fourth set of switches is configured to selectively couple the fourth electrode of the second capacitor to i) the output port of the differential amplifier or ii) an input port of the device.

[0004] The present disclosure further provides a method of amplifying an input voltage, comprising: generating, at a set of capacitors, an input voltage corresponding to an input data; storing, by a first capacitor, a plurality of first charges corresponding to the input voltage, wherein according to the plurality of first charges, a first electrode of the first capacitor has a first voltage and a second electrode of the first capacitor has a second voltage; amplifying, according to the plurality of first charges, the second voltage of the second electrode of the first capacitor by increasing the first voltage of the first electrode of the first capacitor to obtain a third voltage; storing, by a second capacitor, a plurality of second charges corresponding to the third voltage, wherein according to the plurality of second charges, a third electrode of the second capacitor has a fourth voltage and a fourth electrode of the second capacitor has the third voltage; and amplifying, according to the plurality of second charges, the third voltage of the fourth electrode of the second capacitor by increasing the fourth voltage of the third electrode of the second capacitor.

[0005] The present disclosure also provides a system for amplifying an input voltage, comprising a set of capacitors, a voltage amplifier coupled to the set of capacitors, and a controller coupled to the voltage amplifier. The voltage amplifier comprises a first capacitor, a second capacitor, and a set of switches. The controller causes the set of switches to perform the following steps: generate an input voltage at the set of capacitors according to input data; store a plurality of first charges in the first capacitor according to the input voltage to obtain a second voltage; amplify the second voltage according to the plurality of first charges stored in the first capacitor to obtain a third voltage; store a plurality of second charges in the second capacitor according to the third voltage; and amplify the third voltage according to the plurality of second charges stored in the second capacitor to obtain a fourth voltage. BRIEF DESCRIPTION OF DRAWINGS

[0006] The aspects of the disclosure can be better understood when read in conjunction with the following detailed description in conjunction with the following drawings. It is noted that the various features are not drawn to scale. In fact, the dimensions can be arbitrarily increased or decreased for the sake of clarity. It is also noted that, for clarity and the ease of illustration, dimensions of various features can not necessarily be drawn to scale and that certain

[0007] Figure 1 A diagram of a memory system according to an embodiment;

[0008] Figure 2 A diagram of a bit line controller according to an embodiment;

[0009] Figure 3 A diagram illustrating a compensation capacitor and a calculation capacitor according to an embodiment;

[0010] Figure 4 A timing diagram illustrating exemplary operation of a bit line controller according to an embodiment;

[0011] Figure 5 A circuit diagram of a calculation capacitor set and a voltage amplifier according to an embodiment;

[0012] Figure 6 A timing diagram illustrating exemplary operation of a calculation capacitor set and a voltage amplifier according to an embodiment;

[0013] Figure 7 A circuit diagram of an amplifier for reducing amplification of charge due to parasitic capacitance of switches connected to a calculation capacitor according to an embodiment;

[0014] Figure 8 A circuit diagram of a calculation capacitor set and a voltage amplifier according to an embodiment;

[0015] Figure 9 A timing diagram illustrating exemplary operation of a voltage amplifier according to an embodiment;

[0016] Figure 10A flowchart of a method of amplifying a voltage of an input signal according to some embodiments;

[0017] Figure 11 An exemplary block diagram of a computing system according to some embodiments.

[0018] NOTATION

[0019] 100: memory system

[0020] 105: memory controller

[0021] 110: timing controller

[0022] 112: bit line controller

[0023] 114: gate line controller

[0024] 120: memory array

[0025] 125: memory cell / storage circuit

[0026] 210: bit line driver

[0027] 220: compensation capacitor bank

[0028] 230: compute capacitor bank

[0029] 230A: compute capacitor bank

[0030] 230B: compute capacitor bank

[0031] 240: voltage amplifier

[0032] 240A: voltage amplifier

[0033] 240B: voltage amplifier

[0034] 250: analog-to-digital converter

[0035] 400: timing diagram

[0036] 410: pulse

[0037] 415: period

[0038] 420: pulse

[0039] 425: period

[0040] 430: pulse

[0041] 435: period

[0042] 435A: period

[0043] 435A': first sub-period

[0044] 435A: first sub-period

[0045] 435B: period

[0046] 435B': first sub-period

[0047] 435B": second sub-period

[0048] 440: pulse

[0049] 445: period

[0050] 500: circuit diagram

[0051] 510: common metal track

[0052] 530: reference metal track

[0053] 600: timing diagram

[0054] 700: circuit diagram

[0055] 800: circuit diagram

[0056] 900: timing diagram

[0057] 1000: method

[0058] 1010: operation

[0059] 1020: operation

[0060] 1030: operation

[0061] 1040: operation

[0062] 1050: operation

[0063] 1060: operation

[0064] 1100: computing system

[0065] 1105: host device

[0066] 1110: computing system

[0067] 1115: input device

[0068] 1120: output device

[0069] 1125A: interface

[0070] 1125B: interface

[0071] 1125C: interface

[0072] 1130A: central processing unit core

[0073] 1130N: central processing unit core

[0074] 1135: standard cell application

[0075] 1140: memory controller

[0076] 1145: memory array

[0077] A1: differential amplifier

[0078] A2: amplifier

[0079] BL0: bit line

[0080] BL1: bit line

[0081] BL2: bit line

[0082] BL3: bit line

[0083] BLK: bit line

[0084] BLN-1: bit line

[0085] BLN-2: bit line

[0086] CA0: capacitor

[0087] CA1: capacitor

[0088] CAN-1: capacitor

[0089] CAN-2: capacitor

[0090] CB0: capacitor

[0091] CB1: capacitor

[0092] CB2: capacitor

[0093] CB3: capacitor

[0094] CBN-1: capacitor

[0095] CBN-2: capacitor

[0096] Cp: parasitic capacitance

[0097] Cs1: capacitor

[0098] Cs2: capacitor

[0099] GL0: gate line

[0100] GL1: gate line

[0101] GL2: gate line

[0102] GLJ: Gate line

[0103] P0: Pulse

[0104] P1: Pulse

[0105] P2A: Pulse

[0106] P2B: Pulse

[0107] P3: Pulse

[0108] P4: Pulse

[0109] P5: Pulse

[0110] P5A: Pulse

[0111] P6: Pulse

[0112] P6A: Pulse

[0113] P7: Pulse

[0114] P8: Pulse

[0115] P8A: Pulse

[0116] S0: Switch

[0117] S2AA: Switch

[0118] S2AB: Switch

[0119] S2B: Switch

[0120] S3: Switch

[0121] S4: Switch

[0122] S5: Switch

[0123] S5A: Switch

[0124] S6: Switch

[0125] S6A: Switch

[0126] S7: Switch

[0127] S7A: Switch

[0128] S8: Switch

[0129] S8A: Switch

[0130] SA0: Switch

[0131] SA1: Switch

[0132] SAN-1: Switch

[0133] SAN-2: Switch

[0134] SB0: switch

[0135] SB1 : switch

[0136] SBN-1 : switch

[0137] SBN-2: switch

[0138] SB0A: switch

[0139] SB0B: switch

[0140] SB1A: switch

[0141] SB1B: switch

[0142] SB2A: switch

[0143] SB2B: switch

[0144] SB3A: switch

[0145] SB3B: switch

[0146] Vin: input voltage

[0147] Vout: output voltage DETAILED DESCRIPTION

[0148] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features, such that the first and second features can not be in direct contact. In addition, the present disclosure can repeat use of reference numerals in the various examples as a matter of convenience and clarity. This repetition of reference numerals is in no way intended to imply that the same element is being referred to in each instance.

[0149] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.

[0150] Disclosed herein are systems and methods for amplifying an input voltage based on cascaded charge pump boosting. In an aspect, a first charge is stored on a first capacitor according to an input voltage to obtain a second voltage. In an aspect, the second voltage is amplified according to the first charge stored on the first capacitor to obtain a third voltage. In an aspect, a second charge is stored on a second capacitor according to the third voltage. In an aspect, the third voltage is amplified according to the second charge stored on the second capacitor to obtain a fourth voltage.

[0151] Advantageously, the disclosed voltage amplifier can achieve several advantages. In an aspect, accurate voltage amplification can be achieved by implementing a differential amplifier, two capacitors, and a set of switches. In an aspect, the disclosed voltage amplifier can implement two capacitors for cascaded charge pump boosting such that many capacitors (e.g., three capacitors or more) for voltage amplification can be omitted. By reducing the number of implemented capacitors, an area efficiency improvement can be achieved and a signal to noise ratio (SNR) can be improved. In an aspect, the disclosed voltage amplifier can implement a differential amplifier, where the differential amplifier is configured to operate as a single gain buffer with a simple configuration that can consume less power than a complex high gain amplifier (e.g., an operational amplifier). By reusing a single differential amplifier for charge pump boosting, an area efficiency improvement can be achieved.

[0152] Disclosed herein are systems and methods for generating an input voltage from input data, where the input data is degraded due to parasitic capacitance. In an aspect, a set of capacitors can store charges corresponding to the input voltage. In an aspect, each capacitor in the set of capacitors can be connected to a corresponding switch that allows each capacitor in the set of capacitors to be selectively coupled to i) a corresponding bit line or ii) one or more of the other capacitors in the set of capacitors. In some embodiments, the set of capacitors can be connected to an amplifier that can reduce the charges stored by parasitic capacitance associated with the switches. By reducing the charges due to parasitic capacitance, signal linearity can be improved, allowing subsequent processes (e.g., analog processing or digital processing) to be performed in an efficient and accurate manner. In an aspect, a differential amplifier for charge pump boosting can be used to compensate for charges due to parasitic capacitance. By reusing the same differential amplifier, an area efficiency improvement can be achieved.

[0153] Although the voltage amplifiers disclosed herein are implemented for memory systems that store multi-bit data, the voltage amplifiers disclosed herein can be applied to any electronic device or system (e.g., a communication device or a sensing device) to amplify the voltage of an input signal.

[0154] Figure 1 A diagram of a memory system 100 according to an embodiment. In some embodiments, the memory system 100 includes a memory controller 105 and a memory array 120. The memory array 120 can include a plurality of storage circuits or memory cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 can be connected to a corresponding gate line (or word line) and a corresponding bit line. The memory controller 105 can write data into or read data from the memory array 120 according to electrical signals through the gate lines and the bit lines. In other embodiments, the memory system 100 includes more, fewer, or different elements than those shown. Figure 1 More, fewer, or different elements than those shown can be provided.

[0155] The memory array 120 is a hardware element that stores data. In an aspect, the memory array 120 is implemented as a semiconductor memory device. The memory array 120 includes a plurality of memory cells 125. The memory array 120 includes gate lines GL0, GL1, GL2, … GLJ, each of which extends along a first direction (e.g., the X direction); and bit lines BL0, BL1, BL2, … BLK, each of which extends along a second direction (e.g., the Y direction). The gate lines and the bit lines can be conductive metal lines or conductive tracks. In an aspect, each memory cell 125 is connected to a corresponding gate line and a corresponding bit line, and can be operated according to a voltage or a current through the corresponding gate line and the corresponding bit line. In an aspect, each memory cell 125 can be a ferroelectric field-effect transistor (FeFET), a resistive memory cell, a non-volatile memory cell, or a volatile memory cell. In some embodiments, the memory array 120 includes additional conductive lines (e.g., select lines, reference lines, reference control lines, power rails, etc.). The memory array 120 can store weighting data or bias data for constructing a neural network. Details are provided below with respect to Figures 2 to 10 Detailed descriptions of the construction and operation of the memory system 100 are provided.

[0156] Memory controller 105 is a hardware element that controls the operation of memory array 120. In some embodiments, memory controller 105 includes bit line controller 112, gate line controller 114, and timing controller 110. In one configuration, gate line controller 114 is a circuit that provides voltage or current through one or more gate lines of memory array 120, and bit line controller 112 is a circuit that provides or senses voltage or current through one or more bit lines and / or select lines of memory array 120. In one configuration, timing controller 110 is a circuit that provides control signals or clock signals to synchronize the operation of bit line controller 112 and gate line controller 114. Bit line controller 112 can be connected to bit lines and / or select lines of memory array 120, and gate line controller 114 can be connected to gate lines of memory array 120. In one example, to write data to memory cell 125, gate line controller 114 provides voltage or current to memory cell 125 through a gate line connected to memory cell 125, and bit line controller 112 applies a bias to memory cell 125 through a bit line and / or select line connected to memory cell 125. In one example, to read data from memory cell 125, gate line controller 114 provides voltage or current to memory cell 125 through a gate line connected to memory cell 125, and bit line controller 112 senses voltage or current corresponding to data stored in memory cell 125 through a bit line and / or select line connected to memory cell 125. In some embodiments, memory controller 105 includes more, fewer, or different elements than those shown in FIG. 1. Figure 1 In some embodiments, bit line controller 112 includes more, fewer, or different elements than those shown in FIG. 2.

[0157] Figure 2 A diagram of bit line controller 112 according to one embodiment. In some embodiments, bit line controller 112 includes bit line driver 210, compensation capacitor bank 220, computation capacitor bank 230, voltage amplifier 240, and analog to digital converter (ADC) 250. These elements can operate together to read multi-bit data stored in a group of memory cells 125. In one aspect, the multi-bit data stored in the group of memory cells 125 corresponds to weight data or bias data used to construct a neural network. In some embodiments, bit line controller 112 includes more, fewer, or different elements than those shown in FIG. 2. Figure 2 In some embodiments, bit line controller 112 includes more, fewer, or different elements than those shown in FIG. 2.

[0158] In some embodiments, the bit line driver 210 is a circuit or hardware element that generates one or more voltages or currents that the bit line driver 210 provides to a bit line or select line connected to the set of memory cells 125. To write one bit of multi-bit data to a memory cell 125, the bit line driver 210 can apply a voltage or current corresponding to one bit of data to a bit line or select line coupled to the memory cell 125. Thus, each of the set of memory cells 125 can store different bit data. To read multi-bit data from a set of memory cells 125, the bit line driver 112 can also apply voltages or currents to bit lines or select lines coupled to the set of memory cells 125 simultaneously or sequentially. In response to the voltages or currents applied through the bit lines or select lines, the set of memory cells 125 can output voltages or currents corresponding to the stored data.

[0159] In some embodiments, the compute capacitor bank 230 is a circuit or hardware element that stores a plurality of charges corresponding to multi-bit data stored by the set of memory cells 125. In one aspect, the compute capacitor bank 230 includes a set of capacitors coupled to the set of bit lines (or select lines). The set of capacitors of the compute capacitor bank 230 can have weighted capacitance values. Each capacitor in the set of capacitors can have a size or capacitance value associated with a corresponding bit. For example, a first capacitor of the set of capacitors can have a largest capacitance value in the set of capacitors, and each subsequent capacitor can have a smaller capacitance value than its previous capacitor. Thus, according to a voltage or current provided through a corresponding bit line or select line, the first capacitor can store a charge corresponding to a most significant bit (MSB) of multi-bit data. According to a voltage or current provided through a corresponding bit line or select line, each subsequent capacitor can store a charge corresponding to a subsequent bit of multi-bit data. Based on the charges stored in the compute capacitor bank 230, multi-bit data stored by the set of memory cells 125 can be read.

[0160] In some embodiments, the compensation capacitor bank 220 is a circuit or hardware element that provides a uniform capacitive load at the bit lines or select lines. In an aspect, the compensation capacitor bank 220 includes a set of capacitors coupled to the set of bit lines (or select lines). The set of capacitors of the compensation capacitor bank 220 can have weighted capacitance values that allow each bit line (or select line) to have the same total capacitance value. For example, a first bit line is coupled to i) a first capacitor of the computation capacitor bank 230 and ii) a first capacitor of the compensation capacitor bank 220 with the same or substantially close to the total capacitance value as a second bit line is coupled to i) a second capacitor of the computation capacitor bank 230 and ii) a second capacitor of the compensation capacitor bank 220. By implementing the compensation capacitor bank 220, the set of memory cells 125 can have a uniform capacitive load.

[0161] In some embodiments, the voltage amplifier 240 is a circuit or hardware element that amplifies an input voltage at the computation capacitor bank 230 through a series of charge pumps. In an aspect, the voltage amplifier 240 includes a first capacitor, a second capacitor, a differential amplifier, and a set of switches. The differential amplifier can be configured to operate as a unity-gain buffer. The set of switches can be configured according to different pulses from a controller (e.g., the timing controller 110). In a method, the voltage amplifier 240 can store a first charge at the first capacitor according to the input voltage to obtain a second voltage. The voltage amplifier 240 can amplify the second voltage according to the first charge stored at the first capacitor to obtain a third voltage. The voltage amplifier 240 can store a second charge at the second capacitor according to the third voltage. The voltage amplifier 240 can amplify the third voltage according to the second charge stored at the second capacitor to obtain a fourth voltage. The voltage amplifier 240 can provide the fourth voltage to the ADC 250. Through a series of charge pumps, the voltage amplifier 240 can achieve high voltage gain with a simple architecture. Details regarding the implementation and operation of the voltage amplifier 240 are provided below. Figures 4 to 10 Details regarding the implementation and operation of the voltage amplifier 240 are provided below.

[0162] In some embodiments, the ADC 250 is a circuit or hardware element that converts a voltage provided by the voltage amplifier 240 into multi-bit digital data. The ADC 250 can be implemented as a successive-approximation register (SAR) ADC. The ADC 250 can be implemented as any element that can convert an analog voltage into corresponding digital data.

[0163] In one aspect, the voltage sampled according to the least significant bit (LSB) of the multi-bit data stored in the set of memory cells 125 can be low such that the ADC 250 cannot successfully convert the voltage to obtain the LSB. For example, the memory cells 125 corresponding to the least significant bit (LSB) of the capacitor set 230 can be 10-100 femtofarads (fF), and the voltage resulting from such a small capacitance value can be 10-50 millivolts. To convert such a small voltage to corresponding digital data, the ADC 250 can be implemented with a complex architecture that can consume excessive power. By implementing the voltage amplifier 240 between the capacitor set 230 and the ADC 250, the ADC 250 can process the amplified voltage from the voltage amplifier 240. Thus, the ADC 250 can be implemented with a simpler architecture that has less power consumption.

[0164] Figure 3To illustrate the compensation capacitor bank 220 and the calculation capacitor bank 230 according to an embodiment. In some embodiments, the compensation capacitor bank 220 includes a set of capacitors CA0, CA1,...CAN-2, CAN-1 and a set of switches SA0, SA1,...SAN-2, SAN-1. In some embodiments, the calculation capacitor bank 230 includes a set of capacitors CB0, CB1,...CBN-2, CBN-1 and a set of switches SB0, SB1,...SBN-2, SBN-1. The set of switches SA0, SA1,...SAN-2, SAN-1 and the set of switches SB0, SB1,...SBN-2, SBN-1 can be implemented as transistors or any elements that can selectively couple two or more elements. In a configuration, each capacitor of the set of capacitors CA0, CA1,...CAN-2, CAN-1 (e.g., the Xth capacitor CAX) and its corresponding switch (e.g., the Xth switch SAX) are connected in series with each other, and each capacitor of the set of capacitors CB0, CB1,...CBN-2, CBN-1 (e.g., the Xth capacitor CBX) and its corresponding switch (e.g., the Xth switch SBX) are connected in series with each other. Further, i) the Xth capacitor CAX and ii) its corresponding Xth switch SAX first series connection and i) the Xth capacitor CBX and ii) its corresponding Xth switch SBX second series connection can be connected to its corresponding Xth bit line BLX. In an aspect, a controller (e.g., the timing controller 110) can generate a voltage or a pulse to control the Xth switches SAX, SBX to electrically couple the Xth capacitors CAX, CBX to its corresponding Xth bit line BLX. The controller can generate a common pulse and provide the common pulse to the set of switches SA0, SA1,...SAN-2, SAN-1 and the set of switches SB0, SB1,...SBN-2, SBN-1 such that the set of capacitors CA0, CA1,...CAN-2, CAN-1 and the set of capacitors CB0, CB1,...CBN-2, CBN-1 can be electrically coupled to the respective bit lines BL0, BL1,...BLN-2, BLN-1 simultaneously. Additionally or alternatively, the controller can generate individual pulses to individually or sequentially configure the set of switches SA0, SA1,...SAN-2, SAN-1 and the set of switches SB0, SB1,...SBN-2, SBN-1.

[0165] In an aspect, the set of capacitors CA0, CA1,...CAN-2, CAN-1 and the set of capacitors CB0, CB1,...CBN-2, CBN-1 have weighted capacitance values. The Xth capacitor CBX can have a capacitance value C 单位 ×2 X , where C 单位 is a unit capacitance. The Xth capacitor CAX can have a capacitance value C 位元线-C 单元 x2 X where C 位元线 total capacitance value at the Xth bit line BLX. Thus, each of the set of capacitors CB0, CB1...CBN-2, CBN-1 can have a different capacitance value according to a corresponding bit of the multi-bit data, while each of the bit lines BL0, BL1...BLN-2, BLN-1 can have the same total capacitance value.

[0166] Figure 4 A timing diagram 400 is provided to illustrate exemplary operation of the bit line controller 112 according to an embodiment. In some embodiments, a controller (e.g., the timing controller 110) can generate pulses 410, 420, 430, 440 and provide the pulses 410, 420, 430, 440 to the bit line controller 112. The controller can apply the pulses 410, 420, 430, 440 during four different time periods 415, 425, 435, 445. During the time period 415, the bit line controller 112 can perform sampling of voltages corresponding to the multi-bit data. During the time period 425, the bit line controller 112 can perform charge sharing. During the time period 435, the bit line controller 112 can perform voltage amplification. During the time period 445, the bit line controller 112 can perform analog-to-digital conversion. Through the operations performed during the time periods 415, 425, 435, 445, the multi-bit data stored in the set of memory cells 125 can be retrieved and processed.

[0167] During period 415, the controller can configure or cause the bit line controller 112 to sample a voltage corresponding to a multi-bit data stored in the set of memory cells 125. During period 415, the read pulse 410 can be metastable between a logical state "0" and a logical state "1." During period 415, the controller can generate the read pulse 410 and apply the read pulse 410 to the gate line controller 114, the bit line controller 112, or both. In response to the read pulse 410, the gate line controller 114 can apply a pulse corresponding to or synchronized with the read pulse 410 to the word line or control line connected to the set of memory cells 125. Similarly, in response to the read pulse 410, the bit line controller 112 (e.g., the bit line driver 210) can apply a pulse corresponding to or synchronized with the read pulse 410 to the bit line or sense line connected to the set of memory cells 125. The bit line controller 112 can apply the pulse to different bit lines or sense lines simultaneously or sequentially. In response to the pulse applied by the gate line controller 114, the bit line controller 112, or both, the set of memory cells 125 can output a voltage or current according to a logical state or stored bit. For example, in response to the read pulse 410, a first memory cell 125 storing a logical state "1" can output a higher voltage (e.g., 550 mV) than a second memory cell 125 storing a logical state "0" (e.g., 150 mV). During period 415, the pulses 420, 430, 440 can have a logical state "0."

[0168] In a method, the bit line controller 112 can store a charge through the bit line according to a voltage from the set of memory cells 125. As described above with respect to Figure 2 the computing capacitor bank 230, the capacitors of the computing capacitor bank 230 can have weighted capacitance values. Thus, each capacitor of the computing capacitor bank 230 can store a different amount of charge according to its capacitance value. For example, in response to a voltage corresponding to a logical state "1" applied through the bit line BL3 connected to the fourth memory cell used to store the MSB, the fourth capacitor can store a charge corresponding to 2 3 × C 单元 Meanwhile, in response to a voltage corresponding to a logical state "1" applied through another bit line BLO connected to the first memory cell used to store the MSB, the first capacitor can store a charge corresponding to 2 0 × C 单元 .

[0169] During period 425, the controller can configure or cause bit line controller 112 to perform charge sharing based on the sampled voltage during period 415. During period 425, the controller can generate a compute capacitor charge sharing enable pulse 420 having a logic state of “1” and provide pulse 420 to bit line controller 112. In response to compute capacitor charge sharing enable pulse 420 having a logic state of “1,” bit line controller 112 can couple each of the set of capacitors with the others of the set of capacitors such that the set of capacitors can share charge with one another. The amount of charge collectively stored can be indicative of or correspond to the stored multi-bit data. Assuming a set of memory cells 125 stores data

[1001] , the set of capacitors can collectively store a charge corresponding to 9xC 单元 . Assuming a set of memory cells 125 stores data

[0011] , the set of capacitors can collectively store a charge corresponding to 3xC 单元 . The set of memory cells 125 can have or generate a voltage corresponding to the total charge shared. In an aspect, the voltage at the set of memory cells 125 can be represented as follows:

[0170]

[0171] where V is the voltage at the set of capacitors, Q 总 is the total charge shared by the set of capacitors, and N is the number of bits of the multi-bit data. During period 425, pulses 410, 430, 440 can have a logic state of “0.”

[0172] During period 435, the controller can configure or cause bit line controller 112 to amplify the voltage at the set of capacitors of compute capacitor set 230. During period 435, the controller can generate a voltage amplifier enable pulse 430 having a logic state of “1” and provide pulse 430 to bit line controller 112. In response to voltage amplifier enable pulse 430 having a logic state of “1,” bit line controller 112 (e.g., voltage amplifier 240) can amplify the voltage at the set of capacitors. In an aspect, bit line controller 112 performs voltage amplification based on a series charge pump boost. During period 435, pulses 410, 440 can have a logic state of “0” while pulses 420, 430 can have a logic state of “1.”

[0173] During period 445, the controller can configure or cause the bit line controller 112 to perform an analog-to-digital conversion. During period 445, the controller can generate the ADC enable pulse 440 having a logic state of "1" and provide the pulse 440 to the bit line controller 112. In response to the ADC enable pulse 440 having a logic state of "1", the bit line controller 112 (e.g., the ADC 250) can perform an analog-to-digital conversion on the amplified voltage obtained during period 435. In an aspect, the amplified voltage allows the analog-to-digital conversion to be performed in an accurate manner. During period 445, the pulse 410 can have a logic state of "0" and the pulses 420, 430, 440 can have a logic state of "1".

[0174] Figure 5 To illustrate a circuit diagram 500 of the compute capacitor bank 230A and the voltage amplifier 240A according to an embodiment. In a configuration, the compute capacitor bank 230A is coupled to the bit lines BL0-BL3 to receive a voltage or a current corresponding to multi-bit data stored in a set of memory cells 125. In a configuration, the compute capacitor bank 230A generates an input voltage Vin at a common metal rail 510 according to the voltage or the current from the bit lines BL0-BL3. The compute capacitor bank 230A can provide the input voltage Vin to the voltage amplifier 240A. The voltage amplifier 240A can amplify the input voltage Vin to generate an output voltage Vout. The voltage amplifier 240A can provide the output voltage Vout to the ADC 250.

[0175] In some embodiments, the compute capacitor bank 230A is a circuit or a hardware element that can receive a voltage or a current corresponding to multi-bit data stored in a set of memory cells 125 and generate an input voltage Vin according to the received voltage or current. In some embodiments, the compute capacitor bank 230A includes a set of switches SB0A-SB3A, a set of switches SB0B-SB3B, and a set of capacitors CB0-CB3. The set of switches SB0A-SB3A and the set of switches SB0B-SB3B can be implemented as transistors or any components that can selectively couple two or more elements. The set of switches SB0A-SB3A can correspond to the set of switches SB0-SB3 in Figure 3 In some embodiments, the compute capacitor bank 230A includes more capacitors CB0-CB3 than the set of switches SB0-SB3 in Figure 5more, fewer, or different elements than shown in FIG. 6. In some embodiments, the compute capacitor bank 230A is replaced by different circuits or elements that can perform the functionality of the compute capacitor bank 230A disclosed herein. In one configuration, each switch (e.g., the Xth switch SBXA) includes a first electrode connected to a respective bit line (e.g., the Xth bit line BLX), and a second electrode connected to a first electrode of a corresponding capacitor (e.g., the Xth capacitor CBX). In one configuration, each switch (e.g., the Xth switch SBXB) includes a first electrode connected to the common metal rail 510, and a second electrode connected to a first electrode of a corresponding capacitor (e.g., the Xth capacitor CBX). In one configuration, each capacitor (e.g., the Xth capacitor CBX) includes a second electrode connected to the reference metal rail 530 at which a reference voltage (e.g., a ground voltage) can be provided.

[0176] In one aspect, the set of switches SB0A-SB3A and the set of switches SB0B-SB3B can be configured to sample voltages or currents at the bit lines BL0-BL3 and perform charge sharing to generate the input voltage Vin at the common metal rail 510. The set of switches SB0A-SB3A and the set of switches SB0B-SB3B can be operated or configured according to voltages or pulses from a controller (e.g., the timing controller 110). For example, in response to a voltage corresponding to a logic state of “1” applied to the gate electrodes of the set of switches SB0A-SB3A, each of the set of switches SB0A-SB3A can electrically couple a corresponding one of the bit lines BL0-BL3 to a first electrode of a corresponding one of the set of capacitors CB0-CB3. For example, in response to a voltage corresponding to a logic state of “0” applied to the gate electrodes of the set of switches SB0A-SB3A, each of the set of switches SB0A-SB3A can electrically decouple a corresponding one of the bit lines BL0-BL3 from a first electrode of a corresponding one of the set of capacitors CB0-CB3. Similarly, in response to a voltage corresponding to a logic state of “1” applied to the gate electrodes of the set of switches SB0B-SB3B, each of the set of switches SB0B-SB3B can electrically couple a first electrode of a corresponding one of the set of capacitors CB0-CB3 to the common metal rail 510. For example, in response to a voltage corresponding to a logic state of “0” applied to the gate electrodes of the set of switches SB0B-SB3B, each of the set of switches SB0B-SB3B can electrically decouple a first electrode of a corresponding one of the set of capacitors CB0-CB3 from the common metal rail 510.

[0177] In one aspect, the set of switches SB0A-SB3A and the set of switches SB0B-SB3B are configured differently to perform sampling and charge sharing. For example, the set of switches SB0A-SB3A can simultaneously couple bit lines BL0-BL3 to capacitors CB0-CB3, while the set of switches SB0B-SB3B can decouple capacitors CB0-CB3 from common metal rail 510 during time period 425. For example, the set of switches SB0B-SB3B can simultaneously couple capacitors CB0-CB3 to common metal rail, while the set of switches SB0A-SB3A can decouple bit lines BL0-BL3 from capacitors CB0-CB3 during time period 435. Thus, the set of capacitors CB0-CB3 can store charge according to voltages or currents at bit lines BL0-BL3 during time period 425. In addition, the set of capacitors CB0-CB3 can share charge to generate input voltage Vin at common metal rail 510 during time period 435.

[0178] In some embodiments, voltage amplifier 240A is a circuit or hardware element that can amplify input voltage Vin to generate output voltage Vout. In some embodiments, voltage amplifier 240A includes differential amplifier Al, capacitors Csl, Cs2, and a plurality of switches S3, S4, S5, S5A, S6, S6A, S7, S7A, S8, S8A. The plurality of switches S3, S4, S5, S5A, S6, S6A, S7, S7A, S8, S8A can be implemented as transistors or any elements that can selectively couple two or more elements. Capacitors Csl, Cs2 can have the same or different capacitance values. These elements can operate together to amplify input voltage Vin by series charge pump boosting to generate output voltage Vout. In some embodiments, voltage amplifier 240A is replaced by different circuits or different elements that can perform the functionality of voltage amplifier 240A described herein. In some embodiments, voltage amplifier 240A includes more, fewer, or different elements than those shown in FIG. 2B. In some embodiments, capacitor Cs2 can be shared with a portion of ADC 250 or a different element, or can be implemented as a portion of ADC 250 or a different element. Figure 5 In some embodiments, voltage amplifier 240A includes more, fewer, or different elements than those shown in FIG. 2B. In some embodiments, capacitor Cs2 can be shared with a portion of ADC 250 or a different element, or can be implemented as a portion of ADC 250 or a different element.

[0179] In one configuration, switch S3 includes a first electrode and a second electrode, the first electrode of switch S3 is connected to the common metal rail 510 of the computation capacitor bank 230A to receive the input voltage Vin, and the second electrode of switch S3 is connected to a first input port (e.g., the “+” input port) of the differential amplifier Al. In one configuration, switch S4 includes a first electrode and a second electrode, the first electrode of switch S4 is connected to the first input port (e.g., the “+” input port) of the differential amplifier Al, and the second electrode of switch S4 is connected to the first electrode of switch S6A. In one configuration, the differential amplifier Al includes a second input port (e.g., the “-” input port) connected to an output port of the differential amplifier Al, such that the differential amplifier Al is configured or operates as a unity gain buffer.

[0180] In one configuration, the first electrode of switch S6 is connected to the output port of the differential amplifier Al, and the second electrode of switch S6 is connected to the first electrode of the capacitor Csl. In one configuration, the first electrode of switch S5A is connected to the first electrode of the capacitor Csl, and the second electrode of switch S5A is connected to the reference metal rail 530. In one configuration, the first electrode of switch S5 is connected to the output port of the differential amplifier Al, and the second electrode of switch S5 is connected to the second electrode of the capacitor Csl. In one configuration, the second electrode of switch S6A is connected to the second electrode of the capacitor Csl.

[0181] In one configuration, the first electrode of switch S8 is connected to the output port of the differential amplifier Al, and the second electrode of switch S8 is connected to the first electrode of the capacitor Cs2. In one configuration, the first electrode of switch S7A is connected to the first electrode of the capacitor Cs2, and the second electrode of switch S7A is connected to the reference metal rail 530. In one configuration, the first electrode of switch S7 is connected to the output port of the differential amplifier Al, and the second electrode of switch S7 is connected to the second electrode of the capacitor Cs2. In one configuration, the first electrode of switch S8A is connected to the output metal rail at which the output voltage Vout can be provided, and the second electrode of switch S8A is connected to the second electrode of the capacitor Cs2.

[0182] In this configuration, the plurality of switches S3, S4, S5, S5A, S6, S6A, S7, S7A, S8, S8A can receive a voltage or a pulse from a controller (e.g., the timing controller 110) and amplify the input voltage Vin through a series of charge pumps to generate an output voltage Vout. In an aspect, the set of switches S3, S4 can be variously configured to selectively couple a first input port (e.g., the “+” input port) of the differential amplifier Al to i) the set of computational capacitors 230A or ii) the switch S6A. In an aspect, the set of switches S6, S5A can be variously configured to selectively couple a first electrode of the capacitor Csl to i) an output port of the differential amplifier Al or ii) the reference metal rail 530. In an aspect, the set of switches S5, S6A can be variously configured to selectively couple a second electrode of the capacitor Csl to i) the output port of the differential amplifier Al or ii) the switch S4. In an aspect, the set of switches S8, S7A can be variously configured to selectively couple a first electrode of the capacitor Cs2 to i) the output port of the differential amplifier Al or ii) the reference metal rail 530. In an aspect, the set of switches S7, S8A can be variously configured to selectively couple a second electrode of the capacitor Cs2 to i) the output port of the differential amplifier Al or ii) the output metal rail. Further details are provided below with respect to Figure 6 Exemplary operations of the set of computational capacitors 230A and the voltage amplifier 240A are provided.

[0183] Figure 6 A timing diagram 600 illustrating exemplary operations of the set of computational capacitors 230A and the voltage amplifier 240A according to an embodiment is shown. In an aspect, a controller (e.g., the timing controller 110) can generate and apply different pulses P0, PI, P3, P5, P6, P5A, P6A, P4, P7, P8, P8A to the switches of the set of computational capacitors 230A and the voltage amplifier 240A. In an approach, the pulse P0 is applied to the gate electrodes of the switches SB0A-SB3A and the pulse PI is applied to the gate electrodes of the switches SB0B-SB3B. In an approach, the pulse P3 is applied to the gate electrode of the switch S3; the pulse P5 is applied to the gate electrode of the switch S5; the pulse P6 is applied to the gate electrode of the switch S6; the pulse P5A is applied to the gate electrode of the switch S5A; the pulse P6A is applied to the gate electrode of the switch S6A; the pulse P8 is applied to the gate electrode of the switch S8; and the pulse P8A is applied to the gate electrode of the switch S8A. In an approach, the pulse P7 is applied to the gate electrodes of the switches S7 and S7A.

[0184] During period 415, pulse PO can have a first state (e.g., a logic state of "1") to sample a voltage or current at bit lines BL0-BL3. Responsive to pulse PO having the first state (e.g., a logic state of "1"), the set of switches SB0A-SB3A can be enabled to electrically couple bit lines BL0-BL3 to capacitors CB0-CB3, respectively. Responsive to pulse PI having a second state (e.g., a logic state of "0"), the set of switches SB0B-SB3B can be disabled to electrically decouple common metal rail 510 from capacitors CB0-CB3. Accordingly, the set of capacitors CB0-CB3 can store charge corresponding to a voltage or current corresponding to multi-bit data stored at the set of memory cells 125. During period 415, pulses P3, P5, P6, P5A, P6A, P4, P7, P8, P8A can have the second state (e.g., a logic state of "0") such that other switches S3, S5, S6, S5A, S6A, S4, S7, S7A, S8, S8A can be disabled.

[0185] During period 425, pulse PI can have a first state (e.g., a logic state of "1") and pulse PO can have a second state (e.g., a logic state of "0") to perform charge sharing. Responsive to pulse PI having the first state (e.g., a logic state of "1"), the set of switches SB0B-SB3B can be enabled to electrically couple common metal rail 510 to capacitors CB0-CB3. Responsive to pulse PO having the second state (e.g., a logic state of "0"), the set of switches SB0A-SB3A can be disabled to electrically decouple bit lines BL0-BL3 from capacitors CB0-CB3. Accordingly, the set of capacitors CB0-CB3 can be electrically coupled to one another and share stored charge. The set of capacitors CB0-CB3 can have or generate input voltage Vin at common metal rail 510 according to the shared charge, as described above with respect to equation (1). During period 425, pulses P3, P5, P6, P5A, P6A, P4, P7, P8, P8A can have the second state (e.g., a logic state of "0") such that other switches S3, S5, S6, S5A, S6A, S4, S7, S7A, S8, S8A can be disabled.

[0186] During period 435A, pulse P3 can have a first state (e.g., logic state “1”), while pulse PI can have a first state (e.g., logic state “1”). Responsive to pulse P3 having a first state (e.g., logic state “1”) and pulse PI having a first state (e.g., logic state “1”), switches S3 and the set of switches SB0B-SB3B can be enabled to electrically couple the set of capacitors CB0-CB3 to the first input port of differential amplifier Al. Accordingly, differential amplifier Al, which is configured or operated as a unity-gain buffer, can receive input voltage Vin at the first input port from the set of capacitors CB0-CB3 or generate or output input voltage Vin at its output port. During period 435A, pulses PO, P4, P7, P8, P8A can have a second state (e.g., logic state “0”), such that other switches SB0A-SB3A, S4, S7, S7A, S8, S8A can be disabled.

[0187] During a first sub-period 435A’ within period 435A, pulses P5, P5A can have a first state (e.g., logic state “1”), while pulses P6, P6A can have a second state (e.g., logic state “0”). Responsive to pulses P5, P5A having a first state (e.g., logic state “1”), switches S5, S5A can be enabled to electrically couple a first electrode of capacitor Csl to reference metal rail 530 and a second electrode of capacitor Csl to the output port of differential amplifier Al. Responsive to pulses P6, P6A having a second state (e.g., logic state “0”), switches S6, S6A can be disabled to electrically decouple the first electrode of capacitor Csl from the output port of differential amplifier Al and to electrically decouple the second electrode of capacitor Csl from switch S4. Accordingly, capacitor Csl can store a charge corresponding to input voltage Vin during the first sub-period 435A’.

[0188] During a first sub-period 435A" within the period 435A, the pulses P6, P6A can have a first state (e.g., a logic state of "1") and the pulses P5, P5A can have a second state (e.g., a logic state of "0"). Responsive to the pulses P6, P6A having the first state (e.g., a logic state of "1"), the switches S6, S6A can be enabled to electrically couple the first electrode of the capacitor Csl to the output port of the differential amplifier Al and to electrically couple the second electrode of the capacitor Csl to the switch S4. Responsive to the pulses P5, P5A having the second state (e.g., a logic state of "0"), the switches S5, S5A can be disabled to electrically decouple the first electrode of the capacitor Csl from the reference metal rail 530 and to electrically decouple the second electrode of the capacitor Csl from the output port of the differential amplifier Al. In one aspect, the input voltage Vin is applied to the first electrode of the capacitor Csl during the second sub-period 435A". At the same time, the switch S4 is disabled during the second sub-period 435A" such that the second electrode of the capacitor Csl is electrically floated. Because the capacitor Csl holds a charge, the voltage at the second electrode of the capacitor Csl can increase to generate or obtain a first amplified voltage through charge pumping boosting during the second sub-period 435A". For example, the voltage at the second electrode of the capacitor Csl can be doubled during the second sub-period 435A".

[0189] During the period 435B, the pulses P4 can have a first state (e.g., a logic state of "1") and the pulses P6A can have a first state (e.g., a logic state of "1") and the pulses P3 can have a second state (e.g., a logic state of "0"). Responsive to the pulses P4, P6A having the first state (e.g., a logic state of "1"), the switches S4, S6A can be enabled to electrically couple the first input port of the differential amplifier Al to the second electrode of the capacitor Csl. Responsive to the pulses P3 having the second state (e.g., a logic state of "0"), the switch S3 can be disabled to electrically decouple the compute capacitor bank 230A from the first input port of the differential amplifier Al. Thus, the differential amplifier Al configured or operated as a unity gain buffer can receive the first amplified voltage at the first input port from the first capacitor Csl or output the first amplified voltage at its output port. During the period 435B, the pulses P0, PI, P5, P6, P5A, P8A can have the second state (e.g., a logic state of "0") such that the other switches SB0A-SB3A, SB0B-SB3B, S5, S6, S5A, S8A can be disabled.

[0190] During a first sub-period 435B' within the period 435B, the pulse P7 can have a first state (e.g., a logic state of "1") and the pulse P8 can have a second state (e.g., a logic state of "0"). Responsive to the pulse P7 having the first state (e.g., a logic state of "1"), the switches S7, S7A can be enabled to electrically couple the first electrode of the capacitor Cs2 to the reference metal rail 530 and to electrically couple the second electrode of the capacitor Cs2 to the output port of the differential amplifier Al. Responsive to the pulse P8 having the second state (e.g., a logic state of "0"), the switch S8 can be disabled to electrically decouple the first electrode of the capacitor Cs2 from the output port of the differential amplifier Al. Thus, the capacitor Cs2 can store a charge corresponding to the first amplified voltage during the first sub-period 435B'.

[0191] During a second sub-period 435B" within the period 435B, the pulse P8 can have a first state (e.g., a logic state of "1") and the pulse P7 can have a second state (e.g., a logic state of "0"). Responsive to the pulse P8 having the first state (e.g., a logic state of "1"), the switch S8 can be enabled to electrically couple the first electrode of the capacitor Cs2 to the output port of the differential amplifier Al. Responsive to the pulse P7 having the second state (e.g., a logic state of "0"), the switches S7, S7A can be disabled to electrically decouple the first electrode of the capacitor Cs2 from the reference metal rail 530 and to electrically decouple the second electrode of the capacitor Cs2 from the output port of the differential amplifier Al. During the second sub-period 435B", the switch S8A can be disabled to electrically decouple the second electrode of the capacitor Cs2 from the output metal rail, such that the second electrode of the capacitor Cs2 can be electrically floating. In one aspect, the first amplified voltage is applied to the first electrode of the capacitor Cs2 during the second sub-period 435B". Because the second electrode of the capacitor Cs2 is electrically floating while the capacitor Cs2 retains the charge corresponding to the first amplified voltage, the voltage at the second electrode of the capacitor Cs2 can be increased by an additional charge pump boost to obtain the output voltage Vout during the second sub-period 435B". For example, the voltage at the second electrode of the capacitor Cs2 can be doubled during the second sub-period 435B", such that the output voltage Vout at the second electrode of the capacitor Cs2 can be four times the input voltage Vin.

[0192] During period 445, pulse P8A can have a first state (e.g., a logic state of "1"). In response to pulse P8A having the first state, the second electrode of capacitor Cs2 can be electrically coupled to the output metal rail. Meanwhile, pulses P0, PI, P3, P5, P6, P5A, P6A, P4, P7, P8 can have a second state (e.g., a logic state of "0"), such that switches SB0A-SB3A, SB0B-SB3B, S3, S5, S6, S5A, S6A, S4, S7, S7A, S8 can be disabled. Thus, during period 445, output voltage Vout can be provided to ADC 250 through the output metal rail, and analog-to-digital conversion or other processes can be performed in accordance with output voltage Vout during period 445.

[0193] Figure 7 To illustrate an amplifier A2 for reducing charge due to parasitic capacitance of switches SB0A-SB3A connected to a computing capacitor CB0-CB3, a circuit diagram 700 is shown in accordance with an embodiment. In some embodiments, switches SB0A-SB3A, SB0B-SB3B can be implemented as transistors (e.g., N-type transistors). Switches SB0A-SB3A can have parasitic capacitance Cp. The parasitic capacitance Cp can store charge, which can degrade linearity of an input voltage Vin at common metal rail 510. In one configuration, switch S0 and amplifier A2 can be implemented to reduce charge due to parasitic capacitance of switches SB0A-SB3A.

[0194] In one configuration, the second electrode of each capacitor (e.g., the Xth capacitor CBX) is connected to the first electrode of a switch SO and the first input port (e.g., the "-" input port) of an amplifier A2, where the second electrode of the switch SO is connected to a reference metal rail 530 at which a reference voltage (e.g., a ground voltage) is provided. In one configuration, the second input port (e.g., the "+" input port) of the amplifier A2 is connected to the reference metal rail 530, where the output port of the amplifier A2 is connected to the common metal rail 510. The switch SO can be configured according to a voltage or a pulse from a controller (e.g., the timing controller 110). For example, a pulse having a first state (e.g., a logic state "1") is applied to the gate electrode of the switch SO during a time period 415, where a pulse having a second state (e.g., a logic state "0") is applied to the gate electrode of the switch SO during a time period 425. In response to the pulse having the first state (e.g., the logic state "1"), the switch SO can be enabled to electrically couple the second electrodes of the capacitors CB0-CB3 to the reference metal rail 530. Accordingly, in response to the pulse having the first state, the first input port and the second input port of the amplifier A2 can be electrically coupled to the reference metal rail 530, such that the amplifier A2 can be disabled. In response to the pulse having the second state (e.g., the logic state "0"), the switch SO can be disabled to electrically decouple the second electrodes of the capacitors CB0-CB3 from the reference metal rail 530. When the first input port and the second input port of the amplifier A2 are decoupled from each other, the amplifier A2 can sense the charges stored by the parasitic capacitances of the switches SB0A-SB3A and adjust the input voltage Vin at the common metal rail 510 according to the sensed charges. By adjusting the input voltage Vin according to the charges stored by the parasitic capacitances, the linearity of the input voltage Vin at the common metal rail 510 can be improved.

[0195] Figure 8 A circuit diagram 800 of the computing capacitor bank 230B and the voltage amplifier 240B is illustrated according to one embodiment. The configuration of the computing capacitor bank 230B and the voltage amplifier 240B is similar to that of the computing capacitor bank 230A and the voltage amplifier 240A of Figure 5 , except that the computing capacitor bank 230B includes a switch SO and the voltage amplifier 240B includes switches S2AA, S2AB, S2B. The switches SO, S2AA, S2AB, S2B can be implemented as transistors or any elements that can selectively couple two or more elements. Thus, the detailed description of the repetitive parts is omitted herein for brevity.

[0196] In one configuration, switch SO includes a first electrode connected to reference metal rail 530, and a second electrode connected to a second electrode of capacitor CB0-CB3. In one configuration, switch S2AB includes a first electrode connected to a second electrode of switch SO, and a second electrode connected to an output port of differential amplifier Al. In one configuration, switch S2B includes a first electrode connected to i) an output port of differential amplifier Al and ii) a second input port (e.g., a "-" input port) of differential amplifier Al. In one configuration, switch S2AA includes a first electrode connected to common metal rail 510, and a second electrode connected to a second input port of differential amplifier Al. In one aspect, switches SO, S2AA, S2AB, S2B can be configured or operated according to a voltage or pulse from a controller (e.g., timing controller 110) to reduce charge stored by the parasitic capacitance of switches SB0A-SB3A. Details are provided below with respect to Figure 9 An exemplary operation of capacitor bank 230B and voltage amplifier 240B is provided.

[0197] Figure 9 A timing diagram 900 is provided to illustrate an exemplary operation of capacitor bank 230B and voltage amplifier 240B according to one embodiment. Timing diagram 900 is similar to timing diagram 600 in Figure 6 except for the addition of pulses P2A, P2B. Thus, detailed descriptions of repeated portions are omitted herein for brevity. In some embodiments, a controller (e.g., timing controller 110) generates pulses P2A, P2B. The controller can provide pulse P2A to the gate electrodes of switches S2AA, S2AB, and provide pulse P2B to the gate electrode of switch S2B. The controller can also provide pulse PO to the gate electrode of switch SO. According to pulses PO, P2A, P2B, switches SO, S2AA, S2AB, S2B can be configured to reduce charge due to the parasitic capacitance of switches SB0A-SB3A.

[0198] During period 415, pulse P0 can have a first state (e.g., a logic state of "1") and pulses P2A, P2B can have a second state (e.g., a logic state of "0"). In response to pulse P0 having the first state, switch SO can electrically couple the second electrodes of capacitors CB0-CB3 to reference metal rail 530. In response to pulse P2A having the second state, switch S2AA can electrically decouple common metal rail 510 from the second input port of differential amplifier Al and switch S2AB can electrically decouple the output port of differential amplifier Al from the second electrodes of capacitors CB0-CB3. In response to pulse P2B having the second state, switch S2B can electrically decouple the second input port of differential amplifier Al from the output port of differential amplifier Al. In one aspect, during period 415, enabling switch SO allows capacitors CB0-CB3 to sample the voltage or current corresponding to the multi-bit data stored in the set of memory cells 125. Additionally, during period 415, switches S3, S4, S2AA, S2B, S2AB are disabled so that no input is provided to differential amplifier Al.

[0199] During period 425, pulse P2A can have a first state (e.g., a logic state of "1") and pulses P0, P2B can have a second state (e.g., a logic state of "0"). In response to pulse P2A having the first state, switch S2AA can electrically couple common metal rail 510 to the second input port of differential amplifier Al and switch S2AB can electrically couple the output port of differential amplifier Al to the second electrodes of capacitors CB0-CB3. In response to pulse P0 having the second state, switch SO can electrically decouple the second electrodes of capacitors CB0-CB3 from reference metal rail 530. In response to pulse P2B having the second state, switch S2B can electrically decouple the second input port of differential amplifier Al from the output port of differential amplifier Al. In one aspect, during period 425, disabling switch SO allows the second electrodes of capacitors CB0-CB3 to electrically float during charge sharing. Additionally, during period 425, amplifier Al can subtract the charge stored by the parasitic capacitances of switches SB0A-SB3A from the shared charge.

[0200] During time period 435A, pulse P2B can have a first state (e.g., logic state "1") while pulses P0, P2A can have a second state (e.g., logic state "0"). In response to pulse P2B having the first state, switch S2B can electrically couple the second input port of differential amplifier Al to the output port of differential amplifier Al. In response to pulse P0 having the second state, switch S0 can electrically decouple the second electrode of capacitors CB0-CB3 from reference metal rail 530. In response to pulse P2A having the second state, switch S2AA can electrically decouple common metal rail 510 from the second input port of differential amplifier Al and switch S2AB can electrically decouple the output port of differential amplifier Al from the second electrode of capacitors CB0-CB3. In one aspect, during time period 435A, switch S2B is enabled and switches S2AA, S2AB are disabled, such that differential amplifier Al can be configured or operated as a unity gain buffer.

[0201] Advantageously, a single differential amplifier Al can be properly configured or set to perform both the series charge pump boosting and the compensation of charge due to parasitic charge. Thus, an area efficiency improvement can be achieved because multiple amplifiers can not be implemented.

[0202] Figure 10 A flowchart of a method 1000 of amplifying a voltage of an input signal according to some embodiments. Method 1000 can be performed by bit line controller 112. Figure 1 In some embodiments, method 1000 is performed by other entities (e.g., voltage amplifiers). In some embodiments, method 1000 includes more, fewer, or different operations than those shown in FIG. 10. Figure 10

[0203] At operation 1010, bit line controller 112 generates an input voltage Vin at a set of capacitors (e.g., CB0...CBN-1). In one approach, the capacitors of a compute capacitor bank 230 including the set of capacitors can sample a voltage or current corresponding to multi-bit data stored at the set of memory cells 125. Thus, the capacitors of compute capacitor bank 230 can store charges corresponding to the sampled voltage or current. In one aspect, the capacitors of compute capacitor bank 230 can have weighted capacitance values. Thus, each capacitor of compute capacitor bank 230 can store a different amount of charge according to its capacitance value. Bit line controller 112 can generate or obtain input voltage Vin through charge sharing. For example, bit line controller 112 can configure or cause the set of capacitors (e.g., CB0...CBN-1) of compute capacitor bank 230 to share charges. The number of charges collectively stored can indicate or correspond to the multi-bit data stored. If the set of memory cells 125 stores data

[1001] , the set of capacitors can collectively store charges corresponding to 9xC.​单元 of charge. If a set of memory cells 125 stores data

[0011] , then the set of capacitors can collectively store a charge corresponding to 3xC 单元 An input voltage Vin can correspond to the amount of charge collectively stored, as shown in equation (1).

[0204] In operation 1020, the bit line controller 112 compensates for the charge due to the parasitic capacitance to obtain a first charge. The bit line controller 112 can implement an amplifier (e.g., differential amplifier Al) to reduce the charge stored by the parasitic capacitance of the switches (e.g., SBOA-SB3A). By compensating for the charge due to the parasitic capacitance, signal linearity can be improved.

[0205] In operation 1030, the bit line controller 112 stores the first charge through a first capacitor (e.g., Csl) to obtain a first voltage. For example, the differential amplifier Al configured as a unity gain buffer can receive an input voltage Vin at a first input port (e.g., the "+" input port) from the set of capacitors (e.g., CBO...CBN-I) of the set of compute capacitors 230 and generate or output the input voltage Vin at an output port. Meanwhile, switches S5, S5A can be enabled and switches S6, S6A can be disabled such that a reference voltage (e.g., a ground voltage) is applied to a first electrode of the capacitor Csl and the input voltage from the differential amplifier Al is applied to a second electrode of the capacitor Csl. Thus, the capacitor Csl can store a first charge corresponding to the input voltage Vin.

[0206] In operation 1040, the bit line controller 112 amplifies the first voltage according to the first charge. In one approach, the bit line controller 112 amplifies the first voltage according to the first charge through a charge pump. For example, switches S5, S5A can be disabled and switches S6, S6A can be enabled such that the input voltage Vin of the differential amplifier Al is applied to the first electrode of the capacitor Csl and the second electrode of the capacitor Csl is electrically floated. Because the capacitor Csl holds the first charge, the voltage at the first electrode of the capacitor Csl can increase to the input voltage Vin, the voltage at the second electrode can increase to obtain a first amplified voltage. The first amplified voltage at the second electrode of the capacitor Csl can be twice the input voltage Vin.

[0207] In operation 1050, the bit line controller 112 stores a second charge through a second capacitor (e.g., Cs2) to obtain a third voltage. For example, the differential amplifier Al is configured to receive the first amplified voltage from the first capacitor Cs1 at the first input port instead of receiving the input voltage Vin from the set of capacitors (e.g., CBO...CBN-I) of the computation capacitor bank 230, and to generate or output the first amplified voltage at the output port. Meanwhile, the switches S7, S7A can be enabled, and the switches S8, S8A can be disabled, such that a reference voltage (e.g., ground voltage) is applied to the first electrode of the capacitor Cs2, and the first amplified voltage from the differential amplifier Al is applied to the second electrode of the capacitor Cs2. Accordingly, the capacitor Cs2 can store a second charge corresponding to the first amplified voltage. The capacitor Cs2 can have a third voltage (or the first amplified voltage) at the second electrode of the capacitor Cs2.

[0208] In operation 1060, the bit line controller 112 amplifies the third voltage according to the second charge. In one approach, the bit line controller 112 amplifies the third voltage according to the second charge through an additional charge pump. For example, the switches S7, S7A, S8A can be disabled, and the switch S8 can be enabled, such that the first amplified voltage from the differential amplifier Al is applied to the first electrode of the capacitor Cs2, and the second electrode of the capacitor Cs2 is electrically floated. Because the capacitor Cs2 holds the second charge while the voltage at the first electrode of the capacitor Cs2 increases to the first amplified voltage, the voltage at the second electrode can increase to obtain a second amplified voltage or an output voltage Vout. The output voltage at the second electrode of the capacitor Cs2 can be four times the input voltage Vin.

[0209] Advantageously, the voltage amplifier 240 can achieve several advantages. In one aspect, accurate voltage amplification can be achieved by implementing a differential amplifier, two capacitors, and a set of switches. In one aspect, the voltage amplifier 240 can implement two capacitors for series charge pump boosting, such that many capacitors (e.g., three or more) of the voltage amplifier can be omitted. By reducing the number of implemented capacitors, an improvement in area efficiency can be achieved, and the SNR can be improved. Additionally, a single differential amplifier Al can be properly configured or set to perform both stage series charge boosting and compensate for charge due to parasitic charge, such that multiple amplifiers cannot be implemented. In one aspect, the differential amplifier Al is configured to operate as a unity gain buffer with a simple configuration, which can consume less power than a complex high gain amplifier (e.g., an operational amplifier).

[0210] Reference will now be made to Figure 11FIG. 11 illustrates an exemplary block diagram of a computing system 1100, in accordance with some embodiments of the present disclosure. The computing system 1100 can be used by a circuit or layout designer of an integrated circuit design. As used herein, a "circuit" is an interconnection of electronic elements, such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor devices configured to perform a required functionality. The computing system 1100 includes a host device 1105 associated with a memory device 1110. The host device 1105 can be configured to receive input from one or more input devices 1115 and provide output to one or more output devices 1120. The host device 1105 can be configured to communicate with the memory device 1110, the input devices 1115, and the output devices 1120 via appropriate interfaces 1125A, 1125B, and 1125C, respectively. The computing system 1100 can be implemented in various computing devices, such as a computer (e.g., a desktop computer, a notebook computer, a server, a data center, etc.), a tablet computer, a personal digital assistant, a mobile device, other handheld or portable devices, or any other computing unit suitable for performing schematic and / or layout design using the host device 1105.

[0211] The input devices 1115 can include any of a variety of input technologies, such as a keyboard, a stylus, a touch screen, a mouse, a trackball, a keypad, a microphone, voice recognition, motion recognition, a remote controller, an input port, one or more buttons, dials, levers, and any other input peripheral device associated with the host device 1105 that allows an external source, such as a user (e.g., a circuit or layout designer), to input information (e.g., data) into the host device and send instructions to the host device. Similarly, the output devices 1120 can include a variety of output technologies, such as an external memory, a printer, a speaker, a display, a microphone, a light emitting diode, a headphone, a video element, and any other output peripheral device configured to receive information (e.g., data) from the host device 1105. The "data" input into and / or output from the host device 1105 can include a variety of textual data, circuit data, signal data, semiconductor device data, graphical data, combinations of the foregoing, or other types of analog and / or digital data suitable for processing using the computing system 1100.

[0212] The host device 1105 includes one or more processing units / processors, such as central processing unit ("CPU") cores 1130A-1130N or is associated with one or more processing units / processors. The CPU cores 1130A-1130N can be implemented as an application specific integrated circuit ("ASIC"), a field programmable gate array ("FPGA"), or any other kind of processing unit. Each of the CPU cores 1130A-1130N can be configured to execute instructions for running one or more applications of the host device 1105. In some embodiments, the instructions and data for running the one or more applications can be stored within the memory device 1110. The host device 1105 can also be configured to store results of running the one or more applications within the memory device 1110. Thus, the host device 1105 can be configured to request the memory device 1110 to perform various operations. For example, the host device 1105 can request the memory device 1110 to read data, write data, update or delete data, and / or perform administrative or other operations. One such application that the host device 1105 can be configured to run is a standard cell application 1135. The standard cell application 1135 can be part of a computer-aided design or electronic design automation software suite that can be used by a user of the host device 1105 to use, generate, or modify standard cells of a circuit. In some embodiments, the instructions for performing or running the standard cell application 1135 can be stored within the memory device 1110. The standard cell application 1135 can be executed by one or more of the CPU cores 1130A-1130N using instructions associated with the standard cell application from the memory device 1110. In an example, the standard cell application 1135 allows a user to utilize pre-generated schematics and / or circuit designs of the memory system 100, portions of the memory system 100, or the voltage amplifier 240 to assist in integrated circuit design. After the layout design of the integrated circuit is complete, a plurality of integrated circuits, including the memory system 100, portions of the memory system 100, or the voltage amplifier 240, for example, can be manufactured by a fabrication facility according to the layout design.

[0213] Still referring to Figure 11Memory device 1110 includes a memory controller 1140 configured to read data from and write data to the memory array 1145. Memory array 1145 can include a variety of volatile and / or nonvolatile memory. For example, in some embodiments, memory array 1145 can include a NAND flash memory core. In other embodiments, memory array 1145 can include a NOR flash memory core, an SRAM core, a Dynamic Random Access Memory (DRAM) core, a Magnetoresistive Random Access Memory (MRAM) core, a Phase Change Memory (PCM) core, a Resistive Random Access Memory (ReRAM) core, a 3D XPoint memory core, a ferroelectric random-access memory (FeRAM) core, and other types of memory cores suitable for use in a memory array. The memories within memory array 1145 can be controlled independently by memory controller 1140. In other words, memory controller 1140 can be configured to communicate with each memory within memory array 1145 independently. By communicating with memory array 1145, memory controller 1140 can be configured to read data from or write data to the memory array in response to instructions received from host device 1105. Although shown as part of memory device 1110, in some embodiments, memory controller 1140 can be part of host device 1105 or another element of computing system 1100 and associated with a memory device. Memory controller 1140 can be implemented as software, hardware, firmware, or logic circuits of any of the above to perform the functions described herein. For example, in some embodiments, memory controller 1140 can be configured to retrieve instructions associated with standard cell application 1135 and stored in memory array 1145 of memory device 1110 upon receiving a request from host device 1105.

[0214] It should be understood, Figure 11Only some elements of the computing system 1100 are illustrated and described. However, the computing system 1100 can include other elements, such as different batteries and power sources, network interfaces, routers, switches, external memory systems, controllers, etc. In general, the computing system 1100 can include any of the various hardware, software, and / or firmware elements necessary or considered desirable in performing the functions described herein. Similarly, the host device 1105, the input device 1115, the output device 1120, and the memory device 1110, including the memory controller 1140 and the memory array 1145, can include other hardware, software, and / or firmware elements considered necessary or desirable in performing the functions described herein.

[0215] One aspect of the specification relates to a voltage amplifier. In some embodiments, the voltage amplifier includes a first capacitor and a second capacitor. In some embodiments, the first capacitor includes a first electrode and a second electrode. In some embodiments, the second capacitor includes a second capacitor including a third electrode and a fourth electrode. In some embodiments, the voltage amplifier includes a differential amplifier including a first input port, a second input port, and an output port. In some embodiments, the second input port is coupled to the output port of the differential amplifier. In some embodiments, the voltage amplifier includes a first set of switches to selectively electrically couple the first electrode of the first capacitor to i) the output port of the differential amplifier or ii) a reference metal rail. In some embodiments, the voltage amplifier includes a second set of switches to selectively electrically couple the second electrode of the first capacitor to i) the output port of the differential amplifier or ii) the first input port of the differential amplifier. In some embodiments, the voltage amplifier includes a third set of switches to selectively electrically couple the third electrode of the second capacitor to i) the output port of the differential amplifier or ii) the reference metal rail. In some embodiments, the voltage amplifier includes a fourth set of switches to selectively electrically couple the fourth electrode of the second capacitor to i) the output port of the differential amplifier or ii) the input port of the device.

[0216] One aspect of the specification concerns a method of amplifying an input voltage. In some embodiments, the method includes generating, at a set of capacitors, an input voltage corresponding to input data. In some embodiments, the method includes storing, by a first capacitor, a first charge corresponding to the input voltage. In some embodiments, in accordance with the first charge, a first electrode of the first capacitor has a first voltage and a second electrode of the first capacitor has a second voltage. In some embodiments, the method includes amplifying, by the second voltage having by the second electrode of the first capacitor having the second voltage by increasing the first voltage having by the first electrode of the first capacitor, to obtain a third voltage. In some embodiments, the method includes storing, by a second capacitor, a second charge corresponding to the third voltage, wherein in accordance with the second charge, a third electrode of the second capacitor has a fourth voltage and a fourth electrode of the second capacitor has the third voltage. In some embodiments, the method includes amplifying, by the third voltage having by the fourth electrode of the second capacitor having the third voltage by increasing the fourth voltage having by the third electrode of the second capacitor.

[0217] One aspect of the specification concerns a system of amplifying an input voltage. In some embodiments, the system includes a set of capacitors and a voltage amplifier coupled to the set of capacitors. In one aspect, the voltage amplifier includes a first capacitor, a second capacitor, and a set of switches. In some embodiments, the system includes a controller coupled to the voltage amplifier. In some embodiments, the controller causes the set of switches to generate, at the set of capacitors, an input voltage corresponding to input data. In some embodiments, the controller causes the set of switches to store, in accordance with the input voltage, a first charge in the first capacitor to obtain a second voltage. In some embodiments, the controller causes the set of switches to amplify, in accordance with the first charge stored in the first capacitor, the second voltage to obtain a third voltage. In some embodiments, the controller causes the set of switches to store, in accordance with the third voltage, a second charge in the second capacitor. In some embodiments, the controller causes the set of switches to amplify, in accordance with the second charge stored in the second capacitor, the third voltage to obtain a fourth voltage.

[0218] The foregoing summary of some embodiments has been presented with the purpose of providing those skilled in the art with a brief introduction to the aspects of the disclosure. Those skilled in the art will appreciate that the disclosure can be used as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that various changes, substitutions, and alterations can be made thereto without departing from the spirit and scope of the disclosure.

Claims

1. A voltage amplifier, characterized by, comprises: a first capacitor comprising a first electrode and a second electrode; a second capacitor comprising a third electrode and a fourth electrode; a differential amplifier comprising a first input port, a second input port, and an output port, wherein the second input port is coupled to the output port of the differential amplifier; a first set of switches to selectively couple the first electrode of the first capacitor to i) the output port of the differential amplifier or ii) a reference metal rail; a second set of switches to selectively couple the second electrode of the first capacitor to i) the output port of the differential amplifier or ii) the first input port of the differential amplifier; a third set of switches to selectively couple the third electrode of the second capacitor to i) the output port of the differential amplifier or ii) the reference metal rail; and a fourth set of switches to selectively couple the fourth electrode of the second capacitor to i) the output port of the differential amplifier or ii) an input port of a device. The first set of switches comprises:

2. The voltage amplifier of claim 1, wherein, a first switch coupled between the first electrode of the first capacitor and the output port of the differential amplifier; and a second switch coupled between the first electrode of the first capacitor and the reference metal rail. The second set of switches comprises:

3. The voltage amplifier of claim 2, wherein, a third switch coupled between the second electrode of the first capacitor and the output port of the differential amplifier; and a fourth switch coupled between the second electrode of the first capacitor and the first input port of the differential amplifier. The third set of switches comprises:

4. The voltage amplifier of claim 3, wherein, a fifth switch coupled between the third electrode of the second capacitor and the output port of the differential amplifier; and a sixth switch coupled between the third electrode of the second capacitor and the reference metal rail. The fourth set of switches comprises:

5. The voltage amplifier of claim 4, wherein, a seventh switch coupled between the fourth electrode of the second capacitor and the output port of the differential amplifier; and an eighth switch coupled between the fourth electrode of the second capacitor and the input port of the device. Further comprising:

6. The voltage amplifier of claim 1, wherein, a fifth set of switches to selectively couple the first input port of the differential amplifier to i) a set of capacitors or ii) the second set of switches. Further comprising:

7. The voltage amplifier of claim 6, wherein, a controller coupled to the first set of switches, the second set of switches, the third set of switches, the fourth set of switches, and the fifth set of switches, wherein the controller is to perform the following steps: during a first time period, cause the fifth set of switches to couple the first input port of the differential amplifier to the set of capacitors; during a first sub-time period within the first time period, cause the first set of switches to couple the first electrode of the first capacitor to the reference metal rail; and during the first sub-time period, cause the second set of switches to couple the second electrode of the first capacitor to the output port of the differential amplifier. The controller is further to perform the following steps: during a second sub-time period within the first time period, cause the first set of switches to couple the first electrode of the first capacitor to the output port of the differential amplifier; and 8. The voltage amplifier of claim 7, wherein, during the second sub-time period, cause the second set of switches to couple the second electrode of the first capacitor to the first input port of the differential amplifier. ​ ​ During a second sub-period of the second period, causing the second set of switches to couple the second electrode of the first capacitor to the fifth set of switches.

9. The voltage amplifier of claim 8, wherein, wherein the controller is further configured to perform the following steps: During a second period after the first period, causing the fifth set of switches to couple the first input port of the differential amplifier to the second set of switches; During a third sub-period of the second period, causing the third set of switches to couple the third electrode of the second capacitor to the reference metal rail; and During the third sub-period, causing the fourth set of switches to couple the fourth electrode of the second capacitor to the output port of the differential amplifier.

10. The voltage amplifier of claim 9, wherein, wherein the controller is further configured to perform the following steps: During a fourth sub-period of the second period, causing the third set of switches to couple the third electrode of the second capacitor to the output port of the differential amplifier; and During the fourth sub-period, causing the fourth set of switches to couple the fourth electrode of the second capacitor to the input port of the device.

11. The voltage amplifier of claim 1, wherein, Further comprising: a fifth set of switches to selectively couple a first electrode of a set of capacitors to i) the first input port of the differential amplifier or ii) the second input port of the differential amplifier; and a sixth set of switches to selectively couple the output port of the differential amplifier to i) the second input port of the differential amplifier or ii) a second electrode of the set of capacitors.

12. The voltage amplifier of claim 1, wherein, wherein the device is a successive approximation register analog-to-digital converter, and wherein the second capacitor is shared with the successive approximation register analog-to-digital converter.

13. The voltage amplifier of claim 1, wherein, wherein the differential amplifier is a unity gain buffer.

14. A method of amplifying an input voltage, characterized by, Comprising: generating, at a set of capacitors, an input voltage corresponding to input data; storing, by a first capacitor, a plurality of first charges corresponding to the input voltage, wherein according to the plurality of first charges, a first electrode of the first capacitor has a first voltage and a second electrode of the first capacitor has a second voltage; amplifying, according to the plurality of first charges, the second voltage that the second electrode of the first capacitor has by increasing the first voltage that the first electrode of the first capacitor has to obtain a third voltage; storing, by a second capacitor, a plurality of second charges corresponding to the third voltage, wherein according to the plurality of second charges, a third electrode of the second capacitor has a fourth voltage and a fourth electrode of the second capacitor has the third voltage; and amplifying, according to the plurality of second charges, the third voltage that the fourth electrode of the second capacitor has by increasing the fourth voltage that the third electrode of the second capacitor has.

15. The method of claim 14, wherein, wherein storing, by the first capacitor, the plurality of first charges corresponding to the input voltage comprises the following steps: during a first period, causing an input set of switches to couple a first input port of a differential amplifier to the set of capacitors; during a first sub-period of the first period, causing a first set of switches to couple the first electrode of the first capacitor to a reference metal rail; and during a second sub-period of the first period, causing a second set of switches to couple the second electrode of the first capacitor to the first input port of the differential amplifier. During the first sub-period, a second set of switches is caused to couple the second electrode of the first capacitor to an output port of the differential amplifier.

16. The method of claim 15, wherein, wherein amplifying the second voltage that the second electrode of the first capacitor has comprises: During a second sub-period within the first period, the first set of switches is caused to couple the first electrode of the first capacitor to the output port of the differential amplifier; and During the second sub-period, the second set of switches is caused to couple the second electrode of the first capacitor to the input set of switches.

17. The method of claim 16, wherein, wherein storing, by the second capacitor, a plurality of second charges corresponding to the third voltage comprises: During a second period after the first period, the input set of switches is caused to couple the first input port of the differential amplifier to the second set of switches; During a third sub-period within the second period, a third set of switches is caused to couple the third electrode of the second capacitor to the reference metal rail; and During the third sub-period, a fourth set of switches is caused to couple the fourth electrode of the second capacitor to the output port of the differential amplifier.

18. The method of claim 17, wherein, wherein amplifying the third voltage that the fourth electrode of the second capacitor has comprises: During a fourth sub-period within the second period, the third set of switches is caused to couple the third electrode of the second capacitor to the output port of the differential amplifier; and During the fourth sub-period, the fourth set of switches is caused to couple the fourth electrode of the second capacitor to an input port of a device.

19. A system for amplifying an input voltage, characterized by comprises: a set of capacitors; a voltage amplifier coupled to the set of capacitors, wherein the voltage amplifier comprises: a differential amplifier; a first capacitor; a second capacitor; and a switching circuit comprising: a first switch coupled between an output port of the differential amplifier and a first electrode of the first capacitor; a second switch coupled between the output port of the differential amplifier and a second electrode of the first capacitor; a third switch coupled between the output port of the differential amplifier and a first electrode of the second capacitor; and a fourth switch coupled between the output port of the differential amplifier and a second electrode of the second capacitor; and a controller coupled to the voltage amplifier, wherein the controller causes the switching circuit to perform the following steps: generating an input voltage at the set of capacitors according to input data; turning on the first switch and storing a plurality of first charges in the first capacitor according to the input voltage to generate a second voltage at the first electrode of the first capacitor; turning on the second switch and amplifying the second voltage at the first electrode of the first capacitor according to the plurality of first charges stored in the first capacitor to obtain a third voltage; turning on the third switch and storing a plurality of second charges in the second capacitor according to the third voltage; and turning on the fourth switch and amplifying the third voltage according to the plurality of second charges stored in the second capacitor to obtain a fourth voltage.

20. The system of claim 19, wherein, wherein the controller is to cause the set of switches to perform the following steps: According to the input data, the set of capacitors is coupled to share charge stored in the set of capacitors to generate the input voltage at the set of capacitors; the set of capacitors is coupled to a first input port of the differential amplifier to obtain a plurality of first charges by reducing charge associated with parasitic capacitance from the shared charge; and the set of capacitors is coupled to a second input port of the differential amplifier to store the plurality of first charges in the first capacitor.

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