Port delay constraint method, device, electronic device, and storage medium

Abstract

A method, device, electronic device, and storage medium for constraining port delay. The method for constraining port delay includes: obtaining all ports in multiple modules, wherein all ports include multiple first ports; for each of the multiple first ports: obtaining N sequential logic devices corresponding to the first port and module clock information corresponding to the module to which the first port belongs; based on the N sequential logic devices and the module clock information, determining at least one clock object associated with the first port and at least one object information corresponding to at least one clock object; determining the port type of the first port; and setting the port delay of the first port according to the port type, at least one clock object, and at least one object information. The method for constraining port delay can automatically set complete port constraints for the ports of each module based on the design itself, saving iteration time.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a port delay constraint method, a port delay constraint device, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] With the improvement of integrated circuit technology and chip performance, the scale of integrated circuit design is getting larger and larger. When developing and designing large-scale integrated circuits, in order to increase the speed of design and physical implementation and reduce version iteration time, the design circuit is generally cut into smaller modules for processing. In the design and implementation process of different modules, in order to ensure the correctness of chip functions, the timing of the module needs to meet the design requirements. Usually, the timing of the module mainly includes two aspects: module internal timing and module port timing. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a port delay constraint method, which is applied to the design of an integrated circuit, wherein the integrated circuit includes multiple modules, each module includes at least one sequential logic device and at least one port, and the method includes: obtaining all ports in the multiple modules, wherein the all ports include multiple first ports; for each first port in the multiple first ports: obtaining N sequential logic devices corresponding to the first port and module clock information corresponding to the module to which the first port belongs, wherein each of the N sequential logic devices is directly electrically connected to the first port, or each of the sequential logic devices is electrically connected to the first port through at least one combinational logic device, and N is a positive integer; based on the N sequential logic devices and the module clock information, determining at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object; determining the port type of the first port; and setting the port delay of the first port according to the port type, the at least one clock object and the at least one object information.

[0004] For example, in at least one embodiment of the present disclosure, a port delay constraint method is provided, in which N sequential logic devices corresponding to the first port are obtained, including: in response to the first port not being used for inputting a clock signal, determining the N sequential logic devices from at least one sequential logic device included in a module to which the first port belongs.

[0005] For example, in at least one embodiment of the present disclosure, a method for constraining port delay is provided, in which module clock information corresponding to the module to which the first port belongs is obtained, including: determining at least one sequential logic device included in the module to which the first port belongs; obtaining at least one device clock information corresponding one-to-one to the at least one sequential logic device, wherein the module clock information includes the at least one device clock information.

[0006] For example, in at least one embodiment of the present disclosure, a port delay constraint method is provided, in which at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object are determined based on the N sequential logic devices and the module clock information, including: based on the module clock information, determining N device clock information corresponding one-to-one to the N sequential logic devices; and according to the N device clock information, determining the at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object.

[0007] For example, in at least one embodiment of the present disclosure, a port delay constraint method is provided, in which each device clock information includes trigger edge information, and based on the N device clock information, the at least one clock object associated with the first port and the at least one object information corresponding to the at least one clock object are determined, including: determining N clock objects based on the N device clock information; determining the at least one clock object from the N clock objects, wherein the at least one clock object is different from each other; for each clock object in the at least one clock object: determining at least one trigger edge information corresponding to each clock object based on the N device clock information, and determining the phase information corresponding to each clock object based on the at least one trigger edge information, wherein the object information corresponding to each clock object includes the phase information corresponding to each clock object.

[0008] For example, in at least one embodiment of the present disclosure, a port delay constraint method is provided, wherein the trigger edge information includes a first trigger edge or a second trigger edge, and based on the at least one trigger edge information, the phase information corresponding to each clock object is determined, including: in response to the at least one trigger edge information being the first trigger edge or the second trigger edge, determining that the phase information corresponding to each clock object is the first phase; in response to the presence of both the first trigger edge and the second trigger edge in the at least one trigger edge information, determining that the phase information corresponding to each clock object is the second phase.

[0009] For example, in at least one embodiment of the present disclosure, a port delay constraint method is provided, in which the port delay of the first port is set according to the port type, the at least one clock object and the at least one object information, including: determining a delay coefficient according to the port type; for each clock object, setting a clock delay for each clock object for the first port according to the port type, the delay coefficient and the object information of each clock object, wherein the port delay of the first port includes at least one clock delay corresponding to the at least one clock object respectively.

[0010] For example, in at least one embodiment of the present disclosure, a port delay constraint method is provided, wherein the port types include input ports and output ports, and a delay coefficient is determined according to the port types, including: in response to the first port being an input port, setting the delay coefficient to an input delay coefficient; in response to the first port being an output port, setting the delay coefficient to an output delay coefficient, wherein the input delay coefficient is represented by P, and the output delay coefficient is represented by Q, both P and Q are positive numbers, and the sum of P and Q is greater than 1 and less than 2.

[0011] For example, in at least one embodiment of the present disclosure, a method for constraining port delay is provided, wherein each object information includes a clock cycle and phase information. For each clock object, according to the port type, the delay coefficient, and the object information of each clock object, the clock delay for each clock object is set for the first port, including: determining the delay adjustment parameter corresponding to each clock object based on the phase information corresponding to each clock object; in response to the first port being an input port, setting the clock delay of the first port for each clock object based on the input delay coefficient, the delay adjustment parameter, and the clock cycle of each clock object, wherein the clock delay of each clock object is the product of the clock cycle of each clock object, the delay adjustment parameter, and the input delay coefficient; in response to the first port being an output port, setting the clock delay of the first port for each clock object based on the output delay coefficient, the delay adjustment parameter, and the clock cycle of each clock object, wherein the clock delay of each clock object is the product of the clock cycle of each clock object, the delay adjustment parameter, and the output delay coefficient.

[0012] For example, in at least one embodiment of the present disclosure, a port delay constraint method is provided, wherein the phase information includes a first phase and a second phase, and based on the phase information corresponding to each clock object, the delay adjustment parameter corresponding to each clock object is determined, including: in response to the phase information of the i-th clock object being the first phase, determining the delay adjustment parameter of the i-th clock object to be 1; in response to the phase information of the i-th clock object being the second phase, determining the delay adjustment parameter of the i-th clock object to be 1 / 2, wherein i is a positive integer and is less than or equal to the total number of the at least one clock object.

[0013] For example, in at least one embodiment of the present disclosure, a port delay constraint method is provided, wherein all ports also include at least one second port, each second port has preset port constraint information, and the method further includes: for each second port, using the preset port constraint information of each second port as the port delay of each second port.

[0014] For example, at least one embodiment of the present disclosure provides a port delay constraint method that also includes: in response to the at least one clock object being multiple clock objects, determining at least one pseudo timing path, and not performing a timing check on the at least one pseudo timing path, wherein the at least one pseudo timing path includes a timing path that starts with the i-th clock object, passes through the first port, and ends at the j-th clock object, wherein i and j are positive integers and are less than or equal to the total number of the multiple clock objects, and i and j are different.

[0015] At least one embodiment of the present disclosure further provides a port delay constraint device, which is applied to the design of an integrated circuit, wherein the integrated circuit includes a plurality of modules, each module includes at least one sequential logic device and at least one port, and the device includes a port acquisition unit and a processing unit, wherein the port acquisition unit is configured to acquire all ports in the plurality of modules, wherein all ports include a plurality of first ports; the processing unit includes an information acquisition subunit, a clock information determination subunit, a port type determination subunit, and a port delay setting subunit, and for each first port in the plurality of first ports: the information acquisition subunit is configured to acquire N sequential logic devices corresponding to the first port and the module corresponding to the module to which the first port belongs Clock information, wherein each of the N sequential logic devices is directly electrically connected to the first port, or each of the sequential logic devices is electrically connected to the first port through at least one combinational logic device, and N is a positive integer; the clock information determination subunit is configured to determine at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object based on the N sequential logic devices and the module clock information; the port type determination subunit is configured to determine the port type of the first port; and the port delay setting subunit is configured to set the port delay of the first port according to the port type, the at least one clock object and the at least one object information.

[0016] At least one embodiment of the present disclosure provides an electronic device, comprising: a memory, which non-transiently stores computer-executable instructions; and a processor, configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the port delay constraint method according to any embodiment of the present disclosure.

[0017] At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the port delay constraint method according to any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0019] Figure 1 It is a schematic diagram of port delay of cascade module;

[0020] Figure 2A schematic flow chart of a port delay constraint method provided in at least one embodiment of the present disclosure;

[0021] Figure 3A A schematic diagram of a module provided for at least one embodiment of the present disclosure;

[0022] Figure 3B Another module schematic diagram provided for at least one embodiment of the present disclosure;

[0023] Figure 4 A schematic diagram of a processing flow of a port delay constraint method provided in at least one embodiment of the present disclosure;

[0024] Figure 5 A schematic block diagram of a port delay constraint device provided in at least one embodiment of the present disclosure;

[0025] Figure 6 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure;

[0026] Figure 7 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0029] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components.

[0030] Large-scale integrated circuits, such as SOC (System on Chip) integrated circuits, may be divided into dozens or hundreds of modules for separate design during the specific circuit design process. For example, each module can be divided according to module function and position relationship. Each module can implement specific functions, and data exchange between modules is performed through module ports.

[0031] The module port includes an input port and an output port. The port delay of the module port includes an input delay of the input port and an output delay of the output port. For example, the port timing constraint of the input port includes an input delay constraint, and the port timing constraint of the output port includes an output delay constraint.

[0032] For example, input delay is defined as: the delay taken for the output data of the external logic to reach the input port of the module within a valid clock cycle; output delay is defined as: the delay taken for the output data of the output port to reach the external logic within a valid clock cycle.

[0033] Figure 1 Figure 2 is a schematic diagram of the port delay of the cascade module.

[0034] like Figure 1 As shown, module 1 includes output port A, register R1 and combinational logic 1, and module 2 includes input port B, register R2 and combinational logic 2. The output data port Q1 of register R1 in module 1 is electrically connected to output port A after passing through combinational logic 1, and output port A is directly electrically connected to input port B. The input port B in module 2 is electrically connected to input data port D2 of register R2 after passing through combinational logic 2. For example, the combinational logic is composed of one or more combinational logic devices, and there is no sequential logic device in the combinational logic.

[0035] For example, the output delay of the output port A of module 1 is the delay required for data to be transmitted from the output port A to the data input terminal D2 of the register R2 of module 2, that is, T AB +Tb. The input delay of the input port B of module 2 is the delay required for data to be transmitted from the data output terminal Q1 of the register R1 of module 1 to the input port B, that is, Ta+T AB , here, T ABIndicates the delay required for data to be transmitted from output port A to input port B. Ta represents the delay required for data to pass through combinational logic 1, and Tb represents the delay required for data to pass through combinational logic 2. Usually, the value of T AB is very small and can be ignored in some cases.

[0036] To ensure that the port timing of the module meets the design requirements, for the first-stage module and the second-stage module that are driven by the same clock and cascaded, for example, the output port of the first-stage module is electrically connected to the input port of the second-stage module. Usually, it is required that the sum of the output delay of the first-stage module and the input delay of the second-stage module is within one clock cycle.

[0037] For example, for Figure 1 the cascaded module 1 and module 2 shown, to ensure that the port timing of the module meets the design requirements, it is required that the delay for data to be transmitted from the data output terminal Q1 of register R1 to the data input terminal D2 of register R2 is within one clock cycle. The data is output from the data output terminal Q1 of register R1 and passes through combinational logic 1, output port A, input port B, and combinational logic 2 and then transmitted to the data input terminal D2 of register R2. Thus, it can be seen that the delay for data to be transmitted from the data output terminal Q1 of register R1 to the data input terminal D2 of register R2 is expressed as Ta + T AB + Tb, and Ta + T AB + Tb < clk_period, for example, clk_period is the clock cycle of the clock source.

[0038] For example, when the port delay (i.e., output delay) set for output port A is T1, the timing constraint requires that the value of T1 + T Q1-A is less than 1 clock cycle of the clock source (T Q1-A is the delay for data to be transmitted from the data output terminal Q1 of register R1 to output port A), then when the delay for data to be transmitted from output port A to the data input terminal D2 of register R2 is within the range of T1, there will be no timing violation; otherwise, there will be a timing violation.

[0039] For example, when the port delay (i.e., input delay) set for input port B is T2, the clock constraint requires that the value of T B-D2 + T2 is less than 1 clock cycle of the clock source (T B-D2 is the delay for data to be transmitted from output port B to the data input terminal D2 of register R2), then when the delay for data to be transmitted from the data output terminal Q1 of register R1 to output port A is within the range of T2, there will be no timing violation; otherwise, there will be a timing violation.

[0040] At present, it is generally necessary to manually set the port delay constraints for each module so that the timing of the integrated chip meets the design expectations. For example, the designer analyzes the design circuit and sets the port timing constraints according to the reference clock cycle of the port. Usually, a certain proportion of the reference clock cycle is selected to set the input delay and output delay of each port. For example, after the integrated circuit design is completed, the integrated circuit can be initially synthesized, and the path delay of the circuit after the initial synthesis can be analyzed. Based on the delay analysis results, the input delay constraints and output delay constraints of each module port can be set.

[0041] In the first existing solution, it is necessary to make a relatively accurate estimate of the logic before and after each port and the timing. When the design scale of the integrated circuit is large and the design is complex, this solution requires a lot of time to set the constraints. In the second existing solution, it is necessary to set the input delay constraints and output delay constraints of each module port based on the results of the initial synthesis (Synthesizer). This makes it impossible to use this solution to provide the corresponding port constraints when the integrated circuit is synthesized for the first time. In addition, since the information such as the internal phase difference of the circuit is not considered during the first synthesis, the results of the first synthesis may be inaccurate, affecting the accuracy of subsequent delay constraints.

[0042] At least one embodiment of the present disclosure provides a port delay constraint method, a port delay constraint device, an electronic device, and a non-transient computer-readable storage medium. The port delay constraint method includes: obtaining all ports in a plurality of modules, wherein all ports include a plurality of first ports; for each of the plurality of first ports: obtaining N sequential logic devices corresponding to the first port and module clock information corresponding to the module to which the first port belongs, wherein each of the N sequential logic devices is directly electrically connected to the first port, or each sequential logic device is electrically connected to the first port through at least one combinational logic device, and N is a positive integer; based on the N sequential logic devices and the module clock information, determining at least one clock object associated with the first port and at least one object information corresponding to the at least one clock object; determining the port type of the first port; and setting the port delay of the first port according to the port type, the at least one clock object, and the at least one object information.

[0043] This port delay constraint method can automatically set complete port constraints for the ports of each module based on the design itself, without requiring designers to spend too much effort manually setting port constraints. It can also automatically add port constraints to each module in the early stages of the design, saving iteration time.

[0044] It should be noted that the integrated circuit in the present disclosure may refer to a partial design or a partial module in a large circuit design, that is, the integrated circuit in the present disclosure may be a complete integrated circuit itself or a partial circuit in a complete integrated circuit, and the present disclosure does not impose any restrictions on this.

[0045] In addition, in the embodiments of the present disclosure, the logic device includes a combinational logic device and a sequential logic device. Here, the sequential logic device refers to devices such as triggers, registers, latches, etc. in digital circuit design. The sequential logic device has storage and memory functions for input signals. When receiving the valid edge or valid level of the clock signal, it can trigger the storage of the input signal and the state change of the output signal of the sequential logic device. The combinational logic device refers to devices such as AND gates and OR gates in digital circuit design that implement logical operations, such as data selectors, numerical comparators, etc. The combinational logic device does not have storage and memory functions for input signals. At any time, the state of the output signal of the combinational logic device depends on the state of the input signal at the current time.

[0046] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0047] Figure 2 A schematic flowchart of a port delay constraint method provided for at least one embodiment of the present disclosure.

[0048] For example, the port delay constraint method is applied to the design of an integrated circuit. For example, the integrated circuit includes a plurality of modules, each module includes at least one sequential logic device and at least one port.

[0049] For example, multiple modules may include Figure 1 Module 1 and / or module 2 shown.

[0050] For example, Figure 2 As shown, the port delay constraint method provided by the embodiment of the present disclosure includes steps S10 to S50.

[0051] In step S10, all ports in a plurality of modules are obtained.

[0052] For example, all ports include multiple first ports. For example, the first port may be a port that can set the port delay according to the port delay constraint method provided by the present disclosure. For example, the first port does not have pre-set port constraint information.

[0053] For example, all ports further include a plurality of second ports, and each second port has preset port constraint information.

[0054] For example, all ports are traversed, and if the port has preset port constraint information, the port is used as the second port; if the port does not have preset port constraint information, the port is used as the first port, and subsequent steps S20 to S50 are performed on the first port.

[0055] For each first port among the plurality of first ports, step S20 to step S50 are performed.

[0056] In step S20, module clock information corresponding to N sequential logic devices corresponding to the first port and the module to which the first port belongs is obtained. For example, each of the N sequential logic devices is directly electrically connected to the first port, or each sequential logic device is electrically connected to the first port through at least one combinational logic device, and N is a positive integer.

[0057] In step S30, at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object are determined based on N sequential logic devices and module clock information.

[0058] In step S40, the port type of the first port is determined.

[0059] For example, port types include input ports and output ports.

[0060] In step S50, a port delay of a first port is set according to a port type, at least one clock object and at least one object information.

[0061] For example, in step S20, obtaining N sequential logic devices corresponding to the first port may include: in response to the first port not being used for inputting a clock signal, determining N sequential logic devices from at least one sequential logic device included in a module to which the first port belongs.

[0062] For example, in step S20, obtaining module clock information corresponding to the module to which the first port belongs may include: determining at least one sequential logic device included in the module to which the first port belongs; and obtaining at least one device clock information corresponding to the at least one sequential logic device. For example, the module clock information includes at least one device clock information.

[0063] For example, in some embodiments, obtaining module clock information includes: first, traversing all sequential logic devices included in the module to which the first port belongs, analyzing driving clock signals of all sequential logic devices, and determining the clock object that drives each sequential logic device to work and the trigger edge information of each sequential logic device.

[0064] For example, device clock information may include clock objects and trigger edge information.

[0065] For example, one or more sequential logic devices in the module are driven by a first clock, and the clock object in the device clock information corresponding to these sequential logic devices is the first clock.

[0066] For example, the trigger edge information includes the first trigger edge or the second trigger edge, for example, the first trigger edge is a rising edge, the second trigger edge is a falling edge, or the first trigger edge is a falling edge, the second trigger edge is a rising edge. For example, some registers can receive rising edge triggering and falling edge triggering at the same time, in which case the trigger edge information of these registers may include the first trigger edge and the second trigger edge.

[0067] After obtaining the device clock information of each sequential logic device, an array containing the name of the sequential logic device, the name of the clock object, and the trigger edge information is established, that is, the information in the array includes: the name of the sequential logic device, the name of the clock object, and the trigger edge information. Each sequential logic device has two attributes, the name of the clock object and the trigger edge information. The name of the clock object and the trigger edge information corresponding to the sequential logic device can be queried through the name of the sequential logic device.

[0068] For example, in step S20, all first ports are traversed, and if a first port is used to input a clock signal, no subsequent analysis is performed on the first port (for example, steps S30-S50 are no longer executed), that is, no port timing constraint is set for the first port.

[0069] If the first port is not used to input a clock signal, when the first port is an input port, N timing paths starting from the first port are obtained, each timing path starting from the first port, passing through some combinational logic devices (or directly electrically connected via circuit routing), until the data input port of a certain timing logic device is terminated, and the timing logic device at the end of the N timing paths is the N timing logic devices corresponding to the first port; when the first port is an output port, N timing paths ending at the first port are obtained, each timing path starting from the data output port of a certain timing logic device, passing through some combinational logic devices (or directly electrically connected via circuit routing), until the first port is terminated, and the timing logic device at the starting point of the N timing paths is the N timing logic devices corresponding to the first port. The above analysis process can be automatically completed using electronic design automation software, so as to quickly obtain the timing logic devices corresponding to all ports and the timing paths constituting the ports, as well as the module clock information corresponding to all modules, covering all possible timing paths to the maximum extent, and providing a complete port constraint solution.

[0070] It should be noted that the process of obtaining the N sequential logic devices corresponding to the first port and the module clock information corresponding to the module to which the first port belongs in step S20 is not limited to the method provided in the embodiment of the present disclosure, and those skilled in the art may implement it by other methods.

[0071] Afterwards, in combination with the module clock information obtained in step S20 and N sequential logic devices, an association relationship between the first port and the clock object is established, and one or more clock objects associated with each port and the object information corresponding to these clock objects are determined, so as to set delay constraints for each clock object for the input port or output port.

[0072] For example, step S30 may include: determining N device clock information corresponding to N sequential logic devices based on the module clock information; and determining at least one clock object associated with the first port and at least one object information corresponding to the at least one clock object according to the N device clock information.

[0073] For example, determining at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object based on N device clock information may include: determining N clock objects based on the N device clock information; determining at least one clock object from the N clock objects, wherein at least one clock object is different from each other; for each clock object in the at least one clock object: determining at least one trigger edge information corresponding to each clock object based on the N device clock information, and determining phase information corresponding to each clock object based on the at least one trigger edge information, wherein the object information corresponding to each clock object includes the phase information corresponding to each clock object.

[0074] For example, the trigger edge information includes the first trigger edge or the second trigger edge. Based on at least one trigger edge information, determining the phase information corresponding to each clock object may include: in response to at least one trigger edge information being the first trigger edge or the second trigger edge, determining that the phase information corresponding to each clock object is the first phase; in response to the presence of both the first trigger edge and the second trigger edge in the at least one trigger edge information, determining that the phase information corresponding to each clock object is the second phase.

[0075] For example, based on the above process, an association relationship between a port and a clock object can be established. For example, establishing an association relationship between a port and a clock object can include establishing an array of the name of the first port, the name of the clock object, and object information. The information in the array includes: the name of the first port, the name of the clock object, and object information.

[0076] Figure 3A and Figure 3B A schematic diagram of a module provided for at least one embodiment of the present disclosure.

[0077] like Figure 3A As shown, module A includes sequential logic device R3, sequential logic device R4 and sequential logic device R5. Figure 3B As shown, module B includes sequential logic device R6 and sequential logic device R7. Of course, module A and module B may also include more sequential logic devices, which will not be described in detail here.

[0078] For example, the combinational logic includes one or more combinational logic devices, and the circuit logic includes one or more combinational logic devices and sequential logic devices, that is, the combinational logic does not include sequential logic devices, and the circuit logic may include sequential logic devices.

[0079] For example, Figure 3A As shown, the first port is input port 1, which is electrically connected to sequential logic device R3, sequential logic device R4 and sequential logic device R5 through combinational logic, sequential logic device R3 is controlled by the rising edge signal of clock CLK1, sequential logic device R4 is controlled by the falling edge signal of clock CLK2, and sequential logic device R5 is controlled by both the rising edge signal and the falling edge signal of clock CLK2. The output ends of sequential logic device R3, sequential logic device R4 and sequential logic device R5 are connected to other circuit logics, which will not be described here.

[0080] For example, Figure 3B As shown, the first port is output port 2, sequential logic device R6 and sequential logic device R7 are electrically connected to output port 2 through combinational logic, sequential logic device R6 is controlled by the rising edge signal of clock CLK1, and sequential logic device R7 is controlled by the falling edge signal of clock CLK2. The input ends of sequential logic device R6 and sequential logic device R7 are connected to other circuit logics, which will not be described here.

[0081] For example, the first trigger edge is a rising edge, and the second trigger edge is a falling edge.

[0082] Below Figure 3A and Figure 3B Take the example to specifically illustrate the execution process of step S30.

[0083] For example, in Figure 3A In the example shown, input port 1 corresponds to three sequential logic devices, namely sequential logic device R3, sequential logic device R4 and sequential logic device R5. The specific analysis process refers to the content of step S20, which will not be repeated here.

[0084] For example, the device clock information of the sequential logic device R3 includes: the clock object is the clock CLK1, and the trigger edge information is rising edge trigger; the device clock information of the sequential logic device R4 includes: the clock object is the clock CLK2, and the trigger edge information is falling edge trigger; the device clock information of the sequential logic device R5 includes: the clock object is the clock CLK2, and the trigger edge information is rising edge trigger and falling edge trigger.

[0085] According to the device clock information corresponding to the three sequential logic devices respectively, it can be determined that the clock objects corresponding to the input port 1 include the clock CLK1 and the clock CLK2.

[0086] For clock CLK1, according to the clock information of three devices, since only sequential logic device R3 is controlled by the rising edge signal of clock CLK1, the trigger edge information corresponding to clock CLK1 is all rising edges, and the phase information corresponding to clock CLK1 is determined to be the first phase.

[0087] For clock CLK2, according to the clock information of the three devices, the timing logic device R4 is controlled by the falling edge signal of the clock CLK2, and the timing logic device R5 is controlled by the rising edge signal and the falling edge signal of the clock CLK2 at the same time. Therefore, the trigger edge information corresponding to the clock CLK2 includes the rising edge and the falling edge, and the phase information corresponding to the clock CLK2 is determined to be the second phase.

[0088] For example, for Figure 3A For the input port 1 shown, the association relationship between the port and the clock can be that the clock objects corresponding to the input port 1 include clock CLK1 and clock CLK2, the phase information in the object information corresponding to the clock CLK1 is the first phase, and the phase information in the object information corresponding to the clock CLK2 is the second phase.

[0089] For example, in Figure 3B In the example shown, the output port 2 corresponds to two sequential logic devices, namely sequential logic device R6 and sequential logic device R7. The specific analysis process refers to the content of step S20, which will not be repeated here.

[0090] For example, the device clock information of the sequential logic device R6 includes: the clock object is the clock CLK1, and the trigger edge information is rising edge trigger; the device clock information of the sequential logic device R7 includes: the clock object is the clock CLK2, and the trigger edge information is falling edge trigger.

[0091] According to the device clock information corresponding to the two sequential logic devices respectively, it can be determined that the clock objects corresponding to the output port 2 include the clock CLK1 and the clock CLK2.

[0092] For clock CLK1, according to the clock information of two devices, since only sequential logic device R6 is controlled by the rising edge signal of clock CLK1, the trigger edge information corresponding to clock CLK1 is the rising edge, and the phase information corresponding to clock CLK1 is determined to be the first phase.

[0093] For clock CLK2, according to the clock information of two devices, since only sequential logic device R7 is controlled by the falling edge signal of clock CLK2, the trigger edge information corresponding to clock CLK2 is the falling edge, and the phase information corresponding to clock CLK2 is determined to be the first phase.

[0094] For example, for Figure 3B For the output port 2 shown, the association relationship between the port and the clock can be that the clock objects corresponding to the output port 2 include clock CLK1 and clock CLK2, the phase information in the object information corresponding to the clock CLK1 is the first phase, and the phase information in the object information corresponding to the clock CLK2 is also the first phase.

[0095] Afterwards, a port delay is set for the first port according to the association relationship between the first port and the clock object.

[0096] For example, step S50 may include: determining a delay coefficient according to the port type; for each clock object, setting a clock delay for each clock object for the first port according to the port type, the delay coefficient, and the object information of each clock object, wherein the port delay of the first port includes at least one clock delay corresponding to at least one clock object.

[0097] For example, determining the delay coefficient according to the port type may include: in response to the first port being an input port, setting the delay coefficient to an input delay coefficient; in response to the first port being an output port, setting the delay coefficient to an output delay coefficient, wherein the input delay coefficient is represented by P, and the output delay coefficient is represented by Q, both P and Q are positive numbers, and the sum of P and Q is greater than 1 and less than 2.

[0098] For example, the sum of the input delay coefficient and the output delay coefficient is set to be greater than one clock cycle but less than two clock cycles, that is, the sum of P and Q is set to be greater than 1 and less than 2. This over-constraint setting method can make the sum of the input delay and output delay of each port within one cycle during the timing optimization process, and can make it easier for subsequent circuits to meet the timing constraint requirements.

[0099] For example, the specific values ​​of P and Q can be set according to the margin reserved for the process of the integrated circuit and the subsequent physical implementation (such as layout and routing). For example, under different processes, the timing correlation between synthesis and layout and routing is inconsistent, and under different flows, the timing correlation between synthesis and layout and routing is also inconsistent. Generally, the specific values ​​of P and Q can be set considering the margin of layout and routing so that most of the timing paths of the integrated circuit after layout and routing do not have timing violations.

[0100] For example, the device clock information may further include a clock cycle, and thus the object information determined based on the device clock information may also include the clock cycle.

[0101] For example, for each clock object, according to the port type, the delay coefficient, and the object information of each clock object, the clock delay for each clock object is set for the first port, which may include: determining the delay adjustment parameter corresponding to each clock object based on the phase information corresponding to each clock object; in response to the first port being an input port, setting the clock delay of the first port for each clock object based on the input delay coefficient, the delay adjustment parameter, and the clock period of each clock object, wherein the clock delay of each clock object is the product of the clock period of each clock object, the delay adjustment parameter, and the input delay coefficient; in response to the first port being an output port, setting the clock delay of the first port for each clock object based on the output delay coefficient, the delay adjustment parameter, and the clock period of each clock object, wherein the clock delay of each clock object is the product of the clock period of each clock object, the delay adjustment parameter, and the output delay coefficient.

[0102] For example, based on the phase information corresponding to each clock object, determining the delay adjustment parameter corresponding to each clock object may include: in response to the phase information of the i-th clock object being the first phase, determining the delay adjustment parameter of the i-th clock object to be 1; in response to the phase information of the i-th clock object being the second phase, determining the delay adjustment parameter of the i-th clock object to be 1 / 2, where i is a positive integer and is less than or equal to the total number of at least one clock object.

[0103] According to the above content, when the trigger edge corresponding to the clock object has both the first trigger edge and the second trigger edge, the phase information corresponding to the clock object is determined to be the second phase. At this time, a register driven by the clock object can be triggered by both the rising edge and the falling edge, that is, a half-cycle circuit, so the delay adjustment parameter of the clock object is set to 1 / 2. On the contrary, if all registers driven by the clock object are triggered by the rising edge or the falling edge, the delay adjustment parameter of the clock object is set to 1.

[0104] Combine the following Figure 3A and Figure 3B, specifically describe the execution process of step S50.

[0105] As mentioned above, the clock objects corresponding to the input port 1 are the clock CLK1 and the clock CLK2. The phase information in the object information corresponding to the clock CLK1 is the first phase, and the phase information in the object information corresponding to the clock CLK2 is the second phase.

[0106] For input port 1, since its type is an input port, the port constraint to be set should be an input delay constraint.

[0107] For example, the delay coefficient of input port 1 is the input delay coefficient P.

[0108] For example, for clock CLK1, since the phase information in the object information corresponding to clock CLK1 is the first phase, the delay adjustment parameter is 1, and the clock delay of input port 1 for clock CLK1 is set to Tin1, Tin1 = 1*P*clk1_period, where clk1_period is the clock period of clock CLK1. It should be noted that when the phase information in the object information corresponding to clock CLK1 is the first phase, the delay adjustment parameter includes but is not limited to 1, which can be set according to actual conditions.

[0109] For example, for clock CLK2, since the phase information in the object information corresponding to clock CLK2 is the second phase, the delay adjustment parameter is 1 / 2, and the clock delay of input port 1 for clock CLK2 is set to Tin2, Tin2 = 1 / 2*P*clk2_period, where clk2_period is the clock period of clock CLK2. It should be noted that when the phase information in the object information corresponding to clock CLK1 is the second phase, the delay adjustment parameter includes but is not limited to 1 / 2, which can be set according to actual conditions.

[0110] After the above process, an input delay constraint Tin1 for clock CLK1 and an input delay constraint Tin2 for clock CLK2 are added to input port 1.

[0111] As mentioned above, the clock objects corresponding to the output port 2 are the clock CLK1 and the clock CLK2, the phase information in the object information corresponding to the clock CLK1 is the first phase, and the phase information in the object information corresponding to the clock CLK2 is the first phase.

[0112] For output port 2, since its type is an output port, the port constraint to be set should be an output delay constraint.

[0113] For example, the delay coefficient of output port 2 is the output delay coefficient Q.

[0114] For example, for clock CLK1, since the phase information in the object information corresponding to clock CLK1 is the first phase, the delay adjustment parameter is 1, and the clock delay of output port 2 for clock CLK1 is set to Tout1, Tout1 = 1*Q*clk1_period.

[0115] For example, for clock CLK2, since the phase information in the object information corresponding to clock CLK1 is the first phase, the delay adjustment parameter is 1, and the clock delay of output port 2 for clock CLK2 is set to Tout2, Tout2 = Q*clk2_period.

[0116] Through the above process, an output delay constraint Tout1 for clock CLK1 and an output delay constraint Tout2 for clock CLK2 are added to output port 2.

[0117] Different from the previous port delay constraint methods, the port delay constraint method provided by the present invention can provide input delay constraints and output delay constraints for different clocks of the same port, support multiple clock constraints for the same port, and consider the clock phase, support automatic phase identification of multiple clocks, provide more rigorous timing constraints, save version iteration time, and speed up development efficiency.

[0118] For example, when the same port corresponds to multiple clock objects, it is necessary not only to add corresponding port delay constraints for each clock object, but also to set the timing paths between different clock objects of the port as false timing paths. During timing analysis, timing checks are not performed on these false paths to ensure that multiple synchronized clock objects avoid false violations caused by incorrect port constraints due to large differences in the periods of each clock object.

[0119] For example, the port delay constraint method provided by at least one embodiment of the present disclosure may also include: in response to at least one clock object being multiple clock objects, determining at least one pseudo timing path, and not performing a timing check on the at least one pseudo timing path, wherein the at least one pseudo timing path includes a timing path starting from the i-th clock object, passing through the first port, and ending at the j-th clock object, wherein i and j are positive integers and are less than or equal to the total number of multiple clock objects, and i and j are different.

[0120] For example, for Figure 3AIn the module A shown, the clock objects corresponding to input port 1 include clock CLK1 and clock CLK2. When clock CLK1 and clock CLK2 are synchronous clocks, if the product of the clock period of clock CLK1 and the input delay coefficient is greater than the clock period of clock CLK2, the timing path starting from clock CLK1, passing through input port 1 and ending at clock CLK2 is in timing violation, and the timing path needs to be set to a false timing path.

[0121] For example, the port delay constraint method further includes: for each second port, using the preset port constraint information of each second port as the port delay of each second port.

[0122] For example, for modules that usually include more registers, more clocks, and more complex logic, such as macro-cells, there are many clocks that have a driving relationship with the module, but fewer clocks that have an associated relationship with the ports. For example, most of the clocks are used to drive internal sequential logic devices, and these sequential logic devices do not constitute a timing path with the ports. In this case, the port delay set according to the above method may result in a large number of irrelevant delay constraints.

[0123] For example, when executing the port delay constraint method provided by at least one embodiment of the present disclosure for the first time, all ports can be used as the first port, and the port delay of all ports can be set; then, a timing analysis is performed on the circuit with the port delay set to determine which modules' port timing affects the module's internal timing, for example, the macro unit described above is likely to affect the module's internal timing; then, the delay margin of the module's front and back logic is confirmed with the designer to check whether the set port delay is over-constrained. If the port delay is over-constrained, preset constraint information is set for the ports whose port timing affects the module's internal timing. If there is no over-constraint, there is no need to add additional constraint information.

[0124] In addition, since the port delay constraint method provided by the present invention is based on the device timing information of the sequential logic device that constitutes the timing path of the port to establish the corresponding association relationship between the port and the clock, and then set the port constraint for the port, therefore, when the design has not changed or the circuit logic change does not affect the sequential logic device corresponding to the port, the port constraints of the previous version can be reused when performing timing analysis on the circuit, and there is no need to execute the entire process of the present invention again, which saves development time and improves development efficiency.

[0125] Figure 4 A schematic diagram of the processing flow of a port delay constraint method provided in at least one embodiment of the present disclosure.

[0126] Combine the following Figure 4, specifically describes the execution process of the port delay constraint method provided by the present invention.

[0127] First, traverse all ports, and for each port, determine whether the port already has preset constraint information. If the port already has preset constraint information, use the port as the second port, use the preset constraint information of the port as the port delay of the port, and continue to traverse the next port.

[0128] If the port does not have preset constraint information, the port is used as the first port to obtain module clock information corresponding to the module to which the port belongs. For the specific process, see step S20, which will not be repeated here.

[0129] Afterwards, it is determined whether the port is a clock signal input port, that is, whether the port is used to input a clock signal. If the port is used to input a clock signal, subsequent steps are not performed and the next port is traversed.

[0130] If the port is not used to input a clock signal, N sequential logic devices corresponding to the port are obtained. For the specific process, see step S20, which will not be described in detail here.

[0131] Afterwards, the clock objects associated with the port and the object information of these clock objects are obtained. For the specific process, see step S30, which will not be described in detail here.

[0132] Afterwards, the port type is determined. For the specific process, see step S40, which will not be described in detail here.

[0133] Afterwards, according to the port type, the clock object associated with the port and the object information, a port delay constraint is added to the port. For the specific process, see step S50, which will not be described in detail here.

[0134] Afterwards, it is determined whether there are multiple clock objects associated with the port. If there are multiple clock objects associated with the port, pseudo timing path constraints are added between the multiple clock objects. The specific process is as described above and will not be repeated here.

[0135] After that, the above process is performed for the next port until all ports are traversed.

[0136] The port delay constraint method provided by at least one embodiment of the present disclosure has two characteristics: automatic and forward-looking. It can be used in the initial synthesis process after the design is completed. In the early stage of design implementation, the module port can meet the timing requirements as much as possible, reducing the workload of designers. In addition, the method automatically adds port constraints to the ports of each module based on the design itself, without human intervention, thereby improving work efficiency.

[0137] Corresponding to the above-mentioned method for constraining port delay, at least one embodiment of the present disclosure further provides a device for constraining port delay. Figure 5A schematic block diagram of a port delay constraint device provided in at least one embodiment of the present disclosure.

[0138] For example, Figure 5 As shown, the port delay constraint device 500 includes: a port acquisition unit 501 and a processing unit 502 .

[0139] The port acquisition unit 501 is configured to acquire all ports in a plurality of modules, for example, all ports include a plurality of first ports.

[0140] The processing unit 502 includes an information acquisition subunit 5021 , a clock information determination subunit 5022 , a port type determination subunit 5023 , and a port delay setting subunit 5024 .

[0141] For each first port among the multiple first ports, the information acquisition subunit 5021 is configured to acquire module clock information corresponding to N sequential logic devices corresponding to the first port and the module to which the first port belongs, wherein each of the N sequential logic devices is directly electrically connected to the first port, or each sequential logic device is electrically connected to the first port through at least one combinational logic device, and N is a positive integer.

[0142] The clock information determination subunit 5022 is configured to determine at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object based on the N sequential logic devices and module clock information.

[0143] The port type determination subunit 5023 is configured to determine the port type of the first port.

[0144] The port delay setting subunit 5024 is configured to set the port delay of the first port according to the port type, at least one clock object and at least one object information.

[0145] For example, when the information acquisition subunit 5021 performs an operation of acquiring N sequential logic devices corresponding to the first port, it includes performing the following operations: in response to the first port not being used to input a clock signal, determining N sequential logic devices from at least one sequential logic device included in the module to which the first port belongs.

[0146] For example, when the information acquisition subunit 5021 performs an operation of acquiring module clock information corresponding to the module to which the first port belongs, it includes performing the following operations: determining at least one sequential logic device included in the module to which the first port belongs; acquiring at least one device clock information corresponding one-to-one to the at least one sequential logic device, wherein the module clock information includes at least one device clock information.

[0147] For example, when the clock information determination subunit 5022 performs an operation of determining at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object based on N sequential logic devices and module clock information, the operation includes performing the following operations: determining N device clock information corresponding one-to-one to the N sequential logic devices based on the module clock information; and determining at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object based on the N device clock information.

[0148] For example, when the clock information determination subunit 5022 performs an operation of determining at least one clock object associated with the first port and at least one object information corresponding to the at least one clock object according to N device clock information, it includes performing the following operations: determining N clock objects according to the N device clock information; determining at least one clock object from the N clock objects, wherein at least one clock object is different from each other; for each clock object in the at least one clock object: determining at least one trigger edge information corresponding to each clock object according to the N device clock information, and determining phase information corresponding to each clock object based on the at least one trigger edge information, wherein the object information corresponding to each clock object includes the phase information corresponding to each clock object.

[0149] For example, when the clock information determination subunit 5022 performs an operation of determining the phase information corresponding to each clock object based on at least one trigger edge information, it includes performing the following operations: in response to at least one trigger edge information being both the first trigger edge or both the second trigger edge, determining that the phase information corresponding to each clock object is the first phase; in response to the presence of both the first trigger edge and the second trigger edge in at least one trigger edge information, determining that the phase information corresponding to each clock object is the second phase.

[0150] For example, the port delay setting subunit 5024 includes a delay coefficient determination subunit and a clock delay setting subunit.

[0151] For example, the delay coefficient determination subunit is configured to determine the delay coefficient according to the port type.

[0152] For example, the clock delay setting subunit is configured to set the clock delay for each clock object for the first port according to the port type, delay coefficient, and object information of each clock object, wherein the port delay of the first port includes at least one clock delay corresponding to at least one clock object.

[0153] For example, when the clock delay setting subunit performs an operation of setting the clock delay for each clock object for the first port according to the port type, the delay coefficient, and the object information of each clock object for each clock object, the operation includes the following operations: determining the delay adjustment parameter corresponding to each clock object based on the phase information corresponding to each clock object; in response to the first port being an input port, setting the clock delay of the first port for each clock object based on the input delay coefficient, the delay adjustment parameter, and the clock period of each clock object, wherein the clock delay of each clock object is the product of the clock period of each clock object, the delay adjustment parameter, and the input delay coefficient; in response to the first port being an output port, setting the clock delay of the first port for each clock object based on the output delay coefficient, the delay adjustment parameter, and the clock period of each clock object, wherein the clock delay of each clock object is the product of the clock period of each clock object, the delay adjustment parameter, and the output delay coefficient.

[0154] For example, when the clock delay setting subunit performs an operation of determining the delay adjustment parameter corresponding to each clock object based on the phase information corresponding to each clock object, it includes performing the following operations: in response to the phase information of the i-th clock object being the first phase, determining the delay adjustment parameter of the i-th clock object to be 1; in response to the phase information of the i-th clock object being the second phase, determining the delay adjustment parameter of the i-th clock object to be 1 / 2, where i is a positive integer and is less than or equal to the total number of at least one clock object.

[0155] For example, the port acquisition unit 501 and the processing unit 502 include codes and programs stored in a memory; the processor can execute the codes and programs to implement some or all of the functions of the port acquisition unit 501 and the processing unit 502 as described above. For example, the port acquisition unit 501 and the processing unit 502 can be dedicated hardware devices, used to implement some or all of the functions of the port acquisition unit 501 and the processing unit 502 as described above. For example, the port acquisition unit 501 and the processing unit 502 can be a circuit board or a combination of multiple circuit boards, used to implement the functions described above. In an embodiment of the present application, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processor; and (3) firmware stored in the memory that can be executed by the processor.

[0156] It should be noted that the port acquisition unit 501 is used to implement Figure 2 In step S10 shown in FIG. 1 , the information acquisition subunit 5021 is used to implement Figure 2 In step S20, the clock information determining subunit 5022 is used to implement Figure 2 In step S30, the port type determination subunit 5023 is used to implement Figure 2 In step S40, the port delay setting subunit 5024 is used to implement Figure 2 Therefore, the specific description of the port acquisition unit 501 can refer to the embodiment of the above-mentioned port delay constraint method. Figure 2 For the description of step S10 shown in FIG. 1 and the specific description of the information acquisition subunit 5021, reference can be made to the embodiment of the above-mentioned method for constraining port delay. Figure 2 For the description of step S20 shown in FIG. 1 , the specific description of the clock information determination subunit 5022 can refer to the embodiment of the above-mentioned port delay constraint method. Figure 2 For the description of step S30 shown in FIG. 1 , the specific description of the port type determination subunit 5023 can be referred to in the embodiment of the above-mentioned port delay constraint method. Figure 2 For the description of step S40, the specific description of the port delay setting subunit 5024 can refer to the embodiment of the above-mentioned port delay constraint method. Figure 2 The relevant description of step S50 is shown. In addition, the port delay constraint device can achieve the technical effect similar to the above-mentioned port delay constraint method, which will not be described in detail here.

[0157] At least one embodiment of the present disclosure further provides an electronic device, Figure 6 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0158] For example, Figure 6 As shown, the electronic device includes a processor 601, a communication interface 602, a memory 603 and a communication bus 604. The processor 601, the communication interface 602, and the memory 603 communicate with each other through the communication bus 604. The components such as the processor 601, the communication interface 602, and the memory 603 can also communicate with each other through a network connection. The present disclosure does not limit the type and function of the network.

[0159] For example, the memory 603 is used to store computer executable instructions non-transiently. When the processor 601 is used to execute the computer executable instructions, the computer executable instructions are executed by the processor 601 to implement the port delay constraint method according to any of the above embodiments. The specific implementation of each step of the port delay constraint method and related explanations can be found in the embodiment of the port delay constraint method, which will not be repeated here.

[0160] For example, the implementation manner of the port delay constraint method implemented by the processor 601 executing the program stored in the memory 603 is the same as the implementation manner mentioned in the embodiment of the port delay constraint method, which will not be repeated here.

[0161] For example, the communication bus 604 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industrial Standard Architecture (EISA) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0162] For example, the communication interface 602 is used to implement communication between the electronic device and other devices.

[0163] For example, the processor 601 and the memory 603 may be arranged on a server side (or a cloud side).

[0164] For example, the processor 601 can control other components in the electronic device to perform the desired functions. The processor 601 can be a central processing unit (CPU), a network processor (NP), etc., and can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The central processing unit (CPU) can be an X86 or ARM architecture, etc.

[0165] For example, the memory 603 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer executable instructions may be stored on the computer-readable storage medium, and the processor 601 may run the computer executable instructions to implement various functions of the electronic device. Various applications and various data may also be stored in the storage medium.

[0166] For example, for a detailed description of the process of the electronic device executing the port delay constraint, reference may be made to the relevant description in the embodiment of the port delay constraint method, and the repeated parts will not be repeated.

[0167] Figure 7 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Figure 7 As shown, one or more computer executable instructions 701 may be non-transitorily stored on the storage medium 700. For example, when the computer executable instructions 701 are executed by a processor, one or more steps in the port delay constraint method described above may be executed.

[0168] For example, the storage medium 700 may be applied to the above-mentioned electronic device and / or the port delay constraint device 500. For example, the storage medium 700 may include a memory 603 in the electronic device.

[0169] For example, the description of the storage medium 700 may refer to the description of the memory in the embodiment of the electronic device, and the repeated parts will not be repeated.

[0170] There are a few points to note about this disclosure:

[0171] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0172] (2) For the sake of clarity, the thickness and size of layers or structures are exaggerated in the drawings used to describe the embodiments of the present invention. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intervening elements.

[0173] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0174] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A port delay constraint method, applied to the design of integrated circuits, in, The integrated circuit includes a plurality of modules, each module includes at least one sequential logic device and at least one port, The method comprises: Acquire all ports in the multiple modules, wherein the all ports include multiple first ports; For each first port of the plurality of first ports: Acquire module clock information corresponding to N sequential logic devices corresponding to the first port and a module to which the first port belongs, wherein each of the N sequential logic devices is directly electrically connected to the first port, or each of the sequential logic devices is electrically connected to the first port through at least one combinational logic device, and N is a positive integer; Determine, based on the N sequential logic devices and the module clock information, at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object; determining a port type of the first port; A port delay of the first port is set according to the port type, the at least one clock object and the at least one object information.

2. The method according to claim 1, in, Acquiring N sequential logic devices corresponding to the first port, including: In response to the first port not being used to input a clock signal, the N sequential logic devices are determined from at least one sequential logic device included in a module to which the first port belongs.

3. The method according to claim 1, in, Obtaining module clock information corresponding to the module to which the first port belongs, including: Determine at least one sequential logic device included in the module to which the first port belongs; At least one device clock information corresponding to the at least one sequential logic device is acquired, wherein the module clock information includes the at least one device clock information.

4. The method according to claim 3, in, Determining at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object based on the N sequential logic devices and the module clock information, including: Based on the module clock information, determine N device clock information corresponding to the N sequential logic devices one by one; The at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object are determined according to the N device clock information.

5. The method according to claim 4, in, Each device clock information includes trigger edge information, Determining, according to the N device clock information, the at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object, comprising: Determine N clock objects according to the N device clock information; Determining the at least one clock object from the N clock objects, wherein the at least one clock object is different from each other; For each clock object of the at least one clock object: Determine at least one trigger edge information corresponding to each clock object according to the N device clock information, Based on the at least one trigger edge information, phase information corresponding to each clock object is determined, wherein the object information corresponding to each clock object includes the phase information corresponding to each clock object.

6. The method according to claim 5, in, The trigger edge information includes a first trigger edge or a second trigger edge, Determining phase information corresponding to each clock object based on the at least one trigger edge information includes: In response to the at least one trigger edge information being the first trigger edge or the second trigger edge, determining that the phase information corresponding to each clock object is the first phase, In response to the existence of both the first trigger edge and the second trigger edge in the at least one trigger edge information, it is determined that the phase information corresponding to each clock object is the second phase.

7. The method according to any one of claims 1 to 6, in, Setting a port delay of the first port according to the port type, the at least one clock object, and the at least one object information includes: Determining a delay coefficient according to the port type; For each clock object, according to the port type, the delay coefficient, and the object information of each clock object, setting a clock delay for each clock object for the first port, The port delay of the first port includes at least one clock delay corresponding to each of the at least one clock objects.

8. The method according to claim 7, in, The port types include input ports and output ports. Determine a delay coefficient according to the port type, including: In response to the first port being an input port, setting the delay coefficient to an input delay coefficient; In response to the first port being an output port, setting the delay coefficient to an output delay coefficient, The input delay coefficient is represented by P, the output delay coefficient is represented by Q, both P and Q are positive numbers, and the sum of P and Q is greater than 1 and less than 2.

9. The method according to claim 8, in, Each object information includes clock cycle and phase information. For each clock object, according to the port type, the delay coefficient, and the object information of each clock object, setting a clock delay for each clock object for the first port includes: Determine a delay adjustment parameter corresponding to each clock object based on the phase information corresponding to each clock object; In response to the first port being an input port, the clock delay of the first port for each clock object is set based on the input delay coefficient, the delay adjustment parameter and the clock period of each clock object, wherein the clock delay of each clock object is the product of the clock period of each clock object, the delay adjustment parameter and the input delay coefficient. In response to the first port being an output port, the clock delay of the first port for each clock object is set based on the output delay coefficient, the delay adjustment parameter and the clock period of each clock object, wherein the clock delay of each clock object is the product of the clock period of each clock object, the delay adjustment parameter and the output delay coefficient.

10. The method according to claim 9, in, The phase information includes a first phase and a second phase, Determining a delay adjustment parameter corresponding to each clock object based on the phase information corresponding to each clock object includes: In response to the phase information of the i-th clock object being the first phase, determining the delay adjustment parameter of the i-th clock object to be 1; In response to the phase information of the i-th clock object being the second phase, determining the delay adjustment parameter of the i-th clock object to be 1 / 2, Wherein, i is a positive integer and is less than or equal to the total number of the at least one clock object.

11. The method according to any one of claims 1 to 6, in, All the ports also include at least one second port, each second port having preset port constraint information, The method further comprises: For each of the second ports, the preset port constraint information of each of the second ports is used as the port delay of each of the second ports.

12. The method according to any one of claims 1 to 6, further comprising: include: In response to the at least one clock object being a plurality of clock objects, determining at least one pseudo timing path, and not performing a timing check on the at least one pseudo timing path, The at least one pseudo timing path includes a timing path starting from the i-th clock object, passing through the first port, and ending at the j-th clock object. Wherein, i and j are positive integers and are less than or equal to the total number of the multiple clock objects, and i and j are different.

13. A port delay constraint device, used in the design of integrated circuits, in, The integrated circuit includes a plurality of modules, each module includes at least one sequential logic device and at least one port, The device comprises a port acquisition unit and a processing unit. The port acquisition unit is configured to acquire all ports in the multiple modules, wherein the all ports include multiple first ports; The processing unit includes an information acquisition subunit, a clock information determination subunit, a port type determination subunit and a port delay setting subunit. For each first port of the plurality of first ports: The information acquisition subunit is configured to acquire module clock information corresponding to N sequential logic devices corresponding to the first port and a module to which the first port belongs, wherein each of the N sequential logic devices is directly electrically connected to the first port, or each of the sequential logic devices is electrically connected to the first port through at least one combinational logic device, and N is a positive integer; The clock information determination subunit is configured to determine at least one clock object associated with the first port and at least one object information respectively corresponding to the at least one clock object based on the N sequential logic devices and the module clock information; The port type determination subunit is configured to determine the port type of the first port; The port delay setting subunit is configured to set the port delay of the first port according to the port type, the at least one clock object and the at least one object information.

14. An electronic device, include: A memory non-transitorily stores computer executable instructions; a processor configured to execute the computer executable instructions, Wherein, when the computer executable instructions are executed by the processor, the port delay constraint method according to any one of claims 1-12 is implemented.

15. A non-transitory computer-readable storage medium, in, The non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the port delay constraint method according to any one of claims 1 to 12 is implemented.

Images