Semiconductor device

Abstract

The present invention discloses a semiconductor device. A semiconductor device includes: an n-type layer disposed on a first surface of an n+-type silicon carbide substrate; a first trench and a second trench formed in the n-type layer and separated from each other; an n+-type region disposed between side surfaces of the first trench and the second trench and disposed on the n-type layer; a gate insulating layer disposed in the first trench; a source insulating layer disposed in the second trench; a gate disposed on the gate insulating layer; an oxide layer disposed on the gate; a source disposed on the oxide layer, the n+-type region, and the source insulating layer; and a drain disposed on a second surface of the n+-type silicon carbide substrate.

Description

[0001] This application is a divisional application, and the application number of its parent application is 2016110315721, the application date is November 22, 2016, and the invention title is "Semiconductor Device and Method of Manufacturing the Same".

[0002] Citation of Related Applications

[0003] This application claims the priority benefit of Korean Patent Application No. 10-2016-0084838, filed on July 5, 2016, with the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference. Technical Field

[0004] The present disclosure relates to a semiconductor device including silicon carbide (SiC) and a method of manufacturing the same. Background Art

[0005] In order to reduce power loss in a conductive state when a large current flows, a power semiconductor device should have a low on-resistance or a low saturation voltage. In addition, the power semiconductor device should have a characteristic in which its PN junction withstands a reverse high voltage, which may be applied to opposite ends of the power semiconductor device when the power semiconductor device is turned off or when a switch is turned off, that is, the power semiconductor device should have a characteristic of a high breakdown voltage.

[0006] When various power semiconductor devices that satisfy electrical conditions and physical conditions are packaged into one module, the number of semiconductor devices included in the packaged module and their electrical specifications may be changed according to conditions required by a system.

[0007] Generally, a three-phase power semiconductor module is used to generate a Lorentz force for driving a motor. That is, the three-phase power semiconductor module controls current and power applied to the motor so that a driving state of the motor is determined.

[0008] Although conventional silicon insulated gate bipolar transistors (IGBTs) and silicon diodes have been included and used in such three-phase semiconductor modules, the three-phase semiconductor modules recently tend to include silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) and silicon carbide diodes to minimize power consumption therein and increase their switching speed.

[0009] When a silicon IGBT or a silicon carbide MOSFET is connected to a separate diode, a plurality of wirings are required for connection, and since parasitic capacitance and inductance occur due to the plurality of wirings, the switching speed of the module may be reduced.

[0010] The above information disclosed in this background section is only for enhancing the understanding of the background art of the present disclosure, and thus the present disclosure may include information that is not prior art known to those of ordinary skill in the art in this country. Summary of the Invention

[0011] The present disclosure is directed to providing a silicon carbide semiconductor device including a MOSFET region and a diode region.

[0012] According to an exemplary embodiment of the present disclosure, the semiconductor device includes: an n-type layer disposed on a first surface of an n+-type silicon carbide substrate; a first trench and a second trench formed in the n-type layer and separated from each other; an n+-type region disposed between side surfaces of the first trench and side surfaces of the second trench and disposed on the n-type layer; a gate insulating layer disposed inside the first trench; a source insulating layer disposed inside the second trench; a gate disposed on the gate insulating layer; an oxide layer disposed on the gate; a source disposed on the oxide layer, the n+-type region, and the source insulating layer; and a drain disposed on a second surface of the n+-type silicon carbide substrate.

[0013] It may further include a p-type region disposed on two side surfaces of the second trench.

[0014] The p-type region may be disposed between a side surface of the second trench and the n-type layer.

[0015] The p-type region may surround a corner of the second trench and may extend under the corner of the second trench.

[0016] The n+-type region may be disposed on a part of the p-type region and the n-type layer.

[0017] Another part of the p-type region may be disposed between the n+-type region and a side surface of the second trench.

[0018] The source insulating layer and the gate insulating layer may include the same material, and the thickness of the source insulating layer may be thinner than the thickness of the gate insulating layer.

[0019] The source may include a first source and a second source. The first source may be located on the source insulating layer, and the second source may be disposed on the n+-type region, a part of the p-type region, the oxide layer, and the first source.

[0020] The first source and the gate may include polysilicon, and the second source and the drain may include ohmic metal.

[0021] The gate may include polysilicon, and the first source, the second source, and the drain may include ohmic metal.

[0022] The gate insulating layer and the source insulating layer may include the same material, and the thicknesses of the gate insulating layer and the source insulating layer may be the same.

[0023] According to another exemplary embodiment in the present disclosure, a method for manufacturing a semiconductor device includes the following steps: forming an n-type layer at a first surface of an n+-type silicon carbide substrate; forming an n+-type region on the n-type layer; etching the n+-type region and the n-type layer to form a first trench and a second trench separated from each other; forming a gate insulating layer in the first trench; forming a source insulating layer in the second trench; forming a gate on the gate insulating layer; forming an oxide layer on the gate; forming a source on the oxide layer, the n+-type region, and the source insulating layer; and forming a drain at a second surface of the n+-type silicon carbide substrate.

[0024] The method for manufacturing a semiconductor device may further include: implanting p-type ions into a side surface of the second trench before the step of forming the source insulating layer to form a p-type region between the side surface of the second trench and the n-type layer.

[0025] A part of the p-type region may be formed under the n+-type region, and another part of the p-type region may be formed between the n+-type region and the side surface of the second trench.

[0026] In the step of forming the p-type region, the p-type ions may be implanted by an inclined ion implantation method.

[0027] As described above, according to the exemplary embodiment in the present disclosure, when the semiconductor device according to this exemplary embodiment performs MOSFET operation and diode operation, there is no need for wiring connecting a conventional MOSFET element and a conventional diode element. Therefore, the area of the element can be reduced.

[0028] In addition, when a semiconductor device performs MOSFET operation and diode operation without wiring, the switching speed of the semiconductor device can be increased and the power loss can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A layout diagram of a semiconductor device according to an exemplary embodiment in the present disclosure is shown.

[0030] Figure 2 Shows along Figure 1 A cross-sectional view taken along line II-II is shown.

[0031] Figure 3 Shows along Figure 1 A cross-sectional view taken along line III-III is shown.

[0032] Figure 4 Is a view showing Figure 1 The off state of the semiconductor device shown in.

[0033] Figure 5 Is a view showing Figure 1View of the operating state of the MOSFET of the semiconductor device shown in

[0034] Figure 6 is a view showing Figure 1 the operating state of the semiconductor device shown in

[0035] Figures 7 to 11 is a view showing Figure 1 an example of the manufacturing method of the semiconductor device of

[0036] Figure 12 is a cross-sectional view of an example of a semiconductor device according to another exemplary embodiment of the present disclosure. Detailed Description

[0037] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, it should be understood that the present disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications. As those skilled in the art should recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0038] In the drawings, for clarity, the thicknesses of layers, films, panels, regions, etc. are enlarged. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or intervening elements may also be present.

[0039] Figure 1 A layout diagram of a semiconductor device according to an exemplary embodiment of the present disclosure is shown. Figure 2 Shows along Figure 1 a cross-sectional view taken along line II-II of Figure 3 Shows along Figure 1 a cross-sectional view taken along line III-III of

[0040] Referring to Figures 1 to 3 , the semiconductor device according to this exemplary embodiment includes a MOSFET (Metal Oxide Silicon Field Effect Transistor) region A and a diode region B.

[0041] The detailed structure of the semiconductor device according to this exemplary embodiment will be described.

[0042] The semiconductor device according to this exemplary embodiment includes an n+-type silicon carbide substrate 100, an n-type layer 200, an n+-type region 300, a p-type region 400, a gate 600, a source 700, and a drain 800.

[0043] The n-type layer 200 is disposed on the first surface of the n+-type silicon carbide substrate 100, and the first trench 210 and the second trench 220 separated from each other are positioned in the n-type layer 200.

[0044] The p-type region 400 is disposed at both sides of the second trench 220. The p-type region 400 is disposed between the side surface of the second trench 220 and the n-type layer 200. The p-type region 400 surrounds the corner of the second trench 220 and extends to the bottom of the corner of the second trench 220. With this structure, the electric field is concentrated at the bottom of the p-type region 400, thus preventing the electric field from concentrating at the turning of the second trench 220. On the other hand, the p-type region 400 does not exist below the lower surface of the second trench 220.

[0045] The n+-type region 300 is disposed between the side surface of the first trench 210 and the side surface of the second trench 220, and is disposed on the n-type layer 200. In addition, the n+-type region 300 is disposed on a part of the p-type region 400 (refer to Figure 2 ). Another part of the p-type region 400 is disposed between the n+-type region 300 and the side surface of the second trench 220. In this case, the extension line of the upper surface of the other part of the p-type region 400 is the same as the extension line of the upper surface of the n+-type region 300 (refer to Figure 3 ).

[0046] The gate insulating layer 510 is disposed in the first trench 210, and the source insulating layer 520 is disposed in the second trench 220. The gate insulating layer 510 and the source insulating layer 520 may include the same material, and the thickness of the source insulating layer 520 may be thinner than the thickness of the gate insulating layer 510. With the structure in which the p-type region 400 surrounds the corner of the second trench 220 so that the thickness of the source insulating layer 520 can be formed to be thinner than the thickness of the gate insulating layer 510, the electric field can be prevented from concentrating at the turning of the second trench 220. However, it is not limited thereto, and the thickness of the source insulating layer 520 may be the same as the thickness of the gate insulating layer 510.

[0047] The gate 600 is disposed on the gate insulating layer 510. The gate 600 fills the inside of the first trench 210 and may protrude to the upper side of the first trench 210. The gate 600 may include polysilicon or metal.

[0048] The oxide layer 530 is disposed on the gate 600. The oxide layer 530 covers the side surface of the gate 600 protruding from the first trench 210.

[0049] The source electrode 700 is disposed on the n+-type region 300, a portion of the p-type region 400, the oxide layer 530, and the source insulating layer 520, and includes a first source electrode 710 and a second source electrode 720. The first source electrode 710 is disposed on the source insulating layer 520 and fills the interior of the second trench 220. The second source electrode 720 is disposed on the n+-type region 300, a portion of the p-type region 400, the oxide layer 530, and the first source electrode 710.

[0050] In this document, the first source electrode 710 may include polysilicon and the second source electrode 720 may include metal. In this case, the metal may be an ohmic metal. Additionally, in the present exemplary embodiment, it is described that the first source electrode 710 and the second source electrode 720 include different materials, however, without limitation thereto, the first source electrode 710 and the second source electrode 720 may include the same metal. In this case, the metal may be an ohmic metal.

[0051] The drain electrode 800 is disposed on the second surface of the n+-type silicon carbide substrate 100. In this document, the second surface of the n+-type silicon carbide substrate 100 refers to the surface opposite to the first surface of the n+-type silicon carbide substrate 100. The drain electrode 800 may include metal. In this case, the metal may be an ohmic metal.

[0052] Reference Figure 2 , the source electrode 700, the gate electrode 600, the n+-type region 300, the n-type layer 200, the n+-type silicon carbide substrate 100, and the drain electrode 800 form the MOSFET region A, and the source electrode 700, the n+-type region 300, the p-type region 400, the n-type layer 200, the n+-type silicon carbide substrate 100, and the drain electrode 800 form the diode region B.

[0053] In the semiconductor device according to the present exemplary embodiment, the operation of the MOSFET and the operation of the diode are implemented. In this case, the operation of the MOSFET and the operation of the diode region may be separately performed according to the voltage application state.

[0054] Reference will be made to Figures 4 to 6 to describe the operation of the semiconductor device.

[0055] Figures 4 to 6 is Figure 1 a schematic view of the operation of the semiconductor device.

[0056] Figure 4 is a view showing Figure 1 the off state of the semiconductor device shown in Figure 5 is a view showing Figure 1 the operating state of the MOSFET of the semiconductor device shown in Figure 6 is a view showing Figure 1 the operating state of the semiconductor device shown in

[0057] The off-state of the semiconductor device is executed under the following conditions.

[0058] V GS < V TH , V DS ≥ 0V

[0059] The operation of the MOSFET of the semiconductor device is executed under the following conditions.

[0060] V GS ≥ V TH , V DS > 0V

[0061] The operating state of the semiconductor device is executed under the following conditions.

[0062] V GS < V TH , V DS < 0V

[0063] Here, V TH is the threshold voltage of the MOSFET, V GS is V G - V S , and V DS is V D - V S . V G is the voltage applied to the gate, V D is the voltage applied to the drain, and V S is the voltage applied to the source.

[0064] Refer to Figure 4 , a depletion layer 50 is formed at the n-type layer 200 so that no electron current flows in the off-state of the semiconductor device. In this case, the depletion layer 50 is formed between the first trench 210 and the second trench 220, and below the second trench 220, and is arranged to cover the entire p-type region 400.

[0065] Refer to Figure 5 , during the operation of the MOSFET of the semiconductor device, electrons (e-) migrate from the source 700 to the drain 800. Here, the electrons (e-) emitted from the source 700 migrate through the n-type layer 200 to the drain 800.

[0066] During the operation of the MOSFET of the semiconductor device, the depletion layer 50 decreases due to the voltage applied to the gate 600. That is, the depletion layer 50 is formed below the second trench 220 and between the first trench 210 and the second trench 220 to cover the entire p-type region 400, but is not formed at the side surface of the first trench 210. Therefore, electrons (e-) migrate to the side surface of the first trench 210.

[0067] Reference Figure 6 During the operation of the diode of the semiconductor device, electrons (e-) migrate from the drain 800 to the source 700. The drain 800 serves as the negative electrode and the source 700 serves as the positive electrode. Here, the electrons (e-) emitted from the drain 800 migrate to the source 700 through the n-type layer 200 and the p-type region 400.

[0068] A channel is formed at the p-type region 400 so that the movement path of the electrons (e-) is ensured during the operation of the diode of the semiconductor device. Here, the channel is an inversion layer channel. A depletion layer 50 is formed between the first trench 210 and the second trench 220, below the p-type region 400, and below the first trench 210, but not below the second trench 220. That is, the electrons (e-) migrate into the junction portion of the n-type layer 200 and the p-type region 400 below the second trench 220.

[0069] As described above, the semiconductor device according to the present exemplary embodiment performs the operations of the MOSFET and the diode so that the wirings connecting the conventional MOSFET element and the conventional diode element are not required. Therefore, the area of the semiconductor device can be reduced.

[0070] In addition, since the semiconductor device performs the operations of the MOSFET and the diode without wirings, the switching speed of the semiconductor device can be increased and the power loss can be reduced.

[0071] Next, with reference to Table 1, the semiconductor device according to the present exemplary embodiment will be described by comparing the characteristics of a general diode element and a general MOSFET element.

[0072] Table 1 shows the simulation results of the semiconductor device according to the present exemplary embodiment, and a general diode element and a general MOSFET element.

[0073] Comparative Example 1 is a general junction barrier Schottky (JBS) diode element, and Comparative Example 2 is a general MOSFET element. Comparative Example 3 is a general Schottky barrier diode (SBD) element.

[0074] In Table 1, the breakdown voltages of the semiconductor device according to the present exemplary embodiment and the semiconductor devices according to Comparative Example 1, Comparative Example 2, and Comparative Example 3 are controlled to be almost equal and the current densities are compared.

[0075] [Table 1]

[0076]

[0077] Referring to Table 1, the current-carrying area for a current of 100 A is shown as 0.579 cm in the JBS diode element according to Comparative Example 1 2 , and a current-carrying area of 0.126 cm is obtained for the MOSFET element according to Comparative Example 2 2 . The sum of the current-carrying areas for a current of 100 A of the semiconductor devices according to Comparative Example 1 and Comparative Example 2 is 0.705 cm 2 .

[0078] In the SBD element according to Comparative Example 3, the current-carrying area for a current of 100 A is shown as 0.391 cm during diode operation 2 . The sum of the current-carrying areas for a current of 100 A of the semiconductor devices according to Comparative Example 2 and Comparative Example 3 is 0.517 cm 2 .

[0079] In the case of the semiconductor device according to the exemplary embodiment, the current-carrying area for a current of 100 A is shown as 0.385 cm 2 .

[0080] That is, as the current-carrying area for a current of 100 A, it can be confirmed that the area of the semiconductor device according to the exemplary embodiment is reduced by 45.4% compared to the total area of Comparative Examples 1 and 2. Additionally, it can be confirmed that the area of the semiconductor device according to the exemplary embodiment is reduced by 25.5% compared to the total area of Comparative Examples 2 and 3

[0081] Next, reference will be made to Figures 7 to 11 as well as Figure 2 and Figure 3 to describe the manufacturing method of the semiconductor device according to Figure 1 .

[0082] Figures 7 to 11 is a view showing an example of a method of manufacturing the semiconductor device according to Figure 1 .

[0083] Referring to Figure 7 , after preparing the n+-type silicon carbide substrate 100 and forming the n-type layer 200 in the first surface of the n+-type silicon carbide substrate 100, an n+-type region 300 is formed on the n-type layer 200. The n-type layer 200 can be formed by epitaxial growth or n-ion implantation. The n+-type region 300 can also be formed by epitaxial growth or n-ion implantation

[0084] Referring to Figure 8 , the n+-type region 300 and the n-type layer 200 are etched to form the first trench 210 and the second trench 220. In this case, the first trench 210 and the second trench 220 are formed simultaneously

[0085] Reference Figure 9 The side surface of the p-type ion implantation second trench 220 forms a p-type region 400 between the side surface of the second trench 220 and the n-type layer 200. Therefore, the p-type region 400 surrounds the corner of the second trench 220 and extends to the bottom of the corner of the second trench 220. On the other hand, the p-type region 400 is not formed below the lower surface of the second trench.

[0086] In this case, a part of the p-type region 400 is positioned below the n+-type region 300 (reference Figure 2 ), and another part of the p-type region 400 is positioned between the n+-type region 300 and the second trench 220 (reference Figure 3 ). Here, the p-type ions are implanted by an inclined ion implantation method. The inclined ion implantation method is an ion implantation method in which the ion implantation angle is less than a right angle with respect to the horizontal plane.

[0087] Reference Figure 10 A gate insulating layer 510 is formed in the first trench 210, and a source insulating layer 520 is formed in the second trench 220.

[0088] The materials of the gate insulating layer 510 and the source insulating layer 520 may be the same, and the thickness of the source insulating layer 520 may be thinner than the thickness of the gate insulating layer 510. However, it is not limited thereto, and the thickness of the source insulating layer 520 may be the same as the thickness of the gate insulating layer 510.

[0089] Reference Figure 11 A gate 600 is formed on the gate insulating layer 510, and a first source 710 is formed on the source insulating layer 520.

[0090] The gate 600 fills the first trench 210 and may protrude to the upper side of the first trench 210. The gate 600 may be formed of polysilicon or metal.

[0091] The first source 710 fills the second trench 220 and may be formed of polysilicon.

[0092] Next, an oxide layer 530 is formed on the gate 600. The oxide layer 530 is formed to cover the side surface of the gate 600 protruding from the first trench 210.

[0093] Reference Figure 2 and Figure 3 A second source 720 is formed on the n+-type region 300, a part of the p-type region 400, the oxide layer 530, and the first source 710, and a drain 800 is formed at the second surface of the n+-type silicon carbide substrate 100. Here, the second source 720 and the drain 800 may be formed of metal. In this case, the metal may be ohmic metal.

[0094] In the present exemplary embodiment, the first source electrode 710 and the second source electrode 720 are formed of different materials in the manufacturing method of the semiconductor device, but are not limited thereto, and the first source electrode 710 and the second source electrode 720 may be formed of the same metal material. In this case, the metal may be an ohmic metal. In this case, after forming the gate electrode 600 on the gate insulating layer 510 and forming the oxide layer 530 on the gate electrode 600, the source electrode 700 may be formed on the n+-type region 300, a part of the p-type region 400, the oxide layer 530, and the source insulating layer 520.

[0095] In the manufacturing method of the semiconductor device according to the present exemplary embodiment, the p-type region 400 is formed after simultaneously forming the first trench 210 and the second trench 220, but the present disclosure is not limited thereto, and the p-type region 400 may be formed and then the first trench 210 may be formed after first forming the second trench 220.

[0096] The semiconductor device according to the present exemplary embodiment includes the p-type region 400, but the present disclosure is not limited thereto, and the p-type region 400 may be omitted.

[0097] Next, reference will be made to Figure 12 describe a semiconductor device according to another exemplary embodiment of the present disclosure.

[0098] Figure 12 is a cross-sectional view of an example of a semiconductor device according to another exemplary embodiment of the present disclosure.

[0099] Reference Figure 12 , the semiconductor device according to the present exemplary embodiment has the same structure as the semiconductor device shown in Figure 1 except that the p-type region is omitted. Therefore, the description of the same structure is omitted.

[0100] The semiconductor device according to the present exemplary embodiment includes a MOSFET region A and a diode region B adjacent to each other.

[0101] The source electrode 700, the gate electrode 600, the n+-type region 300, the n-type layer 200, the n+-type silicon carbide substrate 100, and the drain electrode 800 form the MOSFET region A, and the source electrode 700, the n+-type region 300, the n-type layer 200, the n+-type silicon carbide substrate 100, and the drain electrode 800 form the diode region B.

[0102] In the semiconductor device according to the present exemplary embodiment, compared with the one according to Figure 1Compared with the semiconductor device, omitting the p-type region allows the n-type layer 200 to be disposed on two sides of the second trench 220. The n+-type region 300 is disposed between the first trench 210 and the second trench 220 and on the n-type layer 200. The source electrode 700 is disposed on the n+-type region 300, the oxide layer 530, and the source insulating layer 520.

[0103] The thickness of the gate insulating layer 510 disposed in the first trench 210 may be the same as the thickness of the source insulating layer 520 disposed in the second trench 220.

[0104] The semiconductor device according to the present exemplary embodiment performs similar Figure 1 MOSFET (Metal Oxide Semiconductor Field Effect Transistor) operation and diode operation of the semiconductor device.

[0105] The conditions of the off state, the MOSFET operation state, and the diode operation state of the semiconductor device according to the present exemplary embodiment are the same as those of the semiconductor device according to Figure 1 the semiconductor device.

[0106] However, compared with the Figure 1 semiconductor device, omitting the p-type region causes the depletion layer 50 to be formed between the first trench 210 and the second trench 220 and below the second trench 220 during the off state of the semiconductor device.

[0107] During the operation of the MOSFET of the semiconductor device, the depletion layer 50 is formed between the first trench 210 and the second trench 220 and below the second trench 220, but not on the side and below the first trench 210. Therefore, electrons (e-) migrate from the source electrode 700 to the drain electrode 800 through the n-type layer 200 on the side of the first trench 210.

[0108] During the diode operation of the semiconductor device, the depletion layer 50 is formed between the first trench 210 and the second trench 220 and below the first trench 210, but not on the side and below the second trench 220. Therefore, electrons (e-) migrate from the drain electrode 800 to the source electrode 700 through the n-type layer 200 on the side of the second trench 220. That is, different from the diode operation of the semiconductor device according to Figure 1 the semiconductor device, electrons (e-) migrate through the n-type layer 200 without a depletion layer instead of through the channel formed in the p-type region 400.

[0109] Although the present invention has been described in connection with presently considered practical exemplary embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: An n-type layer disposed on a first surface of an n+-type silicon carbide substrate; A first trench and a second trench formed in the n-type layer and separated from each other; An n+-type region disposed between side surfaces of the first trench and side surfaces of the second trench, and the n+-type region is disposed on the n-type layer; A gate insulating layer disposed in the first trench; A source insulating layer disposed in the second trench; A gate disposed on the gate insulating layer; An oxide layer disposed on the gate; A source disposed on the oxide layer, the n+-type region, and the source insulating layer; A drain disposed on a second surface of the n+-type silicon carbide substrate; And A p-type region disposed on two side surfaces of the second trench and not existing below a lower surface of the second trench, Wherein the p-type region is disposed between a side surface of the second trench and the n-type layer, Wherein the p-type region surrounds a corner of the second trench and extends below the corner of the second trench, Wherein a thickness of the source insulating layer is thinner than a thickness of the gate insulating layer.

2. The semiconductor device according to claim 1, wherein, The n+-type region is disposed on a first portion of the p-type region and the n-type layer.

3. The semiconductor device according to claim 2, wherein, A second portion of the p-type region is disposed between a side surface of the second trench and the n+-type region.

4. The semiconductor device according to claim 3, wherein, The source insulating layer and the gate insulating layer comprise the same material.

5. The semiconductor device according to claim 4, wherein, The source comprises a first source and a second source, The first source is disposed on the source insulating layer, and The second source is disposed on the n+-type region, a part of the p-type region, the oxide layer, and the first source.

6. The semiconductor device according to claim 5, wherein, The first source and the gate comprise polysilicon, and The second source and the drain comprise ohmic metal.

7. The semiconductor device according to claim 5, wherein, The gate comprises polysilicon, and The first source, the second source, and the drain comprise ohmic metal.

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