Nitride semiconductor substrate and method for manufacturing the same

Abstract

[Problem] When epitaxially growing a nitride semiconductor layer on a silicon single crystal substrate, distortion occurs due to lattice mismatch and differences in thermal expansion coefficients, leading to significant warping and cracking, which hinder device production. Another problem is the inability to obtain a nitride semiconductor with good crystallinity. [Solution] Distortion due to lattice mismatch generated during epitaxial growth of a nitride semiconductor onto a silicon single crystal substrate and thermal distortion due to differences in thermal expansion coefficients occurring during the cooling process after epitaxial growth are mitigated not only by a buffer layer in the nitride semiconductor but also by a misfit dislocation layer formed parallel to the surface of the silicon single crystal substrate. This results in a nitride semiconductor substrate with excellent crystallinity without cracking or significant warping.

Description

Technical Field

[0001] The present invention relates to a silicon substrate for manufacturing a nitride semiconductor substrate, represented by, for example, a GaN-on-Si wafer, in which a nitride semiconductor is epitaxially grown on a silicon single crystal substrate (hereinafter referred to as a silicon substrate), and to a semiconductor substrate in which a nitride semiconductor is epitaxially grown on this substrate. Background Art

[0002] Nitride single crystals are widely used as semiconductor substrates, where nitride semiconductors are epitaxially grown on inexpensive silicon or sapphire substrates. This is because nitride single crystals are extremely difficult to grow from a liquid phase. However, when thick nitride semiconductor layers are grown on silicon or sapphire substrates, differences in lattice constants and thermal expansion coefficients generate stress, leading to dislocations and warping. Especially when using silicon substrates, there is a problem of increased dislocation density in the nitride semiconductor layer, which degrades the electrical performance of the device. Furthermore, there is the problem of increased substrate warpage, which inhibits wafer handling in semiconductor devices and can cause cracks in the nitride semiconductor epitaxial layer.

[0003] As a measure to address substrate warpage, Patent Document 1 describes a method of increasing the thickness of a silicon substrate. Using a thick substrate with a thickness of up to approximately 1 mm reduces warpage and allows for handling within the manufacturing line used in device fabrication. A method is also described of suppressing increased warpage by doping the silicon substrate with high concentrations of impurities to harden the substrate through solidification of the impurities.

[0004] Patent Document 2 also discloses a method for suppressing warpage and cracking by applying a thin film of a material with a lower thermal expansion coefficient than silicon to the backside of a silicon substrate. However, this method suffers from the problem of slip dislocations occurring when high thermal stress is applied to the silicon substrate at high temperatures. Therefore, at low temperatures, the scope for suppressing cracking by reducing warpage in nitride semiconductor substrates is limited.

[0005] When epitaxially growing a nitride semiconductor on a silicon substrate, a widely used method involves forming a buffer layer within the nitride semiconductor layer. This buffer layer mitigates the lattice mismatch between the substrate and the epitaxial layer by introducing misfit dislocations while effectively suppressing the propagation of dislocations toward the surface, and then epitaxially growing gallium nitride. The buffer layer also mitigates thermal stress caused by the difference in thermal expansion coefficient between the nitride semiconductor and the silicon crystal during cooling to room temperature after epitaxial growth. These two roles of the buffer layer are currently incompatible.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Publication No. 2014-192246

[0009] Patent Document 2: Japanese Patent Publication No. 2010-272781

[0010] Non-patent literature

[0011] Non-patent document 1: Takao Abe, "Silicon" (Crystal Growth and Wafer Processing), Baifukan (Baifukan), (1994), p. 17, Figure 2 .5 and page 45, Figure 3 .twenty two

[0012] Non-patent document 2: Yoshimitsu Sugita, Journal of the Crystallographic Society of Japan, 12, (1970), p. 100 Summary of the Invention

[0013] Problems to be solved by the present invention

[0014] As described above, when nitride semiconductors are epitaxially grown on silicon substrates, several methods have been proposed to mitigate the high stress and resulting warpage generated at the interface between the epitaxial layer and the silicon substrate due to lattice constant mismatch or differences in thermal expansion coefficients. However, when silicon substrates are used as substrates for epitaxial growth of nitride semiconductors, warpage is more problematic than when sapphire substrates are used. Furthermore, the dislocation density in the surface of nitride semiconductor layers is approximately an order of magnitude higher than when sapphire substrates are used. Consequently, silicon substrates have not yet gained widespread use.

[0015] The reason for using silicon wafers as substrates for epitaxial growth of nitride semiconductors is to increase the substrate diameter to reduce costs. Sapphire substrates are mostly 2 or 3 inches in diameter, while silicon substrates are mostly 6 inches in diameter. However, as the diameter of the wafer increases, it becomes more difficult to address the warpage problem. If the wafer warpage increases, the equipment will not be able to handle the wafer during the device manufacturing process, and cracks will occur.

[0016] Since the difference in lattice constant between gallium nitride and silicon is large, epitaxial growth of gallium nitride is performed after forming a buffer layer. Inside the buffer layer, lattice distortion is mitigated by introducing a high density of misfit dislocations. Most misfit dislocations are edge dislocations extending parallel to the epitaxial interface, and thus limit dislocations extending toward the surface. Various efforts have been made to prevent misfit dislocations from extending toward the surface by periodically and sharply changing the composition of gallium or aluminum, or nitride buffer layers with graded group III element compositions. The buffer layer not only mitigates lattice distortion, but also mitigates thermal distortion caused by its misfit dislocations due to differences in thermal expansion coefficients during cooling after epitaxial growth.

[0017] The buffer layer is ideally suited to suppress warping due to differences in thermal expansion coefficients that occur during cooling to room temperature after epitaxial growth. This is because if wafer warpage becomes greater, device fabrication becomes impossible. Another reason is that when cracks develop in the nitride semiconductor layer, the cracks can lead to the generation of foreign matter, significantly reducing process yield. In sapphire substrates, which are less prone to cracking and warping, the buffer layer's role in mitigating thermal distortion is reduced. Consequently, using a sapphire substrate reduces the dislocation density in the nitride semiconductor in the region where the device is to be formed by approximately an order of magnitude compared to using a silicon substrate.

[0018] One reason for the desire to use silicon wafers as substrates for epitaxial growth of nitride semiconductors is the goal of finding a way to actually use high-performance, high-voltage transistors by utilizing the superior properties of gallium nitride. Although the actual use of such transistors has begun, problems associated with crystal quality (such as current collapse) remain to be fully resolved. In addition to resolving the warpage problem, it is also desirable to improve the crystallinity of the nitride semiconductor layer. Although some attempts have been made to manufacture LEDs using GaN-on-Si wafers, the dislocation density in gallium nitride crystals is high and their emission efficiency is low, and therefore the advantages of using large-diameter wafers have not yet been exploited, and silicon wafers have not yet surpassed sapphire substrates.

[0019] In epitaxial wafers widely used for LEDs (in which nitride semiconductors are grown on sapphire substrates), compressive stress is applied to the nitride semiconductor film after cooling because the nitride semiconductor has a thermal expansion coefficient 15% smaller than that of sapphire. Therefore, cracks are less likely to occur. Since small-diameter substrates of 2 to 3 inches are widely used, warpage is minimal and rarely a concern. Therefore, the buffer layer can be optimized to prevent an increase in the density of threading dislocations extending toward the surface, focusing on mitigating lattice distortion.

[0020] In contrast, when a nitride semiconductor is epitaxially grown on a silicon substrate, warping and cracking due to tensile stress become a problem, as nitride semiconductors have a thermal expansion coefficient 60% or greater than that of silicon. Lattice distortion needs to be mitigated, with priority given to mitigating thermal distortion that occurs during cooling to room temperature. Therefore, a high density of misfit dislocations needs to be introduced into the buffer layer, which in turn increases the density of threading dislocations extending toward the top of the buffer layer.

[0021] Solutions to the Problem

[0022] The following discussion relates to a wafer in which gallium nitride crystals are epitaxially grown on a silicon substrate, so-called GaN-on-Si.

[0023] Conventionally, in the manufacture of nitride semiconductor substrates, distortion associated with the lattice constant mismatch between silicon and gallium nitride crystals, as well as thermal distortion due to differences in thermal conductivity that occur during cooling after epitaxial growth, is mitigated by forming a buffer layer composed of aluminum nitride, gallium nitride, or mixed crystals within the gallium nitride substrate. The present invention is characterized in that both of these types of distortion are also mitigated within the silicon substrate, enabling the reduction of the density of threading dislocations in the gallium nitride layer overlying the buffer layer, and the manufacture of a gallium nitride substrate free of cracks and significant warpage.

[0024] To improve the crystallinity quality of a gallium nitride layer epitaxially grown on a silicon substrate while preventing the generation of cracks and large warpage, the inventors devised a method for manufacturing gallium nitride epitaxial wafers with small warpage and good crystallinity by inducing misfit dislocations in the silicon substrate to mitigate lattice distortion occurring in the interface with the silicon substrate and from the silicon side during gallium nitride epitaxial growth, and to mitigate thermal stress due to differences in thermal expansion coefficients when cooling to room temperature after epitaxial growth.

[0025] When the undoped silicon epitaxial layer or the boron, phosphorus or arsenic is doped to 1×10 18 The epitaxial growth of silicon epitaxial layers with a concentration of atoms / cc or less is performed by doping boron or phosphorus with a small covalent radius to 1×10 19 When a polished silicon wafer is grown on a surface with a concentration of 100 atoms / cc or more, a lattice mismatch occurs at the interface between the polished wafer and the epitaxial layer, and thus the shape of the silicon epitaxial wafer becomes convex. If arsenic or antimony with a large covalent radius is doped into a polished silicon wafer at a high concentration, the shape of the wafer becomes concave. The thicker the epitaxial layer becomes, the greater the stress and the warpage. It is also well known in silicon epitaxial manufacturing technology that when a silicon epitaxial film with high resistivity is grown thicker on a silicon substrate with low resistivity, mismatch dislocations occur and stress is relieved, and the warpage due to plastic deformation will be almost halved. (Figure 1)

[0026] Single crystal silicon does not exhibit plasticity at room temperature. Even at high temperatures, single crystal silicon without dislocations deforms elastically. However, when a certain amount of stress or greater is applied, dislocations are introduced and plastic deformation occurs in them. The crystal orientation and stress state will determine the type of dislocations produced and the direction in which they extend. When the epitaxial growth interface is a (111) plane, the misfit dislocations that alleviate the lattice mismatch are mainly edge dislocations extending parallel to the growth interface. In the area where dislocations occur, plastic deformation is likely to occur. It is well known that in silicon, this phenomenon becomes apparent at temperatures above 800°C. Figure 3 Schematic diagram illustrating the stress-distortion curves of silicon crystals with and without dislocations at 900°C. (See Non-Patent Document 1)

[0027] When nitride semiconductors are epitaxially grown on silicon substrates, misfit dislocations occur immediately in the early stages of growth due to the significant lattice mismatch. A buffer layer is formed to maintain stress parallel to the growth interface, and then gallium nitride crystals are grown on top. After the lattice mismatch is reduced to a certain degree, devices are formed on top. As the lattice mismatch is reduced in the buffer layer, some dislocations become threading dislocations extending toward the surface layer. Various buffer layer structures are designed to reduce the density of threading dislocations.

[0028] However, using a silicon substrate increases the threading dislocation density in gallium nitride crystals by approximately one order of magnitude compared to using a sapphire substrate, and therefore gallium nitride crystals are rarely used in LEDs. This is primarily because the ratio of the thermal expansion coefficient of sapphire to that of gallium nitride is 1.16, while the ratio of the thermal expansion coefficient of silicon to that of gallium nitride is 0.6, resulting in a significant difference in the thermal stress that occurs during cooling after epitaxial growth. When using a silicon substrate, mitigating thermal stress is a priority in the performance of nitride semiconductor buffer layers. In this method, misfit dislocations in the silicon substrate also contribute to thermal stress mitigation, thereby suppressing the occurrence of cracks and warping, and thus enabling the use of a buffer layer that causes fewer threading dislocations.

[0029] In silicon power MOSFETs, misfit dislocations can become threading dislocations due to distortion during device fabrication and may extend into the device region, which can lead to increased leakage current. Therefore, technologies that can suppress the generation of misfit dislocations have been studied. It is also known that misfit dislocations that are close to each other can cause interactions with each other, resulting in threading dislocations extending toward the surface. (Non-patent document 2) After performing epitaxial growth of gallium nitride in a temperature range of 1050°C to 1150°C, the effect of thermal distortion caused during cooling to room temperature on misfit dislocations is complex. When the misfit dislocations intentionally introduced into the silicon substrate are more than 100 μm away from the nitride semiconductor buffer layer, the stress relief effect is reduced. However, partly due to the relationship with the method used to manufacture the nitride buffer layer, the range of the tightness that will cause interactions between dislocations and subsequently increase the threading dislocations is a separately determined issue.

[0030] from Figure 3 It can be seen that plastic deformation is less likely to occur in a silicon substrate without dislocations. Accordingly, greater stress is applied to the nitride semiconductor buffer layer, resulting in a higher density of misfit dislocations to alleviate the stress. As the dislocation density increases, the likelihood of dislocations intersecting and forming threading dislocations increases. Therefore, it is believed that the density of dislocations extending upward from the buffer layer increases.

[0031] There are several methods for inducing misfit dislocations in silicon epitaxial wafers. The following discussion primarily relates to a method that uses relatively readily available and easily manufactured ultra-low resistance polished silicon wafers as substrates.

[0032] When growing a thick, high-resistance epitaxial film on a very low-resistance silicon substrate, misfit dislocations can occur. Various approaches have been developed to prevent this. However, current methods, on the other hand, require precise substrate and epitaxial growth conditions to induce misfit dislocations.

[0033] Generally speaking, the impurity concentration of the polished silicon substrate is 1×10 19 atoms / cm 3 or more, and the impurity concentration of the epitaxial layer is 2×10 18 atoms / cm 3 Or less. When an epitaxial film doped to a low concentration (high resistance) is grown on a polished silicon substrate doped with phosphorus or boron to a high concentration (low resistance), a lattice mismatch of the order of 0.01% occurs at the interface (Non-Patent Document 2), and convex warping occurs on the surface. When an epitaxial film doped to a low concentration (high resistance) is grown on a low resistance substrate doped with arsenic or antimony to a high concentration, concave warping occurs on the surface. As high-resistance epitaxial growth is carried out at high temperatures and the epitaxial layer becomes thicker, the stress caused by the lattice constant mismatch between the epitaxial layer and the substrate increases, and the warping of the wafer becomes greater. When the epitaxial film thickness exceeds the critical film thickness, misfit dislocations occur, and the stress is relieved by plastic deformation, thereby reducing warping. (Figure 1)

[0034] Whether misfit dislocations occur depends on the silicon epitaxial growth temperature (heat treatment temperature), the resistivity of the substrate, and the thickness of the epitaxial layer. (See Figure 2 ) As described in Non-Patent Document 1, substrates in which mismatches occur can be observed and evaluated by X-ray topography. Even without using this technique, if mismatches exist over a wide range, they can be visually observed as a network of steps on a surface under a spotlight.

[0035] In addition to increasing the concentration of dopants in a polished silicon wafer to form misfit dislocations in a silicon epitaxial wafer, the present invention also includes forming a layer doped with boron or phosphorus to a high concentration in the silicon epitaxial layer. One or more thin silicon germanium layers may be inserted into the epitaxial layer.

[0036] Alternatively, instead of polishing a silicon wafer with low resistance or forming an epitaxial layer with high concentration in an epitaxial substrate, a nitride semiconductor can be epitaxially grown on a silicon substrate in which one or more species of phosphorus, boron, antimony, carbon or germanium have been added at a concentration of 5×10 14 atoms / cm 2Ion implantation has been performed with a dose of 100 nm or more, and recovery heat treatment has been performed, and then silicon epitaxial growth has been performed and misfit dislocations have been introduced.

[0037] Effects of the present invention

[0038] As described above, according to the present invention, when a nitride semiconductor is epitaxially grown on a silicon substrate, a silicon substrate is used in which misfit dislocations are intentionally generated to enable plastic deformation. Therefore, when the nitride semiconductor is epitaxially grown, stress caused by lattice mismatch at the interface with the silicon substrate is mitigated not only by the buffer layer formed in the nitride semiconductor but also by the silicon substrate. Consequently, a nitride semiconductor crystal layer with good crystallinity and low warpage can be formed on the silicon crystal.

[0039] When a nitride semiconductor crystal is cooled to room temperature after being epitaxially grown on a silicon crystal, large concave warping occurs due to the difference in thermal conductivity between silicon and the nitride semiconductor, and cracks may sometimes occur in the nitride semiconductor layer. Figure 4 , it was shown that by forming misfit dislocations in a silicon epitaxial wafer used as a substrate, thermal stress occurring during cooling to approximately 800°C was also alleviated in the silicon substrate due to plastic deformation. Therefore, when cooled to room temperature, thermal stress was reduced, and the occurrence of warping and cracks could be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG. 1 schematically illustrates a situation in which an epitaxial layer becomes thicker as epitaxial growth proceeds and misfit dislocations occur, and a warpage state immediately before the misfit dislocations occur.

[0041] Figure 2 This is a graph showing the relationship between the epitaxial layer thickness of a silicon epitaxial wafer, the resistivity of the substrate, and the occurrence of misfit dislocations during growth at 1130°C.

[0042] Figure 3 This figure illustrates the stress-distortion curves for a silicon crystal with and without dislocations at 900°C. (Tensile distortion is added.)

[0043] Figure 4 The stress state in the step of cooling the nitride semiconductor in the epitaxial substrate of the present invention will be described in the case where misfit dislocations are present and the case where misfit dislocations are not present.

[0044] Figure 5 A semiconductor device in which the semiconductor substrate of the present invention is used is schematically illustrated. DETAILED DESCRIPTION

[0045] The following describes a standard method for fabricating GaN-on-Si substrates. Depending on the equipment used, the conditions described herein may not be optimal. The optimal mode is described assuming that GaN-on-Si wafers for HEMTs are fabricated using indirectly heated single-wafer MOCVD equipment.

[0046] Figure 1 illustrates a (P / P++ type) silicon epitaxial wafer in which an epitaxial layer of several Ωcm is formed on an extremely low resistance p-type substrate. The crystal orientation is (111) and doped with 2 to 4×10 19 atoms / cm 3 The CZ substrate is doped with boron in the range of 10 to 200 nm. Epitaxial growth is performed in a single wafer reactor using trichlorosilane as a silicon source to grow an epitaxial layer. The epitaxial layer is doped with 1 to 2×10 16 atoms / cm 3 concentration of boron. Figure 1A An epitaxial wafer is described, on which epitaxial growth is performed at 1200° C. to a thickness of 6 μm, and in which misfit dislocations (MFD) occur. Figure 1B An epitaxial wafer is described, on which epitaxial growth is performed at 1120° C. to a thickness of 4 μm and in which no mismatch occurs.

[0047] exist Figure 1A In all epitaxial wafers, a network of microscopic steps intersecting at 60°, attributed to misfit dislocations, was visually observed under a spotlight. Parts of the wafers were inspected by X-ray topography, revealing misfit dislocations. Warpage was 14 μm or less.

[0048] against Figure 1B No network of microscopic steps intersecting at 60°, attributed to misfit dislocations, was observed visually under a spotlight on the epitaxial wafer in the image. One wafer was extracted and examined using X-ray topography, but no misfit dislocations were observed. The warpage was approximately 22 μm.

[0049] Next, we describe the steps for producing a GaN-on-Si wafer, in which a nitride semiconductor is epitaxially grown on a silicon epitaxial substrate using an MOCVD apparatus. A single-wafer experimental reactor was used for the MOCVD apparatus. The silicon epitaxial substrate was pre-annealed in a hydrogen atmosphere at 1120°C, and then an AlN film was grown to a thickness of 100 nm using TMA (trimethylaluminum) and NH3 (ammonia) gases to form an initial layer.

[0050] Next, a buffer layer is formed on the initial layer. The buffer layer is grown by repeating the first and second layers several dozen to several hundred times. The first layer is made of AlN and has a thickness of approximately 5 nm, and the second layer is made of GaN and has a thickness of approximately 5 nm. They are grown using TMG (trimethylgallium) and NH3 (ammonia) gases. In this example, the buffer layer thickness is set to 1000 nm.

[0051] After the buffer layer is grown, a gallium nitride layer (iGaN layer) is grown on the buffer layer. During the growth of the gallium nitride layer (which is called the active layer), no impurities are doped. In this case, a GaN-on-Si wafer having a gallium nitride layer having a thickness of 2.5 μm is produced. A barrier layer made of AlGaN (Al composition 0.25) is formed on the gallium nitride layer. The thickness of the barrier layer is 25 nm. By using the above-mentioned manufacturing method, a GaN wafer to be used as a substrate having a Figure 5 The structure of the HEMT device shown is a GaN-on-Si substrate wafer.

[0052] Hereinafter, embodiments having different conditions are described by using the above-described basic manufacturing method as a basis, but the present invention is not limited thereto.

[0053] (Example 1)

[0054] As a silicon substrate, use Figure 1A The epitaxial substrate with misfit dislocations shown in FIG. After pre-annealing in a hydrogen atmosphere at 1120° C., an AlN initial layer was formed to a thickness of 100 nm without changing the temperature, and then a buffer layer was grown in sequence. The total thickness of the buffer layer was 1000 nm. A gallium nitride layer (which is an active layer) was grown on the buffer layer at 1120° C. to a thickness of 2500 nm. In the GaN-on-Si substrate manufactured by such a method, the crystal quality of the GaN layer (iGaN layer and AlGaN layer) was evaluated by x-ray diffraction (XRD) based on the full width at half maximum of the peak waveform (arc seconds). The results were: the full width at half maximum of the (102) plane was 399 arc seconds, and the full width at half maximum of the (002) plane was 318 arc seconds. No cracks were observed on the entire surface of this GaN-on-Si wafer.

[0055] (Example 2)

[0056] As a silicon substrate, use Figure 1AAn epitaxial substrate with misfit dislocations shown in FIG was prepared. After pre-annealing in a hydrogen atmosphere at 1120° C., the epitaxial layer was etched by 2 μm using HCl gas to a thickness of 4 μm, and then processed similarly to the case of Example 1 to obtain a GaN-on-Si wafer. In the obtained GaN-on-Si wafer, the GaN layers (iGaN layer and AlGaN layer) were evaluated by X-ray diffraction. The results were: the full width at half maximum of the (102) plane was 433 arc seconds, and the full width at half maximum of the (002) plane was 367 arc seconds. No cracks were observed on the entire surface of the wafer.

[0057] (Example 3)

[0058] As a silicon substrate, the Figure 1A The epitaxial substrate with misfit dislocations shown in FIG was pre-annealed, and then the epitaxial layer was etched to a thickness of 1.5 μm using HCl gas, and then processed similarly to the case of Example 1 to obtain a GaN-on-Si wafer. In the obtained GaN-on-Si wafer, the GaN layers (iGaN layer and AlGaN layer) were evaluated by X-ray diffraction. The results were: the full width at half maximum of the (102) plane was 568 arc seconds, and the full width at half maximum of the (002) plane was 454 arc seconds. No cracks were found at the periphery of the wafer.

[0059] (Comparative Example 1)

[0060] In addition to Figure 1B A GaN-on-Si wafer was obtained by processing similarly to Example 1, except that the epitaxial substrate without misfit dislocations shown in the figure was used as a silicon substrate. The GaN layers (iGaN layer and AlGaN layer) in the obtained GaN-on-Si wafer were evaluated by X-ray diffraction. The results showed that the full width at half maximum of the (102) plane was 447 arc seconds, and the full width at half maximum of the (002) plane was 572 arc seconds. Cracks were also observed within a range of approximately 20 mm from the outer periphery of the wafer.

[0061] (Comparative Example 2)

[0062] Use 20Ωcm A CZ-polished wafer was used as the silicon substrate. Except for the substrate, processing was performed similarly to that in Example 1 to obtain a GaN-on-Si wafer. In the obtained GaN-on-Si wafer, the GaN layers (iGaN layer and AlGaN layer) were evaluated by X-ray diffraction. The results were: a full width at half maximum (FWHM) of 641 arc seconds in the (102) plane, and a full width at half maximum (FWHM) of 502 arc seconds in the (002) plane. Cracks were also observed within a range of approximately 20 mm from the outer periphery of the wafer.

[0063] The table summarizes the conditions of the silicon substrates, the full width at half maximum in XRD, and the state of crack generation in Example 1, Example 2, Example 3, Comparative Example 1, and Comparative Example 2.

[0064] [Table 1]

[0065] Table 1

[0066]

[0067] As can be seen from Table 1, when a nitride semiconductor is epitaxially grown on a silicon substrate (in which misfit dislocations are intentionally generated at a specific depth so that plastic deformation can occur therein), crack generation is suppressed and the crystallinity of the epitaxial layer of the nitride semiconductor is improved. It can also be seen that if the misfit layer is positioned closer to the interface, at a distance of approximately 1.5 μm or less from the interface, both the beneficial and detrimental effects tend to be eliminated. Even when a silicon substrate doped with a high concentration of boron is used, there is no effect of suppressing crack generation.

[0068] Explanation of symbols

[0069] 11: Silicon epitaxial layer

[0070] 12: Silicon single crystal substrate (low resistance)

[0071] 13: Misfit dislocation

[0072] 14: Warping of mismatched epitaxial wafers

[0073] 15: Warpage of epitaxial wafer without mismatch

[0074] 33: Initial layer

[0075] 34: AlN layer

[0076] 35:GaN layer

[0077] 36: buffer layer

[0078] 37: Active (iGaN) layer

[0079] 38: Barrier layer

[0080] 41: Source electrode

[0081] 42: drain electrode

[0082] 43: Gate electrode.

Claims

1. A nitride semiconductor substrate comprising a silicon substrate and a nitride semiconductor epitaxially grown on the silicon substrate, wherein misfit dislocations are present in the silicon substrate, wherein a position at which the density of the misfit dislocations reaches a maximum in a depth direction is located at a position more than 1.5 μm from an interface between the silicon substrate and the nitride semiconductor, and wherein the silicon substrate comprises a silicon single crystal substrate having a first doping concentration and a silicon epitaxial layer formed on the silicon single crystal substrate, the silicon epitaxial layer having a second doping concentration lower than the first doping concentration.

2. A method for manufacturing the nitride semiconductor substrate according to claim 1, the method comprising the following steps: manufacturing an epitaxial wafer by using a polished silicon wafer as a substrate and vapor-depositing a silicon single crystal thin film on a main surface of the polished silicon wafer, the silicon single crystal thin film having a lattice constant different from that of the polished silicon wafer, the difference in lattice constant causing misfit dislocations at an interface with the substrate; and A nitride semiconductor is epitaxially grown by using the epitaxial wafer as the silicon substrate.

3. A method for manufacturing the nitride semiconductor substrate according to claim 1, the method comprising the following steps: When a silicon epitaxial layer is to be vapor-deposited on a polished silicon wafer, an epitaxial wafer is manufactured by growing the epitaxial layer so as to sandwich an epitaxial layer having a lattice constant different from that of the epitaxial layer, thereby inducing misfit dislocations in the epitaxial layer due to the difference in the lattice constants; and A nitride semiconductor is epitaxially grown by using the epitaxial wafer as the silicon substrate.

4. A method for manufacturing the nitride semiconductor substrate according to claim 1, the method comprising the following steps: ion implanting one or more species of phosphorus, boron, antimony, carbon, or germanium into a polished silicon wafer to a high concentration; Perform recovery heat treatment; performing epitaxial growth by using the wafer as a substrate to induce misfit dislocations at an interface with the substrate, thereby forming an epitaxially grown wafer; and A nitride semiconductor is epitaxially grown by using the epitaxial growth wafer as the silicon substrate.

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