A ferroelectric double annealing process for enhancing the storage window

Abstract

The present invention discloses a ferroelectric double annealing process capable of enhancing the storage window. In this method, pre-annealing is performed before growing the functional layer of the ferroelectric memory, and post-annealing is performed after growing the upper electrode. The pre-annealing means putting the memory with the to-be-grown functional layer into an annealing furnace, heating it at a speed V1 in the atmosphere of nitrogen. When the temperature reaches between 200 and 500 degrees Celsius, hold for a time T1. After T1, perform rapid annealing. When the temperature drops to between 40 and 60 degrees Celsius, take out the memory with the to-be-grown functional layer. The post-annealing means putting the memory with the grown upper electrode into the annealing furnace, heating it at a speed V2 in the atmosphere of nitrogen. When the temperature reaches between 400 and 700 degrees Celsius, hold for a time T2. After T2, perform rapid annealing. When the temperature drops to between 40 and 60 degrees Celsius, take out the memory with the grown upper electrode. Compared with the functional layer without pre-annealing, the present invention can have a larger storage window.

Description

Technical Field

[0001] The present invention relates to a pre-annealing process for one layer in a novel double-layer ferroelectric memory. Specifically, a new double-annealing process is designed to fabricate a novel hafnium oxide-based ferroelectric memory. Background Art

[0002] Major DRAM manufacturers such as Samsung, Micron, and SK hynix have produced DRAM cells scaled down to a 15-nanometer design rule (D / R). Now, they are developing the n+1 and n+2 generations, namely the so-called 1a (or 1α) and 1b (or 1β), which means that the D / R of DRAM cells using EUV may be able to be further scaled down to below 12 nanometers. Due to challenges in patterning, leakage current, and sensing margin, the speed of cell size scaling is getting slower and slower. Graphic DRAM and high-bandwidth memories (such as GDDR6(X) and HBM2(E)) adopt DRAM technology nodes at the 20-nanometer or 10-nanometer level. By adding low-power DRAM chips in the module, the camera module on smartphones has achieved a stack of three chips. Some innovations can be seen in advanced DRAM products, such as high-k dielectric materials, cylindrical capacitors, grooved-channel LV transistors, and HKMG peripheral transistors. Looking ahead to the DRAM technology trend and R & D roadmap, DRAM scaling will continue for more than the next 10 years.

[0003] As major NAND manufacturers compete to increase the number of 3D NAND stacked layers, they have all launched their own 96L or 128L 3D NAND chips. Samsung's 128L V-NAND (V6), KIOXIA and Western Digital Company (WDC)'s 96L BiCS4, Intel / Micron's 96L / 128L and 176L FG CuA, and SK hynix's 128L 4D NAND PUC products have been put on the market. We will discuss many innovative changes in this field.

[0004] In addition to storage density, 3D NAND is also applied to high-speed SSDs, such as Samsung's Z-SSD and KIOXIA's parallel XL-FLASH with multiple planes. SK hynix has achieved a 147-layer vertical storage cell stack, and their solutions as well as Micron's solutions are explored.

[0005] Although Micron's X100 SSD is currently only available for add-in cards (AICs), Intel has extended the XPoint memory application not only to conventional SSDs but also to Intel Optane non-volatile memory. Everspin has released many new pMTJ MRAM products (third generation, 1GB / chip based on 28-nanometer process), Avalanche / Renesas (40 nanometers), and Samsung / Sony (28FDS). The second-generation ReRAM (CBRAM) products from Dialog (previously Adesto) are also on the market. The new hafnium oxide-based ferroelectric, as a non-volatile memory, can have fast read and write speeds (in the picosecond range), low read and write voltages (±2V), an ultrathin functional layer (3 nanometers), and good read and write endurance (10^12). In the case of device scaling, it is the most promising next-generation integrable new memory and also a good opportunity for China to overtake in the memory market. It has both the read and write speeds and tolerance of DRAM, as well as good retention characteristics, and a fabrication process compatible with CMOS. It is a popular choice for the next-generation non-volatile memory.

[0006] Therefore, exploring a fabrication process for hafnium oxide-based ferroelectrics with a high storage window is an important topic. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a ferroelectric double-annealing process that can enhance the storage window. Before growing the functional layer, pre-anneal the pre-annealing interlayer. After annealing, prepare the storage functional layer. The pre-annealing interlayer of zirconia undergoes a phase change under the pre-annealing conditions, providing a good lower interface for the growth of the orthorhombic ferroelectric (O-phase) with ferroelectric properties in the subsequent functional layer. Therefore, compared with the functional layer without pre-annealing, a larger storage window can be obtained.

[0008] To solve the above technical problem, the technical solution adopted by the present invention is: a ferroelectric double-annealing process that can enhance the storage window. In this method, pre-annealing is carried out before the growth of the functional layer of the memory, and post-annealing is carried out after the growth of the upper electrode;

[0009] The pre-annealing means putting the memory with the functional layer to be grown into an annealing furnace, heating it at a speed V1 in a nitrogen atmosphere. When the temperature reaches between 200 and 500 degrees Celsius, hold for a time T1. After T1, perform rapid annealing. When the temperature drops to 40 - 60 degrees Celsius, take out the memory with the functional layer to be grown;

[0010] Post-annealing means putting the memory with the upper electrode grown into an annealing furnace, heating it up at a speed of V2 under the atmosphere of nitrogen. When the temperature reaches between 400 and 700 degrees Celsius, hold for a time T2. After T2, perform rapid annealing. When the temperature is cooled down to 40 - 60 degrees Celsius, take out the memory with the upper electrode grown.

[0011] Further, V1 = (15 - 20) degrees Celsius per second.

[0012] Further, V2 = (15 - 20) degrees Celsius per second.

[0013] Further, T1 = 30 - 90 seconds.

[0014] Further, T2 = 30 - 90 seconds.

[0015] Further, the rapid annealing in pre-annealing and post-annealing means cooling down the holding temperature to 40 - 60 degrees Celsius within 60 seconds.

[0016] Further, prepare the lower electrode and the pre-annealing interlayer before pre-annealing. First, generate the lower electrode on a silicon-based or silicon dioxide substrate by magnetron sputtering, and then prepare the pre-annealing interlayer with a thickness between 0.5 and 5 nanometers on the lower electrode by atomic layer deposition. After preparation, put the substrate, the lower electrode, and the pre-annealing interlayer into the annealing furnace for pre-annealing.

[0017] Further, prepare the functional layer and the upper electrode after pre-annealing. The functional layer is a storage layer with a thickness between 3 and 20 nanometers grown on the pre-annealing interlayer by atomic layer deposition. After forming the functional layer, drop photoresist on the functional layer and rotate it on a spin coater for a period of time, then perform photolithography. After photolithography, dry, develop, and clean. Put the cleaned sample into a magnetron sputtering instrument to grow a certain thickness of titanium nitride, tungsten, or platinum as the upper electrode, then clean the photoresist, and finally perform post-annealing.

[0018] Further, the pre-annealing interlayer and the functional layer are magnetron sputtered by a pulsed cycle method. The growth per single pulsed cycle is 0.9 - 1.1 nanometers. The pre-annealing interlayer sputters zirconia in each pulsed cycle, and each pulsed cycle of the functional layer includes five hafnium oxide pulsed cycles plus five zirconia pulsed cycles.

[0019] Further, this process is applicable to the gate structure of ferroelectric memories or ferroelectric transistors.

[0020] Advantages of the present invention: The present invention adopts a double annealing process, that is, pre-annealing before the preparation of the functional layer and post-annealing after the formation of the upper electrode. With the pre-annealing intercalation of pre-annealed zirconia, a rhombic phase of zirconia appears at a relatively low annealing temperature. This phase of the oxide results in the formation of more orthorhombic phases (ferroelectric phases, structures with storage characteristics) during the preparation of the functional layer (HfZrO2). Compared with the hafnium-based ferroelectric without pre-annealing, a larger storage window can be obtained.

[0021] The two-step annealing process of the present invention can not only be used for the preparation of hafnium-based ferroelectrics, but also obtain a larger storage window during the preparation of hafnium-based Fefet. Under the conditions of the same thickness and the same structure, with the same turn-on speed and read / write speed, this double annealing process can achieve a larger storage window value under the same read / write voltage. Brief Description of the Drawings

[0022] Figure 1 Schematic diagram for the preparation of the intercalation layer;

[0023] Figure 2 Schematic diagram of the structure of the hafnium-based ferroelectric functional layer;

[0024] Figure 3 Schematic diagram of the structure for the preparation of the upper electrode;

[0025] Figure 4 Schematic diagram of the data of the storage window value of the device pre-annealed at 200 °C;

[0026] Figure 5 Schematic diagram of the data of the storage window value of the device pre-annealed at 300 °C;

[0027] Figure 6 Schematic diagram of the data of the storage window value of the device pre-annealed at 400 °C;

[0028] Figure 7 Schematic diagram of the data of the storage window value of the device without pre-annealing;

[0029] Figure 8 Waveform diagram of the applied pulse;

[0030] Figure 9 Schematic diagram of the variable temperature curve of the pre-annealing;

[0031] Figure 10 Flow chart for the preparation of the ferroelectric memory in Example 1;

[0032] In the figures: 1. Substrate, 2. Lower electrode, 3. Pre-annealing intercalation layer, 4. Functional layer, 5. Upper electrode. Detailed Description of the Invention

[0033] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0034] Embodiment 1

[0035] Taking the hafnium-based ferroelectric memory as an example, this embodiment briefly describes a new process step of a double annealing step. Under the same preparation conditions, a two-step annealing process is adopted, which can have a larger storage window under the conditions of the same switching time, the same number of read / write cycles, and the same read / write voltage. Compared with the mainstream land, this device has good retention characteristics and a relatively low operating voltage. It is a non-volatile memory with excellent performance.

[0036] Figure 10 This is the flowchart for preparing the ferroelectric memory in this embodiment, which includes 6 steps: preparing the bottom electrode, preparing the interlayer, pre-annealing the sample, preparing the functional layer, preparing the top electrode, and post-annealing the sample.

[0037] Figure 1 The structures of the bottom electrode 2 and the pre-annealing interlayer 3 are shown. During the preparation process, first, the bottom electrode 2 is grown on a silicon-based or silicon dioxide substrate 1. In this article, magnetron sputtering is used to grow titanium nitride with a thickness of 40 nm as the bottom electrode 2. After preparing the bottom electrode 2, the sample is transferred into an atomic layer deposition (ALD) instrument, and then a 2-nm-thick pre-annealing interlayer 3 is grown. The pre-annealing interlayer 3 is a zirconia layer. The growth method adopted in this article requires 20 pulse cycles (each single growth is approximately 0.1 nm) at a furnace temperature of 280 °C. After preparation, the furnace temperature is reduced and the sample is taken out. After the sample is taken out, the sample is moved into a rapid thermal annealing furnace. In a nitrogen atmosphere, the temperature is raised to 300 °C at a heating rate of 20 °C per second and held for one minute. After one minute, rapid annealing is performed. When the temperature drops to 50 °C, the sample is taken out. The first step, namely the rapid thermal annealing of the interlayer, is completed.

[0038] Figure 2 The process preparation steps after the first-step rapid thermal annealing are shown. After the first-step rapid thermal annealing, the sample is moved into an atomic layer deposition (ALD) instrument, and a 10-nm-thick hafnium zirconium oxide functional layer is grown. In this article, 100 pulse cycles (each single growth is approximately 0.1 nm) are grown in this step, and the cycling method is the superposition growth of 5 hafnium oxide pulse cycles and 5 zirconia pulse cycles. After preparing the storage functional layer, the sample is taken out.

[0039] Figure 3 This is a schematic diagram for preparing the top electrode 5. Take out Figure 2After the growth of the functional layer 4 is completed, to fabricate the upper electrode 5, photolithography of the sample is required first. The photolithography procedure is to first drop the photoresist, then place the sample on a spin coater and spin the photoresist at a speed of 6000 revolutions per minute for 60 seconds. Then perform photolithography, and after photolithography, dry it by baking at 110 °C for 110 seconds. After that, develop it with a developer for 45 seconds and clean it with deionized water. The cleaned sample is placed in a magnetron sputtering instrument to grow 40 nm of titanium nitride as the upper electrode 5. After fabricating the upper electrode 5, take out the sample. Place it in an acetone solution to clean the photoresist. Then place it in an anhydrous ethanol solution to clean the excess acetone solution. After cleaning, take out the sample and place it in deionized water to clean it. Subsequently, move the sample into a rapid thermal annealing furnace. Under a nitrogen atmosphere, with a heating rate of 20 °C per second, heat it up to 500 °C and hold for one minute. After one minute, perform rapid annealing. When the temperature drops to 50 °C, take out the sample. Complete the second step, that is, the rapid post-annealing of the interlayer. After the annealing is completed, take out the sample.

[0040] Figure 5 Adopt Figure 1 For the device fabricated by the high-temperature pre-annealing method, after growing 2 nm of zirconia interlayer, move the sample into a rapid thermal annealing furnace. Under a nitrogen atmosphere, with a heating rate of 20 °C per second, heat it up to 300 °C and hold for one minute. After one minute, perform rapid annealing. When the temperature drops to 50 °C, take out the sample, then fabricate the functional layer. After fabricating and taking out the sample, fabricate the upper electrode, and finally perform the high-temperature annealing in the second step. Move the sample into a rapid thermal annealing furnace. Under a nitrogen atmosphere, with a heating rate of 20 °C per second, heat it up to 500 °C and hold for one minute. After one minute, perform rapid annealing. When the temperature drops to 50 °C, take out the sample. Apply a triangular pulse with a period of 1 ms to the upper and lower electrodes of the sample. The pulse first increases from 0 V to 3 V, then decreases from 3 V to -3 V, and then increases back to 0 V. The pulse waveform is as Figure 8 shown, with a period of 1 ms. While applying the pulse, collect its current. After collecting the current, integrate it. Divide the integrated current sum by the area of the electrode and convert it into the remanent polarization value, with the unit of microcoulomb per square centimeter. For the memory fabricated by pre-annealing at 300 °C, the initial value (the first cycle of the pulse) is 15 microcoulombs per square centimeter, and the maximum value (the wake-up value is also the maximum value) is 20 microcoulombs per square centimeter.

[0041] Example 2

[0042] After preparing the zirconia interlayer in this embodiment, the device is subjected to high-temperature pre-annealing at 200 °C. After preparing the interlayer, continue to grow a 10-nm hafnium zirconium oxide functional layer in an atomic layer deposition (ALD) instrument. In this article, 100 pulse cycles (each single growth is approximately 0.1 nm) are grown in this step. The cycling method is the superposition growth of 5 hafnium oxide pulse cycles plus 5 zirconia pulse cycles. Then, a triangular pulse with a period of 1 ms is applied to the upper and lower electrodes of the sample. The pulse first increases from 0 V to 3 V, then decreases from 3 V to -3 V, and then increases back to 0 V. The pulse waveform is as Figure 8 shown, with a period of 1 ms. The current is collected while applying the pulse. After collecting the current, it is integrated. The sum of the integrated currents is divided by the area of the electrode to convert it into the remanent polarization value, with the unit of microcoulomb per square centimeter (uC / cm2). As Figure 4 shown, for the memory device using 200 °C pre-annealing, the initial value (the first cycle pulse) is 4 uC / cm2, and the maximum value (the wake-up value is also the maximum value) is 12 uC / cm2.

[0043] Example 3

[0044] In this embodiment, after growing a 2-nm zirconia interlayer, the sample is moved into a high-temperature rapid annealing furnace. In an atmosphere of nitrogen, with a heating rate of 20 °C per second, the temperature is raised to 400 °C and held for one minute. After one minute, rapid annealing is performed. When the temperature drops to 50 °C, the sample is taken out, and then the functional layer is prepared. After preparing and taking out the sample, the upper electrode is prepared, and finally, high-temperature annealing is carried out in the second step. The sample is moved into a high-temperature rapid annealing furnace. In an atmosphere of nitrogen, with a heating rate of 20 °C per second, the temperature is raised to 500 °C and held for one minute. After one minute, rapid annealing is performed. When the temperature drops to 50 °C, the sample is taken out. A triangular pulse with a period of 1 ms is applied to the upper and lower electrodes of the sample. The pulse first increases from 0 V to 3 V, then decreases from 3 V to -3 V, and then increases back to 0 V. The pulse waveform is as Figure 8 shown, with a period of 1 ms. The current is collected while applying the pulse. After collecting the current, it is integrated. The sum of the integrated currents is divided by the area of the electrode to convert it into the remanent polarization value, with the unit of microcoulomb per square centimeter. As Figure 6 shown, for the memory device using 400 °C pre-annealing, the initial value (the first cycle pulse) is 10 uC / cm2, and the maximum value (the wake-up value is also the maximum value) is 12 uC / cm2.

[0045] Example 4

[0046] In this embodiment, after growing a 2-nanometer zirconia interlayer, annealing is not performed, and the functional layer is directly prepared. After the sample is taken out after preparation, the upper electrode is prepared, and finally, high-temperature annealing is performed in the second step. The sample is moved into a high-temperature rapid annealing furnace. In a nitrogen atmosphere, with a heating rate of 20 degrees Celsius per second, the temperature is raised to 500 degrees Celsius and maintained for one minute. After one minute, rapid annealing is performed. When the temperature drops to 50 degrees Celsius, the sample is taken out. A triangular pulse with a period of 1 millisecond is applied to the upper and lower electrodes of the sample. The pulse first increases from 0V to 3V, then decreases from 3V to -3V, and then increases back to 0V. The pulse waveform is as Figure 8 shown, with a period of 1 millisecond. The current is collected while the pulse is applied. After the current is collected, it is integrated. The integrated current sum is divided by the area of the electrode to be converted into the remanent polarization value, with the unit of microcoulomb per square centimeter. As Figure 7 shown, for the memory without pre-annealing, the initial value (the first cycle pulse) is 2 microcoulombs per square centimeter, and the maximum value (the wake-up value is also the maximum value) is 10 microcoulombs per square centimeter.

[0047] It can be seen from the comparison of Examples 1, 2, 3, and 4 that the ferroelectric memory using the double-annealing process has a larger storage window. The initial value of the storage window with a pre-annealing temperature of 200 degrees Celsius is 4 microcoulombs per square centimeter, and the maximum value is 12 microcoulombs per square centimeter. The initial value of the annealing window with a pre-annealing temperature of 300 degrees Celsius is 15 microcoulombs per square centimeter, and the maximum value is 20 microcoulombs per square centimeter. The initial value of the storage window with a pre-annealing temperature of 400 degrees Celsius is 10 microcoulombs per square centimeter, and the maximum value is 12 microcoulombs per square centimeter. The initial value of the storage window without pre-annealing is 2 microcoulombs per square centimeter, and the maximum value is 10 microcoulombs per square centimeter.

[0048] Figure 9 shown is the schematic diagram of the temperature change during pre-annealing; it can be seen from this figure that it includes three processes: heating, holding, and cooling (annealing). Its heating rate is approximately 16 degrees Celsius per second. During the cooling process before 100°C, its cooling rate is approximately 13.3 degrees Celsius per second, and during the cooling process after 100°C, its cooling rate is approximately 2.5 degrees Celsius per second.

[0049] The double-annealing process described in the present invention can not only be used for ferroelectric memories but also for the gate structure of ferroelectric transistors. When used as a gate structure, the greater the gate voltage and the duration of the charge injection, the more charge is injected. The positive and negative polarities of the gate voltage will affect the offset direction of the threshold voltage. The increase in charge injection causes more electrons to be captured by the gate oxide layer, increasing the threshold voltage, thereby controlling the threshold voltage.

[0050] Although Example 1 describes that the thickness of the storage layer is 10 nanometers, it is not limited to 10 nanometers and can be in the range of 3 - 20 nanometers.

[0051] In Example 1, 2 - nanometer zirconia is prepared as the interlayer, but the thickness of the interlayer is not limited to 2 nanometers and can be between 0.5 nanometer and 5 nanometers.

[0052] The temperature of the second annealing can vary from 400 to 700 degrees Celsius.

[0053] The electrodes for ferroelectric storage are not limited to titanium nitride, and other conductive electrodes such as tungsten or platinum can also be used to prepare the upper and lower electrodes of the memory.

[0054] Compared with the functional layer without pre - annealing, the present invention can have a larger storage window. When the pre - annealing temperature is low, the influence on the device can be negligible. At the same time, the storage window of the device after secondary annealing is significantly improved.

[0055] The above description only covers the basic principles and preferred embodiments of the present invention. Modifications and substitutions made by those skilled in the art based on the present invention fall within the protection scope of the present invention.

Claims

1. A ferroelectric double annealing process for enhancing the storage window, characterized in that: In this method, pre-annealing is carried out before the functional layer of the ferroelectric memory is generated, and post-annealing is carried out after the upper electrode is grown; pre-annealing is to anneal the pre-annealing interlayer after the pre-annealing interlayer is deposited on the lower electrode. The pre-annealing interlayer is a zirconia layer, the functional layer is a hafnium zirconium oxide functional layer, and the upper electrode material is titanium nitride; The pre-annealing refers to putting the memory to be grown with the functional layer into an annealing furnace, heating it at a speed of V1 in the atmosphere of nitrogen. When the temperature reaches between 200 - 500 degrees Celsius, hold for a time T1. After T1, perform rapid annealing. When the temperature drops to 40 - 60 degrees Celsius, take out the memory to be grown with the functional layer; Post-annealing refers to putting the memory with the upper electrode grown into the annealing furnace, heating it at a speed of V2 in the atmosphere of nitrogen. When the temperature reaches between 400 - 700 degrees Celsius, hold for a time T2. After T2, perform rapid annealing. When the temperature drops to 40 - 60 degrees Celsius, take out the memory with the upper electrode grown.

2. The ferroelectric double annealing process for enhancing the storage window according to claim 1, characterized in that: V1 = (15 - 20) degrees Celsius per second.

3. The ferroelectric double annealing process for enhancing the storage window according to claim 1, characterized in that: V2 = (15 - 20) degrees Celsius per second.

4. The ferroelectric double annealing process for enhancing the storage window according to claim 1, characterized in that: T1 = 30 - 90 seconds.

5. The ferroelectric double annealing process for enhancing the storage window according to claim 1, characterized in that: T2 = 30 - 90 seconds.

6. The ferroelectric double annealing process for enhancing the storage window according to claim 1, characterized in that: The rapid annealing in pre-annealing and post-annealing means that the holding temperature is dropped to 40 - 60 degrees Celsius within 60 seconds.

7. The ferroelectric double annealing process for enhancing the storage window according to claim 1, characterized in that: Before pre-annealing, the lower electrode and the pre-annealing interlayer are prepared. First, the lower electrode is generated on a silicon-based or silicon dioxide substrate by magnetron sputtering, and then a pre-annealing interlayer between 0.5 nanometers and 5 nanometers is prepared on the lower electrode by atomic layer deposition. After preparation, the substrate, the lower electrode, and the pre-annealing interlayer are put into the annealing furnace together for pre-annealing.

8. The ferroelectric double annealing process for enhancing the storage window according to claim 7, characterized in that: After pre-annealing, the functional layer and the upper electrode are prepared. The functional layer is to grow a 3 - 20 nanometer storage layer on the pre-annealing interlayer by atomic layer deposition. After the functional layer is formed, a photoresist is dropped on the functional layer and rotated on a spin coater for a period of time, then lithography is performed. After lithography, it is dried, developed, and cleaned. The cleaned sample is put into a magnetron sputtering instrument to grow a certain thickness of titanium nitride as the upper electrode, and then the photoresist is cleaned, and finally post-annealing is carried out.

9. The ferroelectric double annealing process for enhancing the storage window according to claim 8, characterized in that: The pre-annealing interlayer and the functional layer are magnetron sputtered in a pulsed cycle manner, growing 0.9 - 1.1 nanometers per single pulsed cycle. The pre-annealing interlayer sputters zirconia within each pulsed cycle, and each pulsed cycle of the functional layer includes five hafnium oxide pulsed cycles plus five zirconia pulsed cycles.

10. The ferroelectric double annealing process for enhancing the storage window according to any one of claims 1 - 9, characterized in that: this process is applicable to the gate structure of ferroelectric memories or ferroelectric transistors.

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