Mask plate, driving back plate and preparation method thereof, display panel and spliced screen

Abstract

The present application relates to the technical field of display, and especially relates to a mask plate, a preparation method of a driving back plate, a display panel and a spliced screen. The mask plate of different size display panels can be shared. The preparation method of the driving back plate comprises the following steps: a reference mask plate is made according to the pattern of the second circuit trace of a reference back plate, the size of the reference back plate is larger than the size of the driving back plate, and the second circuit trace comprises a plurality of first patterns arranged periodically along a first direction; the reference mask plate is used to splice and expose a mother plate according to the size of the driving back plate, and a third circuit trace is obtained, the size of the area where the third circuit trace is located along the first direction is equal to the size of the area where the first circuit trace is located along the first direction, the size of the area where the third circuit trace is located along a second direction is equal to the size of the area where the second circuit trace is located along the second direction, and the first direction and the second direction are perpendicular; and the mother plate after splicing and exposure is cut to obtain the driving back plate.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a mask, a driving backplate and its preparation method, a display panel and a splicing screen. Background Technology

[0002] Currently, the market demand for high-brightness, high-contrast MiniLED (Mini Light Emitting Diode) and MicroLED (Micro Light Emitting Diode) products is showing a clear upward trend. Compared with PCB (Printed Circuit Board) based MiniLED and MicroLED, glass-based MiniLED and MicroLED can achieve finer linewidths and denser wiring arrangements, and have great development potential.

[0003] However, the high cost of the masks used in the fabrication of glass-based MiniLEDs and MicroLEDs limits their market competitiveness. Summary of the Invention

[0004] The main objective of this invention is to provide a photomask, a driving backplate, a method for manufacturing the same, a display panel, and a video wall. It enables the sharing of photomasks for display panels of different sizes.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] On one hand, a method for fabricating a drive backplane is provided, the drive backplane having a first circuit trace; the fabrication method includes:

[0007] A reference mask is fabricated based on the pattern of the second circuit traces on the reference backplane. The size of the reference backplane is larger than that of the driving backplane. The second circuit traces include a plurality of first patterns arranged periodically along a first direction. Based on the size of the driving backplane, the master board is spliced ​​and exposed using the reference mask to obtain a third circuit trace. The size of the area where the third circuit trace is located along the first direction is equal to the size of the area where the first circuit trace is located along the first direction, and the size of the area where the third circuit trace is located along the second direction is equal to the size of the area where the second circuit trace is located along the second direction. The first direction and the second direction are perpendicular. The spliced ​​and exposed master board is cut to obtain the driving backplane.

[0008] In some embodiments, the step of splicing and exposing the master plate using the reference mask according to the size of the driving backplate includes:

[0009] Based on the dimension of the area where the first circuit trace is located along the first direction, the motherboard is divided into a splicing exposure area. The dimension of the splicing exposure area along the first direction is equal to the dimension of the area where the first circuit trace is located along the first direction, and the dimension of the splicing exposure area along the second direction is equal to the dimension of the area where the second circuit trace is located along the second direction. By moving the reference mask in the first direction, splicing exposure is performed on different positions of the splicing exposure area corresponding to the first direction to form a pattern of the first circuit trace corresponding to different positions of the splicing exposure area.

[0010] In some embodiments, the step of moving the reference mask in the first direction to perform stitching exposure on different positions of the stitching exposure area corresponding to the first direction includes:

[0011] The splicing exposure area is divided into a first exposure area and a second exposure area arranged sequentially along the first direction. The first exposure area and the second exposure area are adjacent to each other, and their edges overlap to form a splicing line. The first circuit trace includes a second pattern corresponding to the first exposure area and a third pattern corresponding to the second exposure area. The first exposure area is exposed using the first part of the reference mask corresponding to the second pattern, and the second exposure area is exposed using the second part of the reference mask corresponding to the third pattern.

[0012] In some embodiments, exposing the first exposure area using the first portion of the reference mask corresponding to the second pattern, and exposing the second exposure area using the second portion of the reference mask corresponding to the third pattern, includes:

[0013] The reference mask is divided into a first region and a second region along the first direction. The size of the first region along the second direction is larger than the size of the region containing the second pattern along the second direction, and the size of the second region along the second direction is larger than the size of the region containing the third pattern along the second direction. The reference mask is placed on the master plate, with the first region facing the first exposure area, covering the remaining areas of the reference mask except for the first region, and the first exposure area is exposed. The reference mask is then translated so that the second region faces the second exposure area, covering the remaining areas of the reference mask except for the second region, and the second exposure area is exposed.

[0014] In some embodiments, before splicing and exposing the master substrate using the reference mask according to the size of the drive backplane, the method further includes:

[0015] The first pattern portion of the first and second portions of the reference mask, which is interconnected along the first direction and is close to the splicing line, is thickened in the second direction.

[0016] In some embodiments, the first pattern portion of the first and second portions of the reference mask, which is interconnected along the first direction and is close to the splicing line, is thickened in the second direction during the fabrication of the reference mask according to the dimensions of the reference backplate.

[0017] In some embodiments, the first pattern portion of the first and second portions of the reference mask, which is interconnected along the first direction and located near the splicing line, is thickened in the second direction, including:

[0018] Increase the size of the first pattern portion along the second direction, so that the two edges of the first pattern portion in the second direction move to both sides by the same size.

[0019] In some embodiments, the first patterned portion moves to both sides by an amount greater than or equal to 10 micrometers along its two edges in the second direction.

[0020] In some embodiments, the plurality of first patterns include multiple rows of coupling portions arranged periodically along the first direction; the splicing line is formed between two adjacent rows of coupling portions.

[0021] In some embodiments, each first pattern includes at least two rows of coupling portions; the splicing line is formed between two adjacent first patterns.

[0022] In some embodiments, cutting the motherboard after splicing and exposure includes:

[0023] Based on the dimensions of the area where the first circuit trace is located along the second direction, the portion of the motherboard that extends beyond the first circuit trace corresponding to the third circuit trace is cut.

[0024] In some embodiments, the step of cutting the portion of the motherboard corresponding to the third circuit trace that extends beyond the first circuit trace, based on the dimension of the area where the first circuit trace is located along the second direction, includes:

[0025] Based on the difference in dimensions along the second direction between the region where the first circuit trace is located and the region where the third circuit trace is located, the regions where the third circuit trace is located are cut to the same dimensions on both sides along the second direction.

[0026] On the other hand, a drive backplane is provided, comprising: a substrate; a first circuit trace disposed on the substrate, the first circuit trace including a plurality of first patterns periodically arranged along a first direction; the plurality of first patterns including a second pattern portion extending along the first direction; the second pattern portion including at least one set of first bold patterns along its extension direction, each set of first bold patterns including a plurality of first bold patterns, each first bold pattern having a dimension along a second direction larger than the dimension of a first reference pattern along the second direction, the first reference pattern being a portion that contacts the first bold pattern along the extension direction of the second pattern portion; the first direction and the second direction are perpendicular.

[0027] In some embodiments, the plurality of first patterns include multiple rows of coupling portions arranged periodically along the first direction, with any set of first bold patterns located between two adjacent rows of coupling portions. Alternatively, each first pattern includes at least two rows of coupling portions, with any set of first bold patterns located between two adjacent first patterns.

[0028] On the other hand, a display panel is provided, including: a driving backplate as described above, and a plurality of light-emitting devices disposed on the driving backplate.

[0029] On the other hand, a splicing screen is provided, which is composed of multiple display panels spliced ​​together, wherein at least one display panel is the display panel described above.

[0030] In another aspect, a photomask is provided, comprising: a plurality of first patterns arranged periodically along a third direction; the plurality of first patterns including a third pattern portion extending along the third direction; the third pattern portion including at least two sets of second bold patterns along its extension direction, each set of second bold patterns including a plurality of second bold patterns, each second bold pattern having a dimension along a fourth direction greater than the dimension of a second reference pattern along a second direction, the second reference pattern being a portion that contacts the second bold pattern along the extension direction of the third pattern portion; the third direction and the fourth direction are perpendicular.

[0031] The embodiments of the present invention provide a mask, a driving backplate and its preparation method, a display panel and a splicing screen. It can achieve the production of a common set of mask for display panels of different sizes by changing the exposure method without changing the existing process and circuit design. It achieves adaptive size without adding extra process difficulty, which is conducive to the mass production of products. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1A This is a top view of a video wall provided in an embodiment of the present invention;

[0034] Figure 1B A cross-sectional view of a display panel provided in an embodiment of the present invention;

[0035] Figure 1C A cross-sectional view of another display panel provided in an embodiment of the present invention;

[0036] Figure 2A Comparison images of splicing screens with 90-inch, 98-inch, and 110-inch display panels provided in embodiments of the present invention;

[0037] Figure 2B A comparison diagram of the dimensions of a 90-inch, 98-inch, and 110-inch display panel and the dimensions of a photomask provided for embodiments of the present invention;

[0038] Figure 3A The flowcharts for steps S10 and S20 in a method for preparing a drive backplate according to an embodiment of the present invention are shown below.

[0039] Figure 3B A flowchart of steps S10 and S20 in another method for preparing a drive backplate according to an embodiment of the present invention;

[0040] Figure 3C A flowchart of step S20 provided in an embodiment of the present invention;

[0041] Figure 3D This is a top view of the mask and third circuit traces corresponding to step S202 provided in an embodiment of the present invention;

[0042] Figure 3E This is a top view of the mask and third circuit traces corresponding to step S202 provided in an embodiment of the present invention;

[0043] Figure 3F This invention provides a comparison of the mask exposure patterns before and after the corresponding splicing line position in the first circuit trace is thickened, as shown in the embodiment of the invention.

[0044] Figure 3GThis is a structural diagram showing the number of rows of a reference mask corresponding to two exposures of a 90-inch, 98-inch, and 110-inch display panel, provided for embodiments of the present invention.

[0045] Figure 3H A structural diagram of the pattern after exposure of a mask after the thickened stitching line position in another first circuit trace provided in an embodiment of the present invention;

[0046] Figure 3I This invention provides a circuit diagram corresponding to a single lamp zone.

[0047] Figure 3J A flowchart of step S30 in a method for preparing a drive backplate according to an embodiment of the present invention;

[0048] Figure 4A A top view of the second conductive layer of a 100-inch MiniLED display panel provided in an embodiment of the present invention;

[0049] Figure 4B A top view of the second conductive layer of a 90-inch MiniLED display panel provided in an embodiment of the present invention;

[0050] Figure 5 This is a structural diagram of a mask plate provided in an embodiment of the present invention. Detailed Implementation

[0051] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0052] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0053] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0054] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0055] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0056] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0057] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0058] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0059] As used herein, “about” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0060] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0061] Some embodiments of this disclosure provide a video wall 200, such as... Figure 1A As shown, the video wall 200 is composed of multiple display panels 100 spliced ​​together. For example, the video wall 200 may also include a driving circuit configured to drive the multiple display panels 100 for display.

[0062] The video wall 200 can be any of the following: monitor, television, billboard, laser printer with display function, home appliance, large wall area, information query device (such as business query device for e-government, bank, hospital, power and other departments), mobile phone, personal digital assistant (PDA), digital camera, portable camcorder and navigator; it can also be a micro-display, or a product containing a micro-display, such as a near-eye display or wearable device, specifically it can be an AR / VR system, smart glasses, head-mounted display (HMD) and head-up display (HUD).

[0063] In some embodiments, the display panel 100 may be an OLED (Organic Light Emitting Diode) panel, a QLED (Quantum Dot Light Emitting Diodes) panel, an LCD (Liquid Crystal Display) panel, an LED (including Mini LED or MicroLED) panel, etc.

[0064] In some embodiments, such as Figure 1A and Figure 1B As shown, the display panel 100 may include a driving backplate 1 and a plurality of light-emitting devices 2, wherein the driving circuit is used to provide a driving signal to the driving backplate 1, and the driving backplate 1 is used to drive the plurality of light-emitting devices 2 to emit light under the control of the driving signal.

[0065] Here, we will take the display panel 100 as an LED panel and the driver backplane as an LED driver backplane as an example for explanation.

[0066] Some embodiments of this disclosure provide a drive backplane, such as Figure 1C As shown, the system includes a substrate 11 and circuit traces 12 disposed on the substrate 11. The circuit traces 12 may include multiple conductive patterns and multiple insulating layers. For example, the multiple conductive patterns may include a first conductive layer 121 and a second conductive layer 124. The multiple insulating layers may include a first passivation layer 122 and a planarization layer 123 disposed between the first conductive layer 121 and the second conductive layer 124, and a second passivation layer 125 and a protective layer 126 disposed on the side of the second conductive layer 124 away from the substrate 11. Each conductive pattern and each insulating layer can be prepared using a photomask.

[0067] The first conductive layer 121 is typically used to arrange various signal lines, such as the common voltage line GND, the drive voltage line VLED, the source power line PWR, and the source address line DI. Optionally, the thickness of the first conductive layer 121 is approximately 1.5 μm to 7 μm, and its material includes copper. For example, it can be formed by sputtering a stacked material such as MoNb / Cu / MoNb, with the bottom layer being MoNb. To improve adhesion, the intermediate Cu layer is used to transmit electrical signals, and the top layer is MoNb. Used for oxidation prevention. This film can also be formed by electroplating, first forming a seed layer 121a (MoNiTi) to increase the grain nucleation density, and then forming an anti-oxidation layer 121b (MoNiTi) after electroplating.

[0068] The second conductive layer 124 is typically used to provide various pads, such as pads for mounting functional components or pads for mounting driver chips for functional components; the second conductive layer 124 can also provide leads for connection. Optionally, the film thickness of the second conductive layer 124 is approximately The material can be a stacked material such as MoNb / Cu / CuNi, with the bottom layer MoNb used to improve adhesion, the middle layer Cu used to transmit electrical signals, and the top layer CuNi to ensure both oxidation resistance and solidification.

[0069] In some embodiments, the first passivation layer 122 may be made of an inorganic material, such as silicon nitride, silicon oxide, or silicon oxynitride. The planarization layer 123 may be made of an organic material, such as polyimide, epoxy resin, phenolic resin, or other organic materials. Through-holes are provided on the first passivation layer 122 and the planarization layer 123 to couple the second conductive layer 124 and the first conductive layer 121. The second passivation layer 125 may be made of an inorganic material, such as silicon nitride, silicon oxide, or silicon oxynitride. The protective layer 126 may be made of an inorganic-organic composite material. Through-holes may be provided on the second passivation layer 125 and the protective layer 126 for connecting the light-emitting device 2 and the second conductive layer 124.

[0070] To increase the stress between the first conductive layer 121 and the substrate 11, a buffer layer 13 may be provided between the substrate 11 and the first conductive layer 121. The material of the buffer layer 13 is an inorganic material such as silicon nitride or silicon oxide.

[0071] In some embodiments, substrate 11 may be a glass substrate. LED display panels based on PCBs (Printed Circuit Boards) are limited by copper thickness, linewidth, and material properties, making them less advantageous for products requiring finer linewidths, such as AM MiniLED (Active Matrix Mini Light Emitting Diode) products. Glass-based backplanes, on the other hand, allow for finer linewidths and denser wiring arrangements, showing great development potential. Furthermore, glass substrates are more advantageous for large-size products. PCBs, limited by material properties and equipment, require more splicing and result in more noticeable seams in large-size products. Glass substrates, with their larger base material size, can reduce the number of splicing steps, effectively improving the visual effect.

[0072] However, in related technologies, for display panels of different sizes, the pattern of the circuit traces 12 of the driving backplate 1 is also different depending on the spacing of the light-emitting device 2 (such as LED). This means that display panels of different sizes require mask plates M' with different patterns to be manufactured, which undoubtedly increases production costs. This is especially true for glass-based MiniLED display panels, which is not conducive to quickly opening up the market and thus not conducive to improving market competitiveness.

[0073] Additionally, it should be noted that in existing processes, taking 90-inch, 98-inch, and 110-inch MiniLED display panels manufactured on glass substrates on a 6.5-generation production line as examples, such as... Figure 2A and Figure 2B As shown, on the one hand, for splicing screens of different sizes, four MiniLED display panels are required to form a complete product size. On the other hand, during manufacturing, due to the limited size of the mask M' itself (752mm*1100mm), while the size of a 90-inch display panel is 500mm (short side)*1200mm (long side), a 98-inch display panel is 540mm*1220mm, and a 110-inch display panel is 600mm*1370mm, a single mask M' cannot accommodate a display panel of the same size (such as 90-inch, 98-inch, or 110-inch), and they all need to be spliced ​​and exposed along their long sides.

[0074] Based on the above, some embodiments of this disclosure provide a method for preparing a driving backplate 1 that enables the sharing of mask M', which can achieve the sharing of mask M' when manufacturing display panels of different sizes, reducing the manufacturing cost of glass-based large-size MiniLEDs and facilitating rapid market access.

[0075] Among them, for example, such as Figure 2A and Figure 2B As shown, the driving backplane 1 can be a 90-inch MiniLED backplane, that is, the size of the driving backplane 1 is 500mm (short side direction) * 1200mm (long side direction), and the driving backplane 1 has a first circuit trace.

[0076] like Figures 3A to 3I As shown, the preparation method includes:

[0077] S10. Based on the pattern of the second circuit trace 12_2 of the reference backplane 1', a reference mask M is fabricated. The size of the reference backplane 1' is larger than the size of the driving backplane 1. The second circuit trace 12_2 includes traces along a first direction (e.g., ...). Figure 3B Multiple first patterns arranged periodically (as indicated by the middle arrow a).

[0078] The reference backplane 1' can be an example of a 110-inch MiniLED backplane or a 98-inch MiniLED backplane. The multiple first patterns can be examples of the second circuit traces 12_2 located in display area A.

[0079] The reference mask M can be 752mm x 1100mm. Using the reference mask M, the second circuit trace 12_2 can be fabricated by splicing exposures along the long side direction (i.e., the first direction a) of the reference backplate 1'.

[0080] Therefore, based on the dimensions of the reference backplate 1', a pattern is drawn on the reference mask M, and the reference mask M can be fabricated based on the drawn pattern.

[0081] Here, taking the display panel 100 to which the reference backplate 1' belongs as an example, which includes multiple LEDs arranged in an array and the spacing between the LEDs (i.e., the spacing between each two adjacent LEDs) is 8mm, the pattern of the second circuit trace 12_2 in the display area can be multiple first patterns arranged periodically along the first direction. The pattern of the second circuit trace 12_2 in the bonding area B is different from the multiple first patterns. In this case, when making the reference mask M, the reference mask M can include a portion of the patterns corresponding to the multiple first patterns arranged periodically along the first direction, as well as the pattern corresponding to the second circuit trace 12_2 in the bonding area B. In this way, by using the reference mask M to splice and expose the motherboard, the same pattern as the second circuit trace 12_2 can be obtained.

[0082] S20, such as Figure 3A and Figure 3B As shown, based on the dimensions of the driving backplane 1, the motherboard W is spliced ​​and exposed using a reference mask M to obtain the third circuit trace 12_3. The dimension of the area containing the third circuit trace 12_3 along the first direction is equal to the dimension of the area containing the first circuit trace along the first direction (that is, the dimension of the area containing the first circuit trace along the long side of the driving backplane 1). The dimension of the area containing the third circuit trace 12_3 along the second direction (such as...) Figure 3B The size of the area where the second circuit trace 12_2 is located is equal to the size of the area along the second direction, and the first and second directions are perpendicular.

[0083] That is, the reference mask M used to fabricate the reference backplate 1' is used to stitch and expose the mother plate W. Similar to using the reference mask M to stitch and expose the mother plate W to fabricate the reference backplate 1', the reference mask M is used to stitch and expose along the long side direction (i.e., the first direction) of the driving backplate 1. Figure 3B and Figure 3C Specifically, it includes:

[0084] S201. Based on the dimensions of the area where the first circuit trace is located along the first direction, the motherboard W is divided into a splicing exposure area Q. The dimensions of the splicing exposure area Q along the first direction are equal to the dimensions of the area where the first circuit trace is located along the first direction, and the dimensions of the splicing exposure area Q along the second direction are equal to the dimensions of the area where the second circuit trace 12_2 is located along the second direction.

[0085] That is, the size of the splicing exposure area Q along the second direction is greater than the size of the area where the first circuit trace of the driving backplate 1 is located along the second direction, and the size of the splicing exposure area Q along the first direction defines the size of the area where the first circuit trace of the driving backplate 1 is located along the first direction.

[0086] S202. Using the reference mask M to move in the first direction, splicing exposure is performed on different positions of the splicing exposure area Q corresponding to the first direction to form a pattern of the first circuit traces corresponding to different positions of the splicing exposure area Q.

[0087] Specifically, the reference mask M can be used to expose the corresponding parts of the patterns of different regions of the first circuit trace along the first direction, thereby obtaining the pattern of the spliced ​​first circuit trace.

[0088] In some embodiments, a reference mask M is moved in a first direction to perform stitched exposure on different positions of the stitched exposure area corresponding to the first direction, such as... Figure 3C As shown, it includes:

[0089] The splicing exposure area Q is divided into a first exposure area Q1 and a second exposure area Q2 arranged sequentially along the first direction. The first exposure area Q1 and the second exposure area Q2 are adjacent to each other, and their edges overlap to form a splicing line L. The first circuit trace includes a second pattern corresponding to the first exposure area Q1 and a third pattern corresponding to the second exposure area Q2.

[0090] The first exposure area Q1 is exposed using the first part of the second pattern corresponding to the reference mask M, and the second exposure area Q2 is exposed using the second part of the third pattern corresponding to the reference mask M.

[0091] That is, the splicing exposure area Q is divided into two exposure areas for splicing exposure, and the patterns of these two exposure areas can be the same or different.

[0092] Here, combined with Figure 3B and Figure 3C Taking the second circuit trace 12_2 as an example, which includes multiple first patterns located in display area A and a pattern located in binding area B, the second pattern may include multiple first patterns arranged periodically along the first direction, and the third pattern includes at least the pattern located in binding area B.

[0093] For example, such as Figure 3DAs shown, taking a 90-inch MiniLED display panel to which the driving backplate 1 belongs as an example, the driving backplate 1 can include a pattern corresponding to the circuit diagram connecting 45 rows of LEDs, and a pattern for the bonding area B. Since the reference mask M has a pattern corresponding to the circuit diagram connecting 35 rows of LEDs, and a pattern corresponding to the bonding area B, the second pattern can be a circuit diagram connecting N rows of LEDs, where n is greater than or equal to 1 and less than or equal to 35. The third pattern can be the pattern for the bonding area B, and a circuit diagram connecting m rows of LEDs, where m+n equals 45. In this case, the first part of the reference mask M corresponding to the second pattern can be the part corresponding to the circuit diagram connecting n rows of LEDs, and the second part of the reference mask M corresponding to the third pattern can be the part corresponding to the bonding area B and the circuit diagram connecting m rows of LEDs.

[0094] Specifically, in combination Figure 3C and Figure 3D Taking the second pattern corresponding to the patterns in rows 14 (Z14) to 35 (Z35) of the reference mask M as an example, the third pattern corresponds to the pattern in the reference mask M corresponding to the bonding area B, and also to the patterns in rows 1 (Z1) to 23 (Z23) of the reference mask M. Thus, the portion corresponding to rows 14 to 35 of the reference mask M can be used to expose the first exposure area Q1, and the portion corresponding to rows 1 to 23 of the reference mask M can be used to expose the second exposure area Q2. That is, in the first exposure, the stitching line L is located between rows 13 and 14 in the reference mask M, and in the second exposure, the stitching line L is located between rows 23 and 24 in the reference mask M. Alternatively, in the first exposure, the stitching line L is located between rows 23 and 24 in the reference mask M, and in the second exposure, the stitching line L is located between rows 13 and 14 in the reference mask M. In this way, the pattern of the first circuit trace of the LED corresponding to rows 35-14+1+23=45 can be obtained.

[0095] Similarly, in combination Figure 3C and Figure 3E Taking a display panel to which the driving backplate belongs, which includes 50 rows of LEDs, as an example, the first exposure area Q1 can be exposed using the portion of the reference mask M corresponding to the 12th row (Z12) to the 35th row (Z35), and the second exposure area Q2 can be exposed using the portion of the reference mask M corresponding to the 1st row (Z1) to the 26th row (Z26), thereby obtaining the pattern of the first circuit trace 12 corresponding to 35-12+1+26=50 rows of LEDs.

[0096] In some embodiments, exposing the first exposure area Q1 using the first portion of the reference mask M corresponding to the second pattern, and exposing the second exposure area Q2 using the second portion of the reference mask M corresponding to the third pattern, includes:

[0097] like Figure 3C , Figure 3D and Figure 3E As shown, the reference mask M is divided into a first region P1 and a second region P2 along the first direction. The size of the first region P1 along the second direction is larger than the size of the region containing the second pattern along the second direction, and the size of the second region P2 along the second direction is larger than the size of the region containing the third pattern along the second direction.

[0098] Place the reference mask M on the mother plate W, and make the first region P1 face the first exposure region Q1. Cover the rest of the reference mask M except for the first region P1, and expose the first exposure region Q1.

[0099] For example, a baffle can be used to cover the remaining areas of the reference mask M except for the first region P1, thereby enabling the first exposure area Q1 to be exposed.

[0100] The reference mask M is shifted so that the second region P2 is directly opposite the second exposure region Q2, thus covering the remaining areas of the reference mask M except for the second region P2, and the second exposure region Q2 is exposed.

[0101] For example, the reference mask M can be translated along the first direction so that the second region P2 is directly opposite the second exposure region Q2.

[0102] It should be noted that during the process of exposing the first exposure area Q1 using the first part of the second pattern corresponding to the reference mask M, and exposing the second exposure area Q2 using the second part of the third pattern corresponding to the reference mask M, the difference in alignment accuracy between the two exposures may cause poor splicing between the patterns connected along the first direction, resulting in poor connection or even breakage of the patterns at the splicing line.

[0103] In the example above, taking the second pattern corresponding to rows 14 to 35 in the reference mask M as an example, the splicing line L formed by the two exposures is located between the circuit diagrams corresponding to rows 23 and 24 in the first circuit trace, as follows. Figure 3F As shown in the enlarged view within the dashed box on the right, if there is a deviation in the alignment accuracy between the two exposures, it will cause the patterns R that are close to the splicing line L and connected to each other along the first direction to shift, which is not conducive to the effective connection of the patterns R.

[0104] Based on this, in some embodiments, before splicing and exposing the mother plate W using the reference mask M according to the size of the driving backplate 1, the method further includes:

[0105] The first pattern portion of the first and second portions of the reference mask M, which is interconnected along the first direction and close to the splicing line L, is thickened in the second direction.

[0106] By thickening the first pattern portion in the first and second parts of the reference mask M, which is connected to each other in the first direction and close to the splicing line L, in the second direction, when there is a deviation in the alignment accuracy of the two exposures, the thickened first pattern portion can compensate for the alignment deviation, thereby preventing splicing and connection problems between the connected patterns R, or even line breaks.

[0107] In some embodiments, the first pattern portion of the first and second portions of the reference mask M, which is interconnected along a first direction and close to the splicing line L, is thickened in a second direction. This occurs during the fabrication of the reference mask M according to the dimensions of the reference backplate 1'.

[0108] Specifically, during the process of fabricating the reference mask M based on the dimensions of the reference backplate 1', the pattern corresponding to the first pattern portion can be thickened during the pattern drawing process of the reference mask M based on the dimensions of the reference backplate 1', so that the thickened first pattern portion can be obtained during the subsequent fabrication of the reference mask M.

[0109] In some embodiments, the first pattern portion of the first and second portions of the reference mask M, which is interconnected along a first direction and close to the splicing line L, is thickened in a second direction, including:

[0110] Increase the size of the first pattern part along the second direction, so that the two edges of the first pattern part in the second direction move to the sides by the same size.

[0111] That is, by thickening both sides of the first pattern portion in the second direction, it is possible to avoid the problem of a part of the connection in the first pattern portion shifting relative to the other part of the connection in the second direction towards the thickened side during the second exposure, which would be detrimental to compensating for the deviation caused by the shift.

[0112] Based on the above, in some embodiments, in the drive backplane 1, the first circuit trace 12_1 includes a plurality of first patterns arranged periodically along a first direction. The plurality of first patterns includes a second pattern portion extending along the first direction. The second pattern portion includes at least one set of first bold patterns along its extension direction, each set of first bold patterns including a plurality of first bold patterns, each first bold pattern having a dimension along a second direction greater than the dimension of a first reference pattern along the second direction, the first reference pattern being the portion that contacts the first bold pattern along the extension direction of the second pattern portion. The first direction and the second direction are perpendicular.

[0113] That is, by thickening the first pattern portion of the reference mask M near the splicing line L during exposure, the reference mask M will have multiple thickened areas. Thus, during two exposures, the thickened portions will remain in the final product at locations other than the area corresponding to the splicing line L. This results in the first circuit trace 12_1 including at least one set of first thickened patterns (the first thickened patterns are the thickened portions remaining on the drive backplate 1 at locations other than the area corresponding to the splicing line L). Figure 3F The dashed box on the left shows the case where the bolded portion remains on the drive backplate as pattern R (i.e., the first bolded pattern).

[0114] In some embodiments, a reference mask M is used for sharing 90-inch, 98-inch, and 110-inch display panels, see Table 1 and... Figure 3G As shown, taking the patterns between rows 13 and 14, between rows 23 and 24, between rows 11 and 12, between rows 26 and 27, between rows 9 and 10, and between rows 28 and 29 of the reference mask M as an example, when fabricating a 90-inch display panel using this reference mask M, the patterns between rows 1 and 13 are masked during the first exposure, while the bolded patterns in rows 14 to 35 remain on the driving backplate. This way, the patterns between rows 23 and 14 are left on the driving backplate. During the second exposure, the bold patterns between lines 24, 26, and 27, as well as between lines 28 and 29, are masked over the patterns between lines 24 and 35. The bold patterns between lines 1 and 23 remain on the drive backplate 1. That is, the patterns between lines 9 and 10, between lines 11 and 12, and between lines 13 and 14 are left on the drive backplate. In other words, after two exposures, there are six bold patterns left on the drive backplate 1, which means that the first set of bold patterns is six.

[0115] Table 1

[0116]

[0117] In some embodiments, the first patterned portion moves to both sides by an amount greater than or equal to 10 micrometers along its two edges in the second direction. That is, with the maximum offset in the stitching exposure controlled at 10 micrometers, the first patterned portion is thickened by at least 10 micrometers on one side in the second direction.

[0118] In some embodiments, such as Figure 3F As shown, the plurality of first patterns include multiple rows of coupling portions G arranged periodically along a first direction. A splicing line L is formed between two adjacent rows of coupling portions G.

[0119] The coupling part G is the part of the second circuit trace 12 that connects to the LED (i.e., the LED pad). By forming the splicing line L between two adjacent rows of coupling parts G, the thickening effect can be reduced.

[0120] Based on the above, in some embodiments, in the drive backplate 1, a plurality of first patterns include multiple rows of coupling portions G arranged periodically along a first direction, and each group of first bold patterns (i.e., R) is formed between two adjacent rows of coupling portions G.

[0121] In other embodiments, such as Figure 3H As shown, each first pattern includes at least two rows of coupling portions G. A splicing line L is formed between two adjacent first patterns.

[0122] The coupling portion G is the part in the first circuit trace 12_1 that connects to the LED (i.e., the LED pad). Since multiple first patterns are arranged periodically along the second direction, and each first pattern includes at least two rows of coupling portions G, at least two rows of coupling portions G can form a lamp area. By forming the splicing line L between two adjacent lamp areas, that is, on the lower side of each lamp area, the thickening effect can be minimized. This is because, as Figure 3H As shown, this minimizes the amount of bold pattern that ultimately remains on the drive backplate 1.

[0123] Based on the above, in some embodiments, in the drive backplane 1, each first pattern includes at least two rows of coupling portions G, and each set of first bold patterns (i.e., R) is formed between two adjacent first patterns.

[0124] like Figure 3I The diagram shown is a circuit diagram (i.e., a first pattern) corresponding to a lamp area, which includes a driver pad group, which includes: a first input pad Di, a second input pad Pwr, an output pad Out, and a common voltage pad Gnd.

[0125] The first input pad Di is configured to receive a first input signal, such as an address signal, to select a driver chip with a corresponding address, which is mounted on the driver pad group. For example, different driver chips may have the same or different addresses. The first input signal can be an 8-bit address signal, and the driver chip mounted on the driver pad group can determine the address to be transmitted by parsing this address signal.

[0126] The second input pad Pwr is configured to receive a second input signal, such as a power line carrier communication signal. For example, the second input signal not only provides power to the driver chip mounted on the driver pad assembly, but also transmits communication data to the driver chip, which can be used to control the light-emitting duration of the corresponding LED, thereby controlling its visual brightness.

[0127] The output pad Out is configured to output drive signals and relay signals. For example, the relay signal is an address signal provided to other driver chips; that is, the first input pad Di of another driver chip (which could be the driver chip in the next row) receives this relay signal as its first input signal to obtain the address signal. As another example, the drive signal can be a drive current used to drive the LED to emit light.

[0128] The common voltage pad Gnd is configured to receive a common voltage signal, such as a ground signal.

[0129] At this time, the driver chip mounted on the driver pad group is configured to output a relay signal through the output pad Out during a first time period based on the first input signal received from the first input pad Di and the second input signal received from the second input pad Pwr, and to provide a drive signal to a plurality of LEDs connected in series through the output pad Out during a second time period. Specifically, during the first time period, the output pad Out outputs a relay signal, which is provided to other driver chips to enable them to obtain address signals. During the second time period, the output pad Out outputs a drive signal, which is provided to the plurality of LEDs connected in series, causing the LEDs to emit light during the second time period. It should be understood that the first time period and the second time period are different time periods, and the first time period may, for example, be earlier than the second time period. The first time period may be consecutive with the second time period, and the end time of the first time period is the start time of the second time period; or, there may be other time periods between the first time period and the second time period, which may be used to implement other required functions, or these other time periods may only be used to separate the first time period and the second time period to avoid interference between the signals from the output pad Out during the first time period and the second time period.

[0130] In a lamp zone, the driving voltage terminal Vled is coupled to the aforementioned driving voltage line VLED. In the driving pad group, the first input pad Di is coupled to a source address line DI or the output pad Out of another lamp zone, the second input pad Pwr is coupled to the source voltage line PWR, the output pad Out is coupled to the LED of this lamp zone and the first input pad Di of other lamp zones, and the common voltage pad Gnd is coupled to the common voltage line GND.

[0131] The source address line DI is configured to transmit a first input signal. The source address line DI may be coupled to the first input pad Di of the first of at least two lamp zones. The output pad Out of each of these lamp zones, except the last one, is coupled to the first input pad Di of the next lamp zone in that zone. The output pad Out of the last lamp zone may be coupled to a signal output terminal to form a loop. Furthermore, the output pad Out of each of these lamp zones is coupled to the LED of that zone to output a drive signal to a plurality of LEDs mounted in series on that zone.

[0132] The source voltage line PWR is configured to transmit a second input signal. For example, each source voltage line PWR is coupled to at least one lamp zone (one or more lamp zones, such as a row of lamp zones) and provides a second transmission signal to each second input pad Pwr in all lamp zones coupled thereto.

[0133] The drive voltage line VLED is configured to transmit drive voltage. For example, each drive voltage line VLED is coupled to at least one lamp zone (one or more lamp zones, such as a row of lamp zones), providing drive voltage to all lamp zones coupled thereto. The drive voltage terminal of each lamp zone can be the portion of a drive voltage line VLED at the coupling position with that lamp zone.

[0134] The common voltage line GND is configured to transmit a common voltage. For example, each common voltage line GND is coupled to at least one lamp zone (one or more lamp zones, such as a row of lamp zones), providing a common voltage to the common voltage pads Gnd in all lamp zones coupled to it. The common voltage is, for example, a ground signal.

[0135] S30, such as Figure 3J As shown, the motherboard W after splicing and exposure is cut to obtain the driving backplate 1.

[0136] Specifically, this includes: based on the dimensions of the area where the first circuit trace is located along the second direction, cutting the portion of the motherboard corresponding to the third circuit trace that extends beyond the first circuit trace.

[0137] Since the first circuit trace and the third circuit trace are both axisymmetric patterns along the second direction, and the bonding area B is located in the middle of the reference mask M along the second direction, in order not to affect the electrical performance.

[0138] Optionally, based on the dimensions of the area where the first circuit trace is located along the second direction, the portion of the motherboard corresponding to the third circuit trace that extends beyond the first circuit trace is cut, including:

[0139] Based on the difference in dimensions along the second direction between the area where the first circuit trace is located and the area where the third circuit trace is located, the area where the third circuit trace is located is cut to the same dimensions on both sides along the second direction.

[0140] In other words, the area where the third circuit trace is located is cut symmetrically on both sides, which can avoid the impact of cutting from one side on the bonding area.

[0141] In summary, the embodiments of this disclosure can achieve the fabrication of a common set of reference masks for display panels of different sizes without changing the existing process and circuit design, simply by changing the exposure method. While achieving adaptive size, it does not increase the process difficulty and is conducive to the mass production of products.

[0142] In addition, the display panels of different sizes obtained by the above preparation method all have a uniform LED pitch, which can meet the product requirements of display panels of different sizes with uniform LED pitch, thereby obtaining low-cost products.

[0143] However, for situations where different LED pitches are required for products of different sizes, some embodiments of this disclosure propose a design that increases the LED pitch in integer multiples for products of different sizes. Specifically, taking the fabrication of the drive backplate 1 using 7 photomasks (i.e., photomasks 1 and 2 for fabricating the first conductive layer, photomask 3 for fabricating the first passivation layer 123, photomask 4 for fabricating the planarization layer 124, photomask 5 for fabricating the second conductive layer 124, photomask 6 for fabricating the second passivation layer 125, and photomask 7 for fabricating the protective layer 126) as an example, the above design can still achieve the sharing of 5 photomasks, only requiring the replacement of one photomask 5 for fabricating the second conductive layer 124.

[0144] Specifically, a copper metal thin film is first formed on a substrate. A first conductive layer 121 of a certain copper thickness is obtained through mask 1 and mask 2. Then, a first insulating layer thin film is formed on the first conductive layer 121. A first passivation layer 123 is formed by exposure through mask 3. Vias are formed in the first passivation layer 123. A planarization layer 124 is then formed through mask 4, and vias are formed in the planarization layer 124. The vias in the first passivation layer 123 and the planarization layer 124 are used for coupling the first conductive layer 121 with the second conductive layer 124 later. Next, the second conductive layer 124 is formed using mask 5, and the second passivation layer 125 is formed through mask 6, and vias are formed in the second passivation layer 125. A protective layer 126 is formed through mask 7, and vias are formed in the protective layer 126. The LED is coupled to the second conductive layer 124 through the vias in the second passivation layer 125 and the protective layer 126.

[0145] For example, the design benchmark for the driver backplane of a 110-inch MiniLED display panel is still taken as the reference mask. Figure 4A and Figure 4B As shown, the LED pitch of a 90-inch MiniLED display panel is 4mm, and the LED pitch of a 110-inch MiniLED display panel is 8mm. By redesigning the second conductive layer 124 of the 110-inch MiniLED display panel used to connect the LED lamp area, the mask of different sizes of display panels with different LED pitches can be shared.

[0146] Some embodiments of this disclosure provide a mask M', such as Figure 5 As shown, this includes: along a third direction (such as...) Figure 5 (As shown by arrow c) A plurality of first patterns are arranged periodically. The plurality of first patterns include a third pattern portion extending along a third direction; the third pattern portion includes at least two sets of bold patterns along its extension direction, each set of bold patterns including a plurality of second bold patterns, each second bold pattern extending along a fourth direction (e.g., ...). Figure 5 The size of the second reference pattern (as indicated by the middle arrow d) is larger than the size of the second reference pattern along the fourth direction. The second reference pattern is the portion that contacts the second thickened pattern along the extension direction of the third pattern portion; the third and fourth directions are perpendicular.

[0147] In these embodiments, the mask M' can be used for splicing exposures to fabricate display panels. For example, if the mask M' includes two sets of second bolded patterns, the offset caused by the splicing exposure position can be compensated when fabricating the display panel using the mask M'. If the mask M' includes multiple sets, such as six sets of second bolded patterns, then the mask M' can be used for 90-inch, 98-inch, and 110-inch display panels, and the offset caused by the splicing exposure position of display panels of each size can be compensated.

[0148] In some embodiments, the dimension of the mask M' along the third direction can be 1100 mm, and the dimension along the fourth direction can be 752 mm. That is, the third direction is the direction of the long side of the mask M', and the fourth direction is the direction of the short side of the mask M'.

[0149] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for preparing a drive backplate, characterized in that, The drive backplane has a first circuit trace; the fabrication method includes: A reference mask is fabricated based on the pattern of the second circuit traces on the reference backplane. The size of the reference backplane is larger than that of the driving backplane. The second circuit traces include a plurality of first patterns arranged periodically along a first direction. Based on the dimensions of the drive backplane, the motherboard is spliced ​​and exposed using the reference mask to obtain the third circuit trace. The dimension of the area where the third circuit trace is located along the first direction is equal to the dimension of the area where the first circuit trace is located along the first direction, and the dimension of the area where the third circuit trace is located along the second direction is equal to the dimension of the area where the second circuit trace is located along the second direction. The first direction and the second direction are perpendicular. The motherboard after splicing and exposure is cut. Based on the size of the area where the first circuit trace is located along the second direction, the portion of the motherboard that exceeds the first circuit trace in the part corresponding to the third circuit trace is cut so that the size of the area where the third circuit trace is located along the second direction is equal to the size of the area where the first circuit trace is located along the second direction, thus obtaining the driving backplate. The step of splicing and exposing the master plate using the reference mask according to the size of the driving backplate includes: Based on the dimension of the area where the first circuit trace is located along the first direction, the motherboard is divided into a splicing exposure area. The dimension of the splicing exposure area along the first direction is equal to the dimension of the area where the first circuit trace is located along the first direction, and the dimension of the splicing exposure area along the second direction is equal to the dimension of the area where the second circuit trace is located along the second direction. By moving the reference mask in the first direction, the stitching exposure area is stitched and exposed at different positions corresponding to the first direction to form a pattern of the first circuit trace corresponding to different positions of the stitching exposure area.

2. The method for preparing the drive backplate according to claim 1, characterized in that, The step of moving the reference mask in the first direction to perform splicing exposure on different positions of the splicing exposure area corresponding to the first direction includes: The splicing exposure area is divided into a first exposure area and a second exposure area arranged sequentially along the first direction. The first exposure area and the second exposure area are adjacent to each other, and their edges overlap to form a splicing line. The first circuit trace includes a second pattern corresponding to the first exposure area and a third pattern corresponding to the second exposure area. The first exposure area is exposed using the first portion of the reference mask corresponding to the second pattern, and the second exposure area is exposed using the second portion of the reference mask corresponding to the third pattern.

3. The method for preparing the drive backplate according to claim 2, characterized in that, The step of exposing the first exposure area using the first portion of the reference mask corresponding to the second pattern, and exposing the second exposure area using the second portion of the reference mask corresponding to the third pattern, includes: The reference mask is divided into a first region and a second region along the first direction. The size of the first region along the second direction is larger than the size of the region containing the second pattern along the second direction, and the size of the second region along the second direction is larger than the size of the region containing the third pattern along the second direction. The reference mask is placed on the mother plate, with the first area facing the first exposure area, and the remaining areas of the reference mask except for the first area are covered, and the first exposure area is exposed. The reference mask is shifted so that the second region is directly opposite the second exposure area, thus covering the remaining areas of the reference mask except for the second region, and the second exposure area is exposed.

4. The method for preparing the drive backplate according to claim 2, characterized in that, Before splicing and exposing the master plate using the reference mask according to the size of the drive backplate, the process further includes: The first pattern portion of the first and second portions of the reference mask, which is interconnected along the first direction and is close to the splicing line, is thickened in the second direction.

5. The method for preparing the drive backplate according to claim 4, characterized in that, The first pattern portion of the first and second portions of the reference mask, which is interconnected along the first direction and is close to the splicing line, is thickened in the second direction during the process of fabricating the reference mask according to the size of the reference backplate.

6. The method for preparing the drive backplate according to claim 4, characterized in that, The first pattern portion of the first and second portions of the reference mask, which is interconnected along the first direction and close to the splicing line, is thickened in the second direction, including: Increase the size of the first pattern portion along the second direction, so that the two edges of the first pattern portion in the second direction move to both sides by the same size.

7. The method for preparing the drive backplate according to claim 6, characterized in that, The first patterned portion moves to both sides by a dimension greater than or equal to 10 micrometers along its two edges in the second direction.

8. The method for preparing the drive backplate according to claim 2, characterized in that, The plurality of first patterns include multiple rows of coupling portions arranged periodically along the first direction, and the splicing line is formed between two adjacent rows of coupling portions; or, Each first pattern includes at least two rows of coupling portions, with the splicing lines formed between two adjacent first patterns.

9. The method for preparing the drive backplate according to any one of claims 1 to 8, characterized in that, The step of cutting the portion of the motherboard corresponding to the third circuit trace that extends beyond the first circuit trace, based on the dimension of the area where the first circuit trace is located along the second direction, includes: Based on the difference in dimensions along the second direction between the region where the first circuit trace is located and the region where the third circuit trace is located, the regions where the third circuit trace is located are cut to the same dimensions on both sides along the second direction.

10. A drive backplane, characterized in that, The drive backplate is prepared by the method for preparing the drive backplate according to any one of claims 1 to 9; the drive backplate comprises: Substrate; A first circuit trace disposed on the substrate, the first circuit trace including a plurality of fourth patterns arranged periodically along a first direction; The plurality of fourth patterns include a second pattern portion extending along a first direction; The second pattern portion includes at least one set of first bold patterns along its extension direction. Each set of first bold patterns includes multiple first bold patterns. The size of each first bold pattern along the second direction is larger than the size of the first reference pattern along the second direction. The first reference pattern is the portion that contacts the first bold pattern along the extension direction of the second pattern portion. The first direction and the second direction are perpendicular.

11. The drive backplane according to claim 10, characterized in that, The plurality of fourth patterns include multiple rows of coupling portions arranged periodically along the first direction, and any group of first bold patterns is located between two adjacent rows of coupling portions; Alternatively, each fourth pattern may include at least two rows of coupling portions, with any set of first bold patterns located between two adjacent fourth patterns.

12. A display panel, characterized in that, include: The drive backplate as described in any one of claims 10-11; And a plurality of light-emitting devices disposed on the drive backplate.

13. A video wall, characterized in that, The splicing screen is composed of multiple display panels, wherein at least one display panel is the display panel as described in claim 12.

14. A photomask, characterized in that, The method of fabricating a driving backplane as described in any one of claims 1 to 9, wherein the mask is a reference mask in the method of fabricating a driving backplane as described in any one of claims 1 to 9; the mask comprises: Multiple fifth patterns arranged periodically along the first direction; The plurality of fifth patterns include a third pattern portion extending along a first direction; The third pattern portion includes at least two sets of second bold patterns along its extension direction. Each set of second bold patterns includes multiple second bold patterns. The size of each second bold pattern along the second direction is larger than the size of the second reference pattern along the second direction. The second reference pattern is the portion that contacts the second bold pattern along the extension direction of the third pattern portion. The first direction and the second direction are perpendicular.

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